JP6043049B2 - Semiconductor device mounting structure and semiconductor device mounting method - Google Patents

Semiconductor device mounting structure and semiconductor device mounting method Download PDF

Info

Publication number
JP6043049B2
JP6043049B2 JP2011076410A JP2011076410A JP6043049B2 JP 6043049 B2 JP6043049 B2 JP 6043049B2 JP 2011076410 A JP2011076410 A JP 2011076410A JP 2011076410 A JP2011076410 A JP 2011076410A JP 6043049 B2 JP6043049 B2 JP 6043049B2
Authority
JP
Japan
Prior art keywords
semiconductor device
bonding
bonding material
mounting structure
device mounting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2011076410A
Other languages
Japanese (ja)
Other versions
JP2012212712A (en
JP2012212712A5 (en
Inventor
森　三樹
三樹 森
元 中島
元 中島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP2011076410A priority Critical patent/JP6043049B2/en
Publication of JP2012212712A publication Critical patent/JP2012212712A/en
Publication of JP2012212712A5 publication Critical patent/JP2012212712A5/ja
Application granted granted Critical
Publication of JP6043049B2 publication Critical patent/JP6043049B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L24/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L24/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/37001—Core members of the connector
    • H01L2224/37099—Material
    • H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/37138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/37147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/4005—Shape
    • H01L2224/4009—Loop shape
    • H01L2224/40095—Kinked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/848—Bonding techniques
    • H01L2224/84801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/848—Bonding techniques
    • H01L2224/8485—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/84909—Post-treatment of the connector or bonding area
    • H01L2224/84951—Forming additional members, e.g. for reinforcing

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Description

本発明の実施形態は、半導体装置の実装構造及び半導体装置の実装方法に関する。   FIELD Embodiments described herein relate generally to a semiconductor device mounting structure and a semiconductor device mounting method.

従来、半導体装置を配線基板上に実装する場合、半導体装置を含む半導体パッケージを配線基板上に実装してきた。   Conventionally, when a semiconductor device is mounted on a wiring board, a semiconductor package including the semiconductor device has been mounted on the wiring board.

より具体的に説明すると、半導体パッケージは、半導体装置がリードフレームのうちの１つに設けられ、他のリードフレームとワイヤボンディング等の接続部材により電気的に接続している。そして、樹脂によりリードフレームのリード端子を露出するように樹脂封止して形成されている。   More specifically, in the semiconductor package, a semiconductor device is provided on one of the lead frames, and is electrically connected to another lead frame by a connecting member such as wire bonding. And it is formed by resin sealing so as to expose the lead terminals of the lead frame with resin.

また、半導体パッケージを配線基板上に実装する際には、露出しているリード端子を配線基板の金属パッドに位置合わせして半田等により接続させて実装を行ってきた。   Further, when mounting a semiconductor package on a wiring board, the exposed lead terminals are aligned with metal pads of the wiring board and connected by soldering or the like.

特開２００６−４０９２８号JP 2006-40928 A

しかし、従来の半導体装置の実装構造では、半導体装置を有する半導体パッケージのリードフレームの厚みや、接続部材まで覆うように封止している樹脂の厚みにより、半導体パッケージが大型化してしまっていた。そのため、他の電子部品を設ける場所や高さに制約が出てくるという課題があった。また、半導体パッケージのリード端子の長さを配慮して実装面積を確保しなければならないため、他の電子部品を設ける面積を確保するために、配線基板が大型化してしまっていた。   However, in the conventional semiconductor device mounting structure, the size of the semiconductor package has been increased due to the thickness of the lead frame of the semiconductor package having the semiconductor device and the thickness of the resin sealed to cover the connection member. For this reason, there is a problem in that there are restrictions on the location and height of other electronic components. Further, since it is necessary to secure a mounting area in consideration of the length of the lead terminals of the semiconductor package, the wiring board has been enlarged in order to secure an area for providing other electronic components.

そこで本発明では、より省スペースな実装が可能な半導体装置の実装構造及び半導体装置の実装方法の提供を目的とする。   Therefore, an object of the present invention is to provide a semiconductor device mounting structure and a semiconductor device mounting method that can be mounted in a smaller space.

上記目的を達成するために、実施形態の半導体装置の実装構造は、基材上の一部に形成されている配線層と、配線層の一部である複数のパッド部を囲むように形成されているレジスト層と、を有する配線基板と、複数のパッド部の一方の上に電気的に接続するように設けられている半導体装置と、複数のパッド部の他方の上に設けられている接合材と、半導体装置の上に設けられている接合材と、複数のパッド部の他方の上に設けられている接合材と、半導体装置の上に設けられている接合材と、に接するように設けられている接続部材と、を有し、接続部材は、複数のパッド部の他方の上に設けられている接合材と接する第１の接合部材と、半導体装置の上に設けられている接合材と接する第２の接合部材と、第１の接合部材と第２の接合部材と一定の間隔を設けて形成されている第１の部材と、第１の部材を支持し、第１の接合部材と接続している第２の部材と、第１の部材を支持し、第２の接合部材と接続し、０．４ｍｍ以上１．１５ｍｍ以下の長さに設けられている第３の部材とを有することを特徴としている。
In order to achieve the above object, the mounting structure of the semiconductor device of the embodiment is formed so as to surround a wiring layer formed on a part of a substrate and a plurality of pad parts which are a part of the wiring layer. A wiring board having a resist layer, a semiconductor device provided to be electrically connected to one of the plurality of pad portions, and a junction provided on the other of the plurality of pad portions A material, a bonding material provided on the semiconductor device, a bonding material provided on the other of the plurality of pad portions, and a bonding material provided on the semiconductor device A connecting member provided on the semiconductor device, and a connecting member provided on the semiconductor device, the first connecting member contacting the bonding material provided on the other of the plurality of pad portions, and the bonding provided on the semiconductor device. Second joining member in contact with the material, first joining member and second joining A first member that is formed at a certain distance from the material, a second member that supports the first member, is connected to the first joining member, and supports the first member, A third member connected to the second bonding member and having a length of 0.4 mm or more and 1.15 mm or less is provided.

また、実施形態の半導体装置の実装方法は、請求項１乃至請求項８のいずれかに記載の
半導体装置の実装構造を形成するための半導体装置の実装方法であって、基材上の一部に
形成されている配線層と、配線層の一部である複数のパッド部を囲むように形成されてい
るレジスト層と、を有する配線基板と、複数のパッド部の一方の上に電気的に接続するよ
うに半導体装置を設ける工程と、複数のパッド部の他方の上と、半導体装置の上に接合材
を設ける工程と、複数のパッド部の他方の上に設けられている接合材と、半導体装置の上
に設けられている接合材と、に接するように接続部材を設ける工程と、を有することを特
徴としている。 Moreover, the mounting method of the semiconductor device of embodiment is described in any one of Claim 1 thru | or 8.
A semiconductor device mounting method for forming a semiconductor device mounting structure, which is formed so as to surround a wiring layer formed on a part of a substrate and a plurality of pad parts which are part of the wiring layer. A wiring substrate having a resist layer formed thereon, a step of providing a semiconductor device so as to be electrically connected to one of the plurality of pad portions, a top of the other of the plurality of pad portions, and a top of the semiconductor device A step of providing a bonding material, and a step of providing a connection member in contact with the bonding material provided on the other of the plurality of pad portions and the bonding material provided on the semiconductor device. It is characterized in that to Yes.

本発明の第１実施形態に係る半導体装置の実装構造を示す図で、（ａ）は上面図、（ｂ）は配線基板の上面図、（ｃ）は（ａ）のＡ−Ａ線に沿う断面図。1A and 1B are diagrams illustrating a mounting structure of a semiconductor device according to a first embodiment of the present invention, in which FIG. 1A is a top view, FIG. 1B is a top view of a wiring board, and FIG. Sectional drawing. 本発明の第１実施形態の応用例に係る半導体装置の実装構造を示す図で、（ａ）は上面図、（ｂ）は配線基板の上面図、（ｃ）は（ａ）のＢ−Ｂ線に沿う断面図。1A and 1B are diagrams illustrating a mounting structure of a semiconductor device according to an application example of the first embodiment of the present invention, where FIG. 1A is a top view, FIG. 1B is a top view of a wiring board, and FIG. Sectional drawing which follows a line. 本発明の第１実施形態の応用例に係る半導体装置の実装構造を示す断面図。Sectional drawing which shows the mounting structure of the semiconductor device which concerns on the application example of 1st Embodiment of this invention. 本発明の第１実施形態に係る接続部材を示す断面図。Sectional drawing which shows the connection member which concerns on 1st Embodiment of this invention. 本発明の第１実施形態に係る半導体装置の実装方法を示す断面図。Sectional drawing which shows the mounting method of the semiconductor device which concerns on 1st Embodiment of this invention. 本発明の第１実施形態の応用例に係る半導体装置の実装構造を示す図で、（ａ）は断面図、（ｂ）は接続部材の上面図、（ｃ）は（ｂ）のＸ−Ｘ線に沿う断面図。1A is a cross-sectional view of a semiconductor device mounting structure according to an application example of the first embodiment of the present invention, FIG. 2B is a top view of a connection member, and FIG. Sectional drawing which follows a line. 本発明の第１実施形態の応用例に係る半導体装置の実装構造を示す断面図。Sectional drawing which shows the mounting structure of the semiconductor device which concerns on the application example of 1st Embodiment of this invention. 本発明の第２実施形態に係る半導体装置の実装構造を示す図で、（ａ）は上面図、（ｂ）は配線基板の上面図、（ｃ）は（ａ）のＣ−Ｃ線に沿う断面図。It is a figure which shows the mounting structure of the semiconductor device which concerns on 2nd Embodiment of this invention, (a) is a top view, (b) is a top view of a wiring board, (c) follows the CC line of (a). Sectional drawing. 本発明の第２実施形態に係る接続部材を示す断面図。Sectional drawing which shows the connection member which concerns on 2nd Embodiment of this invention. 本発明の第２実施形態に係る半導体装置の実装方法を示す工程断面図。Process sectional drawing which shows the mounting method of the semiconductor device which concerns on 2nd Embodiment of this invention. 本発明の応用例に係る半導体装置の実装構造を示す断面図。Sectional drawing which shows the mounting structure of the semiconductor device which concerns on the application example of this invention. 本発明の応用例に係る半導体装置の実装構造を示す断面図。Sectional drawing which shows the mounting structure of the semiconductor device concerning the application example of this invention.

以下、本発明の実施形態に係るより省スペースな実装が可能な半導体装置の実装構造及び半導体装置の実装方法を、図面を参照して詳細に説明する。   A semiconductor device mounting structure and a semiconductor device mounting method according to an embodiment of the present invention that can be mounted in a smaller space will be described below in detail with reference to the drawings.

（第１実施形態）
まず、本発明の第１実施形態に係る半導体装置の実装構造について、図１乃至図４を参照して説明する。図１（ａ），（ｂ），（ｃ）に示すように、半導体装置の実装構造１は、配線基板２と、半導体装置３と、接続部材４とから構成されている。 (First embodiment)
First, the mounting structure of the semiconductor device according to the first embodiment of the present invention will be described with reference to FIGS. As shown in FIGS. 1A, 1 </ b> B, and 1 </ b> C, the semiconductor device mounting structure 1 includes a wiring substrate 2, a semiconductor device 3, and a connection member 4.

配線基板２は、基材５と絶縁層６、配線層７、レジスト層８とから構成されている。また、基材５の材質としては、本実施形態ではＡｌから形成されている。これは、半導体装置３に大電流を流した際に発生する熱を効率よく放熱させるために設けている。なお、本実施形態では基材５の材質はＡｌであるが、これに限られることはなく、例えばＣｕ等の放熱性の高い金属や、ＡｌＮやＳｉ３Ｎ４等の放熱性の高いセラミックから形成されていれば良い。また、セラミックから形成されている場合、絶縁性が確保出来るため、絶縁層６が不要となる。 The wiring board 2 includes a base material 5, an insulating layer 6, a wiring layer 7, and a resist layer 8. Moreover, as a material of the base material 5, in this embodiment, it is formed from Al. This is provided to efficiently dissipate heat generated when a large current is passed through the semiconductor device 3. In the present embodiment, the material of the base material 5 is Al, but is not limited to this. For example, it is made of a metal having high heat dissipation such as Cu or a ceramic having high heat dissipation such as AlN or Si 3 N 4. It only has to be formed. Moreover, when it forms from a ceramic, since insulation can be ensured, the insulating layer 6 becomes unnecessary.

絶縁層６は、基材５を覆うように設けられており、基材５と後述する配線層７との導通を防ぐために設けられている。また、絶縁層６の材質としては絶縁性の樹脂、あるいは絶縁性の樹脂内に、例えばＳｉＯ２やＡｌ２Ｏ３等の放熱性の高い粒子を含むものから形成されている。 The insulating layer 6 is provided so as to cover the substrate 5 and is provided to prevent conduction between the substrate 5 and a wiring layer 7 described later. The insulating layer 6 is made of an insulating resin or an insulating resin containing particles having high heat dissipation such as SiO 2 or Al 2 O 3 .

配線層７は、絶縁層６上の所定の位置に設けられており、配線層７の端部には、半導体装置３及び接続部材４と接続するための第１，第２のパッド部Ｐ１，Ｐ２が形成されている。また、配線層７の第１のパッド部Ｐ１の面積は、半導体装置３の第１の電極３ａの面積と同等又は大きい面積に形成されており、第２のパッド部Ｐ２の面積は、後述する接続部材４の第１の接合部材４ａの面積と同等又は大きい面積となるように形成されている。   The wiring layer 7 is provided at a predetermined position on the insulating layer 6, and the first and second pad portions P <b> 1 and P <b> 1 for connecting to the semiconductor device 3 and the connection member 4 are provided at the end of the wiring layer 7. P2 is formed. The area of the first pad portion P1 of the wiring layer 7 is formed to be equal to or larger than the area of the first electrode 3a of the semiconductor device 3, and the area of the second pad portion P2 will be described later. The connection member 4 is formed to have an area equal to or larger than the area of the first bonding member 4a.

配線層７の材質としては、本実施形態ではＣｕから形成されているが、これに限られることはなく、導電性の金属であればよい。   The material of the wiring layer 7 is made of Cu in this embodiment, but is not limited to this, and any conductive metal may be used.

レジスト層８は、配線層７の第１，第２のパッド部Ｐ１，Ｐ２から一定の間隔を設けて囲むように、絶縁層６と配線層７上に形成されている。また、レジスト層８の材質としては、絶縁性の樹脂から形成されている。なお、本実施形態では第１，第２のパッド部Ｐ１，Ｐ２から一定の間隔を設けて囲むようにレジスト層８が形成されているが、これに限られることはなく、例えば図２（ａ），（ｂ），（ｃ）に示すように、間隔を設けずに第１，第２のパッド部Ｐ１，Ｐ２を囲むように設けても良く、また、図３に示すように配線層７の一部を覆うように形成されていてもよい。   The resist layer 8 is formed on the insulating layer 6 and the wiring layer 7 so as to surround the first and second pad portions P1 and P2 of the wiring layer 7 with a certain distance therebetween. The material of the resist layer 8 is formed from an insulating resin. In the present embodiment, the resist layer 8 is formed so as to surround the first and second pad portions P1 and P2 with a certain distance therebetween. However, the present invention is not limited to this. For example, FIG. ), (B), and (c) may be provided so as to surround the first and second pad portions P1 and P2 without providing an interval, and as shown in FIG. It may be formed so as to cover a part of.

半導体装置３は、一方の面に第１の電極３ａが形成され、他方の面に第２の電極３ｂが形成されており、お互いが対向するように設けられている。また、半導体装置３は、半導体装置３の第１の電極３ａと、配線層７の第１のパッド部Ｐ１とを第１の接合材９を介して接続するように設けている。接続の為に用いている第１の接合材９の材質としては、本実施形態では半田を使用しているが、これに限られることはなく、例えばＡｇペースト等の導電性の材質であればよい。   The semiconductor device 3 is provided with a first electrode 3a formed on one surface and a second electrode 3b formed on the other surface so as to face each other. Further, the semiconductor device 3 is provided so as to connect the first electrode 3 a of the semiconductor device 3 and the first pad portion P <b> 1 of the wiring layer 7 via the first bonding material 9. As the material of the first bonding material 9 used for the connection, solder is used in the present embodiment. However, the material is not limited to this, and any conductive material such as Ag paste may be used. Good.

このように、配線基板２の第１のパッド部Ｐ１上に第１の接合材９を介して半導体装置３を設けることにより、従来の半導体パッケージのリードフレームの厚みや、接続部材まで覆うように封止している樹脂の厚みの分だけ薄くすることが可能となる。また、リードフレームのリード端子の長さを配慮して実装面積を確保する必要がないため、より省スペースに半導体装置３を実装することが可能となる。   As described above, by providing the semiconductor device 3 on the first pad portion P1 of the wiring board 2 via the first bonding material 9, the lead frame thickness of the conventional semiconductor package and the connection member are covered. It is possible to reduce the thickness by the thickness of the resin being sealed. Further, since it is not necessary to secure a mounting area in consideration of the length of the lead terminal of the lead frame, the semiconductor device 3 can be mounted in a more space-saving manner.

更に、配線基板２と半導体装置３を第１の接合材９を介して設けていることにより、大電流を流した際に半導体装置３から発生する熱を、効率よく配線基板２へと放熱することが可能となる。その結果、半導体装置３の寿命を伸ばす事ができる。   Further, by providing the wiring board 2 and the semiconductor device 3 via the first bonding material 9, heat generated from the semiconductor device 3 when a large current is passed is efficiently radiated to the wiring board 2. It becomes possible. As a result, the life of the semiconductor device 3 can be extended.

接続部材４は、第２の接合材１０と接する第１の接合部材４ａと、第３の接合材１１と接する第２の接合部材４ｂと、第１の接合部材４ａと第２の接合部材４ｂと一定の間隔を設けて形成されている第１の部材４ｃと、第１の部材４ｃを支持し、第１の接合部材４ａと接続している第２の部材４ｄと、第１の部材４ｃを支持し、第２の接合部材４ｂと接続している第３の部材４ｅとから構成されている。   The connecting member 4 includes a first bonding member 4a in contact with the second bonding material 10, a second bonding member 4b in contact with the third bonding material 11, and a first bonding member 4a and a second bonding member 4b. A first member 4c formed at a certain interval, a second member 4d supporting the first member 4c and connected to the first joining member 4a, and the first member 4c And a third member 4e connected to the second bonding member 4b.

より詳しく説明すると、接続部材４の幅Ｗは、第１，第２の接合部材４ａ，４ｂの幅とほぼ同じ幅となるように形成されており、半導体装置３の第２の電極３ｂや第２のパッド部Ｐ２に対して同じ幅、もしくは少し狭くなるように形成されている。なお、本実施形態では接続部材４の幅Ｗが第１，第２の接合部材４ａ，４ｂの幅とほぼ同じ幅となるように形成されているが、異なる幅となるように形成されていてもよい。また、第１，第２の接続部材４ａ，４ｂの幅が異なる幅となるように形成されていてもよい。   More specifically, the width W of the connection member 4 is formed to be substantially the same as the width of the first and second bonding members 4a and 4b, and the second electrode 3b and the second electrode 3b of the semiconductor device 3 are formed. It is formed to be the same width or slightly narrower than the two pad portions P2. In the present embodiment, the width W of the connection member 4 is formed to be substantially the same as the widths of the first and second bonding members 4a and 4b. However, the connection member 4 is formed to have a different width. Also good. Further, the first and second connecting members 4a and 4b may be formed to have different widths.

また、図４に示すように、接続部材４は、板状のＣｕから形成されており、厚みＴが約０．１ｍｍ〜０．３ｍｍのものを用いている。そして、第３の部材４ｅの長さＬ２が、厚みＴより０．２ｍｍ以上長くなるように形成されている。すなわち、第１の部材４ｃと第２の接合部材４ｂの厚みの合計に、更に０．２ｍｍ以上を加えた長さとなるように形成されており、本実施形態では約０．４ｍｍ以上となるように形成されている。また、第２の部材４ｄの長さＬ１は、第１の部材４ｃが配線基板２に略平行となるような高さに調整されている。   As shown in FIG. 4, the connecting member 4 is made of plate-like Cu and has a thickness T of about 0.1 mm to 0.3 mm. The length L2 of the third member 4e is formed to be longer than the thickness T by 0.2 mm or more. That is, it is formed to have a length obtained by adding 0.2 mm or more to the total thickness of the first member 4c and the second bonding member 4b, and in this embodiment, it is about 0.4 mm or more. Is formed. Further, the length L1 of the second member 4d is adjusted to such a height that the first member 4c is substantially parallel to the wiring board 2.

この様に、第３の部材４ｅの長さＬ２が約０．４ｍｍ以上のものを用いている理由としては、第３の接合材１１と第２の接合部材４ｂの接続信頼性を確保するためである。   As described above, the reason why the length L2 of the third member 4e is about 0.4 mm or more is to ensure the connection reliability between the third bonding material 11 and the second bonding member 4b. It is.

配線基板２の基材５や半導体装置３、接続部材４は、半導体装置３に大電流を流した際に発生する熱や、周囲の環境温度の差により膨張するのだが、それぞれの熱膨張係数が異なるため、接続部材４と半導体装置３を接続する第３の接合材１１や、基材５と接続部材４を接続する第２，第３の接合材１０，１１に応力がかかりやすくなる。また、この応力は、第２，第３の部材４ｄ，４ｅの長さＬ１，Ｌ２が短いほど応力が集中しやすくなり、特に第３の部材４ｅの長さＬ２を約０．４ｍｍ未満の長さに形成すると破断しやすくなる。そのため、第３の部材４ｅの長さＬ２を約０．４ｍｍ以上となるように形成することで、応力を分散させ、破断を防いでいる。   The base material 5, the semiconductor device 3, and the connection member 4 of the wiring substrate 2 expand due to the heat generated when a large current is passed through the semiconductor device 3 and the difference in ambient environmental temperature. Therefore, stress is easily applied to the third bonding material 11 that connects the connection member 4 and the semiconductor device 3 and the second and third bonding materials 10 and 11 that connect the base material 5 and the connection member 4. Further, this stress becomes more concentrated as the lengths L1 and L2 of the second and third members 4d and 4e are shorter. In particular, the length L2 of the third member 4e is less than about 0.4 mm. When it is formed, it is easy to break. Therefore, by forming the length L2 of the third member 4e to be about 0.4 mm or more, the stress is dispersed and breakage is prevented.

次に、本発明の第１実施形態に係る半導体装置の実装方法について図５を参照して説明する。   Next, a semiconductor device mounting method according to the first embodiment of the present invention will be described with reference to FIG.

まず、図５（ａ）に示すように、基材５上に絶縁層６が形成され、絶縁層６上の一部に形成されている配線層７と、第１，第２のパッド部Ｐ１，Ｐ２を一定の間隔を設けて囲むように絶縁層６と配線層７上に形成されているレジスト層８とを有する配線基板２を用意し、第１のパッド部Ｐ１と第２のパッド部Ｐ２それぞれに第１の接合材９、第２の接合材１０を設ける。また、第１，第２の接合材９，１０は、本実施形態ではスクリーン印刷により設けているが、これに限られることはなく、一括で形成する事が可能であればどの様な方法でも良い。   First, as shown in FIG. 5A, the insulating layer 6 is formed on the base material 5, the wiring layer 7 formed on a part of the insulating layer 6, and the first and second pad portions P1. , P2 are prepared to have a wiring substrate 2 having an insulating layer 6 and a resist layer 8 formed on the wiring layer 7 so as to surround the P2 with a predetermined interval, and a first pad portion P1 and a second pad portion are prepared. A first bonding material 9 and a second bonding material 10 are provided for each P2. The first and second bonding materials 9 and 10 are provided by screen printing in this embodiment, but the present invention is not limited to this, and any method can be used as long as it can be formed in a lump. good.

次に、図５（ｂ）に示すように、第１の接合材９上に、半導体装置３の第１の電極３ａが接するように設ける。そして、図５（ｃ）に示すように、半導体装置３の第２の電極３ｂ上に第３の接合材１１を設ける。本実施形態では、第３の接合材１１はディスペンサを使用して設けているが、これに限られることは無く、例えば転写等、第３の接合材１１を設けることが出来ればどの様な方法でも良い。   Next, as shown in FIG. 5B, the first electrode 3 a of the semiconductor device 3 is provided on the first bonding material 9 so as to be in contact therewith. Then, as shown in FIG. 5C, the third bonding material 11 is provided on the second electrode 3 b of the semiconductor device 3. In the present embodiment, the third bonding material 11 is provided using a dispenser. However, the present invention is not limited to this, and any method can be used as long as the third bonding material 11 can be provided, such as transfer. But it ’s okay.

その後、図５（ｄ）に示すように、接続部材４の第１の接合部材４ａと第２の接合部材４ｂとをそれぞれ第２の接合材１０と第３の接合材１１に接するように設け、加熱装置１２により加熱を行う。これにより、図１（ａ），（ｂ），（ｃ）に示すような半導体装置の実装構造１となる。   After that, as shown in FIG. 5D, the first bonding member 4a and the second bonding member 4b of the connection member 4 are provided so as to be in contact with the second bonding material 10 and the third bonding material 11, respectively. Then, heating is performed by the heating device 12. As a result, a semiconductor device mounting structure 1 as shown in FIGS. 1A, 1B, and 1C is obtained.

以上、第１実施形態の半導体装置の実装構造１によれば、配線基板２の第１のパッド部Ｐ１上に第１の接合材９を介して半導体装置３を設けている。これにより、小型化して実装することが可能となるため、より省スペースで半導体装置３を設けることができる。   As described above, according to the semiconductor device mounting structure 1 of the first embodiment, the semiconductor device 3 is provided on the first pad portion P <b> 1 of the wiring substrate 2 via the first bonding material 9. Accordingly, the semiconductor device 3 can be provided in a smaller space because it can be downsized and mounted.

更に、半導体装置３から発生する熱を、効率よく配線基板２へと放熱することが可能となり、その結果、半導体装置３の寿命を伸ばす事ができる。   Furthermore, it is possible to efficiently dissipate heat generated from the semiconductor device 3 to the wiring board 2, and as a result, the life of the semiconductor device 3 can be extended.

なお、本実施形態の半導体装置の実装構造１では、半導体チップ３に対して１つの接続部材４を設けているが、これに限られることはなく、図６（ａ）に示す半導体装置の実装構造１００のように、第１の接続部材（接続部材）４と第２の接続部材（接続部材）１０１を設けてもよい。   In the semiconductor device mounting structure 1 of the present embodiment, one connection member 4 is provided for the semiconductor chip 3, but the present invention is not limited to this, and the semiconductor device mounting shown in FIG. As in the structure 100, a first connection member (connection member) 4 and a second connection member (connection member) 101 may be provided.

すなわち、第３のパッド部Ｐ３と、半導体装置３の第３の電極３ｃが形成されている配線基板２上に、第４の接合材１０２と第５の接合材１０３がそれぞれ設けられている。そして、第２の接続部材１０１の第１の接合部材１０１ａは第４の接合材１０２と接するように設けられ、第２の接続部材１０１の第２の接合部材１０１ｂは第５の接合材１０３と接するように設けられている。   That is, the fourth bonding material 102 and the fifth bonding material 103 are respectively provided on the wiring board 2 on which the third pad portion P3 and the third electrode 3c of the semiconductor device 3 are formed. The first connecting member 101 a of the second connecting member 101 is provided so as to be in contact with the fourth bonding material 102, and the second bonding member 101 b of the second connecting member 101 is connected to the fifth bonding material 103. It is provided to touch.

また、図６（ｂ），（ｃ）に示すように、第２の接続部材（接続部材）１０１は、第１の接合部材１０１ａの幅Ｗ１と、第１，第２の部材１０１ｃ，１０１ｄの幅Ｗ３，Ｗ４が同じ幅となるように形成されており、第２の接合部材１０１ｂの幅Ｗ２より広くなるように形成されている。そして、第３の部材１０１ｅは第２の接合部材１０１ｂから第１の部材１０１ｃに向かって、次第に広くなるように形成されている。   Further, as shown in FIGS. 6B and 6C, the second connecting member (connecting member) 101 includes the width W1 of the first joining member 101a and the first and second members 101c and 101d. The widths W3 and W4 are formed to be the same width, and are formed to be wider than the width W2 of the second bonding member 101b. And the 3rd member 101e is formed so that it may become wide gradually toward the 1st member 101c from the 2nd joining member 101b.

第２の接続部材（接続部材）１０１の厚みＴは、約０．２ｍｍであり、第１の接合部材１０１ａの幅Ｗ１と第１，第２の部材１０１ｃ，１０１ｄの幅Ｗ３，Ｗ４は約２．２ｍｍ、第２の接合部材１０１ｂの幅Ｗ２が約１．５ｍｍとなるように形成されている。そして、第２の部材１０１ｄの長さＬ１が約１．４５ｍｍ、第３の部材１０１ｅの長さＬ２が約１．１５ｍｍの長さとなるように形成されている。   The thickness T of the second connecting member (connecting member) 101 is about 0.2 mm, and the width W1 of the first joining member 101a and the widths W3 and W4 of the first and second members 101c and 101d are about 2. 2 mm, and the width W2 of the second bonding member 101b is about 1.5 mm. The length L1 of the second member 101d is about 1.45 mm, and the length L2 of the third member 101e is about 1.15 mm.

また、この他に図７に示す半導体装置の実装構造２００ように、絶縁層６、配線層７、レジスト層８の一部と、半導体装置３の一部と、接続部材４の第２の接合部材４ｂ、第３の部材４ｅの一部を覆うように樹脂２０１を設けても良い。このように形成することにより、例えば低温の環境では、樹脂２０１が収縮することで、半導体装置３と接続部材４へと圧縮する力が働くため、第３の接合材１１に生じるクラックの発生を抑制することができる。その結果、接続信頼性を確保することが可能となる。   In addition to this, as in the semiconductor device mounting structure 200 shown in FIG. The resin 201 may be provided so as to cover part of the member 4b and the third member 4e. By forming in this way, for example, in a low temperature environment, the resin 201 contracts, so that a compressive force acts on the semiconductor device 3 and the connection member 4. Can be suppressed. As a result, connection reliability can be ensured.

（第２実施形態）
次に、本発明の第２実施形態に係る半導体装置の実装構造について、図８、図９を参照して説明する。本実施形態の半導体装置の実装構造２０は、絶縁材２１に配線２２が形成されている点と、接続部材２３の第２の部材２３ｄの長さＬ３と第３の部材２３ｅの長さＬ４が同じである点で第１実施形態と異なり、その他の構成部分については、同様の構成を有している。従って、図８（ａ），（ｂ），（ｃ）及び図９では、第１実施形態と異なる配線２２が形成されている絶縁材２１と、接続部材２３を示し、以下の説明においては、第１実施形態と同様の構成部分については、詳細説明を省略して異なる構成部分についてのみ説明する。 (Second Embodiment)
Next, a semiconductor device mounting structure according to a second embodiment of the present invention will be described with reference to FIGS. In the mounting structure 20 of the semiconductor device of this embodiment, the point that the wiring 22 is formed on the insulating material 21, the length L3 of the second member 23d of the connection member 23, and the length L4 of the third member 23e are Unlike the first embodiment in the same point, the other components have the same configuration. Accordingly, FIGS. 8A, 8B, 8C, and 9 show the insulating member 21 and the connecting member 23 in which the wiring 22 different from that of the first embodiment is formed. In the following description, For the same components as in the first embodiment, detailed description is omitted and only different components are described.

絶縁材２１は、第２の接合材１０と第３の接合材１１を設ける位置がほぼ同じ位置となるような厚みに形成されており、第２のパッド部Ｐ２と、第２の接合材１０とを電気的に接続させるためにビア２２ａが形成されている。また、ビア２２ａ内にはＣｕのめっきが形成されている。なお、本実施形態ではビア２２ａにＣｕのめっきが設けられているがこれに限られることはなく、導電性のペーストの充填等、導電性の金属が形成されていればよい。   The insulating material 21 is formed in such a thickness that the positions where the second bonding material 10 and the third bonding material 11 are provided are substantially the same, and the second pad portion P2 and the second bonding material 10 are provided. A via 22a is formed to electrically connect the two. Also, Cu plating is formed in the via 22a. In the present embodiment, Cu plating is provided on the via 22a, but the present invention is not limited to this, and it is sufficient that a conductive metal such as a conductive paste is formed.

また、絶縁材２１は、第１のパッド部Ｐ１から一定の間隔を設けて囲むように、絶縁層６と配線層７上に形成されている。そのため、第１のパッド部Ｐ１と接続する配線層７の一部が露出する。なお、本実施形態では、第１のパッド部Ｐ１から一定の間隔を設けて囲むように絶縁材２１を設けているが、これに限られることはなく、一定の間隔無く囲むように絶縁材２１を設けてもよく、また、配線層７の一部を覆うように形成されていてもよい。   In addition, the insulating material 21 is formed on the insulating layer 6 and the wiring layer 7 so as to surround the first pad portion P1 with a certain distance. Therefore, a part of the wiring layer 7 connected to the first pad portion P1 is exposed. In the present embodiment, the insulating material 21 is provided so as to surround the first pad portion P1 with a certain interval. However, the insulating material 21 is not limited to this and is surrounded without a certain interval. Or may be formed so as to cover a part of the wiring layer 7.

このように絶縁材２１を、第２の接合材１０と第３の接合材１１を設ける位置がほぼ同じとなるような厚みに形成することにより、例えばスクリーン印刷等で第２，第３の接合材１０，１１を一括で設けることができるようになる。そして、第３の接合材１１の供給量を安定化させることができる。   In this way, the insulating material 21 is formed in such a thickness that the positions where the second bonding material 10 and the third bonding material 11 are provided are substantially the same, so that the second and third bonding are performed by, for example, screen printing or the like. The materials 10 and 11 can be provided collectively. Then, the supply amount of the third bonding material 11 can be stabilized.

これは、例えばディスペンサ等により部分的に第２，第３の接合材１０，１１を供給する場合、第１の接合材９を供給する場合に比べて供給量が少ないため、バラつきが生じやすくなる。そのため、高い精度で第２，第３の接合材１０，１１を設けなければならない。本実施形態の絶縁材２１を形成することにより、例えばスクリーン印刷等のバラつきの少ない方法で第２，第３の接合材１０，１１を設けることができるので、供給量を安定化させ、半導体装置３と接続部材４の接続信頼性を更に確保することが可能となる。   This is because, for example, when the second and third bonding materials 10 and 11 are partially supplied by a dispenser or the like, the supply amount is small compared to the case where the first bonding material 9 is supplied, so that variation tends to occur. . Therefore, the second and third bonding materials 10 and 11 must be provided with high accuracy. By forming the insulating material 21 of the present embodiment, the second and third bonding materials 10 and 11 can be provided by a method with little variation such as screen printing, so that the supply amount can be stabilized and the semiconductor device can be provided. 3 and the connection member 4 can be further ensured in connection reliability.

接続部材２３は、第２の接合材１０と接する第１の接合部材２３ａと、第３の接合材１１と接する第２の接合部材２３ｂと、第１の接合部材２３ａと第２の接合部材２３ｂと一定の間隔を設けて形成されている第１の部材２３ｃと、第１の部材２３ｃを支持し、第１の接合部材２３ａと接続している第２の部材２３ｄと、第１の部材２３ｃを支持し、第２の接合部材２３ｂと接続している第３の部材２３ｅとから構成されている。   The connection member 23 includes a first bonding member 23a that is in contact with the second bonding material 10, a second bonding member 23b that is in contact with the third bonding material 11, and a first bonding member 23a and a second bonding member 23b. A first member 23c formed at a certain interval, a second member 23d supporting the first member 23c and connected to the first joining member 23a, and the first member 23c. And a third member 23e connected to the second bonding member 23b.

また、接続部材２３は、絶縁材２１の厚みの変更に伴い、接続部材２３の第１の部材２３ｃが配線基板２に対して略平行となるようにするため、図９に示すように第２の部材２３ｄの長さＬ３と第３の部材２３ｅの長さＬ４とがほぼ同じとなるように形成されている。   Further, the connection member 23 has a second shape as shown in FIG. 9 in order to make the first member 23c of the connection member 23 substantially parallel to the wiring board 2 as the thickness of the insulating material 21 is changed. The length L3 of the member 23d and the length L4 of the third member 23e are substantially the same.

次に、本発明の第２実施形態に係る半導体装置の実装方法について図１０を参照して説明する。   Next, a semiconductor device mounting method according to the second embodiment of the present invention will be described with reference to FIG.

まず、図１０（ａ）に示すように、第１のパッド部Ｐ１上に第１の接合材９を設ける。より詳しく説明すると、基材５上に絶縁層６、第１，第２のパッド部Ｐ１，Ｐ２を含む配線層７、第２のパッド部Ｐ２と電気的に接続可能に設けられた配線２２が形成された絶縁材２１から形成されている配線基板２を用意し、第１のパッド部Ｐ１上に例えばディスペンサ等を用いて第１の接合材９を設ける。   First, as shown in FIG. 10A, the first bonding material 9 is provided on the first pad portion P1. More specifically, the insulating layer 6, the wiring layer 7 including the first and second pad portions P1 and P2, and the wiring 22 provided so as to be electrically connected to the second pad portion P2 on the base material 5 are provided. The wiring board 2 formed from the formed insulating material 21 is prepared, and the first bonding material 9 is provided on the first pad portion P1 using, for example, a dispenser.

なお、本実施形態では、第１の接合材９をディスペンサにて設けているが、これに限られることはなく、設ける事が可能であればどのような方法でもよい。   In the present embodiment, the first bonding material 9 is provided by a dispenser. However, the present invention is not limited to this, and any method may be used as long as it can be provided.

次に、図１０（ｂ）に示すように、第１の接合材９上に、半導体装置３の第１の電極３ａが接するように設ける。そして、図１０（ｃ）に示すように、半導体装置３の第２の電極３ｂと配線２２上に第２，第３の接合材１０，１１を設ける。本実施形態では、第２，第３の接合材１０，１１をスクリーン印刷により一括で設けているが、これに限られることは無く、第２，第３の接合材１０，１１を安定的に供給することが出来ればどの様な方法でも良い。また、第１の接合材９上に半導体装置３を設けた後、半導体装置３の第２の電極３ｂと配線２２に第２，第３の接合材１０，１１を設けているが、半導体装置３と第１の接合材９を接合させるために、リフロー等により加熱する工程を入れてもよい。これにより、第２，第３の接合材１０，１１を設ける際に、半導体装置３の位置ズレを抑制することが可能となる。   Next, as shown in FIG. 10B, the first electrode 3 a of the semiconductor device 3 is provided on the first bonding material 9 so as to be in contact therewith. Then, as shown in FIG. 10C, second and third bonding materials 10 and 11 are provided on the second electrode 3 b and the wiring 22 of the semiconductor device 3. In this embodiment, the second and third bonding materials 10 and 11 are collectively provided by screen printing. However, the present invention is not limited to this, and the second and third bonding materials 10 and 11 can be stably provided. Any method can be used as long as it can be supplied. Further, after the semiconductor device 3 is provided on the first bonding material 9, the second and third bonding materials 10 and 11 are provided on the second electrode 3 b and the wiring 22 of the semiconductor device 3. In order to join 3 and the first joining material 9, a step of heating by reflow or the like may be included. Thereby, when the second and third bonding materials 10 and 11 are provided, it is possible to suppress the positional deviation of the semiconductor device 3.

その後、図１０（ｄ）に示すように、接続部材２３の第１の接合部材２３ａと第２の接合部材２３ｂとをそれぞれ第２の接合材１０と第３の接合材１１に接するように設け、加熱装置１２により加熱を行う。これにより、図８（ａ），（ｂ），（ｃ）に示すような半導体装置の実装構造２０となる。   Thereafter, as shown in FIG. 10 (d), the first bonding member 23a and the second bonding member 23b of the connection member 23 are provided so as to be in contact with the second bonding material 10 and the third bonding material 11, respectively. Then, heating is performed by the heating device 12. As a result, a semiconductor device mounting structure 20 as shown in FIGS. 8A, 8B, and 8C is obtained.

以上、第２実施形態の半導体装置の実装構造２０によれば、配線基板２の第１のパッド部Ｐ１上に第１の接合材９を介して半導体装置３を設けることにより、小型化して実装することが可能となるため、より省スペースで半導体装置３を設けることができる。   As described above, according to the semiconductor device mounting structure 20 of the second embodiment, the semiconductor device 3 is provided on the first pad portion P1 of the wiring board 2 via the first bonding material 9, thereby reducing the size and mounting. Therefore, the semiconductor device 3 can be provided in a smaller space.

また、半導体装置３から発生する熱を、効率よく配線基板２へと放熱することが可能となり、その結果、半導体装置３の寿命を伸ばす事ができる。   Further, the heat generated from the semiconductor device 3 can be efficiently radiated to the wiring board 2, and as a result, the life of the semiconductor device 3 can be extended.

更に、絶縁材２１を、第２の接合材１０と第３の接合材１１を設ける位置がほぼ同じとなるような厚みに形成することにより、第３の接合材１１の供給量を安定化させることができ、接続部材２３との接続信頼性を確保することが可能となる。   Furthermore, the supply amount of the third bonding material 11 is stabilized by forming the insulating material 21 so that the position where the second bonding material 10 and the third bonding material 11 are provided is substantially the same. Therefore, it is possible to ensure connection reliability with the connection member 23.

本発明のいくつかの実施形態を説明したが、これらの実施形態は、例として提示したものであり、発明の範囲を限定することは意図していない。これら新規な実施形態は、その他のさまざまな形態で実施されることが可能であり、発明の要旨を逸脱しない範囲で、種々の省略、置き換え、変更を行うことができる。これら実施形態やその変形は、発明の範囲や要旨に含まれるとともに、特許請求の範囲に記載された発明とその均等の範囲に含まれる。   Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

例えば、図１１に示す半導体装置の実装構造３０のように、接続部材３１が板状形状であってもよい。より詳しく説明すると、第２の接合材１０と接する第１の接合部材３１ａと、第３の接合材１１と接する領域である第２の接合部材３１ｂと、第１の接合部材３１ａと第２の接合部材３１ｂと同じ高さで接続している接合部材接続部３１ｃとで構成されている。この場合、接続部材３１を設けるためのスペースを減少させることが出来るため、更に小スペースで半導体装置３を設けることができる。   For example, the connection member 31 may have a plate shape as in the semiconductor device mounting structure 30 shown in FIG. More specifically, the first bonding member 31a in contact with the second bonding material 10, the second bonding member 31b that is a region in contact with the third bonding material 11, the first bonding member 31a and the second bonding material. It is comprised by the joining member connection part 31c connected with the same height as the joining member 31b. In this case, since the space for providing the connection member 31 can be reduced, the semiconductor device 3 can be provided in a smaller space.

また、図１１のような構造にすることで、図１２（ａ）に示すような半導体装置の実装構造４０を形成することが可能となる。この半導体装置の実装構造４０は、例えばＣｕやＡｌ等の金属から形成されている基材４１上に絶縁層４２を設け、更にその上に接続部材３１と、接続部材３１の第１，第２の接合部材３１ａ，３１ｂを囲み、露出するように接続部材３１と絶縁層４２上に設けられたレジスト層４３が形成された接続部材付配線基板４４を用いて、第２，第３の接合材１０，１１と第１，第２の接合部材３１ａ，３１ｂとが接するような構造となっている。   Further, by adopting the structure as shown in FIG. 11, it is possible to form the semiconductor device mounting structure 40 as shown in FIG. In this semiconductor device mounting structure 40, for example, an insulating layer 42 is provided on a base material 41 made of a metal such as Cu or Al, and a connection member 31 and first and second connection members 31 are provided thereon. The connection member 31 and the wiring board 44 with the connection member on which the resist layer 43 provided on the insulating layer 42 is formed so as to surround and expose the connection members 31a and 31b are used as the second and third bonding materials. 10, 11 and the first and second joining members 31a and 31b are in contact with each other.

なお、基材４１は、例えばＣｕやＡｌ等の金属から形成されたものを用いているが、これに限られることはなく、ＡｌＮやＳｉ３Ｎ４等の放熱性の高いセラミックから形成されていても良い。また、セラミックから形成されている場合、絶縁性が確保出来るため、絶縁層４２が不要となる。 Incidentally, the substrate 41 is, for example, are used those formed from a metal such as Cu or Al, it is not limited thereto, are formed from a high heat radiation property such as AlN and Si 3 N 4 ceramic May be. Further, when formed from ceramic, the insulating layer 42 becomes unnecessary because the insulating property can be ensured.

これにより、省スペースな実装だけでなく、半導体装置３から放熱される熱を接続部材付配線基板４４から効率よく放熱させることが出来る。   Thereby, not only the space-saving mounting, but also the heat radiated from the semiconductor device 3 can be efficiently radiated from the wiring board with connection member 44.

また、図１２（ｂ）に示すように、配線基板２の絶縁材２１の一部と、向かい合う接続部材付配線基板４４のレジスト層４３の一部にダミー配線Ｄ１を形成し、ダミー接続部材Ｄ２を介して接続する構造にしてもよい。これにより、接続部材３１と半導体装置３の接続信頼性を確保することができる。   Further, as shown in FIG. 12B, a dummy wiring D1 is formed on a part of the insulating material 21 of the wiring board 2 and a part of the resist layer 43 of the wiring board 44 with the connecting member facing each other, and the dummy connecting member D2 is formed. You may make it the structure connected through this. Thereby, the connection reliability of the connection member 31 and the semiconductor device 3 can be ensured.

１，２０，３０，４０，１００，２００…半導体装置の実装構造
２…配線基板
３…半導体装置
３ａ…第１の電極
３ｂ…第２の電極
３ｃ…第３の電極
４，２３，３１，１０１…接続部材
４ａ，２３ａ，３１ａ，１０１ａ…第１の接合部材
４ｂ，２３ｂ，３１ｂ，１０１ｂ…第２の接合部材
４ｃ，２３ｃ…第１の部材
４ｄ，２３ｄ…第２の部材
４ｅ，２３ｅ…第３の部材
３１ｃ…接合部材接続部
５，４１…基材
６，４２…絶縁層
７…配線層
８，４３…レジスト層
９…第１の接合材
１０…第２の接合材
１１…第３の接合材
１２…加熱装置
２１…絶縁材
２２…配線
２２ａ…ビア
４４…接続部材付配線基板
１０２…第４の接合材
１０３…第５の接合材
２０１…樹脂
Ｐ１…第１のパッド部
Ｐ２…第２のパッド部
Ｐ３…第３のパッド部
Ｄ１…ダミー配線
Ｄ２…ダミー接続部材
Ｗ…幅
Ｔ…厚み
Ｌ１，Ｌ３…第２の部材の長さ
Ｌ２，Ｌ４…第３の部材の長さ DESCRIPTION OF SYMBOLS 1,20,30,40,100,200 ... Mounting structure 2 of semiconductor device ... Wiring board 3 ... Semiconductor device 3a ... First electrode 3b ... Second electrode 3c ... Third electrode 4, 23, 31, 101 ... connecting members 4a, 23a, 31a, 101a ... first joining members 4b, 23b, 31b, 101b ... second joining members 4c, 23c ... first members 4d, 23d ... second members 4e, 23e ... first 3 members 31c ... joining member connecting portions 5, 41 ... base material 6, 42 ... insulating layer 7 ... wiring layers 8, 43 ... resist layer 9 ... first joining material 10 ... second joining material 11 ... third Bonding material 12 ... heating device 21 ... insulating material 22 ... wiring 22a ... via 44 ... wiring substrate with connecting member 102 ... fourth bonding material 103 ... fifth bonding material 201 ... resin P1 ... first pad portion P2 ... first 2 pad part P3 ... 3rd pad part D1 ... dummy wiring D2 The length of the dummy connecting member W ... width T ... thickness L1, L3 ... the length of the second member L2, L4 ... third member

Claims (10)

基材上の一部に形成されている配線層と、前記配線層の一部である複数のパッド部を囲むように形成されているレジスト層と、を有する配線基板と、
前記複数のパッド部の一方の上に電気的に接続するように設けられている半導体装置と、
前記複数のパッド部の他方の上に設けられている接合材と、
前記半導体装置の上に設けられている接合材と、
前記複数のパッド部の他方の上に設けられている接合材と、前記半導体装置の上に設けられている接合材と、に接するように設けられている接続部材と、
を有し、
前記接続部材は、前記複数のパッド部の他方の上に設けられている接合材と接する第１の接合部材と、
前記半導体装置の上に設けられている接合材と接する第２の接合部材と、
前記第１の接合部材と前記第２の接合部材と一定の間隔を設けて形成されている第１の部材と、
前記第１の部材を支持し、前記第１の接合部材と接続している第２の部材と、
前記第１の部材を支持し、前記第２の接合部材と接続し、０．４ｍｍ以上１．１５ｍｍ以下の長さに設けられている第３の部材と、
を有することを特徴とする半導体装置の実装構造。 A wiring board having a wiring layer formed on a part of the substrate, and a resist layer formed so as to surround a plurality of pad portions that are a part of the wiring layer;
A semiconductor device provided to be electrically connected to one of the plurality of pad portions;
A bonding material provided on the other of the plurality of pad portions;
A bonding material provided on the semiconductor device;
A connecting member provided to be in contact with a bonding material provided on the other of the plurality of pad portions and a bonding material provided on the semiconductor device;
Have
The connection member includes a first bonding member that contacts a bonding material provided on the other of the plurality of pad portions;
A second bonding member in contact with a bonding material provided on the semiconductor device;
A first member formed at a certain interval from the first joining member and the second joining member;
A second member supporting the first member and connected to the first joining member;
A third member that supports the first member, is connected to the second joining member, and is provided with a length of 0.4 mm or more and 1.15 mm or less;
A mounting structure of a semiconductor device, comprising: 前記接続部材は、板状であることを特徴とする請求項１に記載の半導体装置の実装構造。   The semiconductor device mounting structure according to claim 1, wherein the connection member has a plate shape. 前記第３の部材の長さは、前記第１の部材と前記第２の接合部材の厚みの合計よりも０．２ｍｍ以上長いことを特徴とする請求項１又は請求項２に記載の半導体装置の実装構造。   The length of the said 3rd member is 0.2 mm or more longer than the sum total of the thickness of the said 1st member and the said 2nd joining member, The semiconductor device of Claim 1 or Claim 2 characterized by the above-mentioned. Implementation structure. 前記第１の部材は前記基材と略平行となるように設けられていることを特徴とする請求項１乃至請求項３に記載の半導体装置の実装構造。   4. The semiconductor device mounting structure according to claim 1, wherein the first member is provided so as to be substantially parallel to the base material. 5. 前記第２の部材の長さと前記第３の部材の長さは異なることを特徴とする請求項１乃至請求項４に記載の半導体装置の実装構造。   The semiconductor device mounting structure according to claim 1, wherein a length of the second member is different from a length of the third member. 前記第２の接合部材の厚みは０．１〜０．３ｍｍであることを特徴とする請求項１乃至請求項５に記載の半導体装置の実装構造。   The semiconductor device mounting structure according to claim 1, wherein the thickness of the second bonding member is 0.1 to 0.3 mm. 前記第３の部材は、前記接続部材の高さ方向に対して傾斜するように前記第１の部材を支持していることを特徴とする請求項１乃至請求項６に記載の半導体装置の実装構造。   The semiconductor device mounting according to claim 1, wherein the third member supports the first member so as to be inclined with respect to a height direction of the connection member. Construction. 前記第２の接合部材と前記第３の部材との内角は９０°より大きい角度であることを特徴とする請求項１乃至請求項７に記載の半導体装置の実装構造。   The semiconductor device mounting structure according to claim 1, wherein an inner angle between the second bonding member and the third member is an angle larger than 90 °. 請求項１乃至請求項８のいずれかに記載の半導体装置の実装構造を形成するための半導体装置の実装方法であって、
基材上の一部に形成されている配線層と、前記配線層の一部である複数のパッド部を囲むように形成されているレジスト層と、を有する配線基板と、前記複数のパッド部の一方の上に電気的に接続するように半導体装置を設ける工程と、
前記複数のパッド部の他方の上と、前記半導体装置の上に接合材を設ける工程と、
前記複数のパッド部の他方の上に設けられている接合材と、前記半導体装置の上に設けられている接合材と、に接するように接続部材を設ける工程と、
を有することを特徴とする半導体装置の実装方法。 A semiconductor device mounting method for forming a semiconductor device mounting structure according to any one of claims 1 to 8,
A wiring board having a wiring layer formed on a part of a substrate, and a resist layer formed so as to surround a plurality of pad parts that are a part of the wiring layer, and the plurality of pad parts Providing a semiconductor device so as to be electrically connected on one of
Providing a bonding material on the other of the plurality of pad portions and on the semiconductor device;
Providing a connecting member so as to contact the bonding material provided on the other of the plurality of pad portions and the bonding material provided on the semiconductor device;
A method for mounting a semiconductor device, comprising: 前記第１の部材を前記基材と略平行となるように設ける工程を有することを特徴とする請求項９に記載の半導体装置の実装方法。   The semiconductor device mounting method according to claim 9, further comprising a step of providing the first member so as to be substantially parallel to the base material.
JP2011076410A 2011-03-30 2011-03-30 Semiconductor device mounting structure and semiconductor device mounting method Active JP6043049B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2011076410A JP6043049B2 (en) 2011-03-30 2011-03-30 Semiconductor device mounting structure and semiconductor device mounting method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2011076410A JP6043049B2 (en) 2011-03-30 2011-03-30 Semiconductor device mounting structure and semiconductor device mounting method

Publications (3)

Publication Number Publication Date
JP2012212712A JP2012212712A (en) 2012-11-01
JP2012212712A5 JP2012212712A5 (en) 2014-04-24
JP6043049B2 true JP6043049B2 (en) 2016-12-14

Family

ID=47266464

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2011076410A Active JP6043049B2 (en) 2011-03-30 2011-03-30 Semiconductor device mounting structure and semiconductor device mounting method

Country Status (1)

Country Link
JP (1) JP6043049B2 (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2858100B1 (en) * 2012-05-29 2020-06-10 NSK Ltd. Semiconductor module and production method for same
CN103918076B (en) * 2012-11-05 2016-11-16 日本精工株式会社 Semiconductor module
US9609775B2 (en) 2012-11-05 2017-03-28 Nsk Ltd. Semiconductor module
CN103918066B (en) 2012-11-05 2016-08-24 日本精工株式会社 Semiconductor module
CN108565254B (en) * 2013-10-21 2021-08-24 日本精工株式会社 Semiconductor module
JP6566634B2 (en) * 2014-12-09 2019-08-28 国立大学法人大阪大学 Junction structure and manufacturing method of junction structure

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4550503B2 (en) * 2004-07-22 2010-09-22 ルネサスエレクトロニクス株式会社 Semiconductor device
JP2006344652A (en) * 2005-06-07 2006-12-21 Toshiba Components Co Ltd Semiconductor device and method of mounting semiconductor component
JP5076440B2 (en) * 2006-10-16 2012-11-21 富士電機株式会社 Semiconductor device and manufacturing method of semiconductor device
JP2010050364A (en) * 2008-08-25 2010-03-04 Hitachi Ltd Semiconductor device
JP5388661B2 (en) * 2009-04-03 2014-01-15 三菱電機株式会社 Semiconductor device and manufacturing method thereof
JP2012212713A (en) * 2011-03-30 2012-11-01 Toshiba Corp Mounting structure of semiconductor device
JP2012217213A (en) * 2012-08-01 2012-11-08 Toshiba Corp Image processing device and image processing method

Also Published As

Publication number Publication date
JP2012212712A (en) 2012-11-01

Similar Documents

Publication Publication Date Title
US6972479B2 (en) Package with stacked substrates
JP6043049B2 (en) Semiconductor device mounting structure and semiconductor device mounting method
JP2012212713A (en) Mounting structure of semiconductor device
JP5776701B2 (en) Semiconductor device and method for manufacturing semiconductor device
JP6012533B2 (en) Power semiconductor device
JP2006196709A (en) Semiconductor device and manufacturing method thereof
JP5589950B2 (en) Electronic equipment
JP2007142097A (en) Semiconductor device
JP5214121B2 (en) Light emitting device
JP2008085002A (en) Semiconductor device and its manufacturing method
JP2006261293A (en) Semiconductor device and insulation substrate for use thereof
JP4556732B2 (en) Semiconductor device and manufacturing method thereof
CN211182196U (en) Lead frame, semiconductor device, and circuit device
JP2007012718A (en) Electronic component housing package and electronic device
JP7310161B2 (en) Semiconductor device and its manufacturing method
JP2009164511A (en) Semiconductor device and method of manufacturing the same
JP5217013B2 (en) Power conversion device and manufacturing method thereof
JP5145168B2 (en) Semiconductor device
JP5124329B2 (en) Semiconductor device
JP5217014B2 (en) Power conversion device and manufacturing method thereof
CN110931448A (en) Lead frame, semiconductor device, and circuit device
JP2009158825A (en) Semiconductor device
JP2007201251A (en) Semiconductor package, and manufacturing method thereof
JP2006344652A (en) Semiconductor device and method of mounting semiconductor component
JP2007305911A (en) Semiconductor package and semiconductor module

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20140310

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20140310

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20150213

RD02 Notification of acceptance of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7422

Effective date: 20150216

RD04 Notification of resignation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7424

Effective date: 20150218

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20150219

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20150414

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20151127

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20160126

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20160729

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20160920

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20161014

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20161111

R151 Written notification of patent or utility model registration

Ref document number: 6043049

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R151