JP2010050364A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP2010050364A
JP2010050364A JP2008214779A JP2008214779A JP2010050364A JP 2010050364 A JP2010050364 A JP 2010050364A JP 2008214779 A JP2008214779 A JP 2008214779A JP 2008214779 A JP2008214779 A JP 2008214779A JP 2010050364 A JP2010050364 A JP 2010050364A
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chip
lead
semiconductor device
solder
circuit layer
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Koji Sasaki
康二 佐々木
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Hitachi Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a highly reliable semiconductor device in which fatigue cracks can not be easily generated on a solder bonding layer for bonding a semiconductor chip and a lead even due to a heat cycle in the real use of a power semiconductor device. <P>SOLUTION: The semiconductor device includes the semiconductor chip 104, a circuit layer 106 and a plate-like lead 101 for electrically connecting the semiconductor chip 104 and the circuit layer 106. The lead 101 includes a lead body composed of a chip side bonding portion 101a, a circuit layer side bonding portion 101b, erected portions 101c, and a crossing portion 101d, and a bent portion 101e formed on the peripheral edge of at least the chip side bonding portion 101a, and is constituted so that the chip side bonding portion 101a of the lead body is bonded to the semiconductor chip 104 through a conductive bonding layer 103, the circuit layer side bonding part 101b is bonded to the circuit layer 106 through the conductive bonding layer, and the bent portion 101e and the erected portions 101c are bent from the bonding surface of the chip side bonding portion 101a in a direction reverse to the semiconductor chip 104. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

本発明は、半導体装置に係わり、特にモータ等の電気機器の制御に用いられるパワー半導体装置に関するものである。 The present invention relates to a semiconductor device, and more particularly to a power semiconductor device used for controlling an electric device such as a motor.

パワー半導体装置は、モータ等の電気機器を制御するために用いられる大電力の半導体装置である。近年、省エネ・環境負荷低減の要求によりモータ制御におけるインバータ制御が普及し、ハイブリッド自動車市場等の拡大も合わせて、パワー半導体装置の需要が急伸している。また、モータ制御のさらなる効率化を目的として、パワー半導体装置の使用環境は高電圧・大電流化（大電力化）がさらに進展し、要求される使用温度条件なども益々厳しくなってきている。このような背景の下、パワー半導体装置にとっては信頼性の低下を引き起こさないことが重要であり、特に、電子部材同士の接合層（例えば、はんだ接合層）の信頼性確保が重要な課題となっている。   The power semiconductor device is a high-power semiconductor device used for controlling electric equipment such as a motor. In recent years, inverter control in motor control has become widespread due to demands for energy saving and environmental load reduction, and the demand for power semiconductor devices has rapidly increased along with the expansion of the hybrid vehicle market and the like. In addition, for the purpose of further improving the efficiency of motor control, the use environment of power semiconductor devices has further increased with higher voltage and higher current (higher power), and the required operating temperature conditions have become increasingly severe. Under such a background, it is important for power semiconductor devices not to cause a decrease in reliability, and in particular, ensuring the reliability of a bonding layer (for example, a solder bonding layer) between electronic members is an important issue. ing.

上述したように、パワー半導体装置は高電圧・大電流で動作させられることが多いため、動作中は半導体チップなどに大量のジュール熱が発生する。一方、停止中は環境温度まで冷却されることになる。すなわち、パワー半導体装置は各種半導体装置の中で動作・停止間の温度差が特に大きいという事情がある。その結果、半導体チップ・リード・半導体チップとリードを接合するはんだ接合層には、大きな熱応力が繰返し生じる。この繰返しの熱応力は、機械的強度が比較的低いはんだ接合層に疲労亀裂を発生させる要因となりやすい。はんだ接合層での疲労亀裂の発生・進展（すなわち疲労破壊）は、半導体チップにおける導電障害や放熱障害を引き起こし、パワー半導体装置の機能停止を誘発する恐れがある。   As described above, since power semiconductor devices are often operated at a high voltage and a large current, a large amount of Joule heat is generated in the semiconductor chip or the like during operation. On the other hand, it is cooled to the environmental temperature during the stop. That is, power semiconductor devices have a particularly large temperature difference between operation and stop among various semiconductor devices. As a result, a large thermal stress is repeatedly generated in the semiconductor chip / lead / solder bonding layer for bonding the semiconductor chip and the lead. This repeated thermal stress tends to cause a fatigue crack in the solder joint layer having a relatively low mechanical strength. The occurrence / progress of fatigue cracks (that is, fatigue failure) in the solder joint layer may cause a conduction failure or a heat radiation failure in the semiconductor chip, and may cause the power semiconductor device to stop functioning.

例えば、半導体チップとリードを接合するはんだ接合層の疲労亀裂は、半導体チップの主材質であるシリコン（線膨張係数は約３×10−６℃−１）とリードの主材質である銅（線膨張係数は約17×10−６℃−１）の熱膨張差に起因する剪断応力が原因で発生すると考えられている。また、この剪断応力ははんだ接合層の外周部分に集中するため、はんだ接合層の疲労亀裂は、外周部分から中央に向かって進展することが一般的である。したがって、はんだ接合層の疲労破壊を防止するためには、電子部材の熱膨張差に起因する剪断応力をいかに低減するかが肝要である。 For example, fatigue cracks in a solder joint layer that joins a semiconductor chip and a lead are caused by silicon (linear expansion coefficient is about 3 × 10 −6 ° C. −1 ) which is the main material of the semiconductor chip and copper (wire The expansion coefficient is considered to be caused by shear stress due to a thermal expansion difference of about 17 × 10 −6 ° C. −1 ). Further, since this shear stress is concentrated on the outer peripheral portion of the solder joint layer, the fatigue crack of the solder joint layer generally progresses from the outer peripheral portion toward the center. Therefore, in order to prevent fatigue failure of the solder joint layer, it is important how to reduce the shear stress due to the thermal expansion difference of the electronic member.

上記の課題を解決するため、例えば特許文献１の大電力半導体デバイスには、半導体チップ上の電極バッドとリードとの間に多層構造の応力緩衝部材を挿入し、半導体チップとリードの接合界面に発生する熱応力を低減させる構造が提案されている。また、例えば特許文献２の半導体装置には、半導体素子の外部電極端部と接合する引き出し電極（インナーリード）端部に、溝を設けて引き出し電極端部を複数個に分割することにより、半田接合時の半田溜りの形成を防止するとともに、半田に掛かる熱応力を分散させて半田ひずみを軽減する構造が提案されている。   In order to solve the above-described problem, for example, in a high power semiconductor device of Patent Document 1, a multilayer structure stress buffer member is inserted between an electrode pad on a semiconductor chip and a lead, and the junction interface between the semiconductor chip and the lead is inserted. A structure for reducing the generated thermal stress has been proposed. Further, for example, in the semiconductor device of Patent Document 2, a groove is provided in an end portion of an extraction electrode (inner lead) joined to an end portion of an external electrode of a semiconductor element to divide the extraction electrode end portion into a plurality of parts. A structure has been proposed in which the formation of a solder pool at the time of bonding is prevented and the thermal stress applied to the solder is dispersed to reduce solder strain.

特開平９−６４２５８号公報Japanese Patent Laid-Open No. 9-64258 特開２００４−２２８４６１号公報JP 2004-228461 A

しかしながら、特許文献１に記載の大電力半導体デバイスは、前記課題を解決するにあたり部材点数や組み立て工程が増加することでコスト高の要因になりやすく、低コスト化の観点で課題を残していた。また、特許文献２に記載の半導体装置は、その主たる目的が半導体素子と引き出し電極の半田接合時に、その接合箇所において半田溜り部の形成を防止することであるから、熱サイクルに起因する半田接合層の疲労破壊の防止に関してはその効果が不十分な場合があった。   However, the high-power semiconductor device described in Patent Document 1 tends to be a factor of high cost due to an increase in the number of members and assembly steps in solving the above-described problems, and there remains a problem in terms of cost reduction. In addition, since the main purpose of the semiconductor device described in Patent Document 2 is to prevent the formation of a solder pool portion at the joining portion when the semiconductor element and the extraction electrode are solder-joined, solder joining caused by a thermal cycle is performed. In some cases, the effect of preventing fatigue fracture of the layer is insufficient.

従って、本発明の目的は、パワー半導体装置における実使用時の熱サイクルによっても半導体チップとリードとを接合するはんだ接合層に疲労亀裂が発生しにくく、信頼性の高い半導体装置を提供することにある。   Accordingly, an object of the present invention is to provide a highly reliable semiconductor device in which fatigue cracks are unlikely to occur in a solder joint layer that joins a semiconductor chip and a lead even by a thermal cycle in actual use in a power semiconductor device. is there.

本発明は、上記目的を達成するため、半導体チップと回路層とそれらを電気的に接続する板状のリードとを有する半導体装置であって、
前記リードは、チップ側接合部と回路層側接合部と立ち上がり部と渡り部とからなるリード本体と、少なくとも前記チップ側接合部の周縁に形成された折り返し部とを有し、
前記リード本体の前記チップ側接合部が導電性の接合層を介して前記半導体チップに接合され、前記回路層側接合部が導電性の接合層を介して前記回路層に接合されており、
前記折り返し部と前記立ち上がり部とが前記チップ側接合部の接合面に対して前記半導体チップと反対方向に折り返されていることを特徴とする半導体装置を提供する。 In order to achieve the above object, the present invention is a semiconductor device having a semiconductor chip, a circuit layer, and plate-like leads that electrically connect them,
The lead has a lead body composed of a chip-side bonding portion, a circuit layer-side bonding portion, a rising portion, and a crossing portion, and a folded portion formed at least on the periphery of the chip-side bonding portion,
The chip-side bonding portion of the lead body is bonded to the semiconductor chip via a conductive bonding layer, and the circuit layer-side bonding portion is bonded to the circuit layer via a conductive bonding layer;
The semiconductor device is characterized in that the folded portion and the rising portion are folded in a direction opposite to the semiconductor chip with respect to a bonding surface of the chip side bonding portion.

また、本発明は、上記目的を達成するため、上記の本発明に係る半導体装置において、以下のような改良や変更を加えることができる。
（１）前記チップ側接合部の厚さが１mm以下である。
（２）前記折り返し部の高さが前記チップ側接合部の厚さの２倍以上である。
（３）前記折り返し部および前記立ち上がり部の立ち上がり角度が50〜130°である。
（４）前記チップ側接合部を分割するためのスリットが前記チップ側接合部に形成されている。
（５）前記折り返し部および前記立ち上がり部が前記チップ側接合部の外周の３/４以上に接するように形成されている。 In order to achieve the above object, the present invention can make the following improvements and changes in the semiconductor device according to the present invention.
(1) The thickness of the chip side joint is 1 mm or less.
(2) The height of the folded portion is at least twice the thickness of the chip-side bonded portion.
(3) The rising angle of the folded portion and the rising portion is 50 to 130 °.
(4) A slit for dividing the chip side joint is formed in the chip side joint.
(5) The folded portion and the rising portion are formed so as to be in contact with 3/4 or more of the outer periphery of the chip side joint portion.

本発明によれば、パワー半導体装置における実使用時の熱サイクルによっても半導体チップとリードとを接合するはんだ接合層に疲労亀裂が発生しにくく、信頼性の高い半導体装置を提供することができる。   ADVANTAGE OF THE INVENTION According to this invention, a fatigue crack is hard to generate | occur | produce in the solder joint layer which joins a semiconductor chip and a lead also by the thermal cycle at the time of actual use in a power semiconductor device, and a highly reliable semiconductor device can be provided.

本発明者は、熱サイクルによるはんだ接合層の疲労亀裂に関する詳細な応力解析を行い、リードの形状・厚さとはんだ接合層の疲労亀裂との間に特定の相関関係があることを見出したことに基づき、本発明を完成した（応力解析の詳細は後述する）。以下、図を参照しながら、本発明に係る実施の形態を説明する。ただし、本発明はここで取り上げた実施の形態に限定されることはなく、適宜組み合わせてもよい。なお、図面中で同義の部分には同一の符号を付して重複する説明を省略する。   The inventor conducted detailed stress analysis on fatigue cracks in the solder joint layer due to thermal cycling, and found that there was a specific correlation between the lead shape and thickness and the fatigue cracks in the solder joint layer. Based on this, the present invention was completed (details of stress analysis will be described later). Embodiments according to the present invention will be described below with reference to the drawings. However, the present invention is not limited to the embodiment taken up here, and may be appropriately combined. In addition, the same code | symbol is attached | subjected to the part which is synonymous in drawing, and the overlapping description is abbreviate | omitted.

〔本発明の第１の実施形態〕
（半導体装置の構造）
図１は、本発明の第１の実施形態に係る半導体装置の１例を示す斜視図である。図２は、図１のＡ−Ａ線に沿った断面模式図である。図１，２に示すように、本実施形態に係る半導体装置は、両面に回路層（基板上回路層106および基板下回路層108）を有する絶縁基板107が基板下はんだ109を介して高熱伝導性のベース110上に接合されており、半導体チップ104がチップ下はんだ105を介して基板上回路層106の１つに接合されており、リード101がリード下はんだ103を介して半導体チップ104と他の基板上回路層106とを電気的に接続するように接合されている。 [First embodiment of the present invention]
(Structure of semiconductor device)
FIG. 1 is a perspective view showing an example of a semiconductor device according to the first embodiment of the present invention. FIG. 2 is a schematic cross-sectional view taken along line AA in FIG. As shown in FIGS. 1 and 2, in the semiconductor device according to the present embodiment, an insulating substrate 107 having circuit layers (an on-substrate circuit layer 106 and an under-substrate circuit layer 108) on both sides has high heat conduction through an under-substrate solder 109. The semiconductor chip 104 is bonded to one of the circuit layers 106 on the substrate via the under-chip solder 105, and the lead 101 is connected to the semiconductor chip 104 via the under-lead solder 103. It is joined so as to be electrically connected to another circuit layer 106 on the substrate.

なお、リード101は、チップ側接合部101aと回路層側接合部101bと立ち上がり部101cと渡り部101dとからなるリード本体と、接合部の周縁に形成された折り返し部101eとで構成され、リード本体のチップ側接合部101aと回路層側接合部101bが、それぞれ半導体チップ104や他の基板上回路層106と接合されている。また、チップ側接合部101aと回路層側接合部101bの周縁に設けられた折り返し部101eが、立ち上がり部101cとともに、チップ側接合部101aの接合面に対して半導体チップ104や他の基板上回路層106と反対方向に折り返されている。言い換えると、チップ側接合部101aおよび/または回路層側接合部101bの接合面内の少なくとも四方に折り返された部分が存在することに特徴がある。折り返された部分（折り返し部および立ち上がり部）は、チップ側接合部の外周の３/４以上に接するように形成されていることが望ましい。接合部の外周に対する折り返された部分の比率が大きいほど、はんだ接合層へのひずみ低減に関する効果が大きい。   The lead 101 is composed of a lead body composed of a chip side joint portion 101a, a circuit layer side joint portion 101b, a rising portion 101c, and a transition portion 101d, and a folded portion 101e formed at the periphery of the joint portion. The chip-side bonding portion 101a and the circuit layer-side bonding portion 101b of the main body are bonded to the semiconductor chip 104 and the other on-substrate circuit layer 106, respectively. Further, the folded-back portion 101e provided at the periphery of the chip-side bonding portion 101a and the circuit layer-side bonding portion 101b has the rising portion 101c and the semiconductor chip 104 or other circuit on the substrate with respect to the bonding surface of the chip-side bonding portion 101a. It is folded in the direction opposite to the layer 106. In other words, it is characterized in that there are at least four folded portions within the bonding surface of the chip-side bonding portion 101a and / or the circuit layer-side bonding portion 101b. The folded portion (folded portion and rising portion) is preferably formed so as to be in contact with 3/4 or more of the outer periphery of the chip-side bonded portion. The larger the ratio of the folded portion to the outer periphery of the joint, the greater the effect on reducing the strain on the solder joint layer.

リード本体のチップ側接合部101aの厚さは１mm以下が好ましく、0.25〜１mmがより好ましい（例えば0.5 mm）。折り返し部101eの高さはチップ側接合部101aの厚さの２倍以上が好ましく、４〜６倍がより好ましい（例えば厚さ0.5 mmに対して高さ３mm）。また、折り返し部および立ち上がり部の立ち上がり角度は50〜130°が好ましく、53〜127°がより好ましく、64〜116°が更に好ましい（例えば90°）。なお、折り返し部101eの高さとは、リード101の展開図における、接合部（リード下はんだ103によって接合される部分の外縁）から折り返し部先端までの距離と定義する。立ち上がり角度は、図２に示したように、折り返し部の面と接合部の接合面とのなす角、立ち上がり部の面と接合部の接合面とのなす角と定義する。   The thickness of the chip side joint 101a of the lead body is preferably 1 mm or less, and more preferably 0.25 to 1 mm (for example, 0.5 mm). The height of the folded portion 101e is preferably at least twice the thickness of the chip-side joint portion 101a, and more preferably 4 to 6 times (for example, the height is 3 mm with respect to the thickness of 0.5 mm). The rising angle of the folded portion and the rising portion is preferably 50 to 130 °, more preferably 53 to 127 °, and still more preferably 64 to 116 ° (for example, 90 °). The height of the folded portion 101e is defined as the distance from the joint portion (the outer edge of the portion joined by the solder 103 under the lead) to the tip of the folded portion in the developed view of the lead 101. As shown in FIG. 2, the rising angle is defined as an angle formed between the surface of the folded portion and the bonding surface of the bonding portion, and an angle formed between the surface of the rising portion and the bonding surface of the bonding portion.

チップ側接合部の厚さを薄くすることによりチップ側接合部の面内の剛性を小さくすることができ、接合部の外周に折り返し部と立ち上がり部を設けることによりチップ側接合部全体の曲げ剛性を補強することができる。これにより、リード下はんだ（接合層）に掛かる熱応力を低減することができ、接合層の疲労寿命を向上させることができる。応力解析の詳細は後述する。   The in-plane rigidity of the chip-side joint can be reduced by reducing the thickness of the chip-side joint, and the bending rigidity of the entire chip-side joint can be provided by providing a folded part and a rising part on the outer periphery of the joint. Can be reinforced. Thereby, the thermal stress applied to the solder under the lead (joining layer) can be reduced, and the fatigue life of the joining layer can be improved. Details of the stress analysis will be described later.

（半導体装置の製造方法）
半導体装置の製造方法について説明する。図３は、本発明の第１の実施形態に係る半導体装置の製造方法の１例を示す断面模式図である。 (Method for manufacturing semiconductor device)
A method for manufacturing a semiconductor device will be described. FIG. 3 is a schematic cross-sectional view showing an example of a semiconductor device manufacturing method according to the first embodiment of the present invention.

まず、図３(１)に示すように、両面に回路層（基板上回路層106および基板下回路層108）を有する絶縁基板107を用意する（基板の準備工程）。絶縁基板107の材質は特に限定されないが、パワー半導体装置ではセラミックス基板を用いるのが一般的であり、例えば、窒化ケイ素、窒化アルミ、アルミナ等が利用可能である。また、基板上回路層106および基板下回路層108の材質も特に限定されないが、銅やアルミニウム等が通常用いられる。基板上回路層106および基板下回路層108の形成は、絶縁基板107上に結果的に形成されていればその形成方法を問わないが、パワー半導体装置の製造プロセス中で経験する熱履歴に耐えられる程度の耐熱性が必要とされ、例えば、銀ろう付け、Direct Bonding Copper法と呼ばれる直接接合技術等により接合されるのは好ましい。   First, as shown in FIG. 3A, an insulating substrate 107 having circuit layers (an upper substrate circuit layer 106 and a lower substrate circuit layer 108) on both sides is prepared (substrate preparation step). Although the material of the insulating substrate 107 is not particularly limited, a ceramic substrate is generally used in a power semiconductor device, and for example, silicon nitride, aluminum nitride, alumina, or the like can be used. The material of the on-substrate circuit layer 106 and the under-substrate circuit layer 108 is not particularly limited, but copper, aluminum, or the like is usually used. The formation of the on-substrate circuit layer 106 and the under-substrate circuit layer 108 is not limited as long as it is formed on the insulating substrate 107 as a result, but it can withstand the thermal history experienced during the power semiconductor device manufacturing process. A certain level of heat resistance is required. For example, it is preferable to bond by a silver bonding, a direct bonding technique called a direct bonding copper method, or the like.

次に、図３(２)に示すように、チップ下はんだ105を用いて半導体チップ104と基板上回路層106の１つを接合する（半導体チップの接合工程）。半導体チップ104、チップ下はんだ105および絶縁基板107の位置決めにはスペーサ301を用い、スペーサ301を搭載した状態で全体をはんだ付け炉の中に入れ加熱する。加熱によってチップ下はんだ105が溶融し、基板上回路層106と半導体チップ104とが接合される。チップ下はんだ105には高温はんだ（融点：300℃程度、鉛含有率：約93〜95％）がしばしば用いられる。ただし、高温はんだに限定されるものでなく、製造プロセス上の要求（例えば、階層はんだ構造にするための条件）を満たせばよい。   Next, as shown in FIG. 3B, the semiconductor chip 104 and one of the on-substrate circuit layers 106 are bonded using the under-chip solder 105 (semiconductor chip bonding step). A spacer 301 is used for positioning the semiconductor chip 104, the under-chip solder 105, and the insulating substrate 107, and the whole is placed in a soldering furnace and heated with the spacer 301 mounted. The under-chip solder 105 is melted by heating, and the on-substrate circuit layer 106 and the semiconductor chip 104 are joined. High-temperature solder (melting point: about 300 ° C., lead content: about 93 to 95%) is often used for the under-chip solder 105. However, the present invention is not limited to high-temperature solder, and may satisfy the requirements on the manufacturing process (for example, conditions for forming a hierarchical solder structure).

次に、図３(３)に示すように、基板下はんだ109を用いてベース110と基板下回路層108を接合する（ベースの接合工程）。絶縁基板107、基板下はんだ109およびベース110の位置決めにはスペーサ302を用い、スペーサ302を搭載した状態で全体をはんだ付け炉の中に入れ加熱する。加熱によって基板下はんだ109が溶融し、基板下回路層108とベース110とが接合される。ベース材110の材質は高熱伝導性を有することが望ましく、例えば、銅、アルミシリコンカーバイド、銅タングステン合金等が利用可能である。また、基板下はんだ109としては、錫−鉛はんだの他、錫・銅・銀・ビスマス・ニッケル・インジウム・ゲルマニウム等の金属の全部または一部からなる合金（いわゆる鉛フリーはんだ）を好適に用いることができる。このとき階層はんだ構造の観点から、後工程で使用するはんだ（例えば、基板下はんだ109）は先工程で使用するはんだ（例えば、チップ下はんだ105）よりも融点が低い材料を選定することが望ましい。   Next, as shown in FIG. 3 (3), the base 110 and the under-circuit circuit layer 108 are joined using the under-substrate solder 109 (base joining step). A spacer 302 is used for positioning the insulating substrate 107, the under-substrate solder 109, and the base 110, and the whole is placed in a soldering furnace and heated with the spacer 302 mounted. The under-substrate solder 109 is melted by heating, and the under-substrate circuit layer 108 and the base 110 are joined. The material of the base material 110 desirably has high thermal conductivity. For example, copper, aluminum silicon carbide, copper tungsten alloy, or the like can be used. Moreover, as the under-substrate solder 109, an alloy (so-called lead-free solder) made of all or part of a metal such as tin, copper, silver, bismuth, nickel, indium, germanium, etc. is used in addition to tin-lead solder. be able to. At this time, from the viewpoint of the hierarchical solder structure, it is desirable to select a material having a lower melting point than that used in the previous process (for example, under-chip solder 105) for the solder used in the subsequent process (for example, under-substrate solder 109). .

次に、図３(４)に示すように、リード下はんだ103を介してリード101と半導体チップ104等とを接合する（リードの接合工程）。リード101、リード下はんだ103およびベース110の位置決めにはスペーサ303を用い、スペーサ303を搭載した状態で全体をはんだ付け炉の中に入れ加熱する。加熱によってリード下はんだ103が溶融し、リード本体のチップ側接合部101aと回路層側接合部101bが、それぞれ半導体チップ104や他の基板上回路層106と接合される。リード101の材質にも特段の限定は無いが、一般的に、銅、アルミニウム、鉄−ニッケル合金、モリブデンまたはそれらの複合材が用いられる。リード下はんだ103としては、基板下はんだ109と同等のものを用いることができる。また、基板下はんだ109と同様に、階層はんだ構造の観点から、リード下はんだ103（後工程で使用するはんだ）は先工程で使用するはんだ（例えば、チップ下はんだ105）よりも融点が低い材料を選定することが望ましい。   Next, as shown in FIG. 3 (4), the lead 101 and the semiconductor chip 104 are joined via the solder 103 under the lead (lead joining process). A spacer 303 is used for positioning the lead 101, the solder 103 under the lead, and the base 110, and the whole is placed in a soldering furnace and heated with the spacer 303 mounted. The under-lead solder 103 is melted by heating, and the chip-side bonding portion 101a and the circuit layer-side bonding portion 101b of the lead main body are bonded to the semiconductor chip 104 and the other on-substrate circuit layer 106, respectively. The material of the lead 101 is not particularly limited, but generally copper, aluminum, iron-nickel alloy, molybdenum, or a composite material thereof is used. As the under-lead solder 103, an equivalent to the under-substrate solder 109 can be used. Similarly to the under-substrate solder 109, from the viewpoint of the hierarchical solder structure, the under-lead solder 103 (solder used in the subsequent process) has a lower melting point than the solder used in the previous process (eg, under-chip solder 105). It is desirable to select

以上のような工程により、図１，２に示したような半導体装置を製造できる。なお、上述の説明では３回のリフロー工程（はんだを溶融させる工程）を別々に行ったが、「半導体チップの接合工程」と「ベースの接合工程」を同時に行うことも可能であるし、「ベースの接合工程」と「リードの接合工程」を同時に行うことも可能である。   The semiconductor device as shown in FIGS. 1 and 2 can be manufactured by the process as described above. In the above description, the reflow process (the process of melting the solder) is performed three times separately. However, the “semiconductor chip bonding process” and the “base bonding process” can be performed simultaneously. It is also possible to perform the “base joining step” and the “lead joining step” simultaneously.

また、図１，２においては、リード101のチップ側接合部101aと回路層側接合部101bの両方に折り返し部101eを設けたが、チップ側接合部101aのみに折り返し部101eを設け、回路層側接合部101bに折り返し部101eを設けない構造でもよい。これは、半導体装置において通常の使用条件での主たる発熱領域（温度変化の大きい部位）が半導体チップ104であり、リード下はんだ103に対して大きな熱応力を生じさせるのが主に半導体チップ側であることからである。   In FIGS. 1 and 2, the folded portion 101e is provided in both the chip-side joined portion 101a and the circuit layer-side joined portion 101b of the lead 101, but the folded portion 101e is provided only in the chip-side joined portion 101a, and the circuit layer. A structure in which the folded-back portion 101e is not provided in the side joint portion 101b may be employed. This is because the semiconductor chip 104 is the main heat generation region (part where the temperature change is large) under normal use conditions in the semiconductor device, and it is mainly on the semiconductor chip side that a large thermal stress is generated on the solder 103 under the lead. Because there is.

（接合層の応力解析）
次に、接合層（リード下はんだ）の応力解析について説明する。なお、上述したように、主に半導体チップ側での熱応力が問題になることから、チップ側接合部を代表として説明する。 (Stress analysis of bonding layer)
Next, the stress analysis of the bonding layer (under-lead solder) will be described. As described above, since the thermal stress mainly on the semiconductor chip side is a problem, the chip side bonding portion will be described as a representative.

（i）応力分布
図４は、リード下はんだに掛かる応力とチップ側接合部の幅方向の位置との関係を解析した結果の１例である。該図は、温度変化に起因するリード下はんだの応力分布を表している。リードの素材としては「銅」、リード下はんだの素材としては「共晶はんだ（Sn63mass%−Pb37mass%）」、半導体チップの素材としては「シリコン」を選択し、リードの折り返し部および立ち上がり部の立ち上がり角度は90°とし、温度変化量は40℃として計算機シミュレーションで計算した。図中、401は折り返し部を有しない従来のリード形状でチップ側接合部の厚さが２mmのリードの場合の結果、402は折り返し部を有しない従来のリード形状でチップ側接合部の厚さが厚さ0.5 mmのリードの場合、403は折り返し部（高さ１mm）を有する本発明に係るリード形状でチップ側接合部の厚さが厚さ0.5 mmのリードの場合を表している。また、リード下はんだが疲労亀裂を生じさせない上限値も併記した。 (I) Stress Distribution FIG. 4 is an example of the result of analyzing the relationship between the stress applied to the solder under the lead and the position in the width direction of the chip side joint. The figure shows the stress distribution of the solder under the lead due to the temperature change. Select "Copper" as the lead material, "Eutectic solder (Sn63mass% -Pb37mass%)" as the solder material under the lead, and "Silicon" as the material for the semiconductor chip. The rise angle was 90 ° and the temperature change was 40 ° C. In the figure, 401 is a conventional lead shape having no folded portion and a lead having a thickness of 2 mm in the chip side joint portion. As a result, 402 is a conventional lead shape having no folded portion and the thickness of the chip side joint portion. In the case of a lead having a thickness of 0.5 mm, reference numeral 403 denotes a lead having a folded portion (height of 1 mm) according to the present invention and a lead having a thickness of 0.5 mm in the chip-side joint portion. The upper limit value at which the solder under the lead does not cause fatigue cracks is also shown.

図４に示したように、401の場合、リード中央部で応力が小さいものの、端部近傍で応力が急激に増大し上限値を超えていることが判る。これは、401のリードが厚さ２mmと厚いことからチップ側接合部の面内の剛性が高く、熱膨張差に起因する剪断応力がリードの端部近傍（すなわち、リード下はんだの外周部分）に集中するためと考えられる。   As shown in FIG. 4, in the case of 401, although the stress is small at the center of the lead, it can be seen that the stress rapidly increases near the end and exceeds the upper limit. This is because the lead of 401 has a thickness of 2 mm, so the in-plane rigidity of the chip side joint is high, and the shear stress due to the thermal expansion difference is near the end of the lead (that is, the outer periphery of the solder under the lead) It is thought to concentrate on.

一方、402の場合、端部近傍での応力が401の場合に比して減少しているものの、中央部で応力が急激に増大し上限値を超えていることが判る。これは、402のリードが厚さ0.5 mmと薄いことからチップ側接合部の面内の剛性が低くなったために、リード端部近傍の応力集中を低減する効果があったと認められる。しかしながら、チップ側接合部面内の剛性が低くなったことから、リード中央部で反りを生じさせ、リード下はんだの中央部に引張応力を発生させたものと考えられる。   On the other hand, in the case of 402, although the stress in the vicinity of the end portion is reduced as compared with the case of 401, it can be seen that the stress rapidly increases in the center portion and exceeds the upper limit value. This is considered to be effective in reducing stress concentration in the vicinity of the end of the lead because the 402 lead is as thin as 0.5 mm and the in-plane rigidity of the chip-side joint is reduced. However, since the rigidity in the chip side joint surface is low, it is considered that warpage is generated in the center portion of the lead and tensile stress is generated in the center portion of the solder under the lead.

これらに対し、本発明に係る403の場合、薄いリードを用いることにより、402の場合と同様に面内の剛性を低く抑えることでリード端部近傍の応力集中を低減することができる。加えて、チップ側接合部の周縁（リード端部の外縁）に折り返し部を設けることにより、チップ側接合部全体としての剛性（曲げ剛性）を高めてリード中央部での反りを抑制し、リード下はんだに掛かる引張応力を低減することができる。すなわち、本発明に係る半導体装置は、リード下はんだに掛かる応力が疲労亀裂を生じさせない上限値以下に抑制されることから、リード下はんだの熱疲労寿命を向上させることができる。なお、上述の条件で立ち上がり角度の影響を調査したところ、50〜130°の範囲で略同等の結果が得られることが確認された。   On the other hand, in the case of 403 according to the present invention, by using a thin lead, the stress concentration in the vicinity of the lead end can be reduced by suppressing the in-plane rigidity as in the case of 402. In addition, by providing a folded portion at the periphery of the chip-side joint (the outer edge of the lead end), the rigidity (bending rigidity) of the entire chip-side joint is increased, and warping at the center of the lead is suppressed. The tensile stress applied to the lower solder can be reduced. That is, the semiconductor device according to the present invention is able to improve the thermal fatigue life of the solder under the lead because the stress applied to the solder under the lead is suppressed to the upper limit value that does not cause fatigue cracking. In addition, when the influence of the rising angle was investigated under the above conditions, it was confirmed that substantially the same result was obtained in the range of 50 to 130 °.

（ii）チップ側接合部の厚さの影響
図５は、リード下はんだに掛かる応力とチップ側接合部の厚さとの関係を解析した結果の１例である。該図は、リード下はんだの応力に与えるチップ側接合部の厚さの影響を表している。リードの素材、リード下はんだの素材、半導体チップの素材、温度変化量等の条件は図４の場合と同じで計算した。図中、501は折り返し部を有しない従来のリード形状でチップ側接合部の端部での結果、502は折り返し部を有しない従来のリード形状でチップ側接合部の中央部での結果、503は本発明に係るリード形状で（チップ側接合部厚さの２倍高さの折り返し部を有する）チップ側接合部の端部での結果、504は本発明に係るリード形状で（チップ側接合部厚さの２倍高さの折り返し部を有する）チップ側接合部の中央部での結果を表している。また、図４と同様にリード下はんだが疲労亀裂を生じさせない上限値も併記した。 (Ii) Influence of Thickness of Chip-side Bonded Part FIG. 5 is an example of the result of analyzing the relationship between the stress applied to the solder under the lead and the thickness of the chip-side joined part. The figure shows the influence of the thickness of the chip side joint on the stress of the solder under the lead. The conditions such as the lead material, the solder material under the lead, the semiconductor chip material, and the temperature change amount were calculated in the same manner as in FIG. In the figure, 501 is a conventional lead shape without a folded portion and results at the end of the chip side joint portion, 502 is a conventional lead shape without a folded portion and a result at the center portion of the chip side joint portion, 503 Is a lead shape according to the present invention (having a folded portion that is twice as high as the chip-side joint thickness). As a result, 504 is a lead shape according to the present invention (chip-side joint). The result in the center part of the chip | tip side junction part (with a folding | turning part 2 times as high as part thickness) is represented. Further, as in FIG. 4, the upper limit value at which the solder under the lead does not cause fatigue cracks is also shown.

501，502に示したように、折り返し部を有しない従来のリード形状においては、接合部の端部と中央部とが相反する傾向を有していることが判る。チップ側接合部の端部では板厚の増大に伴って該応力が増大し板厚が１mmを超えると疲労亀裂を生じさせない上限値を超え（図中の501参照）、チップ側接合部の中央部では板厚の減少に伴って該応力が増大し板厚が１mm以下で疲労亀裂を生じさせない上限値を超えている（図中の502参照）。すなわち、折り返し部を有しない従来のリード形状では両立させる解を見つけることが困難であることが解る。   As shown in 501 and 502, it can be seen that in the conventional lead shape having no folded portion, the end portion and the central portion of the joint portion tend to conflict with each other. At the end of the chip-side joint, the stress increases as the plate thickness increases. If the plate thickness exceeds 1 mm, it exceeds the upper limit that does not cause fatigue cracks (see 501 in the figure), and the center of the chip-side joint In the portion, the stress increases as the plate thickness decreases, and the plate thickness is less than 1 mm and exceeds the upper limit value that does not cause fatigue cracks (see 502 in the figure). That is, it can be seen that it is difficult to find a compatible solution with the conventional lead shape having no folded portion.

これに対し、本発明に係るリード形状（チップ側接合部厚さの２倍高さの折り返し部を有する）においては、チップ側接合部の端部での応力は501と略同等であるものの（図中の503参照）、チップ側接合部の中央部の応力は502に比して大きく低下し板厚が１mm以下でも上限値を超えていないことが判る（図中の504参照）。すなわち、板厚の２倍の高さを有する折り返し部を設けた場合、チップ側接合部の板厚を１mm以下とすることでチップ側接合部の端部と中央部の応力をともに低減することが可能となる。   In contrast, in the lead shape according to the present invention (having a folded portion twice as high as the chip-side joint thickness), the stress at the end of the chip-side joint is substantially equal to 501 ( It can be seen that the stress at the center of the chip-side joint is greatly reduced as compared with 502, and does not exceed the upper limit even if the plate thickness is 1 mm or less (see 504 in the figure). That is, when a folded portion having a height twice as large as the plate thickness is provided, the stress at the end portion and the center portion of the chip side joint portion can be reduced by setting the plate thickness of the chip side joint portion to 1 mm or less. Is possible.

（iii）折り返し部の高さの影響
図６は、リード下はんだに掛かる応力と折り返し部の高さとの関係を解析した結果の１例である。該図は、チップ側接合部の中央部におけるリード下はんだの応力に与える折り返し部の高さ（チップ側接合部の厚さに対する比）の影響を表している。リードの素材、リード下はんだの素材、半導体チップの素材、温度変化量等の条件は図４の場合と同じとし、チップ側接合部の厚さは0.25 mmとして計算した。また、図４と同様にリード下はんだが疲労亀裂を生じさせない上限値も併記した。 (Iii) Influence of the height of the folded portion FIG. 6 shows an example of the result of analyzing the relationship between the stress applied to the solder under the lead and the height of the folded portion. The figure shows the influence of the height of the folded portion (ratio to the thickness of the chip-side joint) on the stress of the solder under the lead at the center of the chip-side joint. The calculation was made assuming that the lead material, the solder material under the lead, the material of the semiconductor chip, the amount of temperature change, and the like were the same as those in FIG. Further, as in FIG. 4, the upper limit value at which the solder under the lead does not cause fatigue cracks is also shown.

図６に示したように、折り返し部の高さ（チップ側接合部の厚さに対する比）が増大するにつれてチップ側接合部の中央部におけるリード下はんだの応力が減少し、折り返し部の高さがチップ側接合部の厚さの２倍以上になると該応力が上限値以下に抑制されていることが判る。言い換えると、チップ側接合部の厚さを薄くした場合、折り返し部の高さをチップ側接合部の厚さの２倍以上とすることにより、チップ側接合部の中央部においてもリード下はんだに掛かる応力を上限値以下に抑制することができる。   As shown in FIG. 6, as the height of the folded portion (ratio to the thickness of the chip side joint portion) increases, the stress of the solder under the lead in the center portion of the chip side joint portion decreases, and the height of the folded portion It can be seen that the stress is suppressed to the upper limit value or less when the thickness is twice or more the thickness of the chip-side joint. In other words, when the thickness of the chip-side joint is reduced, the height of the folded portion is set to be twice or more the thickness of the chip-side joint so that the solder under the lead can be used at the center of the chip-side joint. The applied stress can be suppressed below the upper limit value.

以上の応力解析から、チップ側接合部全体としての剛性（曲げ剛性）がリード下はんだに掛かる応力に対して及ぼす影響が大きいことが明らかになった。なお、該曲げ剛性は、リード素材のヤング率の１乗に比例し、チップ側接合部の厚さや折り返し部の高さの３乗に比例すると考えられることから、上述した素材の組み合わせ以外の組み合わせにおいても同様の結果が得られると言える。   From the above stress analysis, it became clear that the rigidity (bending rigidity) of the entire chip side joint has a great influence on the stress applied to the solder under the lead. Since the bending rigidity is proportional to the first power of the Young's modulus of the lead material and proportional to the cube of the thickness of the chip side joint and the height of the folded portion, combinations other than the above-described combinations of materials are possible. It can be said that the same result can be obtained in.

〔本発明の第２の実施形態〕
（半導体装置の構造）
図７は、本発明の第２の実施形態に係る半導体装置の１例を示す斜視図である。本実施形態に係る半導体装置は、チップ側接合部101aにリード111の長手方向と同じ方向のスリット701を設け、チップ側接合部101aを分割した点で第１の実施形態と異なる。なお、図７に示したように、折り返し部101eや立ち上がり部101cは分割していない。 [Second Embodiment of the Present Invention]
(Structure of semiconductor device)
FIG. 7 is a perspective view showing an example of a semiconductor device according to the second embodiment of the present invention. The semiconductor device according to this embodiment is different from that of the first embodiment in that the chip-side bonding portion 101a is provided with slits 701 in the same direction as the longitudinal direction of the leads 111 and the chip-side bonding portion 101a is divided. Note that, as shown in FIG. 7, the folded portion 101e and the rising portion 101c are not divided.

チップ側接合部101aを図のように分割することにより、リード接合面の幅方向長さを小さくすることができ、温度変化に起因する熱膨張差の絶対量が小さくなることでリード下はんだに掛かる剪断応力を低減することができる。また、折り返し部101eや立ち上がり部101cを分割していないことから、チップ側接合部101a全体としての曲げ剛性は、第１の実施形態と同様に高い状態を維持することができる。「曲げ剛性の維持」と「剪断応力の低減効果」とから、本実施形態に係る半導体装置は、第１の実施形態に係る半導体装置よりもリード下はんだの熱疲労寿命を更に向上させることができる。   By dividing the chip-side joint 101a as shown in the figure, the length in the width direction of the lead joint surface can be reduced, and the absolute amount of the difference in thermal expansion caused by temperature changes is reduced, so that the solder under the lead The applied shear stress can be reduced. Further, since the folded-back portion 101e and the rising portion 101c are not divided, the bending rigidity of the entire chip-side joint portion 101a can be maintained at a high level as in the first embodiment. From the “maintenance of bending rigidity” and the “effect of reducing shear stress”, the semiconductor device according to this embodiment can further improve the thermal fatigue life of the solder under the lead than the semiconductor device according to the first embodiment. it can.

図７においては、チップ側接合部101aにリード111の長手方向と同じ方向のスリット701を設けているが、長手方向に限定されることはなく、リード111の幅方向にスリット701を設けてもよい。また、図ではチップ側接合部101aを２分割しているが、２分割に限定されることはなく３分割以上でもよい。なお、回路層側接合部101bにおいては、第１の実施形態と同様に、折り返し部101eを設けても設けなくてもよいし、スリット701を設けても設けなくてもよい。   In FIG. 7, the slit 701 in the same direction as the longitudinal direction of the lead 111 is provided in the chip side joint portion 101a. However, the slit 701 is not limited to the longitudinal direction, and the slit 701 may be provided in the width direction of the lead 111. Good. Further, in the figure, the chip-side bonding portion 101a is divided into two parts, but the invention is not limited to two parts and may be divided into three parts or more. In the circuit layer side bonding portion 101b, similarly to the first embodiment, the folded portion 101e may or may not be provided, and the slit 701 may or may not be provided.

〔本発明の第３の実施形態〕
（半導体装置の構造）
図８は、本発明の第３の実施形態に係る半導体装置の１例を示す斜視図である。本実施形態に係る半導体装置は、チップ側接合部101aにリード121の長手方向と幅方向に伸びる十字形のスリット801を設けた点で第２の実施形態と異なる。折り返し部101eや立ち上がり部101cは、第２の実施形態と同様に分割していない。 [Third embodiment of the present invention]
(Structure of semiconductor device)
FIG. 8 is a perspective view showing an example of a semiconductor device according to the third embodiment of the present invention. The semiconductor device according to the present embodiment is different from the second embodiment in that a cross-shaped slit 801 extending in the longitudinal direction and the width direction of the lead 121 is provided in the chip-side bonding portion 101a. The folded portion 101e and the rising portion 101c are not divided as in the second embodiment.

本実施形態においても、第２の実施形態と同様にリード下はんだに掛かる剪断応力と引張応力の両方を低減することが可能である。スリットの方向を増やすことでリード下はんだに掛かる剪断応力を更に低減することが可能となり、リード下はんだの熱疲労寿命をより一層向上させることができる。   Also in this embodiment, it is possible to reduce both the shear stress and the tensile stress applied to the solder under the lead as in the second embodiment. By increasing the direction of the slit, the shear stress applied to the solder under the lead can be further reduced, and the thermal fatigue life of the solder under the lead can be further improved.

図８においては、リード121の長手方向および幅方向のスリットの本数を１（すなわち十字形）としているが、十字形に限定されることはなく、長手方向または幅方向のいずれか一方のスリット数を２以上としてもよい。また、スリット801の方向もリード121の長手方向および幅方向に限定されることはなく、チップ側接合部101aの面内で回転させた（例えば、面内で45°回転させた）形状としてもよい。なお、回路層側接合部101bにおいては、第１の実施形態と同様に、折り返し部101eを設けても設けなくてもよいし、スリット801を設けても設けなくてもよい。   In FIG. 8, the number of slits in the longitudinal direction and the width direction of the lead 121 is 1 (that is, a cross shape), but is not limited to a cross shape, and the number of slits in either the longitudinal direction or the width direction is not limited. May be 2 or more. In addition, the direction of the slit 801 is not limited to the longitudinal direction and the width direction of the lead 121, and may be a shape rotated in the plane of the chip-side bonding portion 101a (for example, rotated by 45 ° in the plane). Good. In the circuit layer side bonding portion 101b, similarly to the first embodiment, the folded portion 101e may or may not be provided, and the slit 801 may or may not be provided.

本発明の第１の実施形態に係る半導体装置の１例を示す斜視図である。1 is a perspective view showing an example of a semiconductor device according to a first embodiment of the present invention. 図１のＡ−Ａ線に沿った断面模式図である。It is a cross-sectional schematic diagram along the AA line of FIG. 本発明の第１の実施形態に係る半導体装置の製造方法の１例を示す断面模式図である。It is a cross-sectional schematic diagram which shows one example of the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. リード下はんだに掛かる応力とチップ側接合部の幅方向の位置との関係を解析した結果の１例である。It is an example of the result of having analyzed the relationship between the stress concerning the solder under a lead, and the position of the width direction of a chip side joined part. リード下はんだに掛かる応力とチップ側接合部の厚さとの関係を解析した結果の１例である。It is an example of the result of having analyzed the relationship between the stress concerning the solder under a lead, and the thickness of a chip side junction part. リード下はんだに掛かる応力と折り返し部の高さとの関係を解析した結果の１例である。It is an example of the result of having analyzed the relation between the stress applied to the solder under the lead and the height of the folded portion. 本発明の第２の実施形態に係る半導体装置の１例を示す斜視図である。It is a perspective view which shows one example of the semiconductor device which concerns on the 2nd Embodiment of this invention. 本発明の第３の実施形態に係る半導体装置の１例を示す斜視図である。It is a perspective view which shows one example of the semiconductor device which concerns on the 3rd Embodiment of this invention.

符号の説明Explanation of symbols

101，111，121…リード、101a…チップ側接合部、101b…回路層側接合部、
101c…立ち上がり部、101d…渡り部、101e…折り返し部、
103…リード下はんだ、104…半導体チップ、105…チップ下はんだ、
106…基板上回路層、107…絶縁基板、108…基板下回路層、109…基板下はんだ、
110…ベース、301，302，303…スペーサ、
401…折り返し部を有しない従来のリード形状でチップ側接合部の厚さが２mmのリードの場合の解析結果、
402…折り返し部を有しない従来のリード形状でチップ側接合部の厚さが厚さ0.5 mmのリードの場合の解析結果、
403…折り返し部（高さ１mm）を有する本発明に係るリード形状でチップ側接合部の厚さが厚さ0.5 mmのリードの場合の解析結果、
501…折り返し部を有しない従来のリード形状でチップ側接合部の端部での解析結果、
502…折り返し部を有しない従来のリード形状でチップ側接合部の中央部での解析結果、
503…本発明に係るリード形状で（チップ側接合部厚さの２倍高さの折り返し部を有する）チップ側接合部の端部での解析結果、
504…本発明に係るリード形状で（チップ側接合部厚さの２倍高さの折り返し部を有する）チップ側接合部の中央部での解析結果、
701，801…スリット。 101, 111, 121 ... Lead, 101a ... Chip side junction, 101b ... Circuit layer side junction,
101c ... rising part, 101d ... crossing part, 101e ... folding part,
103 ... Solder under lead, 104 ... Semiconductor chip, 105 ... Solder under tip,
106 ... Circuit layer on substrate, 107 ... Insulating substrate, 108 ... Circuit layer under substrate, 109 ... Solder under substrate,
110… Base, 301, 302, 303… Spacer,
401: Analysis result in the case of a lead having a conventional lead shape having no folded portion and a chip side joint thickness of 2 mm,
402… Analysis result in the case of a lead having a conventional lead shape having no folded portion and a chip-side joint thickness of 0.5 mm,
403 ... Analysis result in the case of a lead having a folded part (height 1 mm) and a lead having a thickness of 0.5 mm on the chip side joint part according to the present invention,
501 ... Analysis result at the end of the chip side joint in the conventional lead shape without the folded part,
502 ... Analysis result at the center part of the chip side joint part in the conventional lead shape without the folded part,
503... Analysis result at the end of the chip-side joint (with a folded portion having a height twice the thickness of the chip-side joint) in the lead shape according to the present invention,
504 ... Analysis result at the center part of the chip-side joint portion (having a folded portion twice as high as the chip-side joint thickness) in the lead shape according to the present invention,
701, 801 ... Slit.

Claims (6)

半導体チップと回路層とそれらを電気的に接続する板状のリードとを有する半導体装置であって、
前記リードは、チップ側接合部と回路層側接合部と立ち上がり部と渡り部とからなるリード本体と、少なくとも前記チップ側接合部の周縁に形成された折り返し部とを有し、
前記リード本体の前記チップ側接合部が導電性の接合層を介して前記半導体チップに接合され、前記回路層側接合部が導電性の接合層を介して前記回路層に接合されており、
前記折り返し部と前記立ち上がり部とが前記チップ側接合部の接合面に対して前記半導体チップと反対方向に折り返されていることを特徴とする半導体装置。 A semiconductor device having a semiconductor chip, a circuit layer, and plate-like leads that electrically connect them,
The lead has a lead body composed of a chip-side bonding portion, a circuit layer-side bonding portion, a rising portion, and a crossing portion, and a folded portion formed at least on the periphery of the chip-side bonding portion,
The chip-side bonding portion of the lead body is bonded to the semiconductor chip via a conductive bonding layer, and the circuit layer-side bonding portion is bonded to the circuit layer via a conductive bonding layer;
The semiconductor device, wherein the folded portion and the rising portion are folded in a direction opposite to the semiconductor chip with respect to a bonding surface of the chip side bonding portion. 請求項１に記載の半導体装置において、
前記チップ側接合部の厚さが１mm以下であることを特徴とする半導体装置。 The semiconductor device according to claim 1,
2. A semiconductor device according to claim 1, wherein a thickness of the chip side joint is 1 mm or less. 請求項１または請求項２に記載の半導体装置において、
前記折り返し部の高さが前記チップ側接合部の厚さの２倍以上であることを特徴とする半導体装置。 The semiconductor device according to claim 1 or 2,
The semiconductor device according to claim 1, wherein the height of the folded portion is at least twice the thickness of the chip-side bonding portion. 請求項１乃至請求項３のいずれか１項に記載の半導体装置において、
前記折り返し部および前記立ち上がり部の立ち上がり角度が50〜130°であることを特徴とする半導体装置。 The semiconductor device according to any one of claims 1 to 3,
2. A semiconductor device according to claim 1, wherein a rising angle of the folded portion and the rising portion is 50 to 130 degrees. 請求項１乃至請求項４のいずれか１項に記載の半導体装置において、
前記チップ側接合部を分割するためのスリットが前記チップ側接合部に形成されていることを特徴とする半導体装置。 5. The semiconductor device according to claim 1, wherein:
A semiconductor device, wherein a slit for dividing the chip side joint is formed in the chip side joint. 請求項１乃至請求項５のいずれか１項に記載の半導体装置において、
前記折り返し部および前記立ち上がり部が前記チップ側接合部の外周の３/４以上に接するように形成されていることを特徴とする半導体装置。 The semiconductor device according to claim 1, wherein:
The semiconductor device, wherein the folded portion and the rising portion are formed so as to be in contact with 3/4 or more of the outer periphery of the chip-side bonding portion.
JP2008214779A 2008-08-25 2008-08-25 Semiconductor device Pending JP2010050364A (en)

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Cited By (5)

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JP2012212712A (en) * 2011-03-30 2012-11-01 Toshiba Corp Mounting structure of semiconductor device and method of mounting semiconductor device
KR101278393B1 (en) 2010-11-01 2013-06-24 삼성전기주식회사 Power package module and a fabricating mothod the same
JP2015115471A (en) * 2013-12-12 2015-06-22 三菱電機株式会社 Power semiconductor device
JP5892250B2 (en) * 2012-11-05 2016-03-23 日本精工株式会社 Semiconductor module
US10658284B2 (en) 2014-05-20 2020-05-19 Mitsubishi Electric Corporation Shaped lead terminals for packaging a semiconductor device for electric power

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101278393B1 (en) 2010-11-01 2013-06-24 삼성전기주식회사 Power package module and a fabricating mothod the same
JP2012212712A (en) * 2011-03-30 2012-11-01 Toshiba Corp Mounting structure of semiconductor device and method of mounting semiconductor device
JP5892250B2 (en) * 2012-11-05 2016-03-23 日本精工株式会社 Semiconductor module
US9402311B2 (en) 2012-11-05 2016-07-26 Nsk Ltd. Semiconductor module
JP2015115471A (en) * 2013-12-12 2015-06-22 三菱電機株式会社 Power semiconductor device
US10658284B2 (en) 2014-05-20 2020-05-19 Mitsubishi Electric Corporation Shaped lead terminals for packaging a semiconductor device for electric power

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