JP2016143685A - Semiconductor module - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor module which is excellent in connection reliability even if a junction temperature becomes high.SOLUTION: Disclosed is a semiconductor module having a configuration in which a semiconductor chip 101 equipped with a surface electrode and a back electrode is mounted on a circuit board. This semiconductor module includes: a first sinter junction layer 105 in which a back electrode 106' of the semiconductor chip and wiring 102 of the circuit board are connected; and a second sinter junction layer 105' in which the surface electrode 106 of the semiconductor chip and a conductive plate 150 are connected. The rigidity of the first sinter junction layer 105 is higher than that of the second sinter junction layer 105'.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a semiconductor module having a sintered bonding layer.

  A semiconductor module such as an IGBT module handles a large current of several tens to several hundreds of A per semiconductor chip, and is accompanied by a large heat generation of the semiconductor chip. In recent years, further miniaturization of semiconductor modules has been demanded, and the heat generation density tends to increase more and more. In particular, in order to ensure heat resistance, high lead solder having a melting point of about 300 ° C. and a lead content of 85% or more has been conventionally used for joining a semiconductor chip and a wiring layer. However, lead-free semiconductor devices are required, and Sn-Cu solder, Sn-Ag solder, Sn-Sb solder, etc. are known as lead-free solder materials. Is about 200 ° C., and heat resistance cannot be ensured.

  On the other hand, sintered bonding using the low-temperature firing function of metal nanoparticles is expected as a material to replace high-temperature solder. In the case of metal nanoparticles having a particle size of 100 nm or less, the number of constituent atoms is decreased, the surface area ratio to the volume of the particles is rapidly increased, and the melting point and sintering temperature are greatly reduced as compared with the bulk state. By using this low-temperature firing function to sinter and bond metal particles, the metal particles after bonding change into bulk metal and at the same time are bonded by metal bonds at the bonding interface, so they have extremely high heat resistance. And high heat dissipation.

  On the other hand, the main electrode of a semiconductor chip made of Si or SiC is connected to another chip or electrode by a wiring material such as a wire or ribbon made of copper or aluminum. When the operating temperature of the semiconductor chip is increased, the thermal expansion coefficient of the semiconductor chip and the wiring material are different, so that the joint portion is destroyed due to thermal fatigue while switching operation (energization ON / OFF operation) is repeated. There was a problem.

  Therefore, as a technique for improving the reliability of wiring connection, Patent Document 1 discloses a stress buffer that uses a metal plate having a thermal expansion coefficient intermediate between the wiring member and the semiconductor chip to eliminate a connection portion having a large difference in thermal expansion coefficient. A solution from the viewpoint is proposed. Reference 1 describes that a material containing sinterable silver fine particles is used as a bonding material for bonding a semiconductor chip and a metal plate.

JP 2012-28684 A

  Thus, if it connects with a wiring material via the metal plate (conductive plate) connected using the joining material on the semiconductor chip, the thermal stress of a wiring junction part can be reduced and it is effective for connection reliability improvement. . However, the bonding portion between the circuit surface of the insulating substrate and the semiconductor chip (hereinafter referred to as a lower chip bonding portion) and the bonding portion between the main electrode on the upper surface of the semiconductor chip and the conductive plate (hereinafter referred to as an upper chip bonding portion) are sintered. When it is set as a bonding layer, it has the following problems. The thermal stress accompanying the temperature change during the operation of the semiconductor chip or around the semiconductor device is maximized at the joint on the chip. This is because the deformation is restrained by the insulating substrate at the lower chip joint, and thus the amount of thermal strain is small. On the other hand, since the on-chip joint has a structure that is easy to move without being restrained from deformation, thermal strain at the on-chip joint increases, and thermal stress at the joint interface increases. In addition, a sintered joining layer made of silver or copper is harder than a conventional solder material, and there is a problem that the joining layer hardly absorbs thermal stress. When the operating temperature of the semiconductor chip becomes high, particularly when the junction temperature (Tj) exceeds 150 ° C., the thermal stress concentrated on the on-chip junction increases, and at the junction interface starting from the end of the junction layer of the on-chip junction. May cause damage to the semiconductor chip and damage to the end of the semiconductor chip, and the desired reliability in a high-temperature operating environment cannot be obtained.

  An object of this invention is to provide the semiconductor module which is excellent in connection reliability, even if junction temperature becomes high.

  The semiconductor module of the present invention is a semiconductor module having a configuration in which a semiconductor chip having a front electrode and a back electrode is mounted on a circuit board, and is a first sintered joint in which the back electrode of the semiconductor chip and the wiring of the circuit board are connected. And a second sintered bonding layer in which the surface electrode of the semiconductor chip and the conductive plate are connected, and the first sintered bonding layer has higher rigidity than the second sintered bonding layer. .

  According to the present invention, it is possible to provide a semiconductor module having excellent connection reliability even when the junction temperature increases.

(A) is a top view of the insulation type semiconductor device by one Example of this invention, (b) is AA sectional drawing. It is a figure which shows the detailed structure of a semiconductor chip mounting part. It is a figure which shows the power cycle tolerance of the Example and comparative sample of this invention. It is a figure which shows the destruction state at the time of the power cycle test of a comparative sample.

  The semiconductor module of the present invention is a semiconductor module having a configuration in which a semiconductor chip having a front electrode and a back electrode is mounted on a circuit board, and is a first sintered joint in which the back electrode of the semiconductor chip and the wiring of the circuit board are connected. And a second sintered bonding layer in which the surface electrode of the semiconductor chip and the conductive plate are connected to each other, and the rigidity of the second sintered bonding layer is higher than that of the first sintered bonding layer. . As described above, by relatively reducing the rigidity of the first sintered bonding layer (under-chip bonding layer), the thermal strain generated in the second sintered bonding layer (on-chip bonding layer) can be reduced. It can be absorbed on the bonding layer side. As a result, the thermal strain concentrated on the second sintered bonding layer (on-chip bonding layer) is reduced, and the thermal stress concentrated on the bonded portion can be reduced. Thereby, the connection reliability of the bonding layer on the chip can be improved.

  The method for increasing the rigidity of the second sintered bonding layer than the first sintered bonding layer is not particularly limited. For example, the conditions such as the applied pressure during heating, the heating rate, and the solvent concentration of the bonding material are set. Examples include a method of changing the porosity of the sintered bonding layer by changing the first and second sintered bonding layers, a method of changing the material constituting the sintered bonding layer, and a method of changing the thickness of the sintered bonding layer. It is done. When the rigidity of the second sintered bonding layer is higher than that of the first sintered bonding layer due to the difference in the sintered density, the sintering density of the on-chip bonding layer is set to 10 than the sintering density of the lower chip bonding layer. It is desirable to increase it by at least%. As a result of simulation analysis, it was confirmed that when it is 10% or more, the thermal stress resistance is improved about twice, and as a result, the power cycle resistance is improved more than 10 times that of the conventional solder.

  A wiring member such as a wire or a ribbon is connected to the conductive plate connected to the surface electrode of the semiconductor chip, and is connected to another chip or electrode by the wiring member. The conductive plate is required to have a role of relieving thermal stress due to a difference in thermal expansion coefficient between the semiconductor chip and the wiring member and a role of radiating heat from the semiconductor chip. Therefore, as the conductive plate, it is preferable to use a material having a thermal expansion coefficient intermediate between the semiconductor chip and the wiring member and having a thermal conductivity of 100 W / mK or more. Further, if a material having a higher thermal conductivity than the direction perpendicular to the electrode surface of the semiconductor chip is used as the conductive member, the chip surface of the conductive plate before the heat generated by the chip is transmitted to the upper wires, ribbons, and other wirings Because heat spreads in the plane along the surface and a good soaking effect is obtained, only a specific part of the chip becomes hot and the wire or ribbon does not peel off, improving the wiring connection reliability as a whole chip . For example, a material in which graphite fiber having a heat conduction anisotropy of 20 W / mK on a certain surface and 2000 W / mK in the orthogonal direction and a metal (copper, aluminum, etc.) are combined can be used. Further, it is preferable to use a material in which layers having different thermal conductivities such as a copper / invar / copper cladding material are laminated. This is because, in part, the thermal conductivity of Invar (iron-nickel alloy) is smaller than 13 W / mK, which is 400 W / mK, and it is difficult for the heat generated in the semiconductor chip to be transmitted to the top. This is because the heat propagates and is soaked. The other is that the coefficient of thermal expansion depends on the ratio of copper (about 16 ppm / K) and invar (about 1 ppm / K), and Si and SiC (3-5 ppm / K) and wiring members (Al about 23 ppm / K, Cu about This is because it is possible to adjust to an intermediate preferable value of 16 ppm / K) and to reduce thermal stress. For example, by setting the copper / invar / copper ratio to 1: 1: 1, a coefficient of thermal expansion of about 11 ppm / K can be obtained, and it is not necessary to make a connection part of a material having a large thermal expansion difference, and the wiring connection reliability is also conductive. The connection reliability of the member to the chip can also be improved.

  As a bonding material and a bonding method for forming the sintered bonding layer, known methods can be applied. The bonding material and bonding method used in this embodiment will be described as an example. In the embodiment of the present invention, a material containing copper oxide particles having an average particle diameter of 1 nm to 5 μm and an organic solvent is used as the bonding material. By using this bonding material and bonding in a hydrogen atmosphere, the members can be bonded. In particular, excellent bonding strength can be obtained for Cu and Ni electrodes. In this bonding, the copper oxide particle precursor is reduced, copper particles having an average particle diameter of 100 nm or less are generated at that time, and the phenomenon that the bonding is performed by fusion of the copper particles to each other is utilized. . The copper particles having an average particle size of 100 nm or less are generated, the copper particles are fused with each other, and the mechanism of joining is as follows: (1) The generated copper particles of 100 nm or less form a thin film layer on the surface of the counterpart electrode; ) This layer is grown in the same direction as the crystal growth direction of the counterpart metal electrode plate (Cu, Ni, etc.). (3) Further, the sintered layer is formed by the fusion of copper particles that did not contribute to the formation of the thin film layer. That is, a bonding layer is formed and bonding is achieved. The precursor copper oxide particles may be cuprous oxide or cupric oxide. Since metal oxide particles made of copper oxide generate only oxygen during reduction, the residue after joining hardly remains, and the volume reduction rate is very small. The average particle size of the copper oxide particles used here is 1 nm or more and 5 μm or less. When the average particle size is larger than 5 μm, metal copper particles having a particle size of 100 nm or less are less likely to be generated during bonding. This is because the gaps between the particles increase, and it becomes difficult to obtain a dense bonding layer. The reason why the thickness is 1 nm or more is that it is difficult to actually produce a cupric oxide particle precursor having an average particle size of 1 nm or less.

  The joining process was as follows: (1) Heat at 60 ° C. was applied for about 10 minutes, and pressure was simultaneously applied in a hydrogen atmosphere. (2) The temperature was raised to 250 ° C. while applying pressure and held for 5 minutes.

  The bonding material requires a method of applying only to the required part using a metal mask or mesh mask with an opening on the application part, a method of applying to the required part using a dispenser, and a water-repellent resin containing silicone, fluorine, etc. Apply with a metal mask or mesh mask with only an open part, or apply a photosensitive water-repellent resin on a substrate or electronic component, remove the part where the bonding material is applied by exposure and development, and bond A method of applying a bonding paste to the opening, or a method of applying a bonding paste to the opening after applying a water-repellent resin to a substrate or an electronic component and then removing a portion to which a bonding material is applied by a laser. There is. These application methods can be combined according to the area and shape of the electrodes to be joined.

  In bonding using this bonding material, metal particles having a particle size of 100 nm or less are generated from the metal particle precursor during bonding, and metal bonding is performed by fusing metal particles having a particle size of 100 nm or less while discharging organic substances in the bonding layer. In order to carry out, it is preferable to apply heat and a pressure of 0.01 to 5 MPa. The atmosphere during bonding may be a reducing atmosphere containing hydrogen or formic acid, or a non-oxidizing atmosphere.

  In this bonding, pure metal ultrafine particles are generated by heat reduction during bonding, and the pure metal ultraparticles are fused together to form a bulk. The melting temperature after becoming bulk is the same as the melting temperature of metals in the normal bulk state, and the ultrafine metal particles are melted by low-temperature heating, and after melting, they are heated to the melting temperature in the bulk state. It does not re-melt until This is because when pure metal ultrafine particles are used, bonding can be performed at a low temperature, and the melting temperature is improved after bonding. The advantage of not melting. As the sintered bonding layer, sintered silver can be applied in addition to sintered copper, but it is more preferable to use sintered copper. This is because sintered copper has less vacancy diffusion than sintered silver, and void generation due to temperature rise is suppressed.

  By using the bonding material and the bonding method described above for bonding the electrodes of the semiconductor chip, it is possible to obtain excellent bonding reliability.

  Hereinafter, examples of the present invention will be described with reference to the drawings, but the present invention is not limited to the following embodiments.

  1A and 1B show an insulating semiconductor module to which the present invention is applied. FIG. 1A is a plan view, and FIG. 1B is a sectional view taken along line A-A 'in FIG. FIG. 2 is a detailed cross-sectional view of the periphery of the semiconductor chip.

  In this embodiment, the semiconductor chip 101 is a 12 mm × 12 mm IGBT chip. The electrode structure on the collector side of this IGBT is Al / Ti / Ni and the outermost surface is Ni. The emitter side of the IGBT is Al / Ni and the outermost surface is Ni.

  The wiring layer 102 on the ceramic insulating substrate 103 and the collector electrode 106 ′ of the semiconductor chip 101 are joined by a sintered joining layer 105 (first sintered joining layer). The emitter electrode 106 of the semiconductor chip and the conductor plate 150 are joined by a sintered joining layer 105 ′ (second sintered joining layer). The conductor plate 150 is connected to the wiring layer 104 on the ceramic insulating substrate 103 by a copper ribbon 201. The wiring layer 102 provided on the back surface of the ceramic insulating substrate 103 is bonded to the support member 110 via the solder layer 109. The ceramic insulating substrate 103 and the wiring layer 102 are referred to as a wiring substrate. The wiring layers 102 and 104 are Cu wiring. 1 indicate the case 111, the external terminal 112, the bonding wire 113, and the sealing material 114, respectively.

  In this embodiment, the sintered bonding layer 105 and the sintered bonding layer 105 ′ are formed using a bonding material in which 88 wt% cupric oxide particles (pure copper after bonding) and 12 wt% diethylene glycol monobutyl ether are mixed. did. The thickness of the sintered bonding layer 105 and the sintered bonding layer 105 ′ is 80 μm, and the rigidity of the sintered bonding layer 105 ′ is higher than that of the sintered bonding layer 105.

  A method for forming the sintered bonding layer 105 and the sintered bonding layer 105 ′ of this embodiment will be described.

  A bonding material is printed by a metal mask on a bonding portion on the wiring layer 102 of the ceramic insulating substrate 103, and the semiconductor chip 101 is disposed thereon. In that state, heat at 60 ° C. in the atmosphere is applied for about 10 minutes. This is preheating, which is a process for removing unnecessary organic solvent components and suppressing gas generation. Next, a pressurized state is applied at 0.5 MPa, the temperature is raised to 250 ° C. in hydrogen, and held for 5 minutes. In this embodiment, the pressure is kept applied, but the pressurization at the time of holding at 250 ° C. is not essential. Through the above process, the collector electrode 106 ′ of the semiconductor chip 101 and the wiring layer 102 were joined by the sintered joining layer 105.

  Next, a bonding material is printed with a metal mask on the bonding portion of the emitter electrode 106 of the semiconductor chip 101, and the conductor plate 150 is disposed thereon. Thereafter, the pressure is set at 1.0 MPa. Subsequent steps were performed by bonding the emitter electrode 106 of the semiconductor chip 101 with the sintered bonding layer 105 ′ under the same conditions as the sintered bonding layer 105.

  As a result, the sintered density of the sintered joining layer 105 was about 70% (porosity 30%), and the sintered density of the sintered joining layer 105 'was about 80% (porosity 20%). Further, the rigidity (Young's modulus) of the sintered bonding layer 105 was 84 GPa, the rigidity (Young's modulus) of the sintered bonding layer 105 ′ was 96 GPa, and the sintered density and Young's modulus were in a proportional relationship.

  A power cycle test was performed on the semiconductor module manufactured in this example. In the power cycle test, a predetermined current is passed through a semiconductor chip for a predetermined time, the semiconductor chip itself generates heat, and after rising to a predetermined temperature (150 ° C .; expressed as Tjmax 150 ° C. in this test), the current is turned off. This is a test in which heat generation and cooling of the semiconductor chip itself are repeated after cooling to temperature (room temperature in this test) and then turning on again, and is an important reliability test in semiconductor modules. Figure 3 shows the power cycle test results. In FIG. 3, the horizontal axis represents the number of cycles of heat generation and cooling, and the vertical axis represents the transition of the Tjmax value. Although the Tjmax value is set to 150 ° C., damage occurs in the lower chip bonding portion and upper chip bonding portion of the semiconductor chip, and the value increases as the damage further develops. In this test, the lifetime was determined when the rate of increase was 15% of the initial value. For comparison, a comparative sample in which the sintered bonding layer 105 and the sintered bonding layer 105 ′ are formed under the same conditions is manufactured, and the result of performing the power cycle test in the same manner is also shown in FIG. 3. As shown in FIG. 3, in the comparative sample, the Tjmax value increased by 15% or more after about 30,000 times. The target was 100,000 times or more, about 1/3. On the other hand, in the semiconductor module of this example, the cycle life was about 500,000 times, and the reliability could be greatly improved.

  FIG. 4 is a result of examining the damaged part and the damaged state of the comparative sample, and shows a cross-sectional state. According to this, it was confirmed that cracks developed mainly between the conductor plate on the semiconductor chip and the sintered bonding layer, and the fracture state was almost achieved. It was found that this was the cause of the low life. In order to investigate this cause, thermal strain distribution analysis was performed by the finite element method in a structure in which a conductor plate was installed on a semiconductor chip. As a result, it was confirmed that a larger thermal strain was generated in the joint portion on the chip than in the joint portion under the chip, and it was confirmed that reinforcement of this portion was necessary. On the other hand, in the semiconductor module of this embodiment, the thermal strain concentrated on the on-chip junction is reduced, and the life of the junction can be extended.

  In addition to the power cycle test, a temperature cycle test, which is a reliability evaluation method corresponding to changes in ambient temperature, was performed on the comparative sample and the semiconductor module of this example. As a result, the same tendency as in the power cycle test was confirmed.

  In the semiconductor module of this structure, the semiconductor chip 101 and the insulating wiring board having a thermal expansion coefficient of about 9 ppm / ° C., and the semiconductor chip and the conductor plate having a thermal expansion coefficient of about 9 ppm / ° C. are bonded via a bonding material. Further, it is possible to reduce the thermal stress caused by the difference in thermal expansion of each member that becomes prominent in a high temperature environment. Ideally, by matching the thermal expansion coefficient of the bonding material to that of the wiring board, the thermal stress generated in the bonding material is minimized, and long-term reliability is improved. Since the conductor plate is connected with a copper ribbon, higher reliability can be secured than conventional aluminum wire bonding.

  In the present embodiment, an example will be described in which the sintered bonding layer 105 and the sintered bonding layer 105 ′ having different sintered densities are formed by adjusting the heating rate during bonding. Except for the method of forming the sintered bonding layer 105 and the sintered bonding layer 105 ′, it is the same as the first embodiment.

  A method for forming the sintered bonding layer 105 and the sintered bonding layer 105 ′ of this embodiment will be described.

  A bonding material is printed by a metal mask on a bonding portion on the wiring layer 102 of the ceramic insulating substrate 103, and the semiconductor chip 101 is disposed thereon. In that state, heat at 60 ° C. in the atmosphere is applied for about 10 minutes. Next, a pressure is applied at 0.3 MPa, and the temperature is increased to 250 ° C. in hydrogen at a rate of temperature increase of 10 ° C./min and held for 5 minutes. Through the above process, the collector electrode 106 ′ of the semiconductor chip 101 and the wiring layer 102 were joined by the sintered joining layer 105.

  Next, a bonding material is printed with a metal mask on the bonding portion of the emitter electrode 106 of the semiconductor chip 101, and the conductor plate 150 is disposed thereon. In that state, heat at 60 ° C. in the atmosphere is applied for about 10 minutes. Next, a pressure is applied at 0.3 MPa, and the temperature is increased to 250 ° C. at a rate of temperature increase of 5 ° C./min in hydrogen and held for 5 minutes. Through the above process, the emitter electrode 106 of the semiconductor chip 101 was joined by the sintered joining layer 105 '.

  As a result, the sintered density of the sintered joining layer 105 was about 70% (porosity 30%), and the sintered density of the sintered joining layer 105 'was about 85% (porosity 15%). Further, the rigidity (Young's modulus) of the sintered bonding layer 105 was about 80 GPa, and the rigidity (Young's modulus) of the sintered bonding layer 105 ′ was about 90 GPa, and the sintered density and Young's modulus were in a substantially proportional relationship.

  As a result of conducting a power cycle test on the semiconductor module manufactured in this example, the cycle life was about 700,000 times, and a significant improvement in reliability could be achieved. Although the lifetime was improved as compared with Example 1, it was considered that the effect of reducing damage to the semiconductor element was obtained because the applied pressure was lowered.

  By lowering the heating rate at the time of bonding the sintered bonding layer 105 ′ than that of the sintered bonding layer 105, the porosity of the sintered bonding layer 105 ′ can be made smaller than that of the sintered bonding layer 105. As a result, the sintered bonding layer 105 ′ can be made more rigid than the sintered bonding layer 105.

  In this embodiment, an example will be described in which the sintered bonding layer 105 and the sintered bonding layer 105 ′ having different sintering densities are formed by changing the solvent concentration of the bonding material. Except for the method of forming the sintered bonding layer 105 and the sintered bonding layer 105 ′, it is the same as the first embodiment.

  A method for forming the sintered bonding layer 105 and the sintered bonding layer 105 ′ of this embodiment will be described. As a bonding material for forming the sintered bonding layer 105, a material in which 80 wt% cupric oxide particles (pure copper after bonding) and 20 wt% diethylene glycol monobutyl ether were mixed was used.

  A bonding material is printed by a metal mask on a bonding portion on the wiring layer 102 of the ceramic insulating substrate 103, and the semiconductor chip 101 is disposed thereon. Next, a bonding material is printed with a metal mask on the bonding portion of the emitter electrode 106 of the semiconductor chip 101, and the conductor plate 150 is disposed thereon. In that state, heat at 60 ° C. in the atmosphere is applied for about 10 minutes. Next, a pressurized state is applied at 0.3 MPa, the temperature is raised to 250 ° C. in hydrogen and held for 5 minutes. Through the above process, the collector electrode 106 ′ and the wiring layer 102 of the semiconductor chip 101, and the emitter electrode 106 and the conductor plate 150 of the semiconductor chip 101 were joined together.

  Next, a bonding material is printed with a metal mask on the bonding portion of the emitter electrode 106 of the semiconductor chip 101, and the conductor plate 150 is disposed thereon. As a bonding material for forming the sintered bonding layer 105 ′, a material obtained by mixing 90 wt% cupric oxide particles (pure copper after bonding) and 10 wt% diethylene glycol monobutyl ether was used. In that state, heat at 60 ° C. in the atmosphere is applied for about 10 minutes. Next, a pressure is applied at 0.3 MPa, and the temperature is increased to 250 ° C. at a rate of temperature increase of 5 ° C./min in hydrogen and held for 5 minutes. Through the above process, the emitter electrode 106 of the semiconductor chip 101 was joined by the sintered joining layer 105 '.

  As a result, the sintered density of the sintered joining layer 105 was about 75% (porosity 25%), and the sintered density of the sintered joining layer 105 'was about 91% (porosity 9%). Further, the rigidity (Young's modulus) of the sintered bonding layer 105 was about 80 GPa, and the rigidity (Young's modulus) of the sintered bonding layer 105 ′ was about 95 GPa, and the sintered density and Young's modulus were in a proportional relationship.

  As a result of performing a power cycle test on the semiconductor module manufactured in this example, the cycle life was about 700,000 times, indicating high reliability equivalent to that of Example 2.

  In Examples 1 and 2, the sintered joints 105 and 105 ′ were individually joined, but a paste having a lower solvent concentration was applied to the sintered joint layer 105 ′ than the sintered joint layer 105 as in this example. The porosity of the sintered bonding layer 105 ′ can be made smaller than that of the sintered bonding layer 105 by bonding at the same time. As a result, the sintered bonding layer 105 ′ can be made more rigid than the sintered bonding layer 105.

  In this example, the rigidity of the sintered bonding layer 105 ′ is made higher than that of the sintered bonding layer 105 by changing the material forming the sintered bonding layer 105 and the material forming the sintered bonding layer 105 ′. Will be explained. Except for the configuration of the sintered bonding layer 105 and the sintered bonding layer 105 ′, it is the same as the first embodiment.

  In this embodiment, a sintered silver paste is used as a bonding material for forming the sintered bonding layer 105, and 90 wt% cupric oxide particles (pure copper after bonding) are used as the bonding material for forming the sintered bonding layer 105 ′. ) And 10 wt% of diethylene glycol monobutyl ether, and using the same method as in Example 1, except that the applied pressure was set to 0.1 MPa as a forming condition of the sintered bonding layer 105, A sintered bonding layer 105 ′ was formed.

  As a result, the sintered density of the sintered bonding layer 105 was about 90% (porosity 10%), and the sintered density of the sintered bonding layer 105 'was about 90% (porosity 10%). The rigidity (Young's modulus) of the sintered bonding layer 105 was about 60 GPa, and the rigidity (Young's modulus) of the sintered bonding layer 105 ′ was about 88 GPa.

  As a result of conducting a power cycle test on the semiconductor module manufactured in this example, the cycle life was about 500,000 times.

  In this embodiment, an example will be described in which the rigidity of the sintered bonding layer 105 ′ is apparently higher than that of the sintered bonding layer 105 by changing the thicknesses of the sintered bonding layer 105 and the sintered bonding layer 105 ′. Except for the configuration of the sintered bonding layer 105 and the sintered bonding layer 105 ′, it is the same as the first embodiment. The thickness was about 80 μm for the sintered bonding layer 105 and about 50 μm for the sintered bonding layer 105 ′. Both the sintered bonding layers 105 and 105 ′ had a sintered density of about 80% (void ratio 20%) and rigidity (Young's modulus) of about 90 GPa.

  As a result of conducting a power cycle test on the semiconductor module manufactured in this example, the cycle life was about 300,000 times, which was 10 times higher than the conventional solder.

  The semiconductor device of the present invention can be applied to various power conversion devices. By applying the semiconductor device of the present invention to the power conversion device, long-term reliability can be ensured even if it can be mounted in a place of a high temperature environment and does not have a dedicated cooler.

  Further, the inverter device and the electric motor can be incorporated as a power source in a high-speed vehicle or an electric vehicle. In this car, the drive mechanism from the power source to the wheels has been simplified, so the shock at the time of shifting is reduced and smooth running is possible compared to the conventional car that has been shifting due to the difference in gear engagement ratio. Thus, vibration and noise can be reduced as compared with the conventional case.

  Furthermore, the inverter device incorporating the semiconductor device of this embodiment can be incorporated into an air conditioner. In this case, higher efficiency can be obtained than when a conventional AC motor is used. Thereby, the power consumption at the time of air-conditioning machine use can be reduced. Moreover, the time until the room temperature reaches the set temperature from the start of operation can be shortened compared to the case where the conventional AC motor is used.

  The same effect as that of the present embodiment can be enjoyed even when the semiconductor device is incorporated in a device that stirs or flows another fluid, such as a washing machine or a fluid circulation device.

DESCRIPTION OF SYMBOLS 101 ... Semiconductor chip, 102 ... Wiring layer, 103 ... Ceramic insulating substrate, 105, 105 '... Sintered bonding layer, 106 ... Emitter electrode, 106' ... Collector electrode, 110 ... Support member, 150 ... Conductor plate, 201 ... Copper ribbon

Claims (6)

A semiconductor module having a configuration in which a semiconductor chip having a front electrode and a back electrode is mounted on a circuit board,
A first sintered bonding layer comprising a first sintered bonding layer connecting the back electrode of the semiconductor chip and the wiring of the circuit board; and a second sintered bonding layer connecting the surface electrode of the semiconductor chip and the conductive plate. A semiconductor module, wherein the second sintered bonding layer has higher rigidity than the layer. The semiconductor module according to claim 1,
A semiconductor module, wherein the porosity of the second sintered bonding layer is lower than the porosity of the first sintered bonding layer. The semiconductor module according to claim 1,
A semiconductor module, wherein the first sintered bonding layer is copper and the second sintered bonding layer is silver. The semiconductor module according to claim 1,
A semiconductor module, wherein the thickness of the second sintered bonding layer is smaller than the thickness of the first sintered bonding layer. The semiconductor module according to claim 1,
A semiconductor module, wherein the first sintered bonding layer and the second sintered bonding layer are copper. The semiconductor module according to claim 1,
A semiconductor module comprising a wire or ribbon-like wiring member that electrically connects the conductive plate and other elements or wiring of the circuit board.