JP2014127537A - Semiconductor device using conductive bonding material and method of manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device in which occurrence of conductive residue, due to protrusion of paste, is suppressed.SOLUTION: A semiconductor device has a semiconductor element 101 and an insulating substrate. A wiring layer 102 is formed on the insulating substrate, and a bond layer 105 composed of a sintered metal is formed between the semiconductor element and wiring layer. The bond layer has a first sintered layer 105a arranged on the side close to the semiconductor element, and sintered layers 105b, 105c arranged on the side close to the wiring layer. The sintered layers close to the wiring layer are formed wider than the first sintered layer.

Description

  The present invention relates to a semiconductor device using a conductive bonding material and a method for manufacturing the semiconductor device.

  In general, semiconductor devices are often used in power conversion devices, and control devices such as trains, wind power generation devices, and hybrid vehicles equipped with the power conversion devices. In this semiconductor device, for example, “solder” or “solder alloy” is mainly used for electrical connection between the electrode terminals of electronic components and the electrode terminals of the circuit pattern on the circuit board.

  However, the use of lead is severely restricted from the viewpoint of global environmental protection, and the development of joining electrodes and the like using materials that do not contain lead by restricting the use of lead is being promoted. In particular, no effective material has yet been found for "high temperature solder". Therefore, the appearance of a material that can replace this “high temperature solder” is desired.

  Under such circumstances, as a part of the development, a bonding material for bonding electrodes using a composite material of metal particles and an organic compound has been proposed.

  For example, when the number of constituent atoms decreases as in the case of nanoparticles in which the particle size of metal particles is reduced to 100 nm or less, the ratio of the surface area to the volume of the particles increases rapidly, and the melting point and sintering temperature are in a bulk state. It is known that it is significantly reduced compared to (a state larger than nanoparticles).

  However, when attempting to bond a large area using such a material, it is difficult to volatilize the organic protective film and the organic solvent covering the metal nanoparticles at the center of the bonding surface. There is a problem that it causes deterioration of mechanical characteristics and thermal characteristics.

  Patent Document 1 describes an invention that secures a volatilization path of an organic component by forming a bonding member with a plurality of types of bonding layers having different porosity.

JP 2008-31371 A

  By the way, when joining using a metal nanoparticle, it is necessary to improve the joining reliability of a junction part, For that reason, pressurization is needed when sintering a metal nanoparticle. Since the metal nanoparticles are pasted with the above-described organic solvent or the like, there is a problem that the paste protrudes from between the joining members due to pressurization and remains as a conductive residue after sintering.

  In the invention described in Patent Document 1, the volatilization route of the organic component is considered, but the protrusion of the paste due to pressurization is not considered at all.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device that suppresses the generation of conductive residue resulting from the protrusion of paste.

  The semiconductor device according to the present invention includes a semiconductor element and an insulating substrate, a wiring layer is formed on the insulating substrate, and a bonding layer made of a sintered metal is formed between the semiconductor element and the wiring layer. The bonding layer has a first sintered layer disposed on the side closer to the semiconductor element, and a sintered layer disposed on the side closer to the wiring layer, and the sintered layer on the side closer to the wiring layer includes: It is characterized by being formed wider than the first sintered layer.

  By using the present invention, it is possible to provide a semiconductor device that suppresses the generation of conductive residues resulting from the protrusion of paste.

It is a figure which shows the joining state of the precursor sintering layer 105e. It is an enlarged view of the dotted line part B of FIG. 6 is a diagram illustrating one form of Comparative Example 1. FIG. It is a figure showing the other form of the comparative example 1. It is a figure showing the form of the comparative example 2. FIG. 3 is a diagram showing details of the surface of a wiring layer 102. FIG. It is a figure in which the sintered layer shows (a) crack extension of a simple two-layer sintered structure and (b) crack extension of the sintered structure of the present invention. It is a figure which shows 2nd embodiment of this invention. It is a figure which shows 3rd embodiment of this invention. 2A is a top view of the semiconductor device 150 of the present invention, and FIG. It is a figure which shows the (a) 1st process, (b) 2nd process, and (c) 3rd process of the joining process of this invention.

  Hereinafter, the present invention will be described in detail. First, the structure of the semiconductor device 150 of the present invention will be described with reference to FIG. 10A and 10B show the appearance of the semiconductor device 150, FIG. 10A is a top view, and FIG. 10B is a cross-sectional view taken along line A-A 'in FIG.

  In this embodiment, a collector electrode (not shown) is bonded to the wiring layer 102 on the ceramic insulating substrate 103 on one surface of the semiconductor element 101 by a bonding layer 105 described below. Further, the back wiring layer 122 of the ceramic insulating substrate 103 is bonded to the support member 110 via the solder layer 109. The ceramic insulating substrate 103, the wiring layer 102, and the back surface wiring layer 122 are referred to as a wiring substrate 123. The wiring layer 102 is a Cu wiring. The bonding layer 105 has a thickness of 80 μm. On the other surface of the semiconductor element 101, the emitter electrode is bonded using the connecting aluminum wire 201, and the aluminum wire 201 is bonded to the wiring layer 102 on the ceramic insulating substrate 103. The wiring layer 102 is made of copper.

  The other reference numerals in FIG. 10 indicate the case 111, the external terminal 112, the bonding wire 113, and the sealing material 114, respectively. The case 111 accommodates the wiring substrate 123 on which the semiconductor element 101 is mounted, and the inside thereof is filled with a sealing material 114. The sealing material 114 covers the semiconductor element 101 and the like.

  The external terminal is a terminal for taking out electric power to the outside of the semiconductor device 150, and is connected to the wiring layer 102 through the bonding wire 113.

  Next, details of the junction between the semiconductor element 101 and the wiring layer 102 will be described with reference to FIG. FIG. 2 is an enlarged view of B (dotted line portion) in FIG. Here, the description will focus on the structure of the bonding layer 105 that is a feature of the present invention.

  The bonding layer 105 includes a first sintered layer 105a on the semiconductor element 101 side, a second sintered layer 105b provided between the first sintered layer 105a and the wiring layer 102, and a second sintered layer. Of the 105b, the third sintered layer 105c is present in the outer portion of the semiconductor chip disposed above the first sintered layer 105a.

  At this time, by forming a bonding layer by a method described later, the sintered density of each sintered layer is sintered in the order of the first sintered layer 105a, the second sintered layer 105b, and the third sintered layer 105c. The bonding layer 105 is formed so that the density is low. That is, the sintered density is such that the first sintered layer 105a> the second sintered layer 105b> the third sintered layer 105c.

  The first sintered layer 105 a has a size substantially equal to the size of the semiconductor element 101. Therefore, it is shown that the paste is prevented from protruding during the pressurizing process that is performed when the first sintered layer 105a is formed, that is, when the semiconductor element 101 is mounted. Further, since the second sintered layer 105b which is the base is in a porous state, it can be in a state in which it is difficult to protrude during paste application and pressurization for forming the sintered layer. Next, materials used for the bonding layer 105 will be described.

  For the electrode formation on the wiring layer 102 having Cu or Ni plated on the surface, in the case of using the past paste material mainly composed of silver particles having a particle size of 100 nm or less, the Cu, Ni electrode surface Since the oxide layer exists, there is a problem that the bonding material is not bonded. On the other hand, the electrode formation by the noble metal plating method including silver has a complicated mask formation and process, and there are problems of waste liquid treatment, and its application has many obstacles.

  Therefore, in the present embodiment, a silver particle having an average particle diameter of 1 nm to 5 μm, which is a metal particle precursor, an acetic acid compound having an action of reducing silver oxide particles, or an alcohol, and further including an organic solvent. Depending on the material, a silver electrode is formed on a Cu or Ni electrode by heating at 300 ° C. in a reducing atmosphere. In this process, by adding a reducing agent composed of a compound to the metal particle precursor, the metal particle precursor is reduced at a lower temperature than when the metal particle precursor alone is thermally decomposed. A phenomenon is used in which silver particles of 100 nm or less are produced, and metal particles are fused with each other to perform sintering, that is, electrode formation.

  By using this material, the oxides on the Cu and Ni surfaces can be removed for bonding, so that excellent bonding strength can be obtained for Cu and Ni electrodes.

  Next, a method for forming the bonding layer 105 will be described with reference to FIG.

  First, as shown in FIG. 11A, the above-mentioned bonding paste material is applied on the wiring layer 102 and sintered without pressure to form the second sintered layer 105b and the third sintered material. A precursor sintered layer 105e of the layer 105c is formed. By sintering the paste material without applying pressure, the sintered density of the precursor sintered layer 105e can be lowered and the porosity can be increased. By lowering the sintered density of the precursor sintered layer 105e in the process, a region for absorbing the paste material is formed when the first sintered layer 105a is formed, and the protrusion of the paste can be further suppressed.

  Subsequently, as shown in FIG. 11B, a bonding paste material 101a1 is applied on the precursor sintered layer 105e. At this time, the area to which the paste material 101a1 is applied needs to be an area inside the precursor sintered layer 105e. This is because the protrusion of the paste material 105a1 cannot be suppressed unless it is applied in this way. When the application of the paste material 105a1 is completed, the semiconductor element 101 is disposed thereon. Then, as shown in the figure, sintering is performed while applying pressure from the upper surface of the semiconductor element 101.

  When the sintering of the paste material 105a1 is completed, a first sintered layer 105a, a second sintered layer 105b, and a third sintered layer 105c are formed as shown in FIG.

  The material for forming the precursor sintered layer 105e and the material for forming the first sintered layer 105a may be the same, but acetic acid added as a reduction accelerator to the material for forming the precursor sintered layer 105e. When using a system compound or alcohol, in addition to promoting bonding with the base metal electrode, there is a lot of gas during the reaction, so the state of the sintered layer due to the reduced silver particles is not a high-density sintered state but a sponge-like state It is more preferable because it can be in a porous state.

  Further, more detailed joining conditions and material conditions will be shown in experimental examples.

  Next, the detailed structure of the precursor sintered layer 105e of the second sintered layer 105b and the third sintered layer 105c will be described. By using the above-described materials, silver particles having an average particle diameter of 100 nm or less are produced, and the silver particles are fused with each other to be joined. FIG. 1 is a diagram for explaining the mechanism. The mechanism leading to the bonding is as follows: (1) The generated silver particles of 100 nm or less form a thin film layer 105d on the surface of the counterpart electrode (Cu, Ni), (2) This layer is the counterpart metal electrode plate, that is, Cu or Ni. Part of the crystal grows in the same direction as the crystal growth direction, and (3) a sintered layer is formed by the fusion of silver particles that did not contribute to the formation of the thin film layer. Then, a pre-sintered layer 105e including the thin film layer 105d is formed.

  By being able to have such a structure, the sintering density as the precursor sintered layer 105e is low, but it is high at the interface with the wiring layer 102, so that the resistance with the wiring layer 102 can be reduced. It becomes possible.

  As described above, in the present embodiment, the sintered layer on the wiring layer 102 side is sintered without pressure to create the low-density precursor sintered layer 105e, and then the precursor sintered layer 105e. Apply paste material in a small area and pressurize and bond. By creating a bonding layer using this process, the second sintered layer 105b is created by absorbing the paste that may protrude from the precursor sintered layer 105e by pressurization, and corresponds to the paste application region. It is possible to create the third sintered layer 105c in which the paste material that has not been absorbed by the low-density sintered layer in the region to be absorbed is absorbed in the region around the paste material application region. The protrusion can be suppressed.

  In addition, by forming the bonding material 105 by applying pressure to the paste material 105a1 after forming the precursor sintered layer 105e, the precursor sintering whose resistance is increased due to the low sintering density due to the fact that it was created without pressure. Among the layers 105e, the sintered density of a part of the sintered layers (that is, the portion corresponding to the second sintered layer 105b) can be increased. Therefore, the sintering density of the bonding layer from the semiconductor element 101 to the wiring layer 102 can be kept sufficiently high while preventing the paste from protruding, and an increase in resistance from the semiconductor element 101 to the wiring layer 102 is prevented. It becomes possible.

  Further, the first layer closest to the semiconductor element 101 is formed by setting the sintered density of the bonding layer 105 such that the first sintered layer 105a> the second sintered layer 105b> the third sintered layer 105c. Since the sintered density of the sintered layer 105a increases, the structure of the bonding layer 105 with the lowest contact resistance at the interface between the semiconductor element 101 and the first sintered layer 105a can be obtained.

  Further, the surface of the wiring layer 102 actually has undulations of several μm to several tens of μm as shown in FIG. In the case of not using two sintered layers as shown in FIG. 5 to be described later, as shown in FIG. 6, as shown in FIG. 6, the top of this swell is densely sintered (densely sintered portion 105 g), and the valley is roughly sintered (roughly sintered portion). 105h). As a result, as shown in FIG. 6, the sintered layer has a mixed form of coarse and dense states.

  When the rough region becomes the end portion of the semiconductor element 101, this becomes a starting point of crack extension, and it is difficult to ensure long-term reliability. Furthermore, in the undulation valley, when it becomes a state close to a cavity, it becomes a heat accumulation part, which may cause deterioration of thermal resistance.

  The embodiment shown in FIG. 2 is also a form for solving such a problem, and the second sintered layer 105b fills the swell of the substrate electrode surface and has a certain degree of porous property. A uniform pressurization state can be secured during the pressurization process when forming one sintered layer 105a, and as a result, the sintered density of the first sintered layer 105a can be made uniform.

  Further, unlike the present embodiment, the first sintered layer 105a is not a simple two-layer sintered structure, but the second sintered layer 105b and the third sintered layer 105c (that is, close to the wiring layer 102). The structure having a higher density than the sintered layer disposed on the side is very effective for ensuring long-term reliability by repeatedly applying thermal stress.

  As shown in FIG. 7A, in the simple two-layer structure, cracks often extend at the interface between the semiconductor element 101 and the first sintered layer 105a, and the crack extension at the interface has a very short connection life.

  On the other hand, in the structure of the present invention, the crack extends into the sintered layer as shown in FIG. This is because the semiconductor element 101 side is sintered at high density, so that the bonding strength including the interface with the chip is very high, and thus long-term reliability can be ensured.

  Presenting such a fracture mode without interface fracture is an indispensable index for semiconductor device design. If the interfacial fracture is dominant, the life cannot be determined, and reliability design is difficult or impossible.

In the structure of the present invention, the base electrode plate material may be precious metal plated in addition to copper and nickel. The first sintered layer and the second and third sintered layers are not limited to silver, but may be copper and copper, or a combination of silver and copper.
《Experimental example》
Hereinafter, a process for mounting the semiconductor element 101 on the wiring board 123 for explaining the experimental example will be described. The semiconductor element 101 is an IGBT and a diode element, each having the same size and approximately 13 mm × 13 mm.

  First, a mixture of silver oxide particles containing 5 wt% cetyl alcohol and having an average particle diameter of 2 μm and a diethylene glycol monobutyl ether solvent was prepared as a silver oxide paste. Using this paste, this paste was printed using a metal mask on a wiring board 123 having a solid copper wiring electrode and an insulating part made of silicon nitride. The opening size of the metal mask is about 15 mm × 15 mm, which is larger than the power semiconductor element.

  After printing, a silver electrode was formed on the copper electrode by holding in a hydrogen atmosphere at a heating rate of 10 ° C. and a peak temperature of 300 ° C. for 15 minutes. At this time, the shape of the silver electrode is determined by a mask corresponding to the size and arrangement position of the target semiconductor element. The silver electrode after sintering was in a porous state with a porosity of about 10%. This state is as shown in FIG. Many cavities are scattered in the sintered layer, and a part of the crystal grows in a part of the interface with the counter electrode in the same direction as the crystal growth direction of copper as the counter electrode.

  Next, another silver oxide paste is applied on the formed silver electrode. The paste used at this time was a small amount of a member that actively promotes the reduction of silver oxide, such as alcohol, and the sintered density of the silver sintered layer after the reduction of silver oxide was previously formed on the copper electrode. Make it higher than the layer. This paste can be satisfactorily bonded to the noble metal electrode, but has poor bonding properties to the base metal, so that the outermost electrode of the semiconductor element needs to be a noble metal.

  The paste coating method uses a metal mask here as well. The opening size of the mask is about 12 mm × 12 mm which is the same as the semiconductor element size. In addition, if the area area is 64% or less with respect to the area of the precursor sintered layer 105e, the protrusion can be sufficiently suppressed. After the application, the target semiconductor element is placed and heated by applying pressure. At this time, the pressure was 0.3 MPa and the temperature was 250 ° C. and held for 20 minutes. The atmosphere was air.

In the semiconductor device produced by the production method, no protruding portion of the paste was formed.
<< Comparative Example 1 >>
When the semiconductor device was produced with the same size as the first sintered layer 105a, the second sintered layer 105b, and the semiconductor element 101, the protruding sintered portion 105f was formed as shown in FIG. If this peels off due to the influence of external force or vibration, it becomes conductive dust and may cause a short circuit failure or the like, which is not preferable.

In addition, as shown in FIG. 4, the protrusions 105f were increased. In such a case, when the protruding sintered portion covers the passivation film formed on the semiconductor chip, the electric field is disturbed, which may affect semiconductor characteristics such as withstand voltage. Furthermore, if it comes into contact with the electrode on the chip surface, a short circuit failure occurs, which is not preferable.
<< Comparative Example 2 >>
A second sintered layer 105b was not provided, and a sintered layer having a size equivalent to that of the semiconductor element was prepared. In this case, since there is no porous precursor sintered layer 105e as shown in FIG. 5, the protruding portion 105f is formed as in FIG.

As described above, by using the invention of the present embodiment, it was possible to produce a semiconductor device in which the protrusion of paste was suppressed even when pressure was applied and sintering was performed.
<< Second Embodiment >>
FIG. 8 shows a second embodiment of the present invention. The difference between this embodiment and the first embodiment is that the second sintered layer 205b and the third sintered layer 205c are made of copper. In addition, the same drawing number as the drawing number used in 1st embodiment is used for the same structure as 1st embodiment.

  A copper wiring-formed silicon nitride circuit board was used as the wiring board 123. After forming a copper electrode of 15 mm × 15 mm on the copper wiring-formed silicon nitride circuit substrate using a mixture of cupric oxide particles having an average particle diameter of 2 μm and diethylene glycol monobutyl ether containing 0.5 wt% of copper formate A semiconductor device in which a silver oxide paste composed of a mixture of silver oxide particles having an average particle diameter of 2 μm containing stearic acid of 0.1 wt% and a diethylene glycol monobutyl ether solvent is printed thereon and a 12 mm × 12 mm IGBT chip is bonded. It is.

  The IGBT chip was bonded at a peak temperature of 250 ° C. under a nitrogen atmosphere by applying 0.1 MPa pressure. The electrode structure on the junction surface (collector side) of this IGBT is Al / Ti / Ni / Au, and the outermost surface is Au. In this structure, since the second sintered layer 205b is a copper sintered layer bonded to the copper electrode and the first sintered layer 205a bonded to the semiconductor element 101 having the gold electrode is silver, the bonding strength at each interface Is higher than in the first embodiment.

  On the other hand, the interface between the first sintered layer 205a and the second sintered layer 205b is an interface between sintered copper and sintered silver, and in addition to the bonded structure shown in FIG. An anchor effect is also added, and this interfacial strength becomes very strong.

In addition, since a part of the structure is a base metal, there is an advantage that the migration resistance is improved and the cost is reduced as compared with the first embodiment. .
<< Third embodiment >>
FIG. 9 shows a third embodiment of the present invention. The difference between this embodiment and the first embodiment is that the connection layer 305 (the first sintered layer 305a, the second sintered layer 305b, and the third sintered layer 305c) is all made of copper. is there. In addition, the same drawing number as the drawing number used in 1st embodiment is used for the same structure as 1st embodiment.

  As the wiring substrate 123, a silicon nitride circuit substrate formed with copper wiring was used as in the second embodiment. After forming a copper electrode of 15 mm × 15 mm using a mixture of cupric oxide particles having an average particle size of 2 μm and diethylene glycol monobutyl ether containing 0.5 wt% of copper formate with respect to a silicon nitride circuit board formed with copper wiring, This is a semiconductor device in which a copper oxide paste composed of a mixture of cupric oxide particles having an average particle size of 2 μm and no alpha terpineol, which does not contain copper formate, is printed, and a 12 mm × 12 mm IGBT chip is bonded.

  The IGBT chip was bonded at a peak temperature of 300 ° C. under a hydrogen atmosphere by applying 0.3 MPa pressure. The electrode structure on the IGBT junction surface (collector side) is Al / Ti / Ni, and the outermost surface is Ni. In this structure, the first sintered layer 305a and the second sintered layer 305b are both copper, the wiring board material is copper, and the outermost surface electrode material of the semiconductor element 101 is Ni without Au. Therefore, in addition to the extremely high migration resistance as compared with the first embodiment, the structure is a low-cost structure because it has a structure in which noble metals are omitted.

  The semiconductor device of the present invention can be applied to various power conversion devices. By applying the semiconductor device of the present invention to the power conversion device, long-term reliability can be ensured even if it can be mounted in a place of a high temperature environment and does not have a dedicated cooler.

  Further, the inverter device and the electric motor can be incorporated in the electric vehicle as a power source. In this car, the drive mechanism from the power source to the wheels has been simplified, so the shock at the time of shifting is reduced and smooth running is possible compared to the conventional car that has been shifting due to the difference in gear engagement ratio. Thus, vibration and noise can be reduced as compared with the conventional case.

  Furthermore, the inverter device incorporating the semiconductor device of this embodiment can be incorporated into an air conditioner. In this case, higher efficiency can be obtained than when a conventional AC motor is used. Thereby, the power consumption at the time of air-conditioning machine use can be reduced. Moreover, the time until the room temperature reaches the set temperature from the start of operation can be shortened compared to the case where the conventional AC motor is used.

The same effect as that of the present embodiment can be enjoyed even when the semiconductor device is incorporated in a device that stirs or flows another fluid, such as a washing machine or a fluid circulation device.
[Other Embodiments]
The first to third embodiments described above show examples of realization of the present invention. Therefore, the technical scope of the present invention should not be limitedly interpreted by these. This is because the present invention can be implemented in various forms without departing from the gist or main features thereof.

  For example, in each of the first to third embodiments, a part of the configuration can be replaced with the configuration described in the other embodiments or modifications. In addition, the configuration described in another embodiment or modification may be added to the configuration described in a certain embodiment or modification. Furthermore, as long as it is included in the technical scope of the present invention, a part of the configuration described in each of the first to third embodiments can be deleted.

DESCRIPTION OF SYMBOLS 101 ... Semiconductor element 102 ... Wiring layer 105 ... Bonding layer 105a ... 1st sintered layer 105b ... 2nd sintered layer 105c ... 3rd sintered layer

Claims (8)

In a semiconductor device having a semiconductor element and an insulating substrate,
A wiring layer is formed on the insulating substrate,
A bonding layer made of sintered metal is configured between the semiconductor element and the wiring layer,
The bonding layer has a first sintered layer disposed on the side closer to the semiconductor element, and a sintered layer disposed on the side closer to the wiring layer,
The semiconductor device according to claim 1, wherein the sintered layer closer to the wiring layer is formed wider than the first sintered layer. The semiconductor device according to claim 1,
The sintered layer on the side close to the wiring layer includes the second sintered layer facing the sintered layer on the side close to the semiconductor element, and a third sintered layer other than the second sintered layer. Configured,
The third sintered layer has a higher porosity than the second sintered layer, and the first sintered layer has a lower porosity than the second sintered layer. . The semiconductor device according to claim 2,
The semiconductor device, wherein the first sintered layer, the second sintered layer, and the third sintered layer are each composed of silver. The semiconductor device according to claim 2,
The first sintered layer is made of silver, and the second sintered layer and the third sintered layer are made of copper. The semiconductor device according to claim 2,
The semiconductor device, wherein the first sintered layer, the second sintered layer, and the third sintered layer are each made of copper. The semiconductor device according to claim 1,
The semiconductor device according to claim 1, wherein an outermost surface of the wiring layer disposed under the second sintered layer is copper or nickel. A first step of forming a sintered layer without pressure on a wiring layer provided on an insulating substrate;
After the first step, the method includes a second step of pressurizing together with the semiconductor element on the sintered layer to form a sintered layer different from the sintered layer and joining the semiconductor element. A method for manufacturing a semiconductor device. 8. The semiconductor device according to claim 7, wherein the sintered layer formed without pressure on the wiring layer is formed by sintering a metal oxide paste that can be bonded to nickel or copper. Production method.