WO2016079881A1 - Semiconductor power module, method for manufacturing same and mobile object - Google Patents

Semiconductor power module, method for manufacturing same and mobile object Download PDF

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Publication number
WO2016079881A1
WO2016079881A1 PCT/JP2014/080978 JP2014080978W WO2016079881A1 WO 2016079881 A1 WO2016079881 A1 WO 2016079881A1 JP 2014080978 W JP2014080978 W JP 2014080978W WO 2016079881 A1 WO2016079881 A1 WO 2016079881A1
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semiconductor
power module
solder
solder alloy
insulating substrate
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PCT/JP2014/080978
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French (fr)
Japanese (ja)
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高彰 宮崎
靖 池田
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株式会社日立製作所
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Priority to PCT/JP2014/080978 priority Critical patent/WO2016079881A1/en
Priority to JP2016559781A priority patent/JP6429208B2/en
Publication of WO2016079881A1 publication Critical patent/WO2016079881A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/52—Mounting semiconductor bodies in containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48095—Kinked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H01L2224/48139—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate with an intermediate bond, e.g. continuous wire daisy chain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83101—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • the present invention relates to a semiconductor power module using lead-free solder as a bonding material and a manufacturing method thereof.
  • the present invention relates to a power module that has a high joint temperature.
  • the power module has a structure in which a semiconductor element and an insulating substrate or a heat dissipation base are joined with solder or the like.
  • Solder which is a connecting member used for electrical connection of parts of electrical and electronic equipment, generally contained lead.
  • the lead regulations pointed out have begun. In Europe, the ELV Directive (End-of Life Life Vehicles Directive), which restricts the use of lead in automobiles, and the RoHS (Restriction of the use of certain Hazardous Substances in electrical) that prohibits the use of lead in electrical and electronic equipment and electronic equipment) directive was enforced.
  • solder containing lead (Pb) has been used as a connecting member (bonding material) for semiconductor devices that are required to have high heat resistance, particularly semiconductor devices used in the fields of automobiles, construction equipment, railways, and information equipment.
  • solder containing lead (Pb) has been used as a connecting member (bonding material) for semiconductor devices that are required to have high heat resistance, particularly semiconductor devices used in the fields of automobiles, construction equipment, railways, and information equipment.
  • lead-free connection members to reduce environmental burdens.
  • Si (silicon) semiconductor elements In recent years, development of wide gap semiconductors such as SiC and GaN that can operate at high temperature and can reduce the size and weight of devices has been promoted.
  • the upper limit of the operating temperature of Si (silicon) semiconductor elements is 150 to 175 ° C., whereas SiC semiconductor elements can be used at 175 ° C. or higher.
  • Patent Document 1 Japanese Patent Laid-Open No. 2010-226115.
  • This Patent Document 1 states that “as a connection method with a heat resistance of 200 ° C., an interfacial reaction is suppressed by combining a Sn-based solder containing Cu6Sn5 phase and Ni-based plating from room temperature to 200 ° C., and a heat resistance of 200 ° C. or higher.
  • Semiconductor device (see abstract) ”has been disclosed.
  • Patent Document 2 Japanese Patent Laid-Open No. 2009-255176.
  • This patent document 2 states that “the soldering portion has a composition of Sb of 10 to 40% by mass, Cu of 0.5 to 10% by mass, and a balance of Sn, depending on the solder composition.
  • the problem of the solidification range between the line temperature and the liquidus temperature is solved, and in order to improve the mechanical strength, any one or more of Co, Fe, Mo, Cr, Ag, Bi elements And adding at least one of Ce and Ca as an oxidation-inhibiting element (see summary).
  • a large current is often applied as compared with other electronic components, so that a semiconductor chip (hereinafter also referred to as a chip) generates heat, and stress is applied to the joint.
  • a semiconductor chip hereinafter also referred to as a chip
  • thermal stress is applied due to the difference in coefficient of linear expansion between the chip and the insulating substrate, and between the insulating substrate and the heat dissipation base, and a crack develops from the end part.
  • Grain boundary destruction develops at the center of the joint due to temperature non-uniformity occurring in the joint due to transient heat generation of the chip.
  • the reaction progresses at the bonding interface and the bonding reliability decreases.
  • Patent Document 1 Japanese Patent Application Laid-Open No. 2010-226115 discloses a power module and an inverter using Sn-3 to 10 wt% Cu solder at the joint.
  • the technique described in Patent Document 1 has a problem that when Sn—Cu solder is used for the joint, cracks grow quickly and reliability decreases in a high temperature environment.
  • Patent Document 2 Japanese Patent Laid-Open No. 2009-255176
  • a high-temperature lead-free solder alloy composed of Sb 10 to 40% by mass, Cu 1 to 9% by mass and the balance Sn is disclosed.
  • the structure of the joint and the joining temperature are not defined, and these are unclear.
  • An object of the present invention is to provide a technique capable of improving the reliability of a semiconductor power module under a high temperature environment.
  • the semiconductor power module according to the present invention includes a semiconductor element and a bonding material bonded to the semiconductor element, and the semiconductor element and the insulating substrate, or the insulating substrate and the heat dissipation base are Cu1-7. Bonded by the above-mentioned bonding material comprising wt%, Sb 3 to 15 wt%, and the remaining Sn, and the bonding material is bonded at a temperature of 280 ° C. or higher.
  • another semiconductor power module includes a semiconductor element and a bonding material bonded to the semiconductor element. Further, the first Cu—Sn compound, the Sn—Cu—Sb layer, and the second Cu—Sn compound at the junction between the semiconductor element and the insulating substrate or between the insulating substrate and the heat dissipation base. Assuming that the thickness ratio of the above-mentioned joining portion obtained by adding the respective thicknesses is 100, the ratio of the thicknesses of the first Cu—Sn compound and the second Cu—Sn compound is 1 or more and 10 or less. .
  • the bonding layer between the semiconductor element and the insulating substrate or between the insulating substrate and the heat sink is formed by the first Cu—Sn compound, the Sn—Cu—Sb layer, and the first layer.
  • the thickness of the bonding layer is 100, the thicknesses of the first Cu-Sn compound and the second Cu-Sn compound are 1 or more and 10 or less.
  • the semiconductor power module is provided.
  • the method for manufacturing a semiconductor power module according to the present invention includes a semiconductor element and an insulating substrate, or the insulating substrate and a heat dissipation base, Cu 1 to 7 wt%, Sb 3 to 15 wt%, and the remaining Sn. And joining the semiconductor element and the insulating substrate, or joining the insulating substrate and the heat dissipation base.
  • the reliability of the semiconductor power module in a high temperature environment can be improved.
  • FIG. 1 is a sectional view showing an example of the structure of the main part of a semiconductor device according to an embodiment of the present invention, and FIG. It is sectional drawing.
  • a semiconductor device 9 shown in FIG. 1 is a semiconductor power module using a lead-free solder alloy.
  • a schematic configuration of a main part of the semiconductor device 9 will be described.
  • a semiconductor chip 1 as a semiconductor element is a ceramic substrate (covered member). Solder-bonded onto a bonding member (insulating substrate) 5 via a solder alloy (bonding material) 2b.
  • the solder alloy 2b is a solder that does not contain lead (Pb).
  • the ceramic substrate 5 on which the semiconductor chip 1 is mounted is soldered via a solder alloy (joining material) 2c on a heat radiating metal plate 12 which is a heat radiating member (heat radiating base).
  • the solder alloy 2c is also a solder containing no lead (Pb).
  • a wiring portion 5c is formed on the upper surface 5a of the ceramic substrate 5, and a Ni plating layer (Ni metallized layer) 3 as shown in FIG. 2, for example, is formed on the surface of the wiring portion 5c. .
  • a conductor portion 5d is formed on the lower surface 5b of the ceramic substrate 5. The conductor portion 5d is, for example, the Ni plating layer 3 described above.
  • the ceramic substrate 5 is joined to the solder alloy 2b and the solder alloy 2c through the Ni plating layer 3, respectively.
  • At least one of the solder alloy 2 b and the solder alloy 2 c, or both of the solder is Cu 1 to 7 wt (wt)%, Sb 3 to 15 wt (wt)%, It consists of the remainder Sn.
  • the thickness of the solder alloy 2c is larger than the thickness of the solder alloy 2b.
  • the thickness of the solder alloy 2b is about 0.1 mm, and the thickness of the solder alloy 2c is 0.2 to 0.4 mm.
  • solder joining by the lead-free solder alloy of the present embodiment will be described with reference to FIG.
  • a solder foil (joining material) 2a is sandwiched from above and below by a ceramic substrate 5 which is a connected material to which Ni plating 3 is applied (or ceramic substrate 5 and semiconductor). It may be sandwiched between the chip 1).
  • the solder foil (joining material) 2a has a composition composed of Cu 1 to 7 wt%, Sb 3 to 15 wt%, and the remaining Sn. That is, solder bonding is performed using a solder foil 2a having a composition including Cu 1 to 7 wt%, Sb 3 to 15 wt%, and the remaining Sn. That is, in the composition of the solder foil 2a, Sn has the highest content compared to Cu and Sb. Further, the Cu—Sn compound 6 is contained in the solder before joining.
  • the solder foil 2a is heated at a temperature of 280 ° C. or higher.
  • the Cu—Sn compound for example, Cu 6 Sn 5
  • the Cu—Sn based compound layer 4 is formed on the Ni plating layer 3.
  • Sb contained in the solder dissolves in the Sn phase.
  • a Cu—Sn-based compound layer 4 is formed on the Ni plating layer 3 applied to the ceramic substrate 5 as shown after bonding in FIG.
  • a solder alloy 2 mainly composed of Sn containing Sb contained in the solder is formed between the Cu—Sn compound layer 4 and the Cu—Sn compound layer 4.
  • the structure of the solder joint portion is a three-layer structure including the solder alloy 2 and the Cu—Sn-based compound layer 4 formed on the upper and lower layers thereof.
  • the solder alloy 2 is thicker than the Cu—Sn compound layer 4. In other words, the thickness of the solder alloy 2 serving as an intermediate layer in the three-layer structure is the thickest.
  • FIG. 3 is a cross-sectional view (cross-sectional SEM image) showing the structure of the solder joint portion according to the embodiment of the present invention
  • FIG. 4 is a cross-sectional view showing the structure of the solder joint portion of the comparative example.
  • the compound layer mainly composed of the Cu—Sn-based compound layer 4 forms the joint interface and the solder. It becomes a barrier layer with the alloy 2.
  • the Cu—Sn-based compound layer 4 is obtained by replacing a part of the Cu—Sn compound with another element, and Cu—Sn is the main constituent element.
  • the composition with the largest proportion of the composition constituting the bonding layer is called the main constituent element.
  • connection structure of the present invention Cu contained in the solder dissolves only 0.7 wt% in Sn, so that it is precipitated almost as a Cu—Sn compound at the joint interface. Therefore, the joint after soldering is composed of the first Cu—Sn compound layer, the Sn—Cu—Sb layer, and the second Cu—Sn compound layer.
  • the first Cu—Sn compound: Sn—Cu—Sb layer: second Cu—Sn compound has a thickness of 0.5 ⁇ m: 49 ⁇ m: 0. 5 ⁇ m to 5 ⁇ m: 40 ⁇ m: 5 ⁇ m.
  • the first Cu—Sn compound: Sn—Cu—Sb layer: second Cu—Sn compound is 1 ⁇ m: 98 ⁇ m: 1 ⁇ m to 10 ⁇ m: 80 ⁇ m: 10 ⁇ m.
  • the first Cu—Sn compound layer has a ratio of 1 or more and 10 or less. As described above, this varies depending on the composition ratio of the solder implemented in the present invention. That is, the thickness ratio of the Sn—Cu—Sb layer is a value obtained by subtracting the thickness ratio of the first Cu—Sn compound layer and the second Cu—Sn compound layer from 100, which is the ratio of the total thickness. It means that there is.
  • the solder bonding temperature is lower than 280 ° C., as shown in the structure of the comparative example in FIG. 4, the Cu—Sn compound 6 in the solder foil 20 is distributed in a floating island shape in the bonding layer. It does not become the structure of the junction part (after joining) shown in FIG. 2 of this Embodiment. Therefore, as shown in Comparative Examples 6 and 7 in FIG. 8 to be described later, in the joint structure divided into a floating island shape in FIG. 4, when the joint temperature is 280 ° C. or lower, the stability of the joint interface is lowered.
  • the thickness of the Sn—Cu—Sb layer at the joint is less than 50 ⁇ m, the amount of liquid phase generated at the time of joining is small and void (bubble) discharge is reduced, and a large amount of voids remain in the joint layer. Resulting in. Further, when the average thickness of the solder joint becomes thicker than 400 ⁇ m, the amount of Cu—Sn compound contained in the solder becomes excessive, and not only Cu—Sn compound is formed at the joint interface but also in the joint layer. The crack progresses faster because it remains in a floating island shape. Therefore, it is desirable that the thickness of the solder after solder joining is 50 ⁇ m or more and 400 ⁇ m or less.
  • the Cu—Sn compound layer 4 mainly composed of the Cu—Sn compound is used as a barrier between the connection interface and the solder. Since it becomes a layer, the growth of the compound layer due to the reaction at the connection interface and the accompanying formation of voids can be suppressed.
  • solder of the present application does not contain a noble metal in its composition, it is a low-cost material compared to Sn3Ag0.5Cu, which is a standard lead-free solder.
  • FIG. 5 is a plan view of the joint showing the definition of the void ratio in the embodiment of the present invention
  • FIG. 6 is a plan view of the joint showing the definition of the crack in the embodiment of the present invention
  • FIG. 7 is a comparative example. It is sectional drawing which shows the destruction condition at the time of intermittent electricity supply.
  • FIG. 5 shows the progress of the void 7, and the area ratio of the void 7 in the solder joint can be measured by ultrasonic flaw detection.
  • the void ratio is obtained by dividing the total area of the void 7 by the area in the plane direction of the bonding layer in the plane direction of the solder alloy 2 that is the bonding portion.
  • FIG. 6 shows cracks 8 generated in a solder joint due to thermal stress after performing a temperature cycle test of about 500 cycles, with 15 minutes at ⁇ 55 ° C. and 15 minutes at 200 ° C. It is.
  • the crack progress rate in the solder joint portion was measured by ultrasonic flaw detection on the semiconductor device 9 thus subjected to the temperature cycle test.
  • the crack progress rate is obtained by dividing the total area of the crack 8 by the area of the bonding layer in the plane direction in the plane direction of the solder alloy 2 that is the solder joint portion.
  • the void ratio exceeds 10%
  • the crack 8 is preferentially developed from around the void due to the temperature cycle, and the reliability is lowered at an early stage. Therefore, long-term reliability can be ensured by reducing the void ratio.
  • heat is generated by energizing the semiconductor element.
  • the crack growth rate exceeds 20%
  • the heat generated in the semiconductor element is deteriorated, the temperature of the semiconductor element is increased, and the reliability is rapidly decreased.
  • the material of the material to be joined such as the semiconductor chip 1 and the substrate
  • various metals such as Cu, Ni, Au, Ag, Pt, Pd, Ti, TiN, Fe-based alloys such as Fe—Ni and Fe—Co, etc. Alloys are applicable.
  • the material to be joined is Ni metallized.
  • the barrier layer of the Cu—Sn compound layer 4 is formed on the Ni plating layer 3 to suppress the diffusion of Ni, the bonding interface is kept stable, and the high temperature environment. This is because better reliability can be maintained below.
  • Ni when the metallization of the surface of a to-be-joined material is Ni, the oxidation of Ni itself becomes a problem and wettability may be inhibited. Therefore, Au, Ag, Pt, or Pd that is difficult to oxidize may be laminated on Ni. In other words, it is desirable that the surface of the material to be joined is subjected to metallization such as Ni, Ni / Au, Ni / Ag.
  • the semiconductor chip 1 can be bonded to any semiconductor chip 1 such as Si, SiC, GaAs, CdTe, GaN.
  • the substrate by adding the above metallization, Cu, Al, Cu—Mo, Al—SiC (a composite material of aluminum and silicon carbide), Mg—SiC (a composite material of magnesium and silicon carbide), 42 alloy, CIC (Copper Invar Copper), DBC (Direct Bond Copper), DBA (Direct Bond Aluminum) and other metal substrates bonded together, such as a ceramic substrate (insulating substrate) with high reliability Bonding can be realized.
  • the material to be joined (material to be joined) with Ni metallization is joined by the solder alloy 2 of the present embodiment is described in detail, the material to be joined / Ni / Cu—Sn system Compound / solder alloy / Cu—Sn compound / Ni / bonded material.
  • connection between the semiconductor element and the substrate has been described.
  • such a structure is formed by bonding the semiconductor and the lead, the semiconductor and the heat dissipation substrate, the semiconductor and the frame, the semiconductor and the insulating substrate, or the semiconductor and the general electrode.
  • the configuration described above is not limited to the connection between the semiconductor element and the substrate, and is generally applicable to the case where the first connected member and the second connected member are bonded by the bonding material of the present embodiment. can do.
  • the present invention can be applied to joining a metal plate and a metal plate, a metal plate and a ceramic substrate, or the like.
  • FIG. 8 is an evaluation result diagram showing the results of evaluation of each example and comparative example of the present invention.
  • the semiconductor device 9 shown in FIG. 1 is manufactured using the solder foil (lead-free solder alloy) 2a of Examples 1 to 18 shown in FIG. 8, and the void ratio, the bonding interface stability, the temperature cycle reliability, Intermittent conduction reliability was evaluated and examined.
  • a ceramic substrate 5 on which a Ni plating layer 3 as shown in FIG. 2 is formed, a solder foil 2a having the composition of Examples 1 to 18, a 10 mm square, and a thickness of 0.3 mm The ceramic substrates 5 on which the Ni plating layer 3 was formed were stacked and connected in a heat treatment furnace in a 100% H 2 atmosphere.
  • the temperature cycle reliability is determined by measuring the crack growth rate after conducting a temperature cycle test of about 500 cycles, assuming 15 minutes at -55 ° C and 15 minutes at 200 ° C.
  • the crack growth rate which is a reliability criterion, was 20% or less, and the case where the semiconductor element normally operated was evaluated as ⁇ , and the others were evaluated as ⁇ .
  • Interfacial stability was evaluated as “ ⁇ ” when Ni plating remained after holding at 200 ° C. for 1000 hours, and “X” when disappearance was confirmed even partially. This is because when Ni plating disappears, diffusion proceeds between the material to be joined and the solder alloy, an intermetallic compound is formed, voids 7 are generated due to the volume difference, and long-term reliability cannot be maintained.
  • the heat conduction fatigue reliability is general in which the semiconductor chip 1 generates heat by energization, and after reaching 175 ° C., the current is turned off and cooling to 25 ° C. is performed as one cycle, so that the cooling semiconductor device can obtain a certain reliability.
  • the thermal resistance of the semiconductor chip 1 is measured after a 5000 cycle test, which is a reference thermal fatigue test. Then, when the thermal resistance was increased by less than 20% and the semiconductor chip 1 normally operated, the evaluation was evaluated as “ ⁇ ” and the others were evaluated as “X”.
  • the overall evaluation was evaluated as ⁇ when the evaluation was good under all conditions, and ⁇ when there was one that could not meet the reliability standards, because reliability under a high temperature environment could not be secured.
  • the bonding material having a good crack growth rate in the temperature cycle test is Sn 3 wt% or more 7 wt% or less and 9 wt% or more 11 wt% or less Sb. It was confirmed that it was added.
  • the solder bonding temperature was 300 ° C. was evaluated, and it was confirmed that the same structure after bonding as in the case of 280 ° C. was obtained even at 300 ° C. That is, the structure after joining shown in FIG. 2 can be obtained by joining at a temperature of 280 ° C. or more and 300 ° C. or less using the solder (joining material) of Examples 1 to 18 shown in FIG. In consideration of the influence of heat on other members, it is desirable to join at a temperature as low as possible even at 280 ° C. or higher.
  • Cu—Sn compound is formed at the bonding interface by adding Cu at 1 wt% or more and 7 wt% or less and bonding at a bonding temperature of 280 ° C. or higher.
  • Example 1 shown in FIG. 8 the temperature cycle reliability can be maintained by adding more than 1% by weight of Sb.
  • Comparative Example 6 when 15% or more of Sb is added, the void ratio is evaluated as x, and the temperature cycle reliability is also x. This is because as the amount of Sb added increases, the amount of Sn—Sb-based compound precipitated in the solder increases, and the viscosity of the solder increases, the void ratio increases, the solder becomes harder, and the temperature cycle reliability decreases. It is.
  • FIG. 9 is a cross-sectional view showing an example of the structure of a semiconductor device (semiconductor power module) using the lead-free solder alloy (joining material) according to the embodiment of the present invention.
  • a semiconductor power module (a semiconductor device, hereinafter also referred to as a semiconductor module) 10 shown in FIG. 9 is a power module mounted on, for example, a railway vehicle or an automobile. Therefore, heat dissipation measures for the power module are required.
  • the configuration of the semiconductor module 10 will be described.
  • the semiconductor chip 1 is formed of a ceramic substrate (chip support member, insulating material) using the solder alloy (any of the solder alloys (joining materials) of Examples 1 to 18) 2b of the present embodiment. (Connected substrate, connected member) 5.
  • a metal plate for heat radiation including a concept of a heat radiation member, a heat radiation base, a heat radiation plate, a heat radiation fin, and a heat sink
  • a ceramic substrate 5 that play a role of releasing heat during operation of the semiconductor chip 1 are provided in this embodiment.
  • Solder alloy 2c (a joining material, any of the lead-free solder alloys of Examples 1 to 18), which is a lead-free solder alloy of the form, is connected.
  • the specific structure of the semiconductor module 10 shown in FIG. 9 will be described.
  • the semiconductor chip 1, and a ceramic substrate (insulating substrate, connected member) 5 which is a chip support member connected to the semiconductor chip 1 via a solder alloy 2b; And a lead (external terminal) 13 electrically connected to the semiconductor chip 1. That is, a conductor portion 5d such as a wiring pattern is formed on the upper surface 5a of the substrate body portion 5e of the ceramic substrate 5, and a solder alloy (any of the lead-free solder alloys of Examples 1 to 18) is formed on the conductor portion 5d.
  • the semiconductor chip 1 is mounted via 2b.
  • a wiring part (wiring pattern) 5c is formed on the upper surface 5a of the substrate body 5e of the ceramic substrate 5, and the leads 13 are electrically connected to the wiring part 5c.
  • the electrode pad 1c and the lead 13 formed on the main surface 1a of the semiconductor chip 1 and the electrode pad 1c and the wiring part 5c are electrically connected by a wire 11 such as a gold wire or a copper wire, respectively. ing.
  • a wiring portion 5c is formed on the lower surface 5b of the substrate body portion 5e of the ceramic substrate 5, and the wiring portion 5c is used for heat dissipation via the solder alloy 2c (any of the lead-free solder alloys of Examples 1 to 18).
  • a metal plate (heat radiating member) 12 is connected.
  • the semiconductor module 10 is manufactured by connecting the semiconductor chip 1 and the ceramic substrate 5 with the solder alloy 2b, and then connecting the ceramic substrate 5 and the heat radiating metal plate 12 with another solder alloy 2c.
  • solder alloy 2b that connects the semiconductor chip 1 and the ceramic substrate 5 is remelted by heating when connecting the ceramic substrate 5 and the heat radiating metal plate 12, the molten solder flows, Misalignment or the like occurs, leading to a failure.
  • a material having a melting point lower than that of the solder alloy 2b it is necessary to employ a material having a melting point lower than that of the solder alloy 2b.
  • the solder alloy 2 of Examples 1 to 18 which is the solder alloy 2 (2b, 2c) of the present embodiment is used, the Cu—Sn-based compound layer 4 having undulations as shown in FIG. Therefore, no solder flow occurs and the semiconductor chip 1 is not displaced.
  • any one of the solder alloys 2 of Examples 1 to 18 is applied to the solder alloy 2b of the semiconductor module 10 shown in FIG. 9, and, similarly to Examples 1 to 18, the bonding temperature is 280 ° C., the holding time is 5 min, N In a 2 + 4% H 2 atmosphere, the semiconductor chip 1 and the Ni / Cu / Si 3 N 4 / Cu / Ni ceramic substrate 5 on which the Ni plating layer 3 is formed are connected, thereby the semiconductor device 9 as a connection body.
  • solder alloy 2c of any of Examples 1 to 18 is sandwiched between the heat dissipation metal plate 12 which is an AlSiC / Ni substrate and the semiconductor device 9, and the bonding temperature is 280 ° C., the holding time is 5 min, no load, 100% H 2.
  • the semiconductor module 10 was formed by connecting in an atmosphere. Therefore, the ceramic substrate 5 and the heat radiating metal plate 12 can be connected without remelting the solder alloy 2b of the semiconductor device 9.
  • the lead 13 is connected to the semiconductor device 9 thus formed, and the electrode pad 1c on the main surface 1a of the semiconductor chip 1 is bonded to the wiring portion 5c and the lead 13 on the ceramic substrate 5 with the wire 11.
  • the semiconductor module 10 can be formed.
  • the interface between the lead-free solder alloy (solder alloy 2) and the semiconductor chip 1, the interface between the lead-free solder alloy and the ceramic substrate 5, and the lead-free solder alloy Ni plating layers 3 are respectively formed at the interfaces of the connecting portions with the heat radiating metal plate 12.
  • solder alloy 2 of the present embodiment any of the lead-free solder alloys of Examples 1 to 18 (solder alloy 2, bonding material)
  • solder alloy 2 of the present embodiment any of the lead-free solder alloys of Examples 1 to 18 (solder alloy 2, bonding material)
  • solder alloy 2 of the present embodiment any of the lead-free solder alloys of Examples 1 to 18 (solder alloy 2, bonding material)
  • the solder alloy 2 of the present embodiment any of the lead-free solder alloys of Examples 1 to 18 (solder alloy 2, bonding material)
  • solder alloy 2 of the present embodiment any of the lead-free solder alloys of Examples 1 to 18 (solder alloy 2, bonding material)
  • connection reliability in each connection part of the lead-free solder alloy (solder alloy 2) can be improved.
  • FIG. 10 is a cross-sectional view showing an example of the structure of a semiconductor device (semiconductor power module) using the lead-free solder alloy according to the embodiment of the present invention.
  • a semiconductor module (semiconductor power module) 19 shown in FIG. 10 has a bonding material such as solder alloy 2b or solder alloy 2b bonded to the front and back surfaces of the semiconductor chip 1, and lead frames 28 are bonded to the bonding materials on both surfaces of the semiconductor chip 1. Further, the heat radiating metal plate 12 is bonded to the lead frame 28 via the insulating heat radiating grease 27.
  • the structure of the solder joint portion of the present embodiment is also applicable to a power module (semiconductor module 19) having a structure in which heat is radiated from the front and back both sides of the semiconductor chip 1 by the heat radiating metal plate 12.
  • the structure of the solder joint portion of the present embodiment can be applied to, for example, a miniaturized semiconductor module 34 that is not mounted with a diode chip as shown in FIG. Since the current density generally increases by downsizing the power module (semiconductor module 34), the temperature of the solder joint also increases. However, this can be realized by using the present invention.
  • FIG. 11 is a partial side view showing an example of a railway vehicle on which the semiconductor module 10 using the lead-free solder alloy of the present embodiment is mounted
  • FIG. 12 shows an example of the internal structure of the inverter installed in the vehicle of FIG. FIG.
  • FIG. 11 shows a railway vehicle 21 provided with a pantograph 22 that is a current collector, and an inverter 23 is provided below the vehicle 21.
  • a plurality of semiconductor modules 10 are mounted on a printed circuit board 25, and a cooling device 24 that cools these semiconductor modules 10 is further mounted.
  • the cooling device 24 is attached so that the plurality of semiconductor modules 10 can be cooled to cool the inside of the inverter 23.
  • the inverter 23 equipped with the plurality of semiconductor modules 10 using the lead-free solder alloy (solder alloy 2) of the present embodiment is provided in the railway vehicle 21, so that the temperature inside the inverter 23 is high. Even when it becomes an environment, the reliability of the inverter 23 and the vehicle 21 provided with the inverter 23 can be improved.
  • the semiconductor device shown in FIG. 13 is, for example, a semiconductor module (semiconductor power module) 18 for an on-vehicle AC generator.
  • FIG. 14 is a perspective view showing an example of an automobile on which the semiconductor power module shown in FIG. 13 is mounted.
  • the configuration of the semiconductor module 18 shown in FIG. 13 will be described.
  • the connection portion connected to the semiconductor chip (diode) 1 and the back surface 1b of the semiconductor chip 1 via the solder alloy (lead-free solder alloy) 2c of the present embodiment.
  • a cylindrical cap (lead electrode body) 15 having Ni plating applied thereto.
  • the semiconductor module 18 is for thermal expansion coefficient difference buffering in which Ni-based plating is applied to a connection portion connected to the main surface 1a of the semiconductor chip 1 via the solder alloy (lead-free solder alloy) 2b of the present embodiment.
  • Buffer material 17, and Cu lead (external terminal) 14 having Ni-based plating applied to the connecting portion connected to the other surface of the buffer material 17 via the solder alloy (lead-free solder alloy) 2 c of the present embodiment.
  • Buffer material 17, and Cu lead (external terminal) 14 having Ni-based plating applied to the connecting portion connected to the other surface of the buffer material 17 via the solder alloy (le
  • the cylindrical cap 15 is filled with a sealing resin 16 that seals part of the semiconductor chip 1, the buffer material 17, the solder alloys 2 b and 2 c, and the Cu lead 14.
  • the buffer material 17 is preferably 30 to 500 ⁇ m. This is because when the thickness of the buffer material 17 is less than 30 ⁇ m, the stress cannot be sufficiently buffered, and cracks may occur in the semiconductor chip 1 and the intermetallic compound. Further, when the thickness of the buffer material 17 exceeds 500 ⁇ m, Al, Mg, Ag, and Zn have a larger coefficient of thermal expansion than the Cu lead 14, and therefore the connection reliability is reduced due to the influence of the difference in coefficient of thermal expansion. There is.
  • the buffer material 17 it is preferable to use any one of Cu / Invar alloy / Cu composite material, Cu / Cu composite material Cu—Mo alloy, Ti, Mo, and W.
  • the buffer material 17 it is possible to buffer the stress generated in the connection portion during the temperature cycle and the cooling after the connection resulting from the difference in thermal expansion coefficient between the semiconductor chip 1 and the Cu lead 14.
  • the stress applied to the semiconductor chip 1 can be reduced, and the formation of cracks in the semiconductor chip 1 can be reduced. Furthermore, in the semiconductor module 18, the connection reliability of the solder connection can be improved.
  • the automobile 32 shown in FIG. 14 is mounted with the semiconductor module 18 shown in FIG. 13, and is a vehicle body 31, a tire 29, the semiconductor module 18, and a mounting member that supports the semiconductor module 18. And a mounting unit 30.
  • the semiconductor module 18 is mounted on the mounting unit 30.
  • the mounting unit 30 is, for example, an engine control unit, and in this case, the mounting unit 30 is disposed in the vicinity of the engine. In this case, the mounting unit 30 is used in a high temperature environment, and the semiconductor module 18 is also in a high temperature state.
  • the solder alloy 2 of the present embodiment (the lead-free solder alloys of Examples 1 to 18 ( By applying any one of the solder alloy 2 and the bonding material), the Cu—Sn based compound layer (see FIG. 2) 4 can be formed thick at each interface at each connection portion of the lead-free solder alloy. . As a result, the interface stability at each solder connection portion can be improved.
  • connection reliability in each connection part of the lead-free solder alloy (solder alloy 2) can be improved. That is, the reliability of the semiconductor module 18 can be increased.
  • FIG. 15 is a cross-sectional view showing the structure of a semiconductor power module of a first modification of the embodiment of the present invention.
  • a semiconductor module (semiconductor power module) 33 shown in FIG. 15 is a power module in which a plurality of semiconductor chips 33 a and a plurality of semiconductor chips 33 b are mounted on the ceramic substrate 5.
  • the semiconductor chip 33a is, for example, a MOS (Metal Oxide Semiconductor) made of SiC
  • the semiconductor chip 33b is, for example, a diode made of SiC.
  • the semiconductor module 33 is also called a full SiC module or the like, and each mounted semiconductor chip is made of SiC.
  • solder alloy (joining material, lead-free solder alloy) 2b is applied to each lower surface side of the semiconductor chip 33a and the semiconductor chip 33b, and a solder is interposed between the ceramic substrate 5 and the heat radiating metal plate 12. Alloy 2c (joining material, lead-free solder alloy) is applied.
  • the lead 13 is electrically connected to the wiring part 5 c of the ceramic substrate 5, and the electrode pads of the semiconductor chips 33 a and 33 b and the wiring part 5 c on the ceramic substrate 5 are connected to the wire 11. It is bonded by.
  • solder alloy 2 of this embodiment any of the lead-free solder alloys of Examples 1 to 18 (solder alloy 2, bonding material)
  • solder alloy 2 of this embodiment any of the lead-free solder alloys of Examples 1 to 18 (solder alloy 2, bonding material)
  • solder alloy 2 of this embodiment any of the lead-free solder alloys of Examples 1 to 18 (solder alloy 2, bonding material)
  • solder alloy 2 of this embodiment solder alloy 2, bonding material
  • connection reliability in each connection part of the lead-free solder alloy (solder alloy 2) can be improved. That is, the reliability of the semiconductor module 33 can be increased.
  • FIG. 16 is a cross-sectional view showing the structure of a semiconductor power module of a second modification of the embodiment of the present invention.
  • the semiconductor module 34 shown in FIG. 16 is a power module in which a plurality of semiconductor chips 34 a are mounted on the ceramic substrate 5.
  • the semiconductor chip 34a is, for example, a MOS MOS, and further includes a diode.
  • the diode is incorporated in the semiconductor chip 34a, and the semiconductor module 34 in this case is also called a full SiC module or the like.
  • solder alloy jointing material, lead-free solder alloy
  • solder alloy 2c jointing material, lead-free solder alloy
  • the lead 13 is electrically connected to the wiring portion 5 c of the ceramic substrate 5, and the electrode pad of the semiconductor chip 30 a and the wiring portion 5 c on the ceramic substrate 5 are bonded by the wire 11. ing.
  • solder alloy 2 of the present embodiment any of the lead-free solder alloys of Examples 1 to 18 (solder alloy 2, bonding material)
  • solder alloy 2 of the present embodiment any of the lead-free solder alloys of Examples 1 to 18 (solder alloy 2, bonding material)
  • solder alloy 2 of the present embodiment any of the lead-free solder alloys of Examples 1 to 18 (solder alloy 2, bonding material)
  • solder alloy 2 of the present embodiment any of the lead-free solder alloys of Examples 1 to 18 (solder alloy 2, bonding material)
  • connection reliability in each connection part of the lead-free solder alloy (solder alloy 2) can be improved. That is, the reliability of the semiconductor module 34 can be increased.
  • the number of chips to be mounted can be reduced by incorporating diodes in the chip.
  • the cost of the semiconductor module 34 can be reduced compared to the semiconductor module 33.
  • the heat radiating metal plate 12 described in the above embodiment may be a plate-shaped heat radiating plate, or a heat radiating member provided with a plurality of fins.
  • the joining structure or joining method of the present invention is not limited to automobiles and railway vehicles, but also solar power generators, power conditioners, wind power generators, construction machines, elevators, air conditioners, machine tools, motors, compressors, and other industrial equipment.
  • the present invention can also be applied to an inverter that operates. It can also be applied to IGBT modules, alternators, AC motors, and the like.

Abstract

A semiconductor device (a semiconductor power module) 9 which comprises: a semiconductor chip 1; a ceramic substrate 5 that is connected to the semiconductor chip 1, with a solder alloy (a lead-free solder alloy) 2b being interposed therebetween; an external terminal that is electrically connected to the semiconductor chip 1; and a metal plate for heat dissipation 12 that is connected to the ceramic substrate 5, with a solder alloy (a lead-free solder alloy) 2c being interposed therebetween. The solder alloys 2b, 2c in the semiconductor device 9 are bonding materials, each of which is composed of 1-7% by weight of Cu and 3-15% by weight of Sb with the balance made up of Sn, and is bonded at a temperature of 280°C or more.

Description

半導体パワーモジュールおよびその製造方法ならびに移動体Semiconductor power module, method for manufacturing the same, and moving body
　本発明は、接合材に鉛フリーはんだを用いた半導体パワーモジュールおよびその製造方法に関する。特に接合部が高温となるパワーモジュールに関する。 The present invention relates to a semiconductor power module using lead-free solder as a bonding material and a manufacturing method thereof. In particular, the present invention relates to a power module that has a high joint temperature.
　パワーモジュールは、半導体素子と絶縁基板、または放熱ベースとをはんだ等で接合した構造となっている。電機・電子機器の部品の電気的接続に使用されている接続部材であるはんだには、一般的に鉛が含まれていたが、近年、環境への意識が高まる中、人体への有害性が指摘される鉛の規制が始まっている。欧州では自動車中の鉛使用を制限するＥＬＶ指令（End-of Life Vehicles directive、廃自動車に関する指令）や、電機・電子機器中の鉛使用を禁止するＲｏＨＳ（Restriction of the use of certain Hazardous Substances in electrical and electronic equipment)指令が施行された。 The power module has a structure in which a semiconductor element and an insulating substrate or a heat dissipation base are joined with solder or the like. Solder, which is a connecting member used for electrical connection of parts of electrical and electronic equipment, generally contained lead. However, in recent years, as environmental awareness has increased, it has been harmful to the human body. The lead regulations pointed out have begun. In Europe, the ELV Directive (End-of Life Life Vehicles Directive), which restricts the use of lead in automobiles, and the RoHS (Restriction of the use of certain Hazardous Substances in electrical) that prohibits the use of lead in electrical and electronic equipment and electronic equipment) directive was enforced.
　これまで、高耐熱性が要求される半導体装置、特に自動車や建機、鉄道、情報機器分野等に用いられる半導体装置の接続部材（接合材）としては鉛（Ｐｂ）入りはんだが使用されてきたが、環境負荷低減のため鉛フリーの接続部材とすることが強く要求されている。 Until now, solder containing lead (Pb) has been used as a connecting member (bonding material) for semiconductor devices that are required to have high heat resistance, particularly semiconductor devices used in the fields of automobiles, construction equipment, railways, and information equipment. However, there is a strong demand for lead-free connection members to reduce environmental burdens.
　また、近年、高温動作が可能で、かつ機器の小型軽量化が可能なＳｉＣやＧａＮ等のワイドギャップ半導体の開発が推し進められている。なお、一般的にＳｉ（シリコン）の半導体素子は動作温度の上限が１５０～１７５℃であるのに対し、ＳｉＣ半導体素子は１７５℃以上での使用が可能となる。 In recent years, development of wide gap semiconductors such as SiC and GaN that can operate at high temperature and can reduce the size and weight of devices has been promoted. In general, the upper limit of the operating temperature of Si (silicon) semiconductor elements is 150 to 175 ° C., whereas SiC semiconductor elements can be used at 175 ° C. or higher.
　そして、使用環境温度が高温になると、接続界面の反応が速くなるため界面の安定性が求められる。また、パワーモジュールでは半導体素子に電流の通電と遮断とが繰り返されるため、熱応力が繰り返し加わり、したがって、耐通電熱疲労性や環境温度の変化による耐クラック性、多段階のはんだ接続への適合性も要求される。 And, when the use environment temperature is high, the reaction at the connection interface becomes faster, so the stability of the interface is required. Also, in the power module, current is repeatedly applied and interrupted to the semiconductor element, so thermal stress is repeatedly applied. Therefore, resistance to electrical thermal fatigue, crack resistance due to changes in environmental temperature, and compatibility with multi-stage solder connections. Sex is also required.
　上記要求に対応するために、鉛フリーで、かつ高い耐熱性を持ち高信頼の接合部をもつ半導体装置が必要となる。 In order to meet the above requirements, a lead-free semiconductor device having a high heat resistance and a highly reliable joint is required.
　上記のような鉛フリーはんだを用いた半導体装置の構造が、特許文献１（特開２０１０－２２６１１５号公報）に開示されている。この特許文献１には、「耐熱性２００℃の接続方法として、室温から２００℃においてＣｕ６Ｓｎ５相を含有するＳｎ系はんだとＮｉ系めっきを組合わせることで界面反応を抑制させ、２００℃以上の耐熱性をもつ半導体装置（要約参照）」が開示されている。 A structure of a semiconductor device using the above lead-free solder is disclosed in Patent Document 1 (Japanese Patent Laid-Open No. 2010-226115). This Patent Document 1 states that “as a connection method with a heat resistance of 200 ° C., an interfacial reaction is suppressed by combining a Sn-based solder containing Cu6Sn5 phase and Ni-based plating from room temperature to 200 ° C., and a heat resistance of 200 ° C. or higher. Semiconductor device (see abstract) ”has been disclosed.
　また、鉛フリーはんだを用いた電子部品が、特許文献２（特開２００９－２５５１７６号公報）に開示されている。この特許文献２には、「はんだ付け部の組成が、Ｓｂが１０～４０質量％、Ｃｕが０．５～１０質量％、残部Ｓｎからなるはんだ組成物によって、耐熱性、脆性、或いは固相線温度と液相線温度間の凝固範囲の問題が解決される。さらに機械的強度を向上させるために、Ｃｏ、Ｆｅ、Ｍｏ、Ｃｒ、Ａｇ、Ｂｉの元素のいずれか１種または２種以上を添加し、酸化抑制元素としてＣｅ、Ｃａのいずれか１種以上を添加する（要約参照）」ことが開示されている。 Further, an electronic component using lead-free solder is disclosed in Patent Document 2 (Japanese Patent Laid-Open No. 2009-255176). This patent document 2 states that “the soldering portion has a composition of Sb of 10 to 40% by mass, Cu of 0.5 to 10% by mass, and a balance of Sn, depending on the solder composition. The problem of the solidification range between the line temperature and the liquidus temperature is solved, and in order to improve the mechanical strength, any one or more of Co, Fe, Mo, Cr, Ag, Bi elements And adding at least one of Ce and Ca as an oxidation-inhibiting element (see summary).
特開２０１０－２２６１１５号公報JP 2010-226115 A 特開２００９－２５５１７６号公報JP 2009-255176 A
　パワーモジュールでは、他の電子部品と比較して大電流が印加される場合が多いことによって、半導体チップ（以降、チップとも言う）が発熱することで接合部にストレスが加わる。具体的には、１．チップ下の接合部、および絶縁基板下の接合部においてチップ－絶縁基板間、絶縁基板－放熱ベース間の線膨張係数の違いにより熱応力が加わり端部から亀裂が進展する。２．チップの過渡的な発熱などによって接合部中に温度の不均一が生じることで、接合部の中央において粒界破壊が進展する。３．高温環境に長時間晒されることで接合界面において反応が進展して接合信頼性が低下する。 In a power module, a large current is often applied as compared with other electronic components, so that a semiconductor chip (hereinafter also referred to as a chip) generates heat, and stress is applied to the joint. Specifically, At the joint part under the chip and the joint part under the insulating substrate, thermal stress is applied due to the difference in coefficient of linear expansion between the chip and the insulating substrate, and between the insulating substrate and the heat dissipation base, and a crack develops from the end part. 2. Grain boundary destruction develops at the center of the joint due to temperature non-uniformity occurring in the joint due to transient heat generation of the chip. 3. When exposed to a high temperature environment for a long time, the reaction progresses at the bonding interface and the bonding reliability decreases.
　上記特許文献１（特開２０１０－２２６１１５号公報）には、Ｓｎ－３～１０ｗｔ％Ｃｕのはんだを接合部に使用したパワーモジュールおよびインバータが開示されている。しかしながら、上記特許文献１に記載の技術では、接合部にＳｎ－Ｃｕはんだを使用した場合、亀裂進展が速く、高温環境下で信頼性が低下するという課題がある。 Patent Document 1 (Japanese Patent Application Laid-Open No. 2010-226115) discloses a power module and an inverter using Sn-3 to 10 wt% Cu solder at the joint. However, the technique described in Patent Document 1 has a problem that when Sn—Cu solder is used for the joint, cracks grow quickly and reliability decreases in a high temperature environment.
　また、特許文献２（特開２００９－２５５１７６号公報）に記載の技術では、Ｓｂ１０～４０質量％、Ｃｕ１～９質量％、残部Ｓｎからなる高温鉛フリーはんだ合金が開示されているが、接合後の接合部の構造や接合温度が規定されておらず、これらについて不明確である。 Further, in the technique described in Patent Document 2 (Japanese Patent Laid-Open No. 2009-255176), a high-temperature lead-free solder alloy composed of Sb 10 to 40% by mass, Cu 1 to 9% by mass and the balance Sn is disclosed. The structure of the joint and the joining temperature are not defined, and these are unclear.
　本発明の目的は、半導体パワーモジュールにおける高温環境下での信頼性を向上させることができる技術を提供することにある。 An object of the present invention is to provide a technique capable of improving the reliability of a semiconductor power module under a high temperature environment.
　本発明の上記ならびにその他の目的と新規な特徴は、本明細書の記述および添付図面から明らかになるであろう。 The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
　本願において開示される発明のうち、代表的なものの概要を簡単に説明すれば、以下のとおりである。 Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.
　本発明に係る半導体パワーモジュールは、半導体素子と、上記半導体素子と接合する接合材と、を有し、上記半導体素子と絶縁基板とが、または、上記絶縁基板と放熱ベースとが、Ｃｕ１～７重量％と、Ｓｂ３～１５重量％と、残部Ｓｎとからなる上記接合材によって接合され、上記接合材は２８０℃以上の温度で接合されたものである。 The semiconductor power module according to the present invention includes a semiconductor element and a bonding material bonded to the semiconductor element, and the semiconductor element and the insulating substrate, or the insulating substrate and the heat dissipation base are Cu1-7. Bonded by the above-mentioned bonding material comprising wt%, Sb 3 to 15 wt%, and the remaining Sn, and the bonding material is bonded at a temperature of 280 ° C. or higher.
　また、本発明に係る他の半導体パワーモジュールは、半導体素子と、上記半導体素子と接合する接合材と、を有するものである。さらに、上記半導体素子と絶縁基板との間、または、上記絶縁基板と放熱ベースとの間の接合部における第１のＣｕ－Ｓｎ化合物、Ｓｎ－Ｃｕ－Ｓｂ層、第２のＣｕ－Ｓｎ化合物のそれぞれの厚さを足した上記接合部の厚さ比を１００とした場合、上記第１のＣｕ－Ｓｎ化合物と上記第２のＣｕ－Ｓｎ化合物の厚さの比は、１以上１０以下である。 Further, another semiconductor power module according to the present invention includes a semiconductor element and a bonding material bonded to the semiconductor element. Further, the first Cu—Sn compound, the Sn—Cu—Sb layer, and the second Cu—Sn compound at the junction between the semiconductor element and the insulating substrate or between the insulating substrate and the heat dissipation base. Assuming that the thickness ratio of the above-mentioned joining portion obtained by adding the respective thicknesses is 100, the ratio of the thicknesses of the first Cu—Sn compound and the second Cu—Sn compound is 1 or more and 10 or less. .
　また、本発明に係る移動体は、半導体素子と絶縁基板との間、または、絶縁基板と放熱板との間の接合層は、第１のＣｕ－Ｓｎ化合物とＳｎ－Ｃｕ－Ｓｂ層と第２のＣｕ－Ｓｎ化合物とから構成されており、接合層の厚さを１００とした場合に、第１のＣｕ－Ｓｎ化合物と第２のＣｕ－Ｓｎ化合物の厚さは１以上１０以下で構成された半導体パワーモジュールを有するものである。 In the moving body according to the present invention, the bonding layer between the semiconductor element and the insulating substrate or between the insulating substrate and the heat sink is formed by the first Cu—Sn compound, the Sn—Cu—Sb layer, and the first layer. When the thickness of the bonding layer is 100, the thicknesses of the first Cu-Sn compound and the second Cu-Sn compound are 1 or more and 10 or less. The semiconductor power module is provided.
　また、本発明に係る半導体パワーモジュールの製造方法は、半導体素子と絶縁基板とを、または、上記絶縁基板と放熱ベースとを、Ｃｕ１～７重量％と、Ｓｂ３～１５重量％と、残部Ｓｎとからなる接合材によって接合する工程を有し、上記接合材を２８０℃以上に加熱して上記半導体素子と上記絶縁基板とを、または、上記絶縁基板と上記放熱ベースとを接合するものである。 Also, the method for manufacturing a semiconductor power module according to the present invention includes a semiconductor element and an insulating substrate, or the insulating substrate and a heat dissipation base, Cu 1 to 7 wt%, Sb 3 to 15 wt%, and the remaining Sn. And joining the semiconductor element and the insulating substrate, or joining the insulating substrate and the heat dissipation base.
　本願において開示される発明のうち、代表的なものによって得られる効果を簡単に説明すれば、以下のとおりである。 Among the inventions disclosed in the present application, the effects obtained by typical ones will be briefly described as follows.
　半導体パワーモジュールにおける高温環境下での信頼性を向上させることができる。特に断続通電特性に優れる半導体パワーモジュールを実現することが可能となる。 The reliability of the semiconductor power module in a high temperature environment can be improved. In particular, it is possible to realize a semiconductor power module having excellent intermittent conduction characteristics.
本発明の実施の形態の半導体装置の主要部の構造の一例を示す断面図である。It is sectional drawing which shows an example of the structure of the principal part of the semiconductor device of embodiment of this invention. 本発明の実施の形態のはんだ接合部の接合前と接合後の構造の一例を示す部分断面図である。It is a fragmentary sectional view which shows an example of the structure before the joining of the solder joint part of embodiment of this invention, and after joining. 本発明の実施の形態のはんだ接合部の構造を示す断面図である。It is sectional drawing which shows the structure of the solder joint part of embodiment of this invention. 比較例のはんだ接合部の構造を示す断面図である。It is sectional drawing which shows the structure of the solder joint part of a comparative example. 本発明の実施の形態におけるボイド率の定義を示す、接合部の平面図である。It is a top view of a joined part showing the definition of a void rate in an embodiment of the invention. 本発明の実施の形態におけるクラックの定義を示す、接合部の平面図である。It is a top view of a joined part showing the definition of a crack in an embodiment of the invention. 比較例の断続通電時の破壊状況を示す断面図である。It is sectional drawing which shows the destruction condition at the time of the intermittent electricity supply of a comparative example. 本発明の各実施例と比較例の評価の結果を示す評価結果図である。It is an evaluation result figure which shows the result of evaluation of each Example and comparative example of this invention. 本発明の実施の形態の鉛フリーはんだ合金（接合材）を用いた半導体装置（半導体パワーモジュール）の構造の一例を示す断面図である。It is sectional drawing which shows an example of the structure of the semiconductor device (semiconductor power module) using the lead-free solder alloy (joining material) of embodiment of this invention. 本発明の実施の形態の鉛フリーはんだ合金を用いた半導体装置（半導体パワーモジュール）の構造の一例を示す断面図である。It is sectional drawing which shows an example of the structure of the semiconductor device (semiconductor power module) using the lead-free solder alloy of embodiment of this invention. 本発明の実施の形態の鉛フリーはんだ合金を用いた半導体装置が搭載された鉄道の車両の一例を示す部分側面図である。1 is a partial side view showing an example of a railway vehicle on which a semiconductor device using a lead-free solder alloy according to an embodiment of the present invention is mounted. 図１１に示す車両に設置されたインバータの内部構造の一例を示す平面図である。It is a top view which shows an example of the internal structure of the inverter installed in the vehicle shown in FIG. 本発明の実施の形態の鉛フリーはんだ合金を用いた半導体装置（交流発電機用半導体モジュール）の構造の一例を示す断面図である。It is sectional drawing which shows an example of the structure of the semiconductor device (semiconductor module for AC generators) using the lead-free solder alloy of embodiment of this invention. 本発明の実施の形態の半導体パワーモジュールが搭載された自動車の一例を示す斜視図である。It is a perspective view which shows an example of the motor vehicle carrying the semiconductor power module of embodiment of this invention. 本発明の実施の形態の第１変形例の半導体パワーモジュールの構造を示す断面図である。It is sectional drawing which shows the structure of the semiconductor power module of the 1st modification of embodiment of this invention. 本発明の実施の形態の第２変形例の半導体パワーモジュールの構造を示す断面図である。It is sectional drawing which shows the structure of the semiconductor power module of the 2nd modification of embodiment of this invention.
　以下、本発明の実施の形態を図面に基づいて詳細に説明する。なお、実施の形態を説明するための全図において、同一の機能を有する部材には同一の符号を付し、その繰り返しの説明は省略する。なお、図面をわかりやすくするために平面図であってもハッチングを付す場合がある。 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted. In order to make the drawings easy to understand, even a plan view may be hatched.
　（実施の形態）
　図１は本発明の実施の形態の半導体装置の主要部の構造の一例を示す断面図、図２は本発明の実施の形態のはんだ接合部の接合前と接合後の構造の一例を示す部分断面図である。 (Embodiment)
FIG. 1 is a sectional view showing an example of the structure of the main part of a semiconductor device according to an embodiment of the present invention, and FIG. It is sectional drawing.
　まず、本実施の形態の半導体装置の構造について説明する。図１に示す半導体装置９は、鉛フリーはんだ合金を用いた半導体パワーモジュールであり、その主要部の概略構成について説明すると、半導体素子である半導体チップ１が、チップ支持部材であるセラミック基板（被接合部材、絶縁基板）５上に、はんだ合金（接合材）２ｂを介してはんだ接合されている。なお、はんだ合金２ｂは、鉛（Ｐｂ）を含有していないはんだである。 First, the structure of the semiconductor device of this embodiment will be described. A semiconductor device 9 shown in FIG. 1 is a semiconductor power module using a lead-free solder alloy. A schematic configuration of a main part of the semiconductor device 9 will be described. A semiconductor chip 1 as a semiconductor element is a ceramic substrate (covered member). Solder-bonded onto a bonding member (insulating substrate) 5 via a solder alloy (bonding material) 2b. The solder alloy 2b is a solder that does not contain lead (Pb).
　また、半導体チップ１を搭載したセラミック基板５は、放熱部材（放熱ベース）である放熱用金属板１２上にはんだ合金（接合材）２ｃを介してはんだ接合されている。はんだ合金２ｃも、鉛（Ｐｂ）を含有していないはんだである。 Further, the ceramic substrate 5 on which the semiconductor chip 1 is mounted is soldered via a solder alloy (joining material) 2c on a heat radiating metal plate 12 which is a heat radiating member (heat radiating base). The solder alloy 2c is also a solder containing no lead (Pb).
　なお、セラミック基板５の上面５ａには、配線部５ｃが形成されており、この配線部５ｃの表面には、例えば図２に示すようなＮｉめっき層（Ｎｉメタライズ層）３が形成されている。一方、セラミック基板５の下面５ｂには、導体部５ｄが形成されている。この導体部５ｄは、例えば上記Ｎｉめっき層３である。 A wiring portion 5c is formed on the upper surface 5a of the ceramic substrate 5, and a Ni plating layer (Ni metallized layer) 3 as shown in FIG. 2, for example, is formed on the surface of the wiring portion 5c. . On the other hand, a conductor portion 5d is formed on the lower surface 5b of the ceramic substrate 5. The conductor portion 5d is, for example, the Ni plating layer 3 described above.
　この場合、セラミック基板５は、はんだ合金２ｂおよびはんだ合金２ｃとそれぞれＮｉめっき層３を介して接合している。 In this case, the ceramic substrate 5 is joined to the solder alloy 2b and the solder alloy 2c through the Ni plating layer 3, respectively.
　なお、半導体装置９では、はんだ合金２ｂおよびはんだ合金２ｃのうちの少なくとも何れか一方のはんだ、もしくは両方のはんだが、Ｃｕ１～７重量（ｗｔ）％と、Ｓｂ３～１５重量（ｗｔ）％と、残部Ｓｎとからなる。 In the semiconductor device 9, at least one of the solder alloy 2 b and the solder alloy 2 c, or both of the solder is Cu 1 to 7 wt (wt)%, Sb 3 to 15 wt (wt)%, It consists of the remainder Sn.
　また、はんだ合金２ｃの厚さは、はんだ合金２ｂの厚さより厚い。一例として、はんだ合金２ｂの厚さは、約０．１ｍｍ、はんだ合金２ｃの厚さは、０．２～０．４ｍｍである。 Further, the thickness of the solder alloy 2c is larger than the thickness of the solder alloy 2b. As an example, the thickness of the solder alloy 2b is about 0.1 mm, and the thickness of the solder alloy 2c is 0.2 to 0.4 mm.
　次に、図２を用いて本実施の形態の鉛フリーはんだ合金によるはんだ接合について説明する。図２に示すように、接合前には、はんだ箔（接合材）２ａを、Ｎｉめっき３を施した被接続材であるセラミック基板５で上方と下方とから挟み込む（あるいは、セラミック基板５と半導体チップ１とで挟んでもよい）。 Next, solder joining by the lead-free solder alloy of the present embodiment will be described with reference to FIG. As shown in FIG. 2, before joining, a solder foil (joining material) 2a is sandwiched from above and below by a ceramic substrate 5 which is a connected material to which Ni plating 3 is applied (or ceramic substrate 5 and semiconductor). It may be sandwiched between the chip 1).
　この時、はんだ箔（接合材）２ａは、Ｃｕ１～７重量％と、Ｓｂ３～１５重量％と、残部Ｓｎとからなる組成である。すなわち、Ｃｕ１～７重量％と、Ｓｂ３～１５重量％と、残部Ｓｎとからなる組成のはんだ箔２ａを用いてはんだ接合を行う。つまり、はんだ箔２ａの組成では、ＳｎがＣｕおよびＳｂに比べて最も含有量が多い。また、接合前のはんだにはＣｕ－Ｓｎ化合物６が含まれている。 At this time, the solder foil (joining material) 2a has a composition composed of Cu 1 to 7 wt%, Sb 3 to 15 wt%, and the remaining Sn. That is, solder bonding is performed using a solder foil 2a having a composition including Cu 1 to 7 wt%, Sb 3 to 15 wt%, and the remaining Sn. That is, in the composition of the solder foil 2a, Sn has the highest content compared to Cu and Sb. Further, the Cu—Sn compound 6 is contained in the solder before joining.
　次に、はんだ箔２ａを２８０℃以上の温度で加熱する。これにより、図２の接合後に示すように、Ｃｕ－Ｓｎ化合物（例えばＣｕ６Ｓｎ５）が接続界面上に析出あるいは移動し、その結果、Ｎｉめっき層３上にＣｕ－Ｓｎ系化合物層４が形成される。また、はんだ中に含まれているＳｂはＳｎ相に固溶する。 Next, the solder foil 2a is heated at a temperature of 280 ° C. or higher. As a result, as shown after bonding in FIG. 2, the Cu—Sn compound (for example, Cu 6 Sn 5) precipitates or moves on the connection interface, and as a result, the Cu—Sn based compound layer 4 is formed on the Ni plating layer 3. . In addition, Sb contained in the solder dissolves in the Sn phase.
　詳細には、接合材を２８０℃以上の温度で接続した構造として、図２の接合後に示すように、セラミック基板５に施されたＮｉめっき層３上にＣｕ－Ｓｎ系化合物層４が形成される。さらに、Ｃｕ－Ｓｎ系化合物層４とＣｕ－Ｓｎ系化合物層４との間に、はんだ中に含まれているＳｂを含有するＳｎを主体としたはんだ合金２が形成される。 Specifically, as a structure in which the bonding material is connected at a temperature of 280 ° C. or higher, a Cu—Sn-based compound layer 4 is formed on the Ni plating layer 3 applied to the ceramic substrate 5 as shown after bonding in FIG. The Further, a solder alloy 2 mainly composed of Sn containing Sb contained in the solder is formed between the Cu—Sn compound layer 4 and the Cu—Sn compound layer 4.
　つまり、はんだ接合部の構造は、はんだ合金２と、その上下層に形成されたＣｕ－Ｓｎ系化合物層４とからなる３層構造である。そして、はんだ合金２の厚さは、Ｃｕ－Ｓｎ系化合物層４の厚さより厚い。言い換えると、３層構造のうちの中間層となるはんだ合金２の厚さが最も厚い。 That is, the structure of the solder joint portion is a three-layer structure including the solder alloy 2 and the Cu—Sn-based compound layer 4 formed on the upper and lower layers thereof. The solder alloy 2 is thicker than the Cu—Sn compound layer 4. In other words, the thickness of the solder alloy 2 serving as an intermediate layer in the three-layer structure is the thickest.
　次に、図３は本発明の実施の形態のはんだ接合部の構造を示す断面図（断面ＳＥＭ像）、図４は比較例のはんだ接合部の構造を示す断面図である。 Next, FIG. 3 is a cross-sectional view (cross-sectional SEM image) showing the structure of the solder joint portion according to the embodiment of the present invention, and FIG. 4 is a cross-sectional view showing the structure of the solder joint portion of the comparative example.
　図３に示すように、本実施の形態のはんだ接合部では、１７５℃以上の高温環境下に長時間さらされても、Ｃｕ－Ｓｎ系化合物層４を主体とした化合物層が接合界面とはんだ合金２とのバリア層となる。Ｃｕ－Ｓｎ系化合物層４はＣｕ－Ｓｎ化合物の一部に他の元素が置換したものであり、Ｃｕ－Ｓｎが主な構成元素である。接合層を構成する組成のうち最も多い比率の組成を主な構成元素であると呼ぶ。 As shown in FIG. 3, in the solder joint portion of the present embodiment, even when exposed to a high temperature environment of 175 ° C. or higher for a long time, the compound layer mainly composed of the Cu—Sn-based compound layer 4 forms the joint interface and the solder. It becomes a barrier layer with the alloy 2. The Cu—Sn-based compound layer 4 is obtained by replacing a part of the Cu—Sn compound with another element, and Cu—Sn is the main constituent element. The composition with the largest proportion of the composition constituting the bonding layer is called the main constituent element.
　その結果、接合界面での反応による化合物層の成長およびそれに伴うボイドの形成を抑制することができる。 As a result, the growth of the compound layer due to the reaction at the bonding interface and the formation of voids associated therewith can be suppressed.
　また、本願発明の接続構造では、はんだ中に含まれるＣｕはＳｎ中に０．７重量％しか固溶しないため、ほぼ接合界面にＣｕ－Ｓｎ化合物として析出することとなる。そのため、はんだ接合後の接合部は、第１のＣｕ－Ｓｎ化合物層と、Ｓｎ－Ｃｕ－Ｓｂ層と、第２のＣｕ－Ｓｎ化合物層とから構成される。 Further, in the connection structure of the present invention, Cu contained in the solder dissolves only 0.7 wt% in Sn, so that it is precipitated almost as a Cu—Sn compound at the joint interface. Therefore, the joint after soldering is composed of the first Cu—Sn compound layer, the Sn—Cu—Sb layer, and the second Cu—Sn compound layer.
　はんだの組成によって、第１のＣｕ－Ｓｎ化合物層とＳｎ－Ｃｕ－Ｓｂ層と第２のＣｕ－Ｓｎ化合物層とを足した厚みの構成比率は、第１のＣｕ－Ｓｎ化合物層：Ｓｎ－Ｃｕ－Ｓｂ層：第２のＣｕ－Ｓｎ化合物層＝１：９８：１～１０：８０：１０となる。例えば、接合部（接合層）の厚みが５０μｍである場合には、第１のＣｕ－Ｓｎ化合物：Ｓｎ－Ｃｕ－Ｓｂ層：第２のＣｕ－Ｓｎ化合物は、０．５μｍ：４９μｍ：０．５μｍ～５μｍ：４０μｍ：５μｍということである。 Depending on the composition of the solder, the composition ratio of the thickness of the first Cu—Sn compound layer, the Sn—Cu—Sb layer, and the second Cu—Sn compound layer is as follows: First Cu—Sn compound layer: Sn— Cu—Sb layer: second Cu—Sn compound layer = 1: 98: 1 to 10:80:10. For example, when the thickness of the bonding portion (bonding layer) is 50 μm, the first Cu—Sn compound: Sn—Cu—Sb layer: second Cu—Sn compound has a thickness of 0.5 μm: 49 μm: 0. 5 μm to 5 μm: 40 μm: 5 μm.
　また、接合部（接合層）の厚みが１００μｍである場合には、第１のＣｕ－Ｓｎ化合物：Ｓｎ－Ｃｕ－Ｓｂ層：第２のＣｕ－Ｓｎ化合物は、１μｍ：９８μｍ：１μｍ～１０μｍ：８０μｍ：１０μｍということである。 When the thickness of the bonding portion (bonding layer) is 100 μm, the first Cu—Sn compound: Sn—Cu—Sb layer: second Cu—Sn compound is 1 μm: 98 μm: 1 μm to 10 μm: 80 μm: 10 μm.
　すなわち、第１のＣｕ－Ｓｎ化合物：Ｓｎ－Ｃｕ－Ｓｂ層：第２のＣｕ－Ｓｎ化合物の３層の厚みの構成比率を全体を１００とした場合に、第１のＣｕ－Ｓｎ化合物層と第２のＣｕ－Ｓｎ化合物層は１以上１０以下の比率となる。これは先に述べたように本願発明で実施されるはんだの組成比によって変化する。つまり、Ｓｎ－Ｃｕ－Ｓｂ層の厚さ比は、全体の厚さの比率である１００から第１のＣｕ－Ｓｎ化合物層と第２のＣｕ－Ｓｎ化合物層の厚さ比率を減算した値であることを意味する。 That is, when the total composition ratio of the thickness of the first Cu—Sn compound: Sn—Cu—Sb layer: second Cu—Sn compound is 100, the first Cu—Sn compound layer The second Cu—Sn compound layer has a ratio of 1 or more and 10 or less. As described above, this varies depending on the composition ratio of the solder implemented in the present invention. That is, the thickness ratio of the Sn—Cu—Sb layer is a value obtained by subtracting the thickness ratio of the first Cu—Sn compound layer and the second Cu—Sn compound layer from 100, which is the ratio of the total thickness. It means that there is.
　なお、第１のＣｕ－Ｓｎ化合物層と、Ｓｎ－Ｃｕ－Ｓｂ層と、第２のＣｕ－Ｓｎ化合物層との境界面である接合部の界面は平面ではないため、界面の平均厚さを厚さとするものである。 Note that since the interface of the junction which is the boundary surface between the first Cu—Sn compound layer, the Sn—Cu—Sb layer, and the second Cu—Sn compound layer is not a plane, the average thickness of the interface is Thickness is assumed.
　また、はんだの接合温度が２８０℃より低い場合には、図４の比較例の構造に示すように、はんだ箔２０中のＣｕ－Ｓｎ化合物６は、接合層中に浮島状に分布するため、本実施の形態の図２に示す接合部（接合後）の構造とはならない。そのため、後述する図８の比較例６、７に示すように、図４の浮島状に分部した接合部構造では、接合部温度が２８０℃以下となると接合界面の安定性が低下する。また、接合部におけるＳｎ－Ｃｕ－Ｓｂ層の厚さが５０μｍより薄くなると、接合時に発生する液相の量が少なくボイド（気泡）の排出性が低下し、接合層中に多量のボイドが残存してしまう。さらに、はんだ接合部の平均の厚さが４００μｍより厚くなると、はんだ中に含まれるＣｕ－Ｓｎ化合物量が過剰となり、接合界面にＣｕ－Ｓｎ化合物が形成されるだけでなく、接合層中にも浮島状に残存するため亀裂進展が早くなる。したがって、はんだ接合後のはんだの厚さは、５０μｍ以上４００μｍ以下であることが望ましい。 When the solder bonding temperature is lower than 280 ° C., as shown in the structure of the comparative example in FIG. 4, the Cu—Sn compound 6 in the solder foil 20 is distributed in a floating island shape in the bonding layer. It does not become the structure of the junction part (after joining) shown in FIG. 2 of this Embodiment. Therefore, as shown in Comparative Examples 6 and 7 in FIG. 8 to be described later, in the joint structure divided into a floating island shape in FIG. 4, when the joint temperature is 280 ° C. or lower, the stability of the joint interface is lowered. In addition, when the thickness of the Sn—Cu—Sb layer at the joint is less than 50 μm, the amount of liquid phase generated at the time of joining is small and void (bubble) discharge is reduced, and a large amount of voids remain in the joint layer. Resulting in. Further, when the average thickness of the solder joint becomes thicker than 400 μm, the amount of Cu—Sn compound contained in the solder becomes excessive, and not only Cu—Sn compound is formed at the joint interface but also in the joint layer. The crack progresses faster because it remains in a floating island shape. Therefore, it is desirable that the thickness of the solder after solder joining is 50 μm or more and 400 μm or less.
　上述のように、本願のはんだを用いることで、１７５℃以上の高温下に長時間さらされても、Ｃｕ－Ｓｎ化合物を主体としたＣｕ－Ｓｎ系化合物層４が接続界面とはんだとのバリア層となるため、接続界面の反応による化合物層の成長およびそれに伴うボイドの形成を抑制することができる。 As described above, by using the solder of the present application, even when exposed to a high temperature of 175 ° C. or higher for a long time, the Cu—Sn compound layer 4 mainly composed of the Cu—Sn compound is used as a barrier between the connection interface and the solder. Since it becomes a layer, the growth of the compound layer due to the reaction at the connection interface and the accompanying formation of voids can be suppressed.
　また、Ｓｎ相にＳｂを固溶させることではんだ接合の機械的特性を向上させ、高温での耐亀裂進展性、パワーサイクル試験等の信頼性を向上させることができる。また、本願のはんだは、その組成に貴金属を含んでいないため、標準的な鉛フリーはんだであるＳｎ３Ａｇ０．５Ｃｕと比較して低コストな材料である。 Also, by dissolving Sb in the Sn phase, the mechanical properties of the solder joint can be improved, and the reliability of crack resistance at high temperatures, power cycle tests, etc. can be improved. Moreover, since the solder of the present application does not contain a noble metal in its composition, it is a low-cost material compared to Sn3Ag0.5Cu, which is a standard lead-free solder.
　次に、はんだ接合部におけるボイド、クラックまたは破壊について説明する。図５は本発明の実施の形態におけるボイド率の定義を示す、接合部の平面図、図６は本発明の実施の形態におけるクラックの定義を示す、接合部の平面図、図７は比較例の断続通電時の破壊状況を示す断面図である。 Next, voids, cracks or destruction at the solder joint will be described. FIG. 5 is a plan view of the joint showing the definition of the void ratio in the embodiment of the present invention, FIG. 6 is a plan view of the joint showing the definition of the crack in the embodiment of the present invention, and FIG. 7 is a comparative example. It is sectional drawing which shows the destruction condition at the time of intermittent electricity supply.
　図５はボイド７の進展状態を示しており、超音波探傷によりはんだ接合部のボイド７の面積率を測定することができる。ボイド率は、接合部であるはんだ合金２の平面方向において、ボイド７の全面積を接合層の平面方向の面積で割ったものである。 FIG. 5 shows the progress of the void 7, and the area ratio of the void 7 in the solder joint can be measured by ultrasonic flaw detection. The void ratio is obtained by dividing the total area of the void 7 by the area in the plane direction of the bonding layer in the plane direction of the solder alloy 2 that is the bonding portion.
　また、温度サイクル試験によってはんだ合金２で発生するクラックについて説明する。図６は、－５５℃に１５分、２００℃に１５分を１サイクルとした場合に、５００サイクル程度の温度サイクル試験を行った後に、熱応力によってはんだ接合部に生じたクラック８を示すものである。 Also, cracks generated in the solder alloy 2 by the temperature cycle test will be described. FIG. 6 shows cracks 8 generated in a solder joint due to thermal stress after performing a temperature cycle test of about 500 cycles, with 15 minutes at −55 ° C. and 15 minutes at 200 ° C. It is.
　このように温度サイクル試験した半導体装置９に対して超音波探傷によりはんだ接合部でのクラック進展率を測定した。クラック進展率は、はんだ接合部であるはんだ合金２の平面方向において、クラック８の全面積を接合層の平面方向の面積で割ったものである。 The crack progress rate in the solder joint portion was measured by ultrasonic flaw detection on the semiconductor device 9 thus subjected to the temperature cycle test. The crack progress rate is obtained by dividing the total area of the crack 8 by the area of the bonding layer in the plane direction in the plane direction of the solder alloy 2 that is the solder joint portion.
　なお、ボイド率が１０％を超えると、温度サイクルにより、ボイド周辺から優先的にクラック８が進展し、早期に信頼性が低下する等の問題がある。したがって、ボイド率を少なくすることで長期信頼性を確保することができる。また、半導体素子に通電することで発熱するが、クラック進展率が２０％を超えると半導体素子で発生した熱の引けが悪くなり、半導体素子の温度が上昇して信頼性が急速に低下する。 In addition, when the void ratio exceeds 10%, there is a problem that the crack 8 is preferentially developed from around the void due to the temperature cycle, and the reliability is lowered at an early stage. Therefore, long-term reliability can be ensured by reducing the void ratio. In addition, heat is generated by energizing the semiconductor element. However, if the crack growth rate exceeds 20%, the heat generated in the semiconductor element is deteriorated, the temperature of the semiconductor element is increased, and the reliability is rapidly decreased.
　次に、断続通電試験による破壊について説明する。図７に示すように、はんだ接合の中心部分からクラック８による破壊が進行する。はんだ合金２０ａの接続部にクラックが発生すると、半導体チップ１の発熱を外部に放出するための面積が減少し、熱抵抗が上昇する。熱抵抗が２０％以上に上昇するとチップ温度が急激に上昇し、はんだの溶融や亀裂進展が急激に進行し、信頼性を維持することができない。 Next, the breakdown by the intermittent energization test will be explained. As shown in FIG. 7, destruction by the crack 8 proceeds from the central portion of the solder joint. When a crack occurs in the connection portion of the solder alloy 20a, the area for releasing the heat generated by the semiconductor chip 1 decreases, and the thermal resistance increases. When the thermal resistance rises to 20% or more, the chip temperature rises abruptly, and the melting of the solder and the progress of cracks advance rapidly, and the reliability cannot be maintained.
　なお、半導体チップ１や基板等の被接合材の素材については、Ｃｕ、Ｎｉ、Ａｕ、Ａｇ、Ｐｔ、Ｐｄ、Ｔｉ、ＴｉＮ、Ｆｅ－ＮｉやＦｅ－Ｃｏ等のＦｅ系合金等、様々な金属、合金が適用可能である。ただし、被接合材はＮｉメタライズが施されていることが望ましい。 In addition, as for the material of the material to be joined such as the semiconductor chip 1 and the substrate, various metals such as Cu, Ni, Au, Ag, Pt, Pd, Ti, TiN, Fe-based alloys such as Fe—Ni and Fe—Co, etc. Alloys are applicable. However, it is desirable that the material to be joined is Ni metallized.
　これは、図２に示すように、Ｎｉめっき層３上にＣｕ－Ｓｎ系化合物層４のバリア層が形成されることにより、Ｎｉの拡散を抑制し、接合界面が安定に保たれ、高温環境下でより良好な信頼性を維持できるためである。 This is because, as shown in FIG. 2, the barrier layer of the Cu—Sn compound layer 4 is formed on the Ni plating layer 3 to suppress the diffusion of Ni, the bonding interface is kept stable, and the high temperature environment. This is because better reliability can be maintained below.
　なお、被接合材の表面のメタライズがＮｉの場合は、Ｎｉ自身の酸化が問題となり、濡れ性が阻害される場合がある。そのため、Ｎｉの上に、酸化しにくいＡｕやＡｇ、Ｐｔ、Ｐｄを積層させてもよい。つまり、被接合材の表面にはＮｉ、Ｎｉ／Ａｕ、Ｎｉ／Ａｇ等のメタライズが施されていることが望ましい。 In addition, when the metallization of the surface of a to-be-joined material is Ni, the oxidation of Ni itself becomes a problem and wettability may be inhibited. Therefore, Au, Ag, Pt, or Pd that is difficult to oxidize may be laminated on Ni. In other words, it is desirable that the surface of the material to be joined is subjected to metallization such as Ni, Ni / Au, Ni / Ag.
　このようなメタライズが施されていれば、半導体チップ１は、Ｓｉ、ＳｉＣ、ＧａＡｓ、ＣｄＴｅ、ＧａＮ等どのような半導体チップ１であっても接合することができる。基板についても、上記のメタライズを付けることで、Ｃｕ、Ａｌ、Ｃｕ－Ｍｏ、Ａｌ－ＳｉＣ（アルミニウムと炭化ケイ素の複合材料）、Ｍｇ－ＳｉＣ（マグネシウムと炭化ケイ素の複合材料）、４２アロイや、ＣＩＣ（Copper Invar Copper)、または、ＤＢＣ（Direct Bond Copper）、ＤＢＡ（Direct Bond Aluminum）等の金属を貼り合わせたセラミック基板（絶縁性基板）等、どのような部材に対しても信頼性の高い接合を実現することができる。 If such metallization is applied, the semiconductor chip 1 can be bonded to any semiconductor chip 1 such as Si, SiC, GaAs, CdTe, GaN. For the substrate, by adding the above metallization, Cu, Al, Cu—Mo, Al—SiC (a composite material of aluminum and silicon carbide), Mg—SiC (a composite material of magnesium and silicon carbide), 42 alloy, CIC (Copper Invar Copper), DBC (Direct Bond Copper), DBA (Direct Bond Aluminum) and other metal substrates bonded together, such as a ceramic substrate (insulating substrate) with high reliability Bonding can be realized.
　なお、Ｎｉメタライズが付いた被接合材（被接続材）を、本実施の形態のはんだ合金２により接合した場合の接合後の構造を詳細に書けば、被接合材／Ｎｉ／Ｃｕ－Ｓｎ系化合物／はんだ合金／Ｃｕ－Ｓｎ系化合物／Ｎｉ／被接合材となる。 In addition, if the structure after joining when the material to be joined (material to be joined) with Ni metallization is joined by the solder alloy 2 of the present embodiment is described in detail, the material to be joined / Ni / Cu—Sn system Compound / solder alloy / Cu—Sn compound / Ni / bonded material.
　上記の例は、半導体素子と基板の接続について説明したが、このような構成は、半導体とリード、半導体と放熱基板、半導体とフレーム、半導体と絶縁基板、または半導体と一般的な電極との接合についても適用することができる。また、上記で説明した構成は、半導体素子と基板の接続に限らず、一般的に、第１の被接続部材と第２の被接続部材を本実施例の接合材によって接合する場合にも適用することができる。例えば、金属板と金属板、金属板とセラミック基板等の接合に適用することができる。 In the above example, the connection between the semiconductor element and the substrate has been described. However, such a structure is formed by bonding the semiconductor and the lead, the semiconductor and the heat dissipation substrate, the semiconductor and the frame, the semiconductor and the insulating substrate, or the semiconductor and the general electrode. Can also be applied. In addition, the configuration described above is not limited to the connection between the semiconductor element and the substrate, and is generally applicable to the case where the first connected member and the second connected member are bonded by the bonding material of the present embodiment. can do. For example, the present invention can be applied to joining a metal plate and a metal plate, a metal plate and a ceramic substrate, or the like.
　次に、図８を用いて各実施例について説明する。図８は本発明の各実施例と比較例の評価の結果を示す評価結果図である。 Next, each embodiment will be described with reference to FIG. FIG. 8 is an evaluation result diagram showing the results of evaluation of each example and comparative example of the present invention.
　詳細には、図８に示す実施例１～１８のはんだ箔（鉛フリーはんだ合金）２ａを用いて図１に示す半導体装置９を製造し、ボイド率、接合界面安定性、温度サイクル信頼性、断続通電信頼性を評価、検討したものである。 Specifically, the semiconductor device 9 shown in FIG. 1 is manufactured using the solder foil (lead-free solder alloy) 2a of Examples 1 to 18 shown in FIG. 8, and the void ratio, the bonding interface stability, the temperature cycle reliability, Intermittent conduction reliability was evaluated and examined.
　半導体装置９の代用の構造として、図２に示すようなＮｉめっき層３が形成されたセラミック基板５、実施例１～１８の組成のはんだ箔２ａ、１０ｍｍ角で、かつ厚さ０．３ｍｍのＮｉめっき層３が形成されたセラミック基板５をそれぞれ積み重ね、熱処理炉にて、１００％Ｈ２雰囲気で接続して製造した。 As an alternative structure of the semiconductor device 9, a ceramic substrate 5 on which a Ni plating layer 3 as shown in FIG. 2 is formed, a solder foil 2a having the composition of Examples 1 to 18, a 10 mm square, and a thickness of 0.3 mm The ceramic substrates 5 on which the Ni plating layer 3 was formed were stacked and connected in a heat treatment furnace in a 100% H 2 atmosphere.
　半導体装置が一定の信頼性を得られる一般的な基準である、接合層のボイド率が５％以下となり、正常に半導体素子が動作した場合を○(良好)とし、それ以外を×(不適)とした。 The standard for obtaining a certain level of reliability in semiconductor devices, where the void fraction of the bonding layer is 5% or less, and when the semiconductor element operates normally, it is marked as ◯ (good), and the others are marked as x (unsuitable). It was.
　また、温度サイクル信頼性は、－５５℃に１５分、２００℃に１５分を１サイクルとした場合に、５００サイクル程度の温度サイクル試験を行った後、クラック進展率を測定し、一般的な信頼性の基準であるクラック進展率２０％以下となり、正常に半導体素子が動作した場合を○とし、それ以外を×とした。 The temperature cycle reliability is determined by measuring the crack growth rate after conducting a temperature cycle test of about 500 cycles, assuming 15 minutes at -55 ° C and 15 minutes at 200 ° C. The crack growth rate, which is a reliability criterion, was 20% or less, and the case where the semiconductor element normally operated was evaluated as ◯, and the others were evaluated as ×.
　界面安定性は、２００℃で１０００時間保持した後、Ｎｉめっきが残存しているものを○、一部でも消失が確認されたものを×とした。これは、Ｎｉめっきが消失すると、被接合材とはんだ合金の間で拡散が進み、金属間化合物が形成され体積差によってボイド７が発生し、長期信頼性が保てないからである。 Interfacial stability was evaluated as “◯” when Ni plating remained after holding at 200 ° C. for 1000 hours, and “X” when disappearance was confirmed even partially. This is because when Ni plating disappears, diffusion proceeds between the material to be joined and the solder alloy, an intermetallic compound is formed, voids 7 are generated due to the volume difference, and long-term reliability cannot be maintained.
　通電熱疲労信頼性は、半導体チップ１を通電によって発熱させ、１７５℃に到達後、電流を切り、２５℃までの冷却を１サイクルとして、冷却半導体装置が一定の信頼性を得られる一般的な基準である通電熱疲労試験５０００サイクル試験後に半導体チップ１の熱抵抗を測定する。そして、その熱抵抗が２０％未満の上昇率で、かつ正常に半導体チップ１が動作した場合ものを○、それ以外を×として評価した。 The heat conduction fatigue reliability is general in which the semiconductor chip 1 generates heat by energization, and after reaching 175 ° C., the current is turned off and cooling to 25 ° C. is performed as one cycle, so that the cooling semiconductor device can obtain a certain reliability. The thermal resistance of the semiconductor chip 1 is measured after a 5000 cycle test, which is a reference thermal fatigue test. Then, when the thermal resistance was increased by less than 20% and the semiconductor chip 1 normally operated, the evaluation was evaluated as “◯” and the others were evaluated as “X”.
　総合評価は、すべての条件において評価が良好であったものを○とし、一つでも信頼性基準を満たせないものがあった場合、高温環境下での信頼性が確保できないため×とした。 The overall evaluation was evaluated as ○ when the evaluation was good under all conditions, and × when there was one that could not meet the reliability standards, because reliability under a high temperature environment could not be secured.
　また、これらの実験結果から、温度サイクル試験でクラック進展率が良好である接合材は、Ｓｎに、３重量％以上７重量％以下のＣｕと、９重量％以上１１重量％以下のＳｂとを添加したものであることを確認した。 Further, from these experimental results, the bonding material having a good crack growth rate in the temperature cycle test is Sn 3 wt% or more 7 wt% or less and 9 wt% or more 11 wt% or less Sb. It was confirmed that it was added.
　また、図８に示す実施例１７，１８では、はんだの接合温度が３００℃の場合を評価し、３００℃でも２８０℃の場合と同じ接合後の構造が得られることを確認した。すなわち、図８に示す実施例１～１８のはんだ（接合材）を用いて２８０℃以上３００℃以下の温度で接合することで、図２に示す接合後の構造を得ることができる。なお、他の部材に対する熱の影響を考慮すると、２８０℃以上においてもできるだけ低い温度で接合することが望ましい。 Further, in Examples 17 and 18 shown in FIG. 8, the case where the solder bonding temperature was 300 ° C. was evaluated, and it was confirmed that the same structure after bonding as in the case of 280 ° C. was obtained even at 300 ° C. That is, the structure after joining shown in FIG. 2 can be obtained by joining at a temperature of 280 ° C. or more and 300 ° C. or less using the solder (joining material) of Examples 1 to 18 shown in FIG. In consideration of the influence of heat on other members, it is desirable to join at a temperature as low as possible even at 280 ° C. or higher.
　次に、Ｃｕの添加量（Ｃｕ：１重量％以上７重量％以下）について説明する。 Next, the amount of Cu added (Cu: 1 wt% or more and 7 wt% or less) will be described.
　Ｃｕを１重量％以上で、かつ７重量％以下の添加量とし、接合温度２８０℃以上で接合することにより、接合界面にＣｕ－Ｓｎ化合物が形成される。 Cu—Sn compound is formed at the bonding interface by adding Cu at 1 wt% or more and 7 wt% or less and bonding at a bonding temperature of 280 ° C. or higher.
　しかしながら、図８の比較例１に示すようにＣｕの添加量が１％未満の場合、添加したＣｕはＳｎ中に固溶してしまうため、接合界面にＣｕ－Ｓｎ系化合物層が十分に形成されず界面安定性が維持できない。一方、Ｃｕの添加量が増加すると比較例４に示すように、はんだ合金中の化合物の割合も増加し、溶融時の粘性が上昇しボイド率が上昇するため、Ｃｕの添加量は５重量％以下とした。これらのことより、Ｃｕを１重量％以上７重量％以下の添加量とすることではんだ接合における良好な信頼性を得ることができる。 However, as shown in Comparative Example 1 in FIG. 8, when the added amount of Cu is less than 1%, the added Cu is dissolved in Sn, so that a Cu—Sn based compound layer is sufficiently formed at the bonding interface. Interface stability cannot be maintained. On the other hand, when the amount of Cu increases, as shown in Comparative Example 4, the proportion of the compound in the solder alloy also increases, the viscosity at the time of melting increases and the void ratio increases, so the amount of Cu added is 5% by weight. It was as follows. From these things, the favorable reliability in solder joining can be acquired by making Cu the addition amount of 1 to 7 weight%.
　次に、Ｓｂの添加量（Ｓｂ：３重量%以上１５重量％以下）について説明する。 Next, the amount of Sb added (Sb: 3% by weight to 15% by weight) will be described.
　図８に示す実施例１においてＳｂを１重量％より多く添加することで温度サイクル信頼性が維持可能となる。一方、比較例６に示すようにＳｂを１５％以上添加するとボイド率の評価が×となり、また温度サイクル信頼性も×となる。これは、Ｓｂの添加量が増加するとはんだ中のＳｎ－Ｓｂ系化合物の析出量が増加し、さらにはんだの粘度が上昇しボイド率が上昇するとともにはんだが硬くなり温度サイクル信頼性が低下するためである。 In Example 1 shown in FIG. 8, the temperature cycle reliability can be maintained by adding more than 1% by weight of Sb. On the other hand, as shown in Comparative Example 6, when 15% or more of Sb is added, the void ratio is evaluated as x, and the temperature cycle reliability is also x. This is because as the amount of Sb added increases, the amount of Sn—Sb-based compound precipitated in the solder increases, and the viscosity of the solder increases, the void ratio increases, the solder becomes harder, and the temperature cycle reliability decreases. It is.
　次に、半導体装置の他の構造について説明する。図９は本発明の実施の形態の鉛フリーはんだ合金（接合材）を用いた半導体装置（半導体パワーモジュール）の構造の一例を示す断面図である。 Next, another structure of the semiconductor device will be described. FIG. 9 is a cross-sectional view showing an example of the structure of a semiconductor device (semiconductor power module) using the lead-free solder alloy (joining material) according to the embodiment of the present invention.
　図９に示す半導体パワーモジュール（半導体装置であり、以降、半導体モジュールともいう）１０は、例えば、鉄道の車両や自動車等に搭載されるパワーモジュールである。したがって、パワーモジュールの放熱対策が必要となる。半導体モジュール１０の構成について説明すると、半導体チップ１が、本実施の形態のはんだ合金（実施例１～１８のはんだ合金（接合材）の何れか）２ｂを用いてセラミック基板（チップ支持部材、絶縁性基板、被接続部材）５に接続されたものである。さらに、半導体チップ１の動作時の熱を逃がす役割を果たす放熱用金属板（放熱部材、放熱ベース、放熱板、放熱フィン、ヒートシンクの概念を含むものである）１２とセラミック基板５とが、本実施の形態の鉛フリーはんだ合金であるはんだ合金２ｃ（接合材であり、実施例１～１８の鉛フリーはんだ合金の何れか）を用いて接続されている。 A semiconductor power module (a semiconductor device, hereinafter also referred to as a semiconductor module) 10 shown in FIG. 9 is a power module mounted on, for example, a railway vehicle or an automobile. Therefore, heat dissipation measures for the power module are required. The configuration of the semiconductor module 10 will be described. The semiconductor chip 1 is formed of a ceramic substrate (chip support member, insulating material) using the solder alloy (any of the solder alloys (joining materials) of Examples 1 to 18) 2b of the present embodiment. (Connected substrate, connected member) 5. Further, a metal plate for heat radiation (including a concept of a heat radiation member, a heat radiation base, a heat radiation plate, a heat radiation fin, and a heat sink) 12 and a ceramic substrate 5 that play a role of releasing heat during operation of the semiconductor chip 1 are provided in this embodiment. Solder alloy 2c (a joining material, any of the lead-free solder alloys of Examples 1 to 18), which is a lead-free solder alloy of the form, is connected.
　図９に示す半導体モジュール１０の具体的構造について説明すると、半導体チップ１と、半導体チップ１とはんだ合金２ｂを介して接続されたチップ支持部材であるセラミック基板（絶縁基板、被接続部材）５と、半導体チップ１と電気的に接続されたリード（外部端子）１３とを有している。すなわち、セラミック基板５の基板本体部５ｅの上面５ａには、配線パターン等の導体部５ｄが形成され、この導体部５ｄ上にはんだ合金（実施例１～１８の鉛フリーはんだ合金の何れか）２ｂを介して半導体チップ１が搭載されている。 The specific structure of the semiconductor module 10 shown in FIG. 9 will be described. The semiconductor chip 1, and a ceramic substrate (insulating substrate, connected member) 5 which is a chip support member connected to the semiconductor chip 1 via a solder alloy 2b; And a lead (external terminal) 13 electrically connected to the semiconductor chip 1. That is, a conductor portion 5d such as a wiring pattern is formed on the upper surface 5a of the substrate body portion 5e of the ceramic substrate 5, and a solder alloy (any of the lead-free solder alloys of Examples 1 to 18) is formed on the conductor portion 5d. The semiconductor chip 1 is mounted via 2b.
　また、セラミック基板５の基板本体部５ｅの上面５ａには、配線部（配線パターン）５ｃが形成され、リード１３はこの配線部５ｃに電気的に接続されている。そして、半導体チップ１の主面１ａに形成された電極パッド１ｃとリード１３とが、および、電極パッド１ｃと配線部５ｃとが、それぞれ金線または銅線等のワイヤ１１によって電気的に接続されている。 Further, a wiring part (wiring pattern) 5c is formed on the upper surface 5a of the substrate body 5e of the ceramic substrate 5, and the leads 13 are electrically connected to the wiring part 5c. The electrode pad 1c and the lead 13 formed on the main surface 1a of the semiconductor chip 1 and the electrode pad 1c and the wiring part 5c are electrically connected by a wire 11 such as a gold wire or a copper wire, respectively. ing.
　また、セラミック基板５の基板本体部５ｅの下面５ｂには配線部５ｃが形成され、この配線部５ｃにはんだ合金２ｃ（実施例１～１８の鉛フリーはんだ合金の何れか）を介して放熱用金属板（放熱部材）１２が接続されている。 Further, a wiring portion 5c is formed on the lower surface 5b of the substrate body portion 5e of the ceramic substrate 5, and the wiring portion 5c is used for heat dissipation via the solder alloy 2c (any of the lead-free solder alloys of Examples 1 to 18). A metal plate (heat radiating member) 12 is connected.
　次に、半導体モジュール（パワーモジュール）１０の組立工法について説明する。半導体モジュール１０は、半導体チップ１とセラミック基板５とをはんだ合金２ｂで接続し、その後、セラミック基板５と放熱用金属板１２とを別のはんだ合金２ｃによって接続することで製造される。 Next, an assembly method for the semiconductor module (power module) 10 will be described. The semiconductor module 10 is manufactured by connecting the semiconductor chip 1 and the ceramic substrate 5 with the solder alloy 2b, and then connecting the ceramic substrate 5 and the heat radiating metal plate 12 with another solder alloy 2c.
　ここで、セラミック基板５と放熱用金属板１２とを接続する際の加熱で、半導体チップ１とセラミック基板５とを接続するはんだ合金２ｂが再溶融すると、溶融したはんだが流れ、半導体チップ１の位置ずれ等が発生し、不良に至る。一般的に、はんだ合金２ｂの再溶融を防ぐためには、はんだ合金２ｃは、はんだ合金２ｂよりも融点の低い材料を採用する必要がある。しかしながら、本実施の形態のはんだ合金２（２ｂ，２ｃ）である実施例１～１８のはんだ合金２を用いた場合、接続界面に図３に示すような起伏のあるＣｕ－Ｓｎ系化合物層４が形成されるため、はんだ流れが生じることなく、半導体チップ１の位置ずれは生じない。 Here, when the solder alloy 2b that connects the semiconductor chip 1 and the ceramic substrate 5 is remelted by heating when connecting the ceramic substrate 5 and the heat radiating metal plate 12, the molten solder flows, Misalignment or the like occurs, leading to a failure. Generally, in order to prevent remelting of the solder alloy 2b, it is necessary to employ a material having a melting point lower than that of the solder alloy 2b. However, when the solder alloy 2 of Examples 1 to 18 which is the solder alloy 2 (2b, 2c) of the present embodiment is used, the Cu—Sn-based compound layer 4 having undulations as shown in FIG. Therefore, no solder flow occurs and the semiconductor chip 1 is not displaced.
　そこで、実施例１～１８のはんだ合金２の何れかを、図９に示す半導体モジュール１０のはんだ合金２ｂに適用し、実施例１～１８と同様に、接合温度２８０℃、保持時間５ｍｉｎ、Ｎ2 ＋４％Ｈ2 雰囲気で、半導体チップ１と、Ｎｉめっき層３を形成したＮｉ／Ｃｕ／Ｓｉ3 Ｎ4 ／Ｃｕ／Ｎｉのセラミック基板５とを接続し、これによって接続体である半導体装置９を得た。 Therefore, any one of the solder alloys 2 of Examples 1 to 18 is applied to the solder alloy 2b of the semiconductor module 10 shown in FIG. 9, and, similarly to Examples 1 to 18, the bonding temperature is 280 ° C., the holding time is 5 min, N In a 2 + 4% H 2 atmosphere, the semiconductor chip 1 and the Ni / Cu / Si 3 N 4 / Cu / Ni ceramic substrate 5 on which the Ni plating layer 3 is formed are connected, thereby the semiconductor device 9 as a connection body. Got.
　さらに、ＡｌＳｉＣ／Ｎｉ基板である放熱用金属板１２と半導体装置９とによって実施例１～１８の何れかのはんだ合金２ｃを挟み込み、接合温度２８０℃、保持時間５ｍｉｎ、無荷重、１００％Ｈ2 雰囲気で接続し、半導体モジュール１０を形成した。したがって、半導体装置９のはんだ合金２ｂが再溶融することなくセラミック基板５と放熱用金属板１２とを接続することができる。 Further, the solder alloy 2c of any of Examples 1 to 18 is sandwiched between the heat dissipation metal plate 12 which is an AlSiC / Ni substrate and the semiconductor device 9, and the bonding temperature is 280 ° C., the holding time is 5 min, no load, 100% H 2. The semiconductor module 10 was formed by connecting in an atmosphere. Therefore, the ceramic substrate 5 and the heat radiating metal plate 12 can be connected without remelting the solder alloy 2b of the semiconductor device 9.
　このように形成した半導体装置９について、リード１３を接続し、また、半導体チップ１の主面１ａの電極パッド１ｃと、セラミック基板５上の配線部５ｃやリード１３とをワイヤ１１でボンディングすることにより、半導体モジュール１０を形成することができる。 The lead 13 is connected to the semiconductor device 9 thus formed, and the electrode pad 1c on the main surface 1a of the semiconductor chip 1 is bonded to the wiring portion 5c and the lead 13 on the ceramic substrate 5 with the wire 11. Thus, the semiconductor module 10 can be formed.
　なお、半導体モジュール１０では、鉛フリーはんだ合金（はんだ合金２）と半導体チップ１との接続部の界面、上記鉛フリーはんだ合金とセラミック基板５との接続部の界面、および上記鉛フリーはんだ合金と放熱用金属板１２との接続部の界面に、それぞれＮｉめっき層３が形成されている。 In the semiconductor module 10, the interface between the lead-free solder alloy (solder alloy 2) and the semiconductor chip 1, the interface between the lead-free solder alloy and the ceramic substrate 5, and the lead-free solder alloy Ni plating layers 3 are respectively formed at the interfaces of the connecting portions with the heat radiating metal plate 12.
　そして、上述のように半導体モジュール１０の各接続部に本実施の形態のはんだ合金２（実施例１～１８の鉛フリーはんだ合金（はんだ合金２、接合材）の何れか）を適用することにより、鉛フリーはんだ合金の各接続部において、それぞれの界面にＣｕ－Ｓｎ系化合物層（図２参照）４を厚く形成することができ、その結果、各接続部における界面安定性を向上させることができる。 Then, by applying the solder alloy 2 of the present embodiment (any of the lead-free solder alloys of Examples 1 to 18 (solder alloy 2, bonding material)) to each connection portion of the semiconductor module 10 as described above. In each connection part of the lead-free solder alloy, the Cu—Sn compound layer (see FIG. 2) 4 can be formed thick at each interface, and as a result, the interface stability at each connection part can be improved. it can.
　これにより、鉛フリーはんだ合金（はんだ合金２）の各接続部における接続信頼性を高めることができる。 Thereby, the connection reliability in each connection part of the lead-free solder alloy (solder alloy 2) can be improved.
　なお、本実施例では、片面から冷却する構造のモジュールを説明したが、図１０に示すように半導体チップ１の両側から放熱する構造のモジュールにも適用可能である。図１０は、本発明の実施の形態の鉛フリーはんだ合金を用いた半導体装置（半導体パワーモジュール）の構造の一例を示す断面図である。 In this embodiment, the module having a structure for cooling from one side has been described. However, the present invention can be applied to a module having a structure for radiating heat from both sides of the semiconductor chip 1 as shown in FIG. FIG. 10 is a cross-sectional view showing an example of the structure of a semiconductor device (semiconductor power module) using the lead-free solder alloy according to the embodiment of the present invention.
　図１０に示す半導体モジュール（半導体パワーモジュール）１９は、半導体チップ１の表裏両面にはんだ合金２ｂやはんだ合金２ｂ等の接合材が接合され、これら半導体チップ１の両面の接合材にリードフレーム２８が接合され、さらにリードフレーム２８に絶縁性放熱グリース２７を介して放熱用金属板１２が接合されている。 A semiconductor module (semiconductor power module) 19 shown in FIG. 10 has a bonding material such as solder alloy 2b or solder alloy 2b bonded to the front and back surfaces of the semiconductor chip 1, and lead frames 28 are bonded to the bonding materials on both surfaces of the semiconductor chip 1. Further, the heat radiating metal plate 12 is bonded to the lead frame 28 via the insulating heat radiating grease 27.
　このように本実施の形態のはんだ接合部の構造は、半導体チップ１の表裏両面側から放熱用金属板１２によって放熱する構造のパワーモジュール（半導体モジュール１９）にも適用可能である。 As described above, the structure of the solder joint portion of the present embodiment is also applicable to a power module (semiconductor module 19) having a structure in which heat is radiated from the front and back both sides of the semiconductor chip 1 by the heat radiating metal plate 12.
　また、本実施の形態のはんだ接合部の構造は、例えば、後述する図１６のようなダイオードチップを搭載していない小型化した半導体モジュール３４においても適用可能である。パワーモジュール（半導体モジュール３４）を小型化することで一般に電流密度が上がるため、はんだ接合部の温度も上昇するが、本願発明を用いることにより、実現することができる。 Also, the structure of the solder joint portion of the present embodiment can be applied to, for example, a miniaturized semiconductor module 34 that is not mounted with a diode chip as shown in FIG. Since the current density generally increases by downsizing the power module (semiconductor module 34), the temperature of the solder joint also increases. However, this can be realized by using the present invention.
　次に、図１１に示す、半導体モジュール１０が搭載された鉄道の車両について説明する。図１１は本実施の形態の鉛フリーはんだ合金を用いた半導体モジュール１０が搭載された鉄道の車両の一例を示す部分側面図、図１２は図１１の車両に設置されたインバータの内部構造の一例を示す平面図である。 Next, a railway vehicle on which the semiconductor module 10 shown in FIG. 11 is mounted will be described. FIG. 11 is a partial side view showing an example of a railway vehicle on which the semiconductor module 10 using the lead-free solder alloy of the present embodiment is mounted, and FIG. 12 shows an example of the internal structure of the inverter installed in the vehicle of FIG. FIG.
　図１１は、集電装置であるパンタグラフ２２を備えた鉄道の車両２１であり、車両２１の下部にはインバータ２３が設けられている。図１２に示すように、インバータ２３の内部では、プリント基板２５上に複数の半導体モジュール１０が搭載され、さらにこれらの半導体モジュール１０を冷却する冷却装置２４が搭載されている。 FIG. 11 shows a railway vehicle 21 provided with a pantograph 22 that is a current collector, and an inverter 23 is provided below the vehicle 21. As shown in FIG. 12, inside the inverter 23, a plurality of semiconductor modules 10 are mounted on a printed circuit board 25, and a cooling device 24 that cools these semiconductor modules 10 is further mounted.
　半導体モジュール１０は、パワーモジュールであるため、半導体チップ１からの発熱量が多い。したがって、複数の半導体モジュール１０を冷却してインバータ２３の内部を冷却可能なように冷却装置２４が取り付けられている。 Since the semiconductor module 10 is a power module, it generates a large amount of heat from the semiconductor chip 1. Therefore, the cooling device 24 is attached so that the plurality of semiconductor modules 10 can be cooled to cool the inside of the inverter 23.
　このように鉄道の車両２１に、本実施の形態の鉛フリーはんだ合金（はんだ合金２）が用いられた複数の半導体モジュール１０を搭載したインバータ２３が設けられていることにより、インバータ２３内が高温環境となった場合であっても、インバータ２３およびそれが設けられた車両２１の信頼性を高めることができる。 As described above, the inverter 23 equipped with the plurality of semiconductor modules 10 using the lead-free solder alloy (solder alloy 2) of the present embodiment is provided in the railway vehicle 21, so that the temperature inside the inverter 23 is high. Even when it becomes an environment, the reliability of the inverter 23 and the vehicle 21 provided with the inverter 23 can be improved.
　次に、図１３に示す半導体装置は、例えば、車載用の交流発電機用の半導体モジュール（半導体パワーモジュール）１８である。そして、図１４は、図１３に示す半導体パワーモジュールが搭載された自動車の一例を示す斜視図である。 Next, the semiconductor device shown in FIG. 13 is, for example, a semiconductor module (semiconductor power module) 18 for an on-vehicle AC generator. FIG. 14 is a perspective view showing an example of an automobile on which the semiconductor power module shown in FIG. 13 is mounted.
　図１３に示す半導体モジュール１８の構成について説明すると、半導体チップ（ダイオード）１と、半導体チップ１の裏面１ｂと本実施の形態のはんだ合金（鉛フリーはんだ合金）２ｃを介して接続される接続部にＮｉ系めっきが施された筒状のキャップ（リード電極体）１５と、を備えている。さらに、半導体モジュール１８は、半導体チップ１の主面１ａと本実施の形態のはんだ合金（鉛フリーはんだ合金）２ｂを介して接続される接続部にＮｉ系めっきを施した熱膨張率差緩衝用の緩衝材１７と、緩衝材１７の他方の面と本実施の形態のはんだ合金（鉛フリーはんだ合金）２ｃを介して接続される接続部にＮｉ系めっきを施したＣｕリード（外部端子）１４と、を備えている。 The configuration of the semiconductor module 18 shown in FIG. 13 will be described. The connection portion connected to the semiconductor chip (diode) 1 and the back surface 1b of the semiconductor chip 1 via the solder alloy (lead-free solder alloy) 2c of the present embodiment. And a cylindrical cap (lead electrode body) 15 having Ni plating applied thereto. Further, the semiconductor module 18 is for thermal expansion coefficient difference buffering in which Ni-based plating is applied to a connection portion connected to the main surface 1a of the semiconductor chip 1 via the solder alloy (lead-free solder alloy) 2b of the present embodiment. Buffer material 17, and Cu lead (external terminal) 14 having Ni-based plating applied to the connecting portion connected to the other surface of the buffer material 17 via the solder alloy (lead-free solder alloy) 2 c of the present embodiment. And.
　また、筒状のキャップ１５内には、半導体チップ１や緩衝材１７やはんだ合金２ｂ、２ｃおよびＣｕリード１４の一部を封止する封止用の樹脂１６が充填されている。 The cylindrical cap 15 is filled with a sealing resin 16 that seals part of the semiconductor chip 1, the buffer material 17, the solder alloys 2 b and 2 c, and the Cu lead 14.
　なお、半導体チップ１とＣｕリード１４との間に、緩衝材１７を配置（挿入）することにより、接続後の冷却時および温度サイクル時に、接続部に被接続部材の熱膨張率差により発生する応力を緩衝することができる。緩衝材１７の厚さは、３０～５００μｍにすることが好ましい。これは、緩衝材１７の厚さが、３０μｍ未満の場合、応力を充分に緩衝できずに、半導体チップ１および金属間化合物にクラックが発生する場合がある。また、緩衝材１７の厚さが、５００μｍ超の場合、Ａｌ、Ｍｇ、Ａｇ、ＺｎはＣｕリード１４より熱膨張率が大きいため、熱膨張率差の影響により、接続信頼性の低下につながる場合がある。また、緩衝材１７としては、Ｃｕ／インバー合金／Ｃｕ複合材、Ｃｕ／Ｃｕ複合材Ｃｕ－Ｍｏ合金、Ｔｉ、Ｍｏ、Ｗの何れかを用いることが好ましい。この緩衝材１７が設けられたにより、半導体チップ１とＣｕリード１４との間の熱膨張率差から生じる温度サイクル時および接続後の冷却時の接続部に発生する応力を緩衝することができる。 In addition, by disposing (inserting) the buffer material 17 between the semiconductor chip 1 and the Cu lead 14, it is generated due to the difference in thermal expansion coefficient of the connected member at the time of cooling after connection and at the time of temperature cycle. Stress can be buffered. The thickness of the buffer material 17 is preferably 30 to 500 μm. This is because when the thickness of the buffer material 17 is less than 30 μm, the stress cannot be sufficiently buffered, and cracks may occur in the semiconductor chip 1 and the intermetallic compound. Further, when the thickness of the buffer material 17 exceeds 500 μm, Al, Mg, Ag, and Zn have a larger coefficient of thermal expansion than the Cu lead 14, and therefore the connection reliability is reduced due to the influence of the difference in coefficient of thermal expansion. There is. Further, as the buffer material 17, it is preferable to use any one of Cu / Invar alloy / Cu composite material, Cu / Cu composite material Cu—Mo alloy, Ti, Mo, and W. By providing the buffer material 17, it is possible to buffer the stress generated in the connection portion during the temperature cycle and the cooling after the connection resulting from the difference in thermal expansion coefficient between the semiconductor chip 1 and the Cu lead 14.
　その結果、半導体チップ１にかかる応力を低減することができ、半導体チップ１にクラックが形成されることを低減できる。さらに、半導体モジュール１８において、はんだ接続の接続信頼性を高めることができる。 As a result, the stress applied to the semiconductor chip 1 can be reduced, and the formation of cracks in the semiconductor chip 1 can be reduced. Furthermore, in the semiconductor module 18, the connection reliability of the solder connection can be improved.
　また、図１４に示す自動車３２は、例えば、図１３に示す半導体モジュール１８が搭載されたものであり、車体３１と、タイヤ２９と、半導体モジュール１８と、半導体モジュール１８を支持する実装部材である実装ユニット３０と、を備えている。 Further, for example, the automobile 32 shown in FIG. 14 is mounted with the semiconductor module 18 shown in FIG. 13, and is a vehicle body 31, a tire 29, the semiconductor module 18, and a mounting member that supports the semiconductor module 18. And a mounting unit 30.
　半導体モジュール１８は、実装ユニット３０に搭載されているが、実装ユニット３０は、例えば、エンジン制御ユニット等であり、その場合、実装ユニット３０はエンジンの近傍に配置されている。この場合には、実装ユニット３０は、高温環境下での使用となり、これにより、半導体モジュール１８も高温状態となる。 The semiconductor module 18 is mounted on the mounting unit 30. The mounting unit 30 is, for example, an engine control unit, and in this case, the mounting unit 30 is disposed in the vicinity of the engine. In this case, the mounting unit 30 is used in a high temperature environment, and the semiconductor module 18 is also in a high temperature state.
　しかしながら、自動車３２において、実装ユニット３０が高温環境となった場合であっても、半導体モジュール１８のはんだ接続部に、本実施の形態のはんだ合金２（実施例１～１８の鉛フリーはんだ合金（はんだ合金２、接合材）の何れか）を適用することにより、鉛フリーはんだ合金の各接続部において、それぞれの界面にＣｕ－Ｓｎ系化合物層（図２参照）４を厚く形成することができる。その結果、各はんだ接続部における界面安定性を向上させることができる。 However, in the automobile 32, even when the mounting unit 30 is in a high temperature environment, the solder alloy 2 of the present embodiment (the lead-free solder alloys of Examples 1 to 18 ( By applying any one of the solder alloy 2 and the bonding material), the Cu—Sn based compound layer (see FIG. 2) 4 can be formed thick at each interface at each connection portion of the lead-free solder alloy. . As a result, the interface stability at each solder connection portion can be improved.
　これにより、鉛フリーはんだ合金（はんだ合金２）の各接続部における接続信頼性を高めることができる。すなわち、半導体モジュール１８の信頼性を高めることができる。 Thereby, the connection reliability in each connection part of the lead-free solder alloy (solder alloy 2) can be improved. That is, the reliability of the semiconductor module 18 can be increased.
　その結果、自動車３２の信頼性を高めることができる。 As a result, the reliability of the automobile 32 can be improved.
　（変形例）
　図１５は本発明の実施の形態の第１変形例の半導体パワーモジュールの構造を示す断面図である。図１５に示す半導体モジュール（半導体パワーモジュール）３３は、複数の半導体チップ３３ａと複数の半導体チップ３３ｂが、セラミック基板５上に搭載されたパワーモジュールである。半導体チップ３３ａは、例えば、ＳｉＣから成るＭＯＳ(Metal Oxide Semiconductor)であり、半導体チップ３３ｂは、例えば、ＳｉＣから成るダイオードである。この場合、半導体モジュール３３は、フルＳｉＣモジュール等とも呼ばれ、搭載されている各半導体チップがＳｉＣから成る。 (Modification)
FIG. 15 is a cross-sectional view showing the structure of a semiconductor power module of a first modification of the embodiment of the present invention. A semiconductor module (semiconductor power module) 33 shown in FIG. 15 is a power module in which a plurality of semiconductor chips 33 a and a plurality of semiconductor chips 33 b are mounted on the ceramic substrate 5. The semiconductor chip 33a is, for example, a MOS (Metal Oxide Semiconductor) made of SiC, and the semiconductor chip 33b is, for example, a diode made of SiC. In this case, the semiconductor module 33 is also called a full SiC module or the like, and each mounted semiconductor chip is made of SiC.
　半導体モジュール３３においても、半導体チップ３３ａや半導体チップ３３ｂの各下面側にはんだ合金（接合材、鉛フリーはんだ合金）２ｂが適用され、セラミック基板５と放熱用金属板１２との間には、はんだ合金２ｃ（接合材、鉛フリーはんだ合金）が適用されている。 Also in the semiconductor module 33, a solder alloy (joining material, lead-free solder alloy) 2b is applied to each lower surface side of the semiconductor chip 33a and the semiconductor chip 33b, and a solder is interposed between the ceramic substrate 5 and the heat radiating metal plate 12. Alloy 2c (joining material, lead-free solder alloy) is applied.
　さらに、半導体モジュール３３においても、リード１３がセラミック基板５の配線部５ｃに電気的に接続され、そして、半導体チップ３３ａ，３３ｂそれぞれの電極パッドと、セラミック基板５上の配線部５ｃとがワイヤ１１によってボンディングされている。 Further, also in the semiconductor module 33, the lead 13 is electrically connected to the wiring part 5 c of the ceramic substrate 5, and the electrode pads of the semiconductor chips 33 a and 33 b and the wiring part 5 c on the ceramic substrate 5 are connected to the wire 11. It is bonded by.
　上述のように半導体モジュール３３のはんだ接続部に本実施の形態のはんだ合金２（実施例１～１８の鉛フリーはんだ合金（はんだ合金２、接合材）の何れか）を適用することにより、鉛フリーはんだ合金の各接続部において、それぞれの界面にＣｕ－Ｓｎ系化合物層（図２参照）４を厚く形成することができ、その結果、各はんだ接続部における界面安定性を向上させることができる。 By applying the solder alloy 2 of this embodiment (any of the lead-free solder alloys of Examples 1 to 18 (solder alloy 2, bonding material)) to the solder connection portion of the semiconductor module 33 as described above, lead In each connection portion of the free solder alloy, the Cu—Sn-based compound layer (see FIG. 2) 4 can be formed thick at each interface, and as a result, the interface stability at each solder connection portion can be improved. .
　これにより、鉛フリーはんだ合金（はんだ合金２）の各接続部における接続信頼性を高めることができる。すなわち、半導体モジュール３３の信頼性を高めることができる。 Thereby, the connection reliability in each connection part of the lead-free solder alloy (solder alloy 2) can be improved. That is, the reliability of the semiconductor module 33 can be increased.
　次に、図１６は、本発明の実施の形態の第２変形例の半導体パワーモジュールの構造を示す断面図である。図１６に示す半導体モジュール３４は、複数の半導体チップ３４ａが、セラミック基板５上に搭載されたパワーモジュールである。半導体チップ３４ａは、例えば、ＳｉＣから成るＭＯＳであり、さらにダイオードを内蔵している。 Next, FIG. 16 is a cross-sectional view showing the structure of a semiconductor power module of a second modification of the embodiment of the present invention. The semiconductor module 34 shown in FIG. 16 is a power module in which a plurality of semiconductor chips 34 a are mounted on the ceramic substrate 5. The semiconductor chip 34a is, for example, a MOS MOS, and further includes a diode.
　つまり、ダイオードが半導体チップ３４ａ内に組み込まれており、この場合の半導体モジュール３４も、フルＳｉＣモジュール等とも呼ばれる。 That is, the diode is incorporated in the semiconductor chip 34a, and the semiconductor module 34 in this case is also called a full SiC module or the like.
　半導体モジュール３４においても、半導体モジュール３３と同様に、半導体チップ３４ａの下面側にはんだ合金（接合材、鉛フリーはんだ合金）２ｂが適用され、セラミック基板５と放熱用金属板１２との間には、はんだ合金２ｃ（接合材、鉛フリーはんだ合金）が適用されている。 Also in the semiconductor module 34, like the semiconductor module 33, a solder alloy (joining material, lead-free solder alloy) 2 b is applied to the lower surface side of the semiconductor chip 34 a, and between the ceramic substrate 5 and the heat radiating metal plate 12. Solder alloy 2c (joining material, lead-free solder alloy) is applied.
　さらに、半導体モジュール３４においても、リード１３がセラミック基板５の配線部５ｃに電気的に接続され、そして、半導体チップ３０ａの電極パッドと、セラミック基板５上の配線部５ｃとがワイヤ１１によってボンディングされている。 Further, also in the semiconductor module 34, the lead 13 is electrically connected to the wiring portion 5 c of the ceramic substrate 5, and the electrode pad of the semiconductor chip 30 a and the wiring portion 5 c on the ceramic substrate 5 are bonded by the wire 11. ing.
　上述のように半導体モジュール３４のはんだ接続部に本実施の形態のはんだ合金２（実施例１～１８の鉛フリーはんだ合金（はんだ合金２、接合材）の何れか）を適用することにより、鉛フリーはんだ合金の各接続部において、それぞれの界面にＣｕ－Ｓｎ系化合物層（図２参照）４を厚く形成することができ、その結果、各接続部における界面安定性を向上させることができる。 By applying the solder alloy 2 of the present embodiment (any of the lead-free solder alloys of Examples 1 to 18 (solder alloy 2, bonding material)) to the solder connection portion of the semiconductor module 34 as described above, lead In each connection portion of the free solder alloy, the Cu—Sn-based compound layer (see FIG. 2) 4 can be formed thick at each interface, and as a result, the interface stability at each connection portion can be improved.
　これにより、鉛フリーはんだ合金（はんだ合金２）の各接続部における接続信頼性を高めることができる。すなわち、半導体モジュール３４の信頼性を高めることができる。 Thereby, the connection reliability in each connection part of the lead-free solder alloy (solder alloy 2) can be improved. That is, the reliability of the semiconductor module 34 can be increased.
　さらに、チップ内にダイオードを組み込むことにより、搭載するチップの数を少なくすることができる。その結果、半導体モジュール３３に比べて半導体モジュール３４のコストの低減化を図ることができる。 Furthermore, the number of chips to be mounted can be reduced by incorporating diodes in the chip. As a result, the cost of the semiconductor module 34 can be reduced compared to the semiconductor module 33.
　以上、本発明者によってなされた発明を発明の実施の形態に基づき具体的に説明したが、本発明は前記発明の実施の形態に限定されるものではなく、その要旨を逸脱しない範囲で種々変更可能であることは言うまでもない。 As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments of the invention. However, the present invention is not limited to the embodiments of the invention, and various modifications can be made without departing from the scope of the invention. It goes without saying that it is possible.
　なお、本発明は上記した実施の形態に限定されるものではなく、様々な変形例が含まれる。例えば、上記した実施の形態は本発明を分かりやすく説明するために詳細に説明したものであり、必ずしも説明した全ての構成を備えるものに限定されるものではない。 Note that the present invention is not limited to the above-described embodiment, and includes various modifications. For example, the above-described embodiment has been described in detail for easy understanding of the present invention, and is not necessarily limited to one having all the configurations described.
　また、ある実施の形態の構成の一部を他の実施の形態の構成に置き換えることが可能であり、また、ある実施の形態の構成に他の実施の形態の構成を加えることも可能である。また、各実施の形態の構成の一部について、他の構成の追加、削除、置換をすることが可能である。なお、図面に記載した各部材や相対的なサイズは、本発明を分かりやすく説明するため簡素化・理想化しており、実装上はより複雑な形状となる。 Further, a part of the configuration of one embodiment can be replaced with the configuration of another embodiment, and the configuration of another embodiment can be added to the configuration of one embodiment. . In addition, it is possible to add, delete, and replace other configurations for a part of the configuration of each embodiment. In addition, each member and relative size which were described in drawing are simplified and idealized in order to demonstrate this invention clearly, and it becomes a more complicated shape on mounting.
　また、上記実施の形態で説明した放熱用金属板１２は、板状の放熱板であってもよいし、あるいは複数のフィンが設けられた放熱部材等であってもよい。 Further, the heat radiating metal plate 12 described in the above embodiment may be a plate-shaped heat radiating plate, or a heat radiating member provided with a plurality of fins.
　また、本願発明の接合構造または接合方法は、自動車や鉄道車両の他、太陽光発電機またはパワーコンディショナまたは風力発電機または建設機械またはエレベータまたはエアコンまたは工作機械またはモータや圧縮機等の産業機器を動作させるインバータにも適用することができる。また、ＩＧＢＴモジュール、オルタネータ、交流発動機等にも適用することができる。 The joining structure or joining method of the present invention is not limited to automobiles and railway vehicles, but also solar power generators, power conditioners, wind power generators, construction machines, elevators, air conditioners, machine tools, motors, compressors, and other industrial equipment. The present invention can also be applied to an inverter that operates. It can also be applied to IGBT modules, alternators, AC motors, and the like.
　　　１　半導体チップ（半導体素子）
２，２ｂ，２ｃ，　はんだ合金（接合材）
　　　３　Ｎｉめっき層（Ｎｉメタライズ層）
　　　５　セラミック基板（チップ支持部材、絶縁基板、被接続部材）
　　　９　半導体装置（半導体モジュール、半導体パワーモジュール）
　　１０　半導体モジュール（半導体装置、半導体パワーモジュール）
　　１２　放熱用金属板（放熱ベース、放熱部材）
１８，１９，３３，３４　半導体モジュール（半導体装置、半導体パワーモジュール） 1 Semiconductor chip (semiconductor element)
2, 2b, 2c, solder alloy (joining material)
3 Ni plating layer (Ni metallized layer)
5 Ceramic substrate (chip support member, insulating substrate, connected member)
9 Semiconductor devices (semiconductor modules, semiconductor power modules)
10 Semiconductor modules (semiconductor devices, semiconductor power modules)
12 Metal plate for heat dissipation (heat dissipation base, heat dissipation member)
18, 19, 33, 34 Semiconductor module (semiconductor device, semiconductor power module)

Claims (11)

  1. 　半導体パワーモジュールであって、
    　半導体素子と、
    　前記半導体素子と接合する接合材と、
    　を有し、
    　前記半導体素子と絶縁基板とが、または、前記絶縁基板と放熱ベースとが、Ｃｕ１～７重量％と、Ｓｂ３～１５重量％と、残部Ｓｎとからなる前記接合材によって接合され、
    　前記接合材は２８０℃以上の温度で接合された、半導体パワーモジュール。     A semiconductor power module,
    A semiconductor element;
    A bonding material for bonding to the semiconductor element;
    Have
    The semiconductor element and the insulating substrate, or the insulating substrate and the heat dissipation base are bonded by the bonding material composed of Cu 1 to 7 wt%, Sb 3 to 15 wt%, and the remaining Sn,
    The semiconductor power module, wherein the bonding material is bonded at a temperature of 280 ° C. or higher.
  2. 　請求項１に記載の半導体パワーモジュールにおいて
    　前記接合材の接合部の界面にＣｕ－Ｓｎを主な構成元素とする金属間化合物が形成されている、半導体パワーモジュール。     The semiconductor power module according to claim 1, wherein an intermetallic compound containing Cu—Sn as a main constituent element is formed at an interface of a joint portion of the joining material.
  3. 　半導体パワーモジュールであって、
    　半導体素子と、
    　前記半導体素子と接合する接合材と、
    　を有し、
    　前記半導体素子と絶縁基板との間、または、前記絶縁基板と放熱ベースとの間の接合部における第１のＣｕ－Ｓｎ化合物、Ｓｎ－Ｃｕ－Ｓｂ層、第２のＣｕ－Ｓｎ化合物のそれぞれの厚さを足した前記接合部の厚さ比を１００とした場合、前記第１のＣｕ－Ｓｎ化合物と前記第２のＣｕ－Ｓｎ化合物の厚さの比は、１以上１０以下である、半導体パワーモジュール。     A semiconductor power module,
    A semiconductor element;
    A bonding material for bonding to the semiconductor element;
    Have
    Each of the first Cu—Sn compound, the Sn—Cu—Sb layer, and the second Cu—Sn compound at the junction between the semiconductor element and the insulating substrate or between the insulating substrate and the heat dissipation base. When the thickness ratio of the joint portion plus the thickness is 100, the ratio of the thicknesses of the first Cu—Sn compound and the second Cu—Sn compound is 1 or more and 10 or less. Power module.
  4. 　請求項１乃至３のいずれか１項に記載の半導体パワーモジュールにおいて、
    　前記半導体素子の裏面、前記絶縁基板、または、前記放熱ベースそれぞれの表面にＮｉメタライズ層が形成されている、半導体パワーモジュール。     The semiconductor power module according to any one of claims 1 to 3,
    A semiconductor power module, wherein a Ni metallized layer is formed on the back surface of the semiconductor element, the insulating substrate, or the surface of the heat dissipation base.
  5. 　請求項４に記載の半導体パワーモジュールにおいて、
    　前記絶縁基板と前記放熱ベースとの間の前記接合部の平均厚さが５０μｍ～４００μｍである、半導体パワーモジュール。     The semiconductor power module according to claim 4, wherein
    A semiconductor power module, wherein an average thickness of the joint portion between the insulating substrate and the heat dissipation base is 50 μm to 400 μm.
  6. 　半導体パワーモジュールを有する移動体であって、
    　前記半導体パワーモジュールは、半導体素子と絶縁基板との間、または、前記絶縁基板と放熱板との間に接合層を有しており、
    　前記接合層は、第１のＣｕ－Ｓｎ化合物とＳｎ－Ｃｕ－Ｓｂ層と第２のＣｕ－Ｓｎ化合物とから構成されており、前記接合層の厚さを１００とした場合に、前記第１のＣｕ－Ｓｎ化合物と前記第２のＣｕ－Ｓｎ化合物の厚さは１以上１０以下で構成された、移動体。     A mobile body having a semiconductor power module,
    The semiconductor power module has a bonding layer between a semiconductor element and an insulating substrate, or between the insulating substrate and a heat sink,
    The bonding layer includes a first Cu—Sn compound, a Sn—Cu—Sb layer, and a second Cu—Sn compound. When the thickness of the bonding layer is 100, the first A moving body in which the Cu—Sn compound and the second Cu—Sn compound have a thickness of 1 or more and 10 or less.
  7. 請求項６に記載の移動体において、
    　前記半導体素子が有する面のうち前記絶縁基板側の面、または、前記絶縁基板、または、前記放熱板の表面にＮｉメタライズ層が形成された、移動体。     The mobile body according to claim 6,
    A movable body in which a Ni metallized layer is formed on a surface of the semiconductor element on a surface of the insulating substrate, or on a surface of the insulating substrate or the heat sink.
  8. 　請求項６に記載の移動体において、
    　前記接合層の平均厚さが５０μｍ以上４００μｍ以下である、移動体。     The mobile body according to claim 6,
    The moving body in which the average thickness of the bonding layer is 50 μm or more and 400 μm or less.
  9. 　請求項６乃至８のいずれか１項に記載の移動体において、
    　前記移動体は、自動車である移動体。     The moving body according to any one of claims 6 to 8,
    The mobile body is a mobile body that is an automobile.
  10. 　請求項６乃至８のいずれか１項に記載の移動体において、
    　前記移動体は、鉄道車両である移動体。     The moving body according to any one of claims 6 to 8,
    The moving body is a moving body that is a railway vehicle.
  11. 　半導体パワーモジュールの製造方法であって、
    　半導体素子と絶縁基板とを、または、前記絶縁基板と放熱ベースとを、Ｃｕ１～７重量％と、Ｓｂ３～１５重量％と、残部Ｓｎとからなる接合材によって接合する工程を有し、
    　前記接合材を２８０℃以上に加熱して前記半導体素子と前記絶縁基板とを、または、前記絶縁基板と前記放熱ベースとを接合する、半導体パワーモジュールの製造方法。     A method for manufacturing a semiconductor power module, comprising:
    Bonding the semiconductor element and the insulating substrate or the insulating substrate and the heat dissipation base with a bonding material composed of Cu 1 to 7 wt%, Sb 3 to 15 wt%, and the remaining Sn,
    A manufacturing method of a semiconductor power module, wherein the bonding material is heated to 280 ° C. or more to bond the semiconductor element and the insulating substrate, or the insulating substrate and the heat dissipation base.
PCT/JP2014/080978 2014-11-21 2014-11-21 Semiconductor power module, method for manufacturing same and mobile object WO2016079881A1 (en)

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