WO2016147252A1 - Semiconductor apparatus and manufacturing method of same - Google Patents

Semiconductor apparatus and manufacturing method of same Download PDF

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Publication number
WO2016147252A1
WO2016147252A1 PCT/JP2015/057477 JP2015057477W WO2016147252A1 WO 2016147252 A1 WO2016147252 A1 WO 2016147252A1 JP 2015057477 W JP2015057477 W JP 2015057477W WO 2016147252 A1 WO2016147252 A1 WO 2016147252A1
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WO
WIPO (PCT)
Prior art keywords
bonding material
semiconductor device
melting point
semiconductor chip
wiring board
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Application number
PCT/JP2015/057477
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French (fr)
Japanese (ja)
Inventor
高彰 宮崎
靖 池田
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株式会社日立製作所
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Priority to PCT/JP2015/057477 priority Critical patent/WO2016147252A1/en
Publication of WO2016147252A1 publication Critical patent/WO2016147252A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/52—Mounting semiconductor bodies in containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/40—Mountings or securing means for detachable cooling or heating arrangements ; fixed by friction, plugs or springs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

Definitions

  • the present invention relates to a semiconductor device and a manufacturing technique thereof, and more particularly to a power semiconductor device used for an inverter.
  • power semiconductor devices have a structure in which a semiconductor element (hereinafter also referred to as a semiconductor chip or simply a chip) and an insulating substrate, or an insulating substrate and a metal plate for heat dissipation are joined together by solder or the like. .
  • Solder which is a connecting member used for electrical connection of electrical and electronic equipment components, generally contained lead.
  • ELV Directive End-of Life Life Vehicles Directive
  • RoHS Restriction of the use of certain Hazardous Substances in electrical
  • lead (Pb) -containing solder has been used as a connecting member for semiconductor devices that require high heat resistance, particularly semiconductor devices used in the fields of automobiles, construction machinery, railways, and information equipment. There is a strong demand to use lead-free connecting members for reduction.
  • Si (silicon) semiconductor elements In recent years, development of wide gap semiconductors such as SiC and GaN capable of operating at high temperatures and reducing the size and weight of devices has been promoted.
  • the upper limit of the operating temperature of Si (silicon) semiconductor elements is 150 to 175 ° C., whereas SiC semiconductor elements can be used at 175 ° C. or higher.
  • Patent Document 1 Japanese Patent Application Laid-Open No. 2008-300792 discloses that “a base layer formed by curing a metal particle paste at a high temperature and a metal particle in a surface film formed by curing the metal particle paste at a low temperature include a low-temperature metal solder. A bonding layer composed of a high-temperature metal brazing material layer that is dispersed and absorbed in the material. By joining the back side of the semiconductor chip and the copper wiring pattern, it is possible to ensure strong heat resistance and power cycle performance. In addition, a technique capable of improving the reliability of a semiconductor device (see summary) is disclosed.
  • a semiconductor device in which a high-temperature metal brazing material is formed at the center of the joint and a low-temperature metal brazing material is formed outside the semiconductor chip and the insulating substrate. A part of the low-temperature metal brazing material is formed. Therefore, there is a concern that a crack in the substrate thickness direction (vertical direction) is formed in the power cycle test.
  • An object of the present invention is to provide a technique capable of improving the reliability of a semiconductor device.
  • a semiconductor device supports a semiconductor chip and is electrically connected to the semiconductor chip, a metal plate supporting the wiring board, and disposed between the wiring board and the metal plate. And a bonding material for bonding the wiring board and the metal plate. Furthermore, the bonding material is disposed around the first bonding material in a plan view and a first bonding material formed directly below the semiconductor chip and having a plane size equal to or larger than the plane size of the semiconductor chip. The first bonding material has a melting point higher than that of the second bonding material.
  • the method for manufacturing a semiconductor device includes: (a) a step of mounting a semiconductor chip on a wiring board; (b) mounting the wiring board on which the semiconductor chip is mounted on a metal plate via a bonding material. And in the step (b), the bonding material is heated and melted to bond the wiring board and the metal plate. Further, the bonding material is provided immediately below the semiconductor chip, around a first bonding material formed in a plane size equal to or larger than the plane size of the semiconductor chip, and around the first bonding material in plan view. The first bonding material has a melting point higher than that of the second bonding material.
  • FIG. 2 is a cross-sectional view showing an example of main processes in assembling the semiconductor device shown in FIG. 1.
  • FIG. 2 is a cross-sectional view showing an example of main processes in assembling the semiconductor device shown in FIG. 1.
  • FIG. shows the main processes in the assembly of the 1st modification of the semiconductor device shown in FIG.
  • FIG. 2nd modification of this invention shows the structure of the semiconductor device of the 2nd modification of this invention.
  • FIG. 8 is a plan view illustrating an example of an internal structure of the semiconductor device illustrated in FIG. 7.
  • FIG. 8 is a plan view illustrating an example of an internal structure of the semiconductor device illustrated in FIG. 7.
  • FIG. 2 is a partial side view showing an example of a railway vehicle on which the semiconductor device shown in FIG. 1 is mounted. It is a top view which shows an example of the internal structure of the inverter installed in the rail vehicle shown in FIG. It is a perspective view which shows an example of the motor vehicle carrying the semiconductor device shown in FIG. It is sectional drawing which shows the structure of the semiconductor device of a comparative example.
  • the constituent elements are not necessarily indispensable unless otherwise specified and clearly considered essential in principle. Needless to say.
  • FIG. 1 is a cross-sectional view showing an example of the structure of a semiconductor device (power module) according to an embodiment of the present invention.
  • the semiconductor device of the present embodiment is, for example, a semiconductor module (power module) mounted on a railway vehicle, an automobile body, or the like. Therefore, the semiconductor device includes a plurality of power semiconductor chips (semiconductor elements) 1 and requires heat dissipation measures.
  • the semiconductor chip 1 is, for example, an IGBT (Insulated Gate Bipolar Transistor) or the like, but is not limited thereto.
  • the configuration of the power module 20 shown in FIG. 1 will be described.
  • the power module 20 electrically connects a ceramic substrate (wiring substrate) 3 that supports the semiconductor chip 1, an electrode 1 c on the upper surface (main surface) 1 a of the semiconductor chip 1, and an electrode 3 cb (3 c) on the upper surface 3 a of the ceramic substrate 3. And a terminal (lead) 7 that is electrically connected to the electrode 3cb of the ceramic substrate 3 and drawn to the outside.
  • the ceramic substrate 3 on which the plurality of semiconductor chips 1 and the plurality of terminals 7 are mounted is mounted on a base plate (metal plate) 4 via solder (joining material, solder alloy) 5. That is, the base plate 4 supports the ceramic substrate 3 via the solder 5.
  • the ceramic substrate 3 has a plurality of electrodes 3ca (3c) and electrodes 3cb (3c) formed on the upper surface 3a, while an electrode 3cc (3c) is also formed on the lower surface 3b.
  • These electrodes 3ca, 3cb, 3cc are made of, for example, copper (Cu) or aluminum (Al). Alternatively, copper or aluminum may be subjected to desired metallization such as nickel (Ni) or gold (Au).
  • the electrode 3 cc formed on the lower surface 3 b of the ceramic substrate 3 is electrically connected to the base plate 4 by the solder 5.
  • the semiconductor chip 1 is connected to the ceramic substrate (wiring substrate, insulating substrate, connected member) 3 via the solder 2, and further, the semiconductor chip 1 A base plate (metal plate) 4 for heat release that plays a role of releasing heat during the operation of the ceramic substrate 3 and the ceramic substrate 3 are connected via a solder 5. That is, the ceramic substrate 3 and the base plate 4 are joined by the solder 5 disposed between the ceramic substrate 3 and the base plate 4.
  • the specific structure of the power module 20 will be described.
  • the semiconductor chip 1, the ceramic substrate 3 that is a chip support member connected to the semiconductor chip 1 via the solder (joining material) 5, and the semiconductor chip 1 are electrically connected.
  • the base plate 4 that is also a heat radiating plate is provided with a case 8 that covers the plurality of semiconductor chips 1, the plurality of wires 6, and the ceramic substrate 3, and a sealing resin (not shown) is contained in the case 8. Filled. That is, the plurality of semiconductor chips 1, the plurality of wires 6, and the ceramic substrate 3 are sealed with the sealing resin.
  • a gel-like resin material is preferably used as the resin.
  • the semiconductor chip 1 is joined to the electrode 3ca on the upper surface 3a of the ceramic substrate 3 via the solder 2. That is, the lower surface 1 b of the semiconductor chip 1 and the upper surface 3 a of the ceramic substrate 3 are opposed to each other, and the back electrode of the semiconductor chip 1 and the electrode 3 ca of the ceramic substrate 3 are electrically connected by the solder 2.
  • a gate electrode 1 c is formed on the upper surface 1 a of the semiconductor chip 1, and is electrically connected to the electrode 3 cb of the ceramic substrate 3 via a wire 6.
  • the base plate 4 is a metal plate for heat dissipation.
  • each of the plurality of wires 6 is, for example, an aluminum or copper wire or a ribbon.
  • an electrode 3cc as a wiring portion is formed on the lower surface 3b of the ceramic substrate 3, and a base plate for heat dissipation (metal) is connected to the electrode 3cc via a solder 5 as a bonding material. Plate, heat radiating member) 4 are joined.
  • This solder 5 is the same as a high melting point bonding material (first bonding material) 5a formed directly below the semiconductor chip 1 and having a planar size that is the same as the planar size of the semiconductor chip 1 as viewed from above. It consists of a low melting point bonding material (second bonding material) 5b disposed around the high melting point bonding material 5a in plan view. That is, the high melting point bonding material (first bonding material) 5a has a planar size that is the same as or larger than the planar size of the semiconductor chip 1 immediately below the semiconductor chip 1 corresponding to the position of the semiconductor chip 1. It is formed with.
  • the size of the high melting point bonding material (first bonding material) 5a in plan view may be larger than the size of the semiconductor chip 1 in plan view.
  • the melting point of the high melting point bonding material 5a is higher than the melting point of the low melting point bonding material 5b.
  • the solder 5 as a bonding material includes a high melting point bonding material 5a disposed immediately below the semiconductor chip 1 where the temperature rises, and a periphery of the high melting point bonding material 5a (around the high melting point bonding material 5a in plan view or And a low melting point bonding material 5b disposed on the outer side.
  • the high melting point bonding material 5a is disposed directly below the semiconductor chip 1 with the ceramic substrate 3 interposed therebetween.
  • the thickness of the solder 5 may be thicker than the thickness of the solder 2. Further, the solder 5 is larger than the solder 2 in the area in plan view.
  • the high melting point bonding material 5a is a bonding material having high heat resistance, and preferably a sintered material made of metal particles. Further, a bonding material such as Zn—Al, Au—Ge, or Au—Si may be used.
  • the low melting point bonding material 5b is preferably an Sn-based solder alloy, for example, an Sn-based solder alloy such as Sn—Cu, Sn—Cu—Sn, Sn—Sb, Sn—Ag—Cu.
  • high heat-resistant bonding (bonding with the high melting point bonding material 5a) having high reliability is applied only to a portion immediately below the semiconductor chip 1 that generates large heat, and the high melting point bonding material 5a.
  • a sintered material of metal particles as the high melting point bonding material 5a and to use an Sn-based solder alloy as the low melting point bonding material 5b. This is because there is a concern that sintered metal joints have fine voids in the joining layer even after joining, and have a large surface area compared to the bulk material and oxidize in a high temperature environment to reduce strength.
  • the joining portion (high melting point joining material 5a) of sintered metal is sealed by low melting point metal joining such as Sn-based solder alloy, the joining is performed. Even when the temperature of the portion becomes high, the sintered metal joint can be protected from oxidation.
  • FIG. 13 is a cross-sectional view showing the structure of a semiconductor device of a comparative example that the present inventors have conducted a comparative study.
  • the breakdown progresses only at the junction between the semiconductor chip 1 and the insulating substrate (ceramic substrate 3) close to the heat generating portion.
  • the operating temperature of the chip also rises at the junction of the base plate 4), and the heat generation of the chip causes temperature nonuniformity in the junction between the insulating substrate and the heat dissipation base.
  • the breakage progresses from the joint, particularly when the Sn-based solder 40 is used.
  • the joint portion between the insulating substrate and the heat dissipation base has a larger area than the joint portion between the semiconductor chip 1 and the insulating substrate, and the crack 42 from the end portion develops due to the increased strain at the end portion of the joint portion. Reliability is also required.
  • the chip generates heat when a large current is applied as compared with other electronic components. Therefore, the junction between the insulating substrate and the heat dissipation base is different from other electronic devices. Destruction is a problem.
  • the Sn-based solder 40 when used, the generation of voids at the Sn grain boundaries and the progress of breakage in the vertical direction (substrate thickness direction, vertical direction) are problematic.
  • the crack 41 in the vertical direction is generated because tensile stress acts in the joint due to a temperature change of the joint.
  • the chip (semiconductor chip 1) generates heat during its operation. At that time, it became clear that the temperature rose to almost the same level as that of the chip at the junction between the insulating substrate and the heat dissipation base, particularly in the portion directly under the chip. This is presumably because Al, Cu, AlN, Si 3 N 4 or the like having good thermal conductivity is used for the insulating substrate (ceramic substrate 3). Since the portion immediately below the chip is at a high temperature, destruction of the joint progresses due to ON / OFF of energization. When the breakage progresses in this portion which is a heat radiation path, the heat radiation performance is lowered, the temperature of the chip rises, and finally the power module 50 is broken.
  • Possible joining materials with high power cycle tolerance include sintered metal joining with high melting point after joining, joining with Zn-Al alloy, joining with Au-based solder, etc. Fine metal particles of several hundred ⁇ m are made into a paste with a solvent such as alcohol, and it is necessary to remove the solvent by heating or pressurize when joining. However, in the case of bonding with a large area such as an insulating substrate and a heat dissipation base, the area is large and it is difficult to remove the solvent to the center.
  • the power module 20 of the present embodiment in a large-area joint such as the ceramic substrate (insulating substrate) 3 and the base plate (heat radiating metal plate) 4, high heat-resistant bonding is performed only at a portion directly below the chip (necessary portion).
  • the portion (high melting point bonding material 5a) is the other portion (periphery) is a bonding portion (low melting point bonding material 5b) made of a low melting point metal such as Sn-based solder.
  • the bonded portion (high melting point bonding material 5a) made of sintered metal is sealed by a low melting point metal bonding (low melting point bonding material 5b) such as an Sn-based solder alloy. Even if the temperature becomes high, the sintered metal joint can be protected from oxidation.
  • the reliability of the power module 20 can be improved.
  • FIG. 2 is a cross-sectional view showing an example of main processes in the assembly of the semiconductor device shown in FIG. 1
  • FIG. 3 is a cross-sectional view showing an example of main processes in the assembly of the semiconductor device shown in FIG.
  • a sintered metal (sintered material by metal particles) and other parts (high melting point bonding material 5 a of high melting point bonding material 5 a) are placed on a high heat resistant bonding portion (high melting point bonding material 5 a) immediately below the chip.
  • high melting point bonding material 5 a high melting point bonding material 5 a
  • the semiconductor chip 1 is mounted on the ceramic substrate (wiring substrate, insulating substrate) 3 via the solder 2.
  • the solder 2 has a melting point of 400 ° C., for example. Accordingly, the semiconductor chip 1 is joined to the ceramic substrate 3 via the solder 2 by heating and melting the solder 2 to 400 ° C. or higher.
  • a sintered metal paste which is a high melting point bonding material 5a is applied to the back side (lower surface 3b) side of the ceramic substrate 3. Further, Sn-based solder, which is the low melting point bonding material 5b, is supplied as a foil or a paste to portions other than the high melting point bonding material 5a (around the high melting point bonding material 5a and outside the high melting point bonding material 5a).
  • the size is equal to or larger than that of the semiconductor chip 1 in a plan view immediately below the semiconductor chip 1.
  • the high melting point bonding material 5a is applied, and further, the low melting point bonding material 5b is applied around the high melting point bonding material 5a in plan view.
  • the high melting point bonding material 5a has a higher melting point than the low melting point bonding material 5b.
  • the high melting point bonding material 5a has a melting point of about 320 ° C.
  • the low melting point bonding material 5b has a melting point of less than 320 ° C.
  • the ceramic substrate 3 is disposed on the base plate 4 via the solder 5, and after the placement, the solder (joining material) 5 composed of the high melting point bonding material 5a and the low melting point bonding material 5b. Are heated and melted to join the ceramic substrate 3 and the base plate (metal plate for heat dissipation) 4 together.
  • solder 5 is melted and the ceramic substrate 3 and the base plate 4 are joined. Thereby, the solder joint between the ceramic substrate 3 and the base plate 4 in the module structure shown in FIG. 3 (FIG. 1) is completed.
  • the size of the high melting point bonding material (first bonding material) 5a immediately below the chip may be larger than the size of the semiconductor chip 1 in plan view.
  • the structure is such that the joint portion (high melting point bonding material 5a) made of sintered metal is sealed by low melting point metal bonding such as Sn-based solder alloy. Therefore, the sintered metal joint can be protected from oxidation even if the joint becomes high temperature.
  • bonding can be performed even if the area of the bonded portion of the sintered metal bonding is 400 mm 2 or more.
  • the high melting point bonding material 5 a and the low melting point bonding material 5 b are not applied to the lower surface 3 b side of the ceramic substrate 3, but the high melting point bonding material 5 a and the low melting point bonding material 5 b are applied to the base plate 4.
  • the solder 5 may be heated and melted after the bonding material 5a and the low-melting-point bonding material 5b are applied and the ceramic substrate 3 is disposed thereon.
  • a semiconductor chip 1 is mounted on a ceramic substrate (wiring substrate, insulating substrate) 3 via a solder 2.
  • the mounting of the semiconductor chip 1 on the ceramic substrate 3 via the solder 2 is the same as the above method.
  • a Zn-based sintered metal paste which is a high melting point bonding material 5a
  • Sn-based solder which is the low melting point bonding material 5b
  • Sn-based solder is supplied as a foil or a paste to portions other than the high melting point bonding material 5a (around the high melting point bonding material 5a and outside the high melting point bonding material 5a).
  • the size is equal to or larger than that of the semiconductor chip 1 in a plan view immediately below the semiconductor chip 1.
  • the high melting point bonding material 5a is applied, and further, the low melting point bonding material 5b is applied around the high melting point bonding material 5a in plan view.
  • the high melting point bonding material 5a has a higher melting point than the low melting point bonding material 5b.
  • the high melting point bonding material 5a has a melting point of about 320 ° C.
  • the low melting point bonding material 5b has a melting point of less than 320 ° C.
  • the ceramic substrate 3 is disposed on the base plate 4 via the solder 5, and after the placement, the solder (joining material) 5 composed of the high melting point bonding material 5a and the low melting point bonding material 5b. Are heated and melted to join the ceramic substrate 3 and the base plate (metal plate for heat dissipation) 4 together.
  • solder 5 is melted and the ceramic substrate 3 and the base plate 4 are joined. Thereby, the solder joint between the ceramic substrate 3 and the base plate 4 in the module structure shown in FIG. 3 (FIG. 1) is completed.
  • the size (planar size) of the high melting point bonding material (first bonding material) 5a immediately below the chip in plan view is the size of the semiconductor chip 1 in plan view ( (Plane size) or more.
  • the Zn-based solder alloy when the Zn-based solder alloy is melted, there is a concern that the vapor pressure of Zn is low and Zn evaporates and adheres to the surface of other members, thereby contaminating the other members.
  • the melting point is around 220 ° C., and the molten Sn-based solder alloy surrounds the Zn-based solder alloy. Therefore, it is possible to prevent Zn from adhering to other members.
  • the joint portion by the solder 5 has a large joint area, an Sn-based solder alloy that is softer (easily deformed) than the high heat-resistant joint by a Zn-based solder alloy or the like is applied to the end portion of the joint portion where a large strain occurs. By applying, it is possible to obtain resistance to crack propagation from the end of the joint.
  • ⁇ First Modification> 4, 5, and 6 are cross-sectional views showing main processes in assembling the first modification of the semiconductor device shown in FIG. 1.
  • a sintered material (sintered metal) made of metal particles is applied as the high heat resistant joint (high melting point bonding material 5a), and an Sn-based solder alloy is applied to the other part (low melting point bonding material 5b).
  • high melting point bonding material 5a high melting point bonding material
  • Sn-based solder alloy low melting point bonding material 5b
  • the semiconductor chip 1 is mounted on the ceramic substrate (wiring substrate, insulating substrate) 3 via the solder 2.
  • the mounting of the semiconductor chip 1 on the ceramic substrate 3 via the solder 2 is the same as the above method.
  • a porous metal joint (porous joint material) 9 shown in FIG. 5 is formed by applying a sintered metal paste (high melting point joint material 5a) on the base plate 4 and heating to 300 ° C. or higher. . Thereafter, a low melting point bonding material 5b (for example, a low melting point metal foil, a second bonding material) made of an Sn-based solder alloy is supplied between the ceramic substrate 3 and the base plate 4 so as to cover the porous bonding portion 9. And heating at 300 ° C. or higher for 15 minutes or longer.
  • a sintered metal paste high melting point joint material 5a
  • a low melting point bonding material 5b for example, a low melting point metal foil, a second bonding material
  • the structure of the molten Sn-based solder alloy (low melting point bonding material 5b) and the porous bonding portion (high melting point bonding material 5a) 9 reacts, and Sn—Cu, Sn— as shown in FIG.
  • An intermetallic compound (layer) 10 such as Ag or Ni—Sn is formed. Thereby, the high melting point is achieved.
  • An Sn-based solder alloy (low melting point bonding material 5b) is disposed around the intermetallic compound 10.
  • the intermetallic compound 10 generally has a high melting point, but has a drawback of being hard and brittle. Therefore, an Sn-based solder alloy (low melting point bonding material 5b) is disposed at the end of the joint where large distortion occurs. . Thereby, it becomes possible to satisfy the power cycle reliability required as a joint portion between the ceramic substrate 3 and the base plate 4 for heat dissipation, and the resistance to crack propagation from the end portion of the joint portion.
  • Sn-based solder alloy low melting point bonding material 5b
  • the high melting point joining material (intermetallic compound 10, first joining material) 5a immediately below the chip in plan view.
  • the size (planar size) is not less than the size (planar size) of the semiconductor chip 1 in plan view.
  • the sintered metal paste (the high melting point bonding material 5a, the first bonding material) is not applied on the base plate 4, but is applied to the lower surface 3b side of the ceramic substrate 3. May be.
  • the power module 20 and the assembly thereof according to the present embodiment can be applied to the semiconductor chip 1 made of any material such as Si, SiC, GaAs, CdTe, and GaN.
  • the base plate (metal plate) 4 for heat dissipation may be made of any member such as Cu, Al, Cu—Mo, Al—SiC, Mg—SiC, etc. Can achieve highly reliable bonding.
  • FIG. 7 is a cross-sectional view showing the structure of a semiconductor device according to a second modification of the present invention
  • FIGS. 8 and 9 are plan views showing examples of the internal structure of the semiconductor device shown in FIG.
  • FIG. 1 a plan view at a joint portion between a ceramic substrate (insulating substrate) 3 and a heat radiating base plate (metal plate) 4
  • a high heat-resistant bonding part (first bonding material, high melting point bonding material 5a) is disposed near the center.
  • the installation location of the high heat-resistant bonding part may be changed depending on the position of the semiconductor chip 1 as shown in FIGS.
  • the planar size of the semiconductor chip 1 is directly below each semiconductor chip 1 as shown in FIGS.
  • a high melting point bonding material (first bonding material, high heat resistant bonding portion) 5a having the same plane size (or a plane size larger than the plane size of the semiconductor chip 1) may be disposed.
  • a low melting point bonding material (for example, Sn-based solder alloy) 5b is disposed around each of the four high melting point bonding materials 5a.
  • each of the four high melting point bonding materials 5a is surrounded by the low melting point bonding material 5b.
  • ⁇ Application example> 10 is a partial side view showing an example of a railway vehicle on which the semiconductor device shown in FIG. 1 is mounted
  • FIG. 11 is a plan view showing an example of an internal structure of an inverter installed in the railway vehicle shown in FIG.
  • a railway vehicle 21 shown in FIG. 10 is mounted with the power module 20 shown in FIG. 1, for example, and includes a vehicle main body 26, a power module 20, a mounting member that supports the power module 20, and a current collector.
  • a pantograph 22 and an inverter 23 are provided.
  • the power module 20 is mounted on an inverter 23 installed at the lower part of the vehicle body 26.
  • a plurality of power modules 20 are mounted on a printed circuit board (mounting member) 25 inside the inverter 23, and a cooling device 24 for cooling these power modules 20 is mounted.
  • the cooling device 24 is attached so that the plurality of power modules 20 can be cooled to cool the inside of the inverter 23.
  • FIG. 12 is a perspective view showing an example of an automobile on which the semiconductor device shown in FIG. 1 is mounted.
  • An automobile 27 shown in FIG. 12 is mounted with the power module 20 shown in FIG. 1, for example, and includes a vehicle body 28, a tire 29, the power module 20, and a mounting unit that is a mounting member that supports the power module 20. 30.
  • the power module 20 is mounted on an inverter included in the mounting unit 30.
  • the mounting unit 30 is, for example, an engine control unit, and in this case, the mounting unit 30 is disposed in the vicinity of the engine. ing. In this case, the mounting unit 30 is used in a high temperature environment, and the power module 20 is also in a high temperature state.
  • the mounting unit 30 is in a high temperature environment by providing an inverter in which a plurality of power modules 20 using the module joining structure shown in FIG.
  • the reliability of the automobile 27 can be improved. That is, in the automobile 27 as well, it is possible to realize the power module 20 that can withstand operation stability under a high temperature environment and a high current load, and an inverter system using the same.

Abstract

A power module 20 according to the present invention comprises a ceramic substrate 3 that supports a semiconductor chip 1 and that is electrically connected to the semiconductor chip 1, a base plate 4 for heat radiation that supports the ceramic substrate 3, and a solder 5 that is disposed between the ceramic substrate 3 and the base plate 4 and that bonds the ceramic substrate 3 and the base plate 4. Directly below the semiconductor chip 1, the solder 5 comprises a high melting point bonding material 5a formed into a plane size that is the same as the plane size of the semiconductor chip 1 or that is larger than the plane size of the semiconductor chip 1 and a low melting point bonding material 5b that is disposed around the high melting point bonding material 5a in planar view, wherein the high melting point bonding material 5a has a melting point higher than that of the low melting point bonding material 5b.

Description

半導体装置およびその製造方法Semiconductor device and manufacturing method thereof
　本発明は、半導体装置およびその製造技術に関し、特にインバータに使用されるパワー系の半導体装置に関する。 The present invention relates to a semiconductor device and a manufacturing technique thereof, and more particularly to a power semiconductor device used for an inverter.
　パワー系の半導体装置（パワーモジュール）は、半導体素子（以下、半導体チップまたは単にチップとも言う）と絶縁基板、もしくは絶縁基板と放熱用金属板をはんだ等で接合した構造となっているものが多い。 Many power semiconductor devices (power modules) have a structure in which a semiconductor element (hereinafter also referred to as a semiconductor chip or simply a chip) and an insulating substrate, or an insulating substrate and a metal plate for heat dissipation are joined together by solder or the like. .
　なお、電機・電子機器の部品の電気的接続に使用されている接続部材であるはんだには、一般的に鉛が含まれていたが、近年、環境への意識が高まる中、鉛の規制が始まっている。欧州では自動車中の鉛使用を制限するＥＬＶ指令（End-of Life Vehicles directive、廃自動車に関する指令）や、電機・電子機器中の鉛使用を禁止するＲｏＨＳ（Restriction of the use of certain Hazardous Substances in electrical and electronic equipment)指令が施行された。 Solder, which is a connecting member used for electrical connection of electrical and electronic equipment components, generally contained lead. However, in recent years, as environmental awareness has increased, lead regulations It has begun. In Europe, the ELV Directive (End-of Life Life Vehicles Directive), which restricts the use of lead in automobiles, and the RoHS (Restriction of the use of certain Hazardous Substances in electrical) that prohibits the use of lead in electrical and electronic equipment and electronic equipment) directive was enforced.
　これまで、高耐熱性が要求される半導体装置、特に自動車や建機、鉄道、情報機器分野等に用いられる半導体装置の接続部材としては鉛（Ｐｂ）入りはんだが使用されてきたが、環境負荷低減のため、鉛フリーの接続部材を使用することが強く要求されている。 Until now, lead (Pb) -containing solder has been used as a connecting member for semiconductor devices that require high heat resistance, particularly semiconductor devices used in the fields of automobiles, construction machinery, railways, and information equipment. There is a strong demand to use lead-free connecting members for reduction.
　近年、高温動作が可能で、かつ機器の小型軽量化が可能なＳｉＣやＧａＮ等のワイドギャップ半導体の開発が推し進められている。なお、一般的にＳｉ（シリコン）の半導体素子は動作温度の上限が１５０～１７５℃であるのに対し、ＳｉＣの半導体素子は１７５℃以上での使用が可能である。 In recent years, development of wide gap semiconductors such as SiC and GaN capable of operating at high temperatures and reducing the size and weight of devices has been promoted. In general, the upper limit of the operating temperature of Si (silicon) semiconductor elements is 150 to 175 ° C., whereas SiC semiconductor elements can be used at 175 ° C. or higher.
　ただし、使用環境温度が高温になると、半導体装置（パワーモジュール）において半導体素子に電流の通電と遮断とが繰り返された際に、繰り返しの熱応力が大きくなる。したがって、耐通電熱疲労性や環境温度の変化による耐亀裂進展性が要求される。 However, when the use environment temperature becomes high, repeated energization and interruption of current to the semiconductor element in the semiconductor device (power module) increase repetitive thermal stress. Therefore, resistance to energization thermal fatigue and resistance to crack propagation due to changes in environmental temperature are required.
　上記要求に対応するために、鉛フリーで、かつ高い耐熱性を有し、さらに高信頼性を備えた接合部を有する半導体装置が必要となる。 In order to meet the above requirements, a lead-free semiconductor device having a high heat resistance and having a highly reliable junction is required.
特開２００８－３００７９２号公報JP 2008-300792 A
　半導体装置の動作時を模擬した信頼性試験として断続的に通電（ＯＮ／ＯＦＦ）を繰り返すパワーサイクル試験がある。パワーモジュール等の半導体装置では、一般的な電子部品と比較して大電流が印加されることによって、チップが発熱し高温となる。その際、チップの発熱に伴って絶縁基板と放熱用金属板との接合部で、特にチップ直下の部分においてチップとほぼ同等程度まで温度が上昇することを本発明者は見出した。 There is a power cycle test in which energization (ON / OFF) is repeated intermittently as a reliability test simulating the operation of a semiconductor device. In a semiconductor device such as a power module, when a large current is applied compared to a general electronic component, the chip generates heat and becomes high temperature. At that time, the present inventor has found that the temperature rises to almost the same level as the chip at the joint between the insulating substrate and the heat radiating metal plate, particularly in the portion directly under the chip, as the chip generates heat.
　そして、本発明者が検討した結果、接続部材としてＳｎ系はんだを使用した場合、温度が変化した際に部材間の線膨張係数差により生じる接合部の端部からの亀裂進展だけではなく、チップ直下の部分でのＳｎ粒界でのボイドの発生および縦方向（基板厚さ方向）への破壊が進展することが判った。 As a result of investigation by the present inventor, when Sn-based solder is used as the connecting member, not only the crack progress from the end of the joint caused by the difference in linear expansion coefficient between the members when the temperature changes, but also the chip It was found that the generation of voids at the Sn grain boundary in the portion immediately below and the breakdown in the vertical direction (substrate thickness direction) progress.
　このように放熱経路であるチップ直下の部分に破壊が進展すると放熱性が低下し、チップの温度が上昇して最終的に半導体装置（パワーモジュール）の破壊に至って半導体装置の信頼性が低下することが課題である。 As described above, when the breakage progresses to the portion immediately below the chip, which is a heat radiation path, the heat radiation performance is lowered, the temperature of the chip rises, and finally the semiconductor device (power module) is broken and the reliability of the semiconductor device is lowered. This is a problem.
　上記特許文献１（特開２００８－３００７９２号公報）には、「金属粒子ペーストを高温硬化させて形成した下地層と、金属粒子ペーストを低温硬化させて形成した表面膜の金属粒子が低温金属ロウ材に分散吸収されて形成された高温化金属ロウ材の層で構成される接合層で、半導体チップの裏側と銅配線パターンを接合することで、耐熱性およびパワーサイクル性に強い接合性を確保し、半導体装置の信頼性を向上させることができる（要約参照）」技術が開示されている。すなわち、半導体チップと絶縁基板の接合において接合部の中央部に高温化金属ロウ材が形成され、その外側に低温金属ロウ材が形成された半導体装置が開示されているが、半導体チップの直下の一部に低温金属ロウ材が形成されており、そのため、パワーサイクル試験で基板厚さ方向（垂直方向）への亀裂が形成されることが懸念される。 Patent Document 1 (Japanese Patent Application Laid-Open No. 2008-300792) discloses that “a base layer formed by curing a metal particle paste at a high temperature and a metal particle in a surface film formed by curing the metal particle paste at a low temperature include a low-temperature metal solder. A bonding layer composed of a high-temperature metal brazing material layer that is dispersed and absorbed in the material. By joining the back side of the semiconductor chip and the copper wiring pattern, it is possible to ensure strong heat resistance and power cycle performance. In addition, a technique capable of improving the reliability of a semiconductor device (see summary) is disclosed. That is, a semiconductor device is disclosed in which a high-temperature metal brazing material is formed at the center of the joint and a low-temperature metal brazing material is formed outside the semiconductor chip and the insulating substrate. A part of the low-temperature metal brazing material is formed. Therefore, there is a concern that a crack in the substrate thickness direction (vertical direction) is formed in the power cycle test.
　本発明の目的は、半導体装置における信頼性を向上させることができる技術を提供することにある。 An object of the present invention is to provide a technique capable of improving the reliability of a semiconductor device.
　本発明の上記ならびにその他の目的と新規な特徴は、本明細書の記述および添付図面から明らかになるであろう。 The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
　本願において開示される発明のうち、代表的なものの概要を簡単に説明すれば、以下のとおりである。 Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.
　本発明に係る半導体装置は、半導体チップを支持し、上記半導体チップと電気的に接続された配線基板と、上記配線基板を支持する金属板と、上記配線基板と上記金属板との間に配置され、上記配線基板と上記金属板とを接合する接合材と、を有するものである。さらに、上記接合材は、上記半導体チップの直下において上記半導体チップの平面サイズと同じかまたはそれより大きな平面サイズで形成された第１接合材と、平面視で上記第１接合材の周囲に配置された第２接合材とからなり、上記第１接合材は、上記第２接合材より融点が高い。 A semiconductor device according to the present invention supports a semiconductor chip and is electrically connected to the semiconductor chip, a metal plate supporting the wiring board, and disposed between the wiring board and the metal plate. And a bonding material for bonding the wiring board and the metal plate. Furthermore, the bonding material is disposed around the first bonding material in a plan view and a first bonding material formed directly below the semiconductor chip and having a plane size equal to or larger than the plane size of the semiconductor chip. The first bonding material has a melting point higher than that of the second bonding material.
　本発明に係る半導体装置の製造方法は、（ａ）配線基板上に半導体チップを搭載する工程、（ｂ）上記半導体チップが搭載された上記配線基板を、接合材を介して金属板上に搭載する工程、を有し、上記（ｂ）工程において、上記接合材を加熱溶融して上記配線基板と上記金属板とを接合するものである。さらに、上記接合材は、上記半導体チップの直下において、上記半導体チップの平面サイズと同じかまたはそれより大きな平面サイズで形成された第１接合材と、平面視で上記第１接合材の周囲に配置された第２接合材とからなり、上記第１接合材は、上記第２接合材より融点が高い。 The method for manufacturing a semiconductor device according to the present invention includes: (a) a step of mounting a semiconductor chip on a wiring board; (b) mounting the wiring board on which the semiconductor chip is mounted on a metal plate via a bonding material. And in the step (b), the bonding material is heated and melted to bond the wiring board and the metal plate. Further, the bonding material is provided immediately below the semiconductor chip, around a first bonding material formed in a plane size equal to or larger than the plane size of the semiconductor chip, and around the first bonding material in plan view. The first bonding material has a melting point higher than that of the second bonding material.
　本願において開示される発明のうち、代表的なものによって得られる効果を簡単に説明すれば、以下のとおりである。 Among the inventions disclosed in the present application, the effects obtained by typical ones will be briefly described as follows.
　半導体装置における信頼性を向上させることができる。 Reliability in semiconductor devices can be improved.
本発明の実施の形態の半導体装置（パワーモジュール）の構造の一例を示す断面図である。It is sectional drawing which shows an example of the structure of the semiconductor device (power module) of embodiment of this invention. 図１に示す半導体装置の組立てにおける主要工程の一例を示す断面図である。FIG. 2 is a cross-sectional view showing an example of main processes in assembling the semiconductor device shown in FIG. 1. 図１に示す半導体装置の組立てにおける主要工程の一例を示す断面図である。FIG. 2 is a cross-sectional view showing an example of main processes in assembling the semiconductor device shown in FIG. 1. 図１に示す半導体装置の第１変形例の組立てにおける主要工程を示す断面図である。It is sectional drawing which shows the main processes in the assembly of the 1st modification of the semiconductor device shown in FIG. 図１に示す半導体装置の第１変形例の組立てにおける主要工程を示す断面図である。It is sectional drawing which shows the main processes in the assembly of the 1st modification of the semiconductor device shown in FIG. 図１に示す半導体装置の第１変形例の組立てにおける主要工程を示す断面図である。It is sectional drawing which shows the main processes in the assembly of the 1st modification of the semiconductor device shown in FIG. 本発明の第２変形例の半導体装置の構造を示す断面図である。It is sectional drawing which shows the structure of the semiconductor device of the 2nd modification of this invention. 図７に示す半導体装置の内部構造の一例を示す平面図である。FIG. 8 is a plan view illustrating an example of an internal structure of the semiconductor device illustrated in FIG. 7. 図７に示す半導体装置の内部構造の一例を示す平面図である。FIG. 8 is a plan view illustrating an example of an internal structure of the semiconductor device illustrated in FIG. 7. 図１に示す半導体装置が搭載された鉄道車両の一例を示す部分側面図である。FIG. 2 is a partial side view showing an example of a railway vehicle on which the semiconductor device shown in FIG. 1 is mounted. 図１０に示す鉄道車両に設置されたインバータの内部構造の一例を示す平面図である。It is a top view which shows an example of the internal structure of the inverter installed in the rail vehicle shown in FIG. 図１に示す半導体装置が搭載された自動車の一例を示す斜視図である。It is a perspective view which shows an example of the motor vehicle carrying the semiconductor device shown in FIG. 比較例の半導体装置の構造を示す断面図である。It is sectional drawing which shows the structure of the semiconductor device of a comparative example.
　以下の実施の形態では特に必要なとき以外は同一または同様な部分の説明を原則として繰り返さない。 In the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.
　さらに、以下の実施の形態では便宜上その必要があるときは、複数のセクションまたは実施の形態に分割して説明するが、特に明示した場合を除き、それらはお互いに無関係なものではなく、一方は他方の一部または全部の変形例、詳細、補足説明などの関係にある。 Further, in the following embodiment, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments, but they are not irrelevant to each other unless otherwise specified. The other part or all of the modifications, details, supplementary explanations, and the like are related.
　また、以下の実施の形態において、要素の数など（個数、数値、量、範囲などを含む）に言及する場合、特に明示した場合および原理的に明らかに特定の数に限定される場合などを除き、その特定の数に限定されるものではなく、特定の数以上でも以下でも良いものとする。 Also, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), particularly when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and it may be more or less than the specific number.
　また、以下の実施の形態において、その構成要素（要素ステップ等も含む）は、特に明示した場合および原理的に明らかに必須であると考えられる場合等を除き、必ずしも必須のものではないことは言うまでもない。 Further, in the following embodiments, the constituent elements (including element steps) are not necessarily indispensable unless otherwise specified and clearly considered essential in principle. Needless to say.
　また、以下の実施の形態において、構成要素等について、「Ａからなる」、「Ａよりなる」、「Ａを有する」、「Ａを含む」と言うときは、特にその要素のみである旨明示した場合等を除き、それ以外の要素を排除するものでないことは言うまでもない。同様に、以下の実施の形態において、構成要素等の形状、位置関係等に言及するときは、特に明示した場合および原理的に明らかにそうでないと考えられる場合等を除き、実質的にその形状等に近似または類似するもの等を含むものとする。このことは、上記数値および範囲等についても同様である。 Further, in the following embodiments, regarding constituent elements and the like, when “consisting of A”, “consisting of A”, “having A”, and “including A” are specifically indicated that only those elements are included. It goes without saying that other elements are not excluded except in the case of such cases. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.
　以下、本発明の実施の形態を図面に基づいて詳細に説明する。なお、実施の形態を説明するための全図において、同一の機能を有する部材には同一の符号を付し、その繰り返しの説明は省略する。また、図面をわかりやすくするために平面図であってもハッチングを付す場合がある。 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted. Further, even a plan view may be hatched for easy understanding of the drawing.
　（実施の形態）
　図１は本発明の実施の形態の半導体装置（パワーモジュール）の構造の一例を示す断面図である。 (Embodiment)
FIG. 1 is a cross-sectional view showing an example of the structure of a semiconductor device (power module) according to an embodiment of the present invention.
　本実施の形態の半導体装置は、例えば、鉄道の車両や自動車の車体等に搭載される半導体モジュール（パワーモジュール）である。したがって、複数のパワー系の半導体チップ（半導体素子）１を備えており、放熱対策が必要な半導体装置である。なお、半導体チップ１は、例えばＩＧＢＴ（Insulated Gate Bipolar Transistor ）等であるが、ただしこれに限定されるものではない。 The semiconductor device of the present embodiment is, for example, a semiconductor module (power module) mounted on a railway vehicle, an automobile body, or the like. Therefore, the semiconductor device includes a plurality of power semiconductor chips (semiconductor elements) 1 and requires heat dissipation measures. The semiconductor chip 1 is, for example, an IGBT (Insulated Gate Bipolar Transistor) or the like, but is not limited thereto.
　図１に示すパワーモジュール２０の構成について説明する。パワーモジュール２０は、半導体チップ１を支持するセラミック基板（配線基板）３と、半導体チップ１の上面（主面）１ａの電極１ｃとセラミック基板３の上面３ａの電極３ｃｂ（３ｃ）とを電気的に接続する導電性のワイヤ６と、セラミック基板３の電極３ｃｂと電気的に接続し、外部に引き出される端子（リード）７とを有している。 The configuration of the power module 20 shown in FIG. 1 will be described. The power module 20 electrically connects a ceramic substrate (wiring substrate) 3 that supports the semiconductor chip 1, an electrode 1 c on the upper surface (main surface) 1 a of the semiconductor chip 1, and an electrode 3 cb (3 c) on the upper surface 3 a of the ceramic substrate 3. And a terminal (lead) 7 that is electrically connected to the electrode 3cb of the ceramic substrate 3 and drawn to the outside.
　また、複数の半導体チップ１および複数の端子７が搭載されたセラミック基板３は、はんだ（接合材、はんだ合金）５を介してベース板（金属板）４に搭載されている。すなわち、ベース板４は、はんだ５を介してセラミック基板３を支持している。ここで、セラミック基板３は、その上面３ａに複数の電極３ｃａ（３ｃ）および電極３ｃｂ（３ｃ）が形成されており、一方、下面３ｂにも電極３ｃｃ（３ｃ）が形成されている。これらの電極３ｃａ，３ｃｂ，３ｃｃは、例えば、銅（Ｃｕ）やアルミニウム（Ａｌ）からなる。もしくは、銅やアルミニウムにニッケル（Ｎｉ）や金（Ａｕ）などの所望のメタライズを施したものでもよい。そして、セラミック基板３の下面３ｂに形成された電極３ｃｃは、はんだ５によってベース板４に電気的に接続されている。 Further, the ceramic substrate 3 on which the plurality of semiconductor chips 1 and the plurality of terminals 7 are mounted is mounted on a base plate (metal plate) 4 via solder (joining material, solder alloy) 5. That is, the base plate 4 supports the ceramic substrate 3 via the solder 5. Here, the ceramic substrate 3 has a plurality of electrodes 3ca (3c) and electrodes 3cb (3c) formed on the upper surface 3a, while an electrode 3cc (3c) is also formed on the lower surface 3b. These electrodes 3ca, 3cb, 3cc are made of, for example, copper (Cu) or aluminum (Al). Alternatively, copper or aluminum may be subjected to desired metallization such as nickel (Ni) or gold (Au). The electrode 3 cc formed on the lower surface 3 b of the ceramic substrate 3 is electrically connected to the base plate 4 by the solder 5.
　すなわち、本実施の形態のパワーモジュール２０は、半導体チップ１が、はんだ２を介してセラミック基板（配線基板、絶縁性基板、被接続部材）３に接続されたものであり、さらに、半導体チップ１の動作時の熱を逃がす役割を果たす放熱用のベース板（金属板）４とセラミック基板３とが、はんだ５を介して接続されている。つまり、セラミック基板３とベース板４との間に配置されたはんだ５によってセラミック基板３とベース板４とが接合されている。 That is, in the power module 20 of the present embodiment, the semiconductor chip 1 is connected to the ceramic substrate (wiring substrate, insulating substrate, connected member) 3 via the solder 2, and further, the semiconductor chip 1 A base plate (metal plate) 4 for heat release that plays a role of releasing heat during the operation of the ceramic substrate 3 and the ceramic substrate 3 are connected via a solder 5. That is, the ceramic substrate 3 and the base plate 4 are joined by the solder 5 disposed between the ceramic substrate 3 and the base plate 4.
　パワーモジュール２０の具体的構造について説明すると、半導体チップ１と、半導体チップ１とはんだ（接合材）５を介して接続されたチップ支持部材であるセラミック基板３と、半導体チップ１と電気的に接続された複数のワイヤ６とを有している。つまり、セラミック基板３の基材の上面３ａには、配線パターン等の電極（導体部、配線部）３ｃａが形成され、この電極３ｃａ上にはんだ２を介して半導体チップ１が搭載されている。 The specific structure of the power module 20 will be described. The semiconductor chip 1, the ceramic substrate 3 that is a chip support member connected to the semiconductor chip 1 via the solder (joining material) 5, and the semiconductor chip 1 are electrically connected. A plurality of wires 6. That is, an electrode (conductor portion, wiring portion) 3 ca such as a wiring pattern is formed on the upper surface 3 a of the base material of the ceramic substrate 3, and the semiconductor chip 1 is mounted on the electrode 3 ca via the solder 2.
　また、放熱板でもあるベース板４には、複数の半導体チップ１、複数のワイヤ６およびセラミック基板３を覆うケース８が設けられており、そのケース８内には図示しない封止用の樹脂が充填されている。つまり、複数の半導体チップ１、複数のワイヤ６およびセラミック基板３は、上記封止用の樹脂によって封止されている。上記樹脂は、例えばゲル状の樹脂材を用いることが好ましい。 The base plate 4 that is also a heat radiating plate is provided with a case 8 that covers the plurality of semiconductor chips 1, the plurality of wires 6, and the ceramic substrate 3, and a sealing resin (not shown) is contained in the case 8. Filled. That is, the plurality of semiconductor chips 1, the plurality of wires 6, and the ceramic substrate 3 are sealed with the sealing resin. For example, a gel-like resin material is preferably used as the resin.
　また、半導体チップ１は、セラミック基板３の上面３ａの電極３ｃａ上にはんだ２を介して接合されている。つまり、半導体チップ１の下面１ｂとセラミック基板３の上面３ａとが対向しており、半導体チップ１の裏面電極とセラミック基板３の電極３ｃａとがはんだ２によって電気的に接続されている。 The semiconductor chip 1 is joined to the electrode 3ca on the upper surface 3a of the ceramic substrate 3 via the solder 2. That is, the lower surface 1 b of the semiconductor chip 1 and the upper surface 3 a of the ceramic substrate 3 are opposed to each other, and the back electrode of the semiconductor chip 1 and the electrode 3 ca of the ceramic substrate 3 are electrically connected by the solder 2.
　また、半導体チップ１の上面１ａには、例えばゲート用の電極１ｃが形成されており、セラミック基板３の電極３ｃｂとワイヤ６を介して電気的に接続されている。 Further, for example, a gate electrode 1 c is formed on the upper surface 1 a of the semiconductor chip 1, and is electrically connected to the electrode 3 cb of the ceramic substrate 3 via a wire 6.
　また、端子７は、その一端が、セラミック基板３の電極３ｃｂに接合されており、さらに他端がケース８の外部に引き出されている。また、ベース板４は、放熱用の金属板である。 Further, one end of the terminal 7 is joined to the electrode 3 cb of the ceramic substrate 3, and the other end is drawn out of the case 8. The base plate 4 is a metal plate for heat dissipation.
　また、複数のワイヤ６のそれぞれは、例えば、アルミニウムまたは銅のワイヤ、もしくはリボン状のものである。 Further, each of the plurality of wires 6 is, for example, an aluminum or copper wire or a ribbon.
　そして、本実施の形態のパワーモジュール２０では、セラミック基板３のの下面３ｂに配線部である電極３ｃｃが形成され、この電極３ｃｃに接合材であるはんだ５を介して放熱用のベース板（金属板、放熱部材）４が接合されている。 In the power module 20 of the present embodiment, an electrode 3cc as a wiring portion is formed on the lower surface 3b of the ceramic substrate 3, and a base plate for heat dissipation (metal) is connected to the electrode 3cc via a solder 5 as a bonding material. Plate, heat radiating member) 4 are joined.
　このはんだ５は、半導体チップ１の直下において、上方から眺めた平面視で半導体チップ１の平面サイズと同じ大きさの平面サイズで形成された高融点接合材（第１接合材）５ａと、同じく平面視で高融点接合材５ａの周囲に配置された低融点接合材（第２接合材）５ｂとからなる。つまり、高融点接合材（第１接合材）５ａは、半導体チップ１の位置に対応した半導体チップ１の直下において、半導体チップ１の平面サイズと同じ、もしくは半導体チップ１の平面サイズより大きな平面サイズで形成されている。言い換えると、高融点接合材（第１接合材）５ａの平面視での大きさは、半導体チップ１の平面視の大きさ以上であればよい。そして、高融点接合材５ａの融点は、低融点接合材５ｂの融点より高い。 This solder 5 is the same as a high melting point bonding material (first bonding material) 5a formed directly below the semiconductor chip 1 and having a planar size that is the same as the planar size of the semiconductor chip 1 as viewed from above. It consists of a low melting point bonding material (second bonding material) 5b disposed around the high melting point bonding material 5a in plan view. That is, the high melting point bonding material (first bonding material) 5a has a planar size that is the same as or larger than the planar size of the semiconductor chip 1 immediately below the semiconductor chip 1 corresponding to the position of the semiconductor chip 1. It is formed with. In other words, the size of the high melting point bonding material (first bonding material) 5a in plan view may be larger than the size of the semiconductor chip 1 in plan view. The melting point of the high melting point bonding material 5a is higher than the melting point of the low melting point bonding material 5b.
　すなわち、接合材であるはんだ５は、温度が上昇する半導体チップ１の直下に配置された高融点接合材５ａと、この高融点接合材５ａの周囲（平面視で高融点接合材５ａの周りもしくは外側）に配置された低融点接合材５ｂとからなる。 That is, the solder 5 as a bonding material includes a high melting point bonding material 5a disposed immediately below the semiconductor chip 1 where the temperature rises, and a periphery of the high melting point bonding material 5a (around the high melting point bonding material 5a in plan view or And a low melting point bonding material 5b disposed on the outer side.
　そして、高融点接合材５ａは、セラミック基板３を介して半導体チップ１の直下に配置されている。 The high melting point bonding material 5a is disposed directly below the semiconductor chip 1 with the ceramic substrate 3 interposed therebetween.
　なお、はんだ５の厚さは、はんだ２の厚さより厚くてもよい。さらにその平面視での面積においてもはんだ５は、はんだ２より大きい。 In addition, the thickness of the solder 5 may be thicker than the thickness of the solder 2. Further, the solder 5 is larger than the solder 2 in the area in plan view.
　また、高融点接合材５ａは、高耐熱性を有した接合材であり、好ましくは、金属粒子による焼結材である。さらに、Ｚｎ－Ａｌ、Ａｕ－Ｇｅ、Ａｕ－Ｓｉ等の接合材であってもよい。 The high melting point bonding material 5a is a bonding material having high heat resistance, and preferably a sintered material made of metal particles. Further, a bonding material such as Zn—Al, Au—Ge, or Au—Si may be used.
　一方、低融点接合材５ｂは、好ましくは、Ｓｎ系はんだ合金であり、例えば、Ｓｎ－Ｃｕ、Ｓｎ－Ｃｕ－Ｓｎ、Ｓｎ－Ｓｂ、Ｓｎ－Ａｇ－Ｃｕ等のＳｎ系はんだ合金である。 On the other hand, the low melting point bonding material 5b is preferably an Sn-based solder alloy, for example, an Sn-based solder alloy such as Sn—Cu, Sn—Cu—Sn, Sn—Sb, Sn—Ag—Cu.
　つまり、本実施の形態のパワーモジュール２０では、発熱の大きな半導体チップ１の直下の部分のみに高い信頼性を有する高耐熱接合（高融点接合材５ａによる接合）を適用し、高融点接合材５ａの周囲の部分には接合部の端部からの亀裂進展を抑制可能なＳｎ系はんだ合金等の低融点接合材５ｂによる接合を適用している。 That is, in the power module 20 of the present embodiment, high heat-resistant bonding (bonding with the high melting point bonding material 5a) having high reliability is applied only to a portion immediately below the semiconductor chip 1 that generates large heat, and the high melting point bonding material 5a. The joining by the low melting-point joining material 5b, such as Sn type solder alloy which can suppress the crack progress from the edge part of a junction part, is applied to the surrounding part.
　その結果、セラミック基板３の下部のベース板４との接合部の接合信頼性を高めることができ、これにより、パワーモジュール２０における信頼性を向上させることができる。 As a result, it is possible to increase the bonding reliability of the bonded portion with the base plate 4 below the ceramic substrate 3, thereby improving the reliability of the power module 20.
　さらに、例えば、高融点接合材５ａとして金属粒子による焼結材を用い、低融点接合材５ｂとしてＳｎ系はんだ合金を用いることが好ましい。これは、焼結金属接合は接合後も接合層中に微細なボイドが存在するため、バルク材と比較して表面積が大きく高温環境下において酸化することで強度が低下するという懸念がある。 Further, for example, it is preferable to use a sintered material of metal particles as the high melting point bonding material 5a and to use an Sn-based solder alloy as the low melting point bonding material 5b. This is because there is a concern that sintered metal joints have fine voids in the joining layer even after joining, and have a large surface area compared to the bulk material and oxidize in a high temperature environment to reduce strength.
　しかしながら、本実施の形態のパワーモジュール２０では、焼結金属による接合部（高融点接合材５ａ）が、Ｓｎ系はんだ合金等の低融点金属接合によって封止されるような構造となるため、接合部が高温となっても焼結金属接合を酸化から保護することが可能となる。 However, in the power module 20 of the present embodiment, since the joining portion (high melting point joining material 5a) of sintered metal is sealed by low melting point metal joining such as Sn-based solder alloy, the joining is performed. Even when the temperature of the portion becomes high, the sintered metal joint can be protected from oxidation.
　ここで、図１３を用いて比較例のモジュール構造を説明して、本実施の形態のパワーモジュール２０の上記比較例との違いを説明する。 Here, the module structure of the comparative example will be described with reference to FIG. 13, and the difference from the comparative example of the power module 20 of the present embodiment will be described.
　図１３は本発明者が比較検討を行った比較例の半導体装置の構造を示す断面図である。 FIG. 13 is a cross-sectional view showing the structure of a semiconductor device of a comparative example that the present inventors have conducted a comparative study.
　図１３に示すようなモジュール構造（パワーモジュール５０）では、発熱部に近い半導体チップ１と絶縁基板（セラミック基板３）の接合においてのみ破壊が進展すると考えられてきたが、絶縁基板と放熱ベース（ベース板４）の接合部においてもチップの動作温度が上昇し、チップの発熱によって絶縁基板と放熱ベースの接合部中に温度の不均一が生じる。その結果、特にＳｎ系はんだ４０を使用した場合、接合部中から破壊が進展することが明らかとなってきた。 In the module structure (power module 50) as shown in FIG. 13, it has been considered that the breakdown progresses only at the junction between the semiconductor chip 1 and the insulating substrate (ceramic substrate 3) close to the heat generating portion. The operating temperature of the chip also rises at the junction of the base plate 4), and the heat generation of the chip causes temperature nonuniformity in the junction between the insulating substrate and the heat dissipation base. As a result, it has been clarified that the breakage progresses from the joint, particularly when the Sn-based solder 40 is used.
　また、絶縁基板と放熱ベースの接合部は、半導体チップ１と絶縁基板の接合部と比較して大面積であり、接合部の端部におけるひずみが大きくなることによって端部からの亀裂４２の進展に対する信頼性も要求される。 Further, the joint portion between the insulating substrate and the heat dissipation base has a larger area than the joint portion between the semiconductor chip 1 and the insulating substrate, and the crack 42 from the end portion develops due to the increased strain at the end portion of the joint portion. Reliability is also required.
　また、パワーモジュール２０では、他の電子部品と比較して大電流が印加されることによって、チップが発熱するため、絶縁基板と放熱ベースの接合部において他の電子機器とは異なる接合部中からの破壊が問題となっている。特にＳｎ系はんだ４０を使用した場合、Ｓｎ粒界でのボイドの発生および縦方向（基板厚さ方向、垂直方向）への破壊の進展が問題となっている。特に縦方向への亀裂４１は、接合部の温度変化によって接合部中に引っ張りの応力が働くため、発生すると考えられる。 Further, in the power module 20, the chip generates heat when a large current is applied as compared with other electronic components. Therefore, the junction between the insulating substrate and the heat dissipation base is different from other electronic devices. Destruction is a problem. In particular, when the Sn-based solder 40 is used, the generation of voids at the Sn grain boundaries and the progress of breakage in the vertical direction (substrate thickness direction, vertical direction) are problematic. In particular, it is considered that the crack 41 in the vertical direction is generated because tensile stress acts in the joint due to a temperature change of the joint.
　パワーモジュール５０ではその動作時に、チップ（半導体チップ１）が発熱する。その際、絶縁基板と放熱ベースの接合部で特にチップ直下の部分においてチップとほぼ同等程度まで温度が上昇することが明らかとなった。これは、絶縁基板（セラミック基板３）に熱伝導の良いＡｌ、Ｃｕ、ＡｌＮやＳｉ3 Ｎ4 等が使用されているためだと考えられる。チップの直下の部分は高温となるため通電のＯＮ／ＯＦＦによって接合部の破壊が進展する。放熱経路であるこの部分に破壊が進展すると放熱性が低下し、チップの温度が上昇して最終的にパワーモジュール５０の破壊に至る。 In the power module 50, the chip (semiconductor chip 1) generates heat during its operation. At that time, it became clear that the temperature rose to almost the same level as that of the chip at the junction between the insulating substrate and the heat dissipation base, particularly in the portion directly under the chip. This is presumably because Al, Cu, AlN, Si 3 N 4 or the like having good thermal conductivity is used for the insulating substrate (ceramic substrate 3). Since the portion immediately below the chip is at a high temperature, destruction of the joint progresses due to ON / OFF of energization. When the breakage progresses in this portion which is a heat radiation path, the heat radiation performance is lowered, the temperature of the chip rises, and finally the power module 50 is broken.
　パワーサイクル耐量の高い接合材として、接合後の融点の高い焼結金属接合やＺｎ－Ａｌ合金による接合、Ａｕ系はんだによる接合等が候補として想定されるが、焼結金属接合は、数ｎｍ～数１００μｍの微細な金属粒子をアルコール等の溶剤でペースト状にしたものであり、接合の際には加熱によって溶剤の除去や、加圧が必要である。しかしながら、絶縁基板と放熱ベースなど大面積の接合の場合、面積が大きく中心部まで溶剤を除去することが難しい。 Possible joining materials with high power cycle tolerance include sintered metal joining with high melting point after joining, joining with Zn-Al alloy, joining with Au-based solder, etc. Fine metal particles of several hundred μm are made into a paste with a solvent such as alcohol, and it is necessary to remove the solvent by heating or pressurize when joining. However, in the case of bonding with a large area such as an insulating substrate and a heat dissipation base, the area is large and it is difficult to remove the solvent to the center.
　さらに、大きな加圧力が必要となり大規模な設備が必要となるなど大面積の接合部への適用は困難である。また、Ａｕ系はんだを適用した場合、Ａｕは高コストなため大面積の接合部全体に適用した場合コストが高くなるといった懸念がある。 Furthermore, it is difficult to apply to large-area joints because a large pressure is required and a large-scale facility is required. In addition, when Au-based solder is applied, there is a concern that since Au is expensive, the cost increases when applied to the entire large-area joint.
　しかしながら本実施の形態のパワーモジュール２０では、セラミック基板（絶縁基板）３とベース板（放熱用金属板）４といった大面積の接合部において、チップ直下の部分（必要な部分）においてのみ高耐熱接合部（高融点接合材５ａ）とし、その他の部分（周囲）はＳｎ系はんだ等の低融点な金属による接合部（低融点接合材５ｂ）としている。 However, in the power module 20 of the present embodiment, in a large-area joint such as the ceramic substrate (insulating substrate) 3 and the base plate (heat radiating metal plate) 4, high heat-resistant bonding is performed only at a portion directly below the chip (necessary portion). The portion (high melting point bonding material 5a) is the other portion (periphery) is a bonding portion (low melting point bonding material 5b) made of a low melting point metal such as Sn-based solder.
　高耐熱な接合材を少なくとも耐熱性、信頼性が要求されるチップ直下の部分に適応することで、接合面積を抑えることが可能となり、前述の高耐熱接合を適用することが可能となる。そして、その他（周囲）の温度の上昇が少ない部分には、Ｓｎ－Ｃｕ、Ｓｎ－Ｃｕ－Ｓｂ、Ｓｎ－Ａｇ－Ｃｕ等のＳｎ系はんだ合金を適用することで端部からの亀裂進展を抑制することが可能となる。 適 応 By applying a high heat-resistant bonding material to at least the part directly under the chip where heat resistance and reliability are required, it becomes possible to reduce the bonding area and to apply the high heat bonding described above. And, in other parts where the temperature rise is small, Sn-Cu, Sn-Cu-Sb, Sn-Ag-Cu and other Sn-based solder alloys are used to suppress crack growth from the edges. It becomes possible to do.
　これにより、大面積な接合部においてもパワーサイクル信頼性と組立て性を両立することが可能となる。 This makes it possible to achieve both power cycle reliability and ease of assembly even in a large-area joint.
　また、上述のように焼結金属による接合部（高融点接合材５ａ）が、Ｓｎ系はんだ合金等の低融点金属接合（低融点接合材５ｂ）によって封止される構造であるため、接合部が高温となっても焼結金属接合を酸化から保護することができる。 Further, as described above, the bonded portion (high melting point bonding material 5a) made of sintered metal is sealed by a low melting point metal bonding (low melting point bonding material 5b) such as an Sn-based solder alloy. Even if the temperature becomes high, the sintered metal joint can be protected from oxidation.
　以上により、パワーモジュール２０における信頼性を向上させることができる。 As described above, the reliability of the power module 20 can be improved.
　次に、本実施の形態のパワーモジュール２０の組立てについて説明する。図２は図１に示す半導体装置の組立てにおける主要工程の一例を示す断面図、図３は図１に示す半導体装置の組立てにおける主要工程の一例を示す断面図である。 Next, the assembly of the power module 20 of this embodiment will be described. 2 is a cross-sectional view showing an example of main processes in the assembly of the semiconductor device shown in FIG. 1, and FIG. 3 is a cross-sectional view showing an example of main processes in the assembly of the semiconductor device shown in FIG.
　ここでは、図２、図３に示すように、チップ直下の高耐熱接合部（高融点接合材５ａ）に焼結金属（金属粒子による焼結材）、その他の部分（高融点接合材５ａの周囲の部分）にＳｎ系はんだ合金（低融点接合材５ｂ）を適用した場合について示す。 Here, as shown in FIG. 2 and FIG. 3, a sintered metal (sintered material by metal particles) and other parts (high melting point bonding material 5 a of high melting point bonding material 5 a) are placed on a high heat resistant bonding portion (high melting point bonding material 5 a) immediately below the chip. A case where an Sn-based solder alloy (low melting point bonding material 5b) is applied to the surrounding portion will be described.
　パワーモジュール２０の組立てでは、まず、図２に示すように、セラミック基板（配線基板、絶縁基板）３上に、はんだ２を介して半導体チップ１を搭載する。はんだ２は、例えば融点が４００℃である。したがって、はんだ２を４００℃以上に加熱溶融することで、セラミック基板３上にはんだ２を介して半導体チップ１を接合する。 In assembling the power module 20, first, as shown in FIG. 2, the semiconductor chip 1 is mounted on the ceramic substrate (wiring substrate, insulating substrate) 3 via the solder 2. The solder 2 has a melting point of 400 ° C., for example. Accordingly, the semiconductor chip 1 is joined to the ceramic substrate 3 via the solder 2 by heating and melting the solder 2 to 400 ° C. or higher.
　次に、セラミック基板３の裏（下面３ｂ）側に高融点接合材５ａである焼結金属ペーストを塗布する。さらに、高融点接合材５ａ以外の部分（高融点接合材５ａの周囲、高融点接合材５ａの外側部分）に、低融点接合材５ｂであるＳｎ系はんだを箔もしくはペーストで供給する。 Next, a sintered metal paste which is a high melting point bonding material 5a is applied to the back side (lower surface 3b) side of the ceramic substrate 3. Further, Sn-based solder, which is the low melting point bonding material 5b, is supplied as a foil or a paste to portions other than the high melting point bonding material 5a (around the high melting point bonding material 5a and outside the high melting point bonding material 5a).
　すなわち、高融点接合材５ａと低融点接合材５ｂとからなるはんだ（接合材）５において、半導体チップ１の直下に、平面視で半導体チップ１と同じ大きさまたは半導体チップ１より大きくなるように高融点接合材５ａを塗布し、さらに、平面視で高融点接合材５ａの周囲に低融点接合材５ｂを塗布する。ここで、高融点接合材５ａは、低融点接合材５ｂより融点が高い。例えば、高融点接合材５ａの融点は、約３２０℃であり、低融点接合材５ｂの融点は、３２０℃未満である。 That is, in the solder (bonding material) 5 composed of the high melting point bonding material 5a and the low melting point bonding material 5b, the size is equal to or larger than that of the semiconductor chip 1 in a plan view immediately below the semiconductor chip 1. The high melting point bonding material 5a is applied, and further, the low melting point bonding material 5b is applied around the high melting point bonding material 5a in plan view. Here, the high melting point bonding material 5a has a higher melting point than the low melting point bonding material 5b. For example, the high melting point bonding material 5a has a melting point of about 320 ° C., and the low melting point bonding material 5b has a melting point of less than 320 ° C.
　次に、図３に示すように、ベース板４上にはんだ５を介してセラミック基板３を配置し、配置後、高融点接合材５ａと低融点接合材５ｂとからなるはんだ（接合材）５を加熱溶融してセラミック基板３とベース板（放熱用の金属板）４とを接合する。 Next, as shown in FIG. 3, the ceramic substrate 3 is disposed on the base plate 4 via the solder 5, and after the placement, the solder (joining material) 5 composed of the high melting point bonding material 5a and the low melting point bonding material 5b. Are heated and melted to join the ceramic substrate 3 and the base plate (metal plate for heat dissipation) 4 together.
　この時、例えば、リフロー炉等で加圧と３００℃以上の加熱を加えることで、はんだ５を溶融してセラミック基板３とベース板４とを接合する。これにより、図３（図１）に示すモジュール構造におけるセラミック基板３とベース板４とのはんだ接合を完了する。 At this time, for example, by applying pressure and heating at 300 ° C. or higher in a reflow furnace or the like, the solder 5 is melted and the ceramic substrate 3 and the base plate 4 are joined. Thereby, the solder joint between the ceramic substrate 3 and the base plate 4 in the module structure shown in FIG. 3 (FIG. 1) is completed.
　なお、接合後のはんだ５において、チップ直下の高融点接合材（第１接合材）５ａの平面視での大きさは、半導体チップ１の平面視の大きさ以上であればよい。 In addition, in the solder 5 after bonding, the size of the high melting point bonding material (first bonding material) 5a immediately below the chip may be larger than the size of the semiconductor chip 1 in plan view.
　上述のように焼結金属接合は接合後も接合層中に微細なボイドが存在するため、バルク材と比較して表面積が大きく高温環境下において酸化することで強度が低下するという懸念がある。 As described above, since sintered metal bonding has fine voids in the bonding layer even after bonding, there is a concern that the surface area is larger than that of the bulk material and the strength is reduced by oxidation in a high temperature environment.
　しかし、本実施の形態のパワーモジュール２０の組立てにおいては、焼結金属による接合部（高融点接合材５ａ）が、Ｓｎ系はんだ合金等の低融点金属接合によって封止されるような構造となるため、接合部が高温となっても焼結金属接合を酸化から保護することができる。 However, in the assembly of the power module 20 of the present embodiment, the structure is such that the joint portion (high melting point bonding material 5a) made of sintered metal is sealed by low melting point metal bonding such as Sn-based solder alloy. Therefore, the sintered metal joint can be protected from oxidation even if the joint becomes high temperature.
　また、焼結金属接合（高融点接合材５ａによる接合）において接合面積が４００ｍｍ2 となると、端部から中央部までの距離が長く、中央部付近の溶剤が接合中に除去しにくくなるが、本実施の形態のパワーモジュール２０では、焼結金属接合の接合部面積が４００ｍｍ2 以上であっても接合することができる。 Further, when the bonding area is 400 mm 2 in the sintered metal bonding (bonding with the high melting point bonding material 5a), the distance from the end to the center is long, and the solvent near the center is difficult to remove during the bonding. In the power module 20 according to the present embodiment, bonding can be performed even if the area of the bonded portion of the sintered metal bonding is 400 mm 2 or more.
　なお、図２、図３に示すパワーモジュールの組立てについては、高融点接合材５ａと低融点接合材５ｂとをセラミック基板３の下面３ｂ側に塗布するのではなく、ベース板４上に高融点接合材５ａおよび低融点接合材５ｂを塗布して、その上にセラミック基板３を配置してからはんだ５を加熱溶融するようにしてもよい。 2 and 3, the high melting point bonding material 5 a and the low melting point bonding material 5 b are not applied to the lower surface 3 b side of the ceramic substrate 3, but the high melting point bonding material 5 a and the low melting point bonding material 5 b are applied to the base plate 4. The solder 5 may be heated and melted after the bonding material 5a and the low-melting-point bonding material 5b are applied and the ceramic substrate 3 is disposed thereon.
　次に、図２、図３に示すパワーモジュールにおいて、高融点接合材５ａとしてＺｎ系はんだ合金を適用し、低融点接合材５ｂとしてＳｎ系はんだ合金を適用する場合の組立てについて説明する。 Next, in the power module shown in FIG. 2 and FIG. 3, the assembly in the case where a Zn solder alloy is applied as the high melting point bonding material 5a and the Sn solder alloy is applied as the low melting point bonding material 5b will be described.
　まず、図２に示すように、セラミック基板（配線基板、絶縁基板）３上にはんだ２を介して半導体チップ１を搭載する。セラミック基板３上へのはんだ２を介した半導体チップ１の搭載については、上記方法と同様である。 First, as shown in FIG. 2, a semiconductor chip 1 is mounted on a ceramic substrate (wiring substrate, insulating substrate) 3 via a solder 2. The mounting of the semiconductor chip 1 on the ceramic substrate 3 via the solder 2 is the same as the above method.
　次に、セラミック基板３の裏（下面３ｂ）側に高融点接合材５ａであるＺｎ系の焼結金属ペーストを塗布する。さらに、高融点接合材５ａ以外の部分（高融点接合材５ａの周囲、高融点接合材５ａの外側部分）に、低融点接合材５ｂであるＳｎ系はんだを箔もしくはペーストで供給する。 Next, a Zn-based sintered metal paste, which is a high melting point bonding material 5a, is applied to the back side (lower surface 3b) side of the ceramic substrate 3. Further, Sn-based solder, which is the low melting point bonding material 5b, is supplied as a foil or a paste to portions other than the high melting point bonding material 5a (around the high melting point bonding material 5a and outside the high melting point bonding material 5a).
　すなわち、高融点接合材５ａと低融点接合材５ｂとからなるはんだ（接合材）５において、半導体チップ１の直下に、平面視で半導体チップ１と同じ大きさまたは半導体チップ１より大きくなるように高融点接合材５ａを塗布し、さらに、平面視で高融点接合材５ａの周囲に低融点接合材５ｂを塗布する。ここで、高融点接合材５ａは、低融点接合材５ｂより融点が高い。例えば、高融点接合材５ａの融点は、約３２０℃であり、低融点接合材５ｂの融点は、３２０℃未満である。 That is, in the solder (bonding material) 5 composed of the high melting point bonding material 5a and the low melting point bonding material 5b, the size is equal to or larger than that of the semiconductor chip 1 in a plan view immediately below the semiconductor chip 1. The high melting point bonding material 5a is applied, and further, the low melting point bonding material 5b is applied around the high melting point bonding material 5a in plan view. Here, the high melting point bonding material 5a has a higher melting point than the low melting point bonding material 5b. For example, the high melting point bonding material 5a has a melting point of about 320 ° C., and the low melting point bonding material 5b has a melting point of less than 320 ° C.
　次に、図３に示すように、ベース板４上にはんだ５を介してセラミック基板３を配置し、配置後、高融点接合材５ａと低融点接合材５ｂとからなるはんだ（接合材）５を加熱溶融してセラミック基板３とベース板（放熱用の金属板）４とを接合する。 Next, as shown in FIG. 3, the ceramic substrate 3 is disposed on the base plate 4 via the solder 5, and after the placement, the solder (joining material) 5 composed of the high melting point bonding material 5a and the low melting point bonding material 5b. Are heated and melted to join the ceramic substrate 3 and the base plate (metal plate for heat dissipation) 4 together.
　この時、例えば、リフロー炉等で加圧と３００℃以上の加熱を加えることで、はんだ５を溶融してセラミック基板３とベース板４とを接合する。これにより、図３（図１）に示すモジュール構造におけるセラミック基板３とベース板４とのはんだ接合を完了する。 At this time, for example, by applying pressure and heating at 300 ° C. or higher in a reflow furnace or the like, the solder 5 is melted and the ceramic substrate 3 and the base plate 4 are joined. Thereby, the solder joint between the ceramic substrate 3 and the base plate 4 in the module structure shown in FIG. 3 (FIG. 1) is completed.
　なお、図３に示す接合後のはんだ５において、チップ直下の高融点接合材（第１接合材）５ａの平面視での大きさ（平面サイズ）は、半導体チップ１の平面視の大きさ（平面サイズ）以上である。 In the solder 5 after bonding shown in FIG. 3, the size (planar size) of the high melting point bonding material (first bonding material) 5a immediately below the chip in plan view is the size of the semiconductor chip 1 in plan view ( (Plane size) or more.
　また、Ｚｎ系はんだ合金を溶融した際に、Ｚｎの蒸気圧が低くＺｎが蒸発してしまい他の部材の表面に付着することで上記他の部材を汚染してしまうという課題の発生が懸念される。しかしながら、本実施の形態のパワーモジュール２０の構成とすることで、Ｚｎ系はんだ合金の溶融時には、融点が２２０℃前後であり、溶融しているＳｎ系はんだ合金がＺｎ系はんだ合金を取り囲む構造となっており他の部材へのＺｎの付着を防止することが可能になる。 Also, when the Zn-based solder alloy is melted, there is a concern that the vapor pressure of Zn is low and Zn evaporates and adheres to the surface of other members, thereby contaminating the other members. The However, with the configuration of the power module 20 of the present embodiment, when the Zn-based solder alloy is melted, the melting point is around 220 ° C., and the molten Sn-based solder alloy surrounds the Zn-based solder alloy. Therefore, it is possible to prevent Zn from adhering to other members.
　さらに、はんだ５による接合部は接合面積が大きいため、大きなひずみの発生する接合部の端部に、Ｚｎ系はんだ合金等による高耐熱接合と比較して軟らかい（変形し易い）Ｓｎ系はんだ合金を適用することにより、接合部の端部からの亀裂進展に対しても耐性を得ることができる。 Furthermore, since the joint portion by the solder 5 has a large joint area, an Sn-based solder alloy that is softer (easily deformed) than the high heat-resistant joint by a Zn-based solder alloy or the like is applied to the end portion of the joint portion where a large strain occurs. By applying, it is possible to obtain resistance to crack propagation from the end of the joint.
　また、高耐熱接合部（高融点接合材５ａ）にＡｕ系はんだ合金を使用した場合、セラミック基板３とベース板４の間の接合部全体にＡｕ系はんだ合金を使用するのに比較してコストを低減することができる。 In addition, when an Au-based solder alloy is used for the high heat-resistant joint (high melting point bonding material 5a), the cost is lower than when an Au-based solder alloy is used for the entire joint between the ceramic substrate 3 and the base plate 4. Can be reduced.
　＜第１変形例＞
　図４、図５、図６はそれぞれ図１に示す半導体装置の第１変形例の組立てにおける主要工程を示す断面図である。 <First Modification>
4, 5, and 6 are cross-sectional views showing main processes in assembling the first modification of the semiconductor device shown in FIG. 1.
　本第１変形例では、高耐熱接合部（高融点接合材５ａ）として金属粒子による焼結材（焼結金属）を適用し、その他の部分（低融点接合材５ｂ）にＳｎ系はんだ合金を適用する場合の組立てについて説明する。 In the first modification, a sintered material (sintered metal) made of metal particles is applied as the high heat resistant joint (high melting point bonding material 5a), and an Sn-based solder alloy is applied to the other part (low melting point bonding material 5b). The assembly in the case of applying will be described.
　まず、図４に示すように、セラミック基板（配線基板、絶縁基板）３上にはんだ２を介して半導体チップ１を搭載する。セラミック基板３上へのはんだ２を介した半導体チップ１の搭載については、上記方法と同様である。 First, as shown in FIG. 4, the semiconductor chip 1 is mounted on the ceramic substrate (wiring substrate, insulating substrate) 3 via the solder 2. The mounting of the semiconductor chip 1 on the ceramic substrate 3 via the solder 2 is the same as the above method.
　次に、ベース板４上に焼結金属ペースト（高融点接合材５ａ）を塗布し、３００℃以上に加熱することで、図５に示すポーラス状接合部（多孔質接合材）９を形成する。その後、Ｓｎ系はんだ合金からなる低融点接合材５ｂ（例えば、低融点金属箔、第２接合材）をセラミック基板３とベース板４との間において上記ポーラス状接合部９を覆うように供給し、３００℃以上で１５ｍｉｎ間以上加熱する。これにより、溶融したＳｎ系はんだ合金（低融点接合材５ｂ）とポーラス状接合部（高融点接合材５ａ）９との構造体が反応し、図６に示すような、Ｓｎ－Ｃｕ、Ｓｎ－Ａｇ、Ｎｉ－Ｓｎ等の金属間化合物（層）１０が形成される。これにより、高融点化が達成される。なお、金属間化合物１０の周囲には、Ｓｎ系はんだ合金（低融点接合材５ｂ）が配置される。 Next, a porous metal joint (porous joint material) 9 shown in FIG. 5 is formed by applying a sintered metal paste (high melting point joint material 5a) on the base plate 4 and heating to 300 ° C. or higher. . Thereafter, a low melting point bonding material 5b (for example, a low melting point metal foil, a second bonding material) made of an Sn-based solder alloy is supplied between the ceramic substrate 3 and the base plate 4 so as to cover the porous bonding portion 9. And heating at 300 ° C. or higher for 15 minutes or longer. As a result, the structure of the molten Sn-based solder alloy (low melting point bonding material 5b) and the porous bonding portion (high melting point bonding material 5a) 9 reacts, and Sn—Cu, Sn— as shown in FIG. An intermetallic compound (layer) 10 such as Ag or Ni—Sn is formed. Thereby, the high melting point is achieved. An Sn-based solder alloy (low melting point bonding material 5b) is disposed around the intermetallic compound 10.
　ここで、金属間化合物１０は、一般的に高融点であるが、硬く脆いという欠点があるため、大きな歪みが生じる接合部の端部にＳｎ系はんだ合金（低融点接合材５ｂ）を配置する。これにより、セラミック基板３と放熱用のベース板４との接合部として必要なパワーサイクル信頼性、および接合部の端部からの耐亀裂進展性をそれぞれ満たすことが可能になる。 Here, the intermetallic compound 10 generally has a high melting point, but has a drawback of being hard and brittle. Therefore, an Sn-based solder alloy (low melting point bonding material 5b) is disposed at the end of the joint where large distortion occurs. . Thereby, it becomes possible to satisfy the power cycle reliability required as a joint portion between the ceramic substrate 3 and the base plate 4 for heat dissipation, and the resistance to crack propagation from the end portion of the joint portion.
　なお、図６に示すモジュール構造のセラミック基板３とベース板４との接合部（はんだ５）において、チップ直下の高融点接合材（金属間化合物１０、第１接合材）５ａの平面視での大きさ（平面サイズ）は、半導体チップ１の平面視の大きさ（平面サイズ）以上である。 In addition, in the joint portion (solder 5) between the ceramic substrate 3 and the base plate 4 having the module structure shown in FIG. 6, the high melting point joining material (intermetallic compound 10, first joining material) 5a immediately below the chip in plan view. The size (planar size) is not less than the size (planar size) of the semiconductor chip 1 in plan view.
　また、図４～図６に示す組立てについては、焼結金属ペースト（高融点接合材５ａ、第１接合材）をベース板４上に塗布するのではなく、セラミック基板３の下面３ｂ側に塗布してもよい。 4 to 6, the sintered metal paste (the high melting point bonding material 5a, the first bonding material) is not applied on the base plate 4, but is applied to the lower surface 3b side of the ceramic substrate 3. May be.
　以上、本実施の形態のパワーモジュール２０およびその組立てでは、Ｓｉ、ＳｉＣ、ＧａＡｓ、ＣｄＴｅ、ＧａＮ等どのような材料からなる半導体チップ１であっても適用することが可能である。 As described above, the power module 20 and the assembly thereof according to the present embodiment can be applied to the semiconductor chip 1 made of any material such as Si, SiC, GaAs, CdTe, and GaN.
　さらに、基板については、Ｃｕ、Ａｌ、４２アロイや、ＣＩＣ（Copper Invar Copper)、または、ＤＢＣ（Direct Bond Copper）、ＤＢＡ（Direct Bond Aluminum）等の金属を貼り合わせたセラミック基板（絶縁基板）３であってもよい。また、放熱用のベース板（金属板）４は、Ｃｕ、Ａｌ、Ｃｕ－Ｍｏ、Ａｌ－ＳｉＣ、Ｍｇ－ＳｉＣ等どのような部材からなるものであってもよく、どのような部材に対しても信頼性の高い接合を実現することができる。 Furthermore, as for the substrate, a ceramic substrate (insulating substrate) 3 bonded with a metal such as Cu, Al, 42 alloy, CIC (Copper Invar Copper), DBC (Direct Bond Copper), DBA (Direct Bond Aluminum) 3 or the like. It may be. The base plate (metal plate) 4 for heat dissipation may be made of any member such as Cu, Al, Cu—Mo, Al—SiC, Mg—SiC, etc. Can achieve highly reliable bonding.
　＜第２変形例＞
　図７は本発明の第２変形例の半導体装置の構造を示す断面図であり、図８、図９は、それぞれ図７に示す半導体装置の内部構造の一例を示す平面図である。 <Second Modification>
FIG. 7 is a cross-sectional view showing the structure of a semiconductor device according to a second modification of the present invention, and FIGS. 8 and 9 are plan views showing examples of the internal structure of the semiconductor device shown in FIG.
　図１や図２～図３および図４～図６で示したパワーモジュールでは、一例としてセラミック基板（絶縁基板）３と放熱用のベース板（金属板）４との接合部における平面視での中央部付近に高耐熱接合部（第１接合材、高融点接合材５ａ）を配置している。しかしながら、高耐熱接合部（第１接合材、高融点接合材５ａ）の設置箇所は、図７～図９に示すように半導体チップ１の位置によって変化させてもよい。 In the power modules shown in FIG. 1, FIG. 2 to FIG. 3 and FIG. 4 to FIG. 6, as an example, a plan view at a joint portion between a ceramic substrate (insulating substrate) 3 and a heat radiating base plate (metal plate) 4 A high heat-resistant bonding part (first bonding material, high melting point bonding material 5a) is disposed near the center. However, the installation location of the high heat-resistant bonding part (first bonding material, high melting point bonding material 5a) may be changed depending on the position of the semiconductor chip 1 as shown in FIGS.
　例えば、図８に示すようにセラミック基板３上に４つの半導体チップ１が搭載されている構造の場合、図７、図９に示すように各半導体チップ１の直下に半導体チップ１の平面サイズと同じ平面サイズ（あるいは半導体チップ１の平面サイズより大きな平面サイズでもよい）となるような高融点接合材（第１接合材、高耐熱接合部）５ａを配置するものである。その際、４つの高融点接合材５ａのそれぞれの周囲には低融点接合材（例えば、Ｓｎ系はんだ合金等）５ｂが配置されている。 For example, in the case of a structure in which four semiconductor chips 1 are mounted on a ceramic substrate 3 as shown in FIG. 8, the planar size of the semiconductor chip 1 is directly below each semiconductor chip 1 as shown in FIGS. A high melting point bonding material (first bonding material, high heat resistant bonding portion) 5a having the same plane size (or a plane size larger than the plane size of the semiconductor chip 1) may be disposed. At that time, a low melting point bonding material (for example, Sn-based solder alloy) 5b is disposed around each of the four high melting point bonding materials 5a.
　つまり、図９に示すように４つの高融点接合材５ａのそれぞれは、それらの周りを低融点接合材５ｂによって取り囲まれている。 That is, as shown in FIG. 9, each of the four high melting point bonding materials 5a is surrounded by the low melting point bonding material 5b.
　このようなモジュール構造であっても、図１に示すパワーモジュール２０と同様の効果を得ることができ、接合信頼性の高いモジュール構造を実現することができる。 Even with such a module structure, the same effect as that of the power module 20 shown in FIG. 1 can be obtained, and a module structure with high bonding reliability can be realized.
　＜適用例＞
　図１０は図１に示す半導体装置が搭載された鉄道車両の一例を示す部分側面図、図１１は図１０に示す鉄道車両に設置されたインバータの内部構造の一例を示す平面図である。 <Application example>
10 is a partial side view showing an example of a railway vehicle on which the semiconductor device shown in FIG. 1 is mounted, and FIG. 11 is a plan view showing an example of an internal structure of an inverter installed in the railway vehicle shown in FIG.
　本適用例では、上記実施の形態のパワーモジュール２０を搭載した鉄道車両について説明する。図１０に示す鉄道車両２１は、例えば、図１に示すパワーモジュール２０が搭載されたものであり、車両本体２６と、パワーモジュール２０と、パワーモジュール２０を支持する実装部材と、集電装置であるパンタグラフ２２と、インバータ２３とを備えている。そして、パワーモジュール２０は、車両本体２６の下部に設置されたインバータ２３に搭載されている。 In this application example, a railway vehicle equipped with the power module 20 of the above embodiment will be described. A railway vehicle 21 shown in FIG. 10 is mounted with the power module 20 shown in FIG. 1, for example, and includes a vehicle main body 26, a power module 20, a mounting member that supports the power module 20, and a current collector. A pantograph 22 and an inverter 23 are provided. The power module 20 is mounted on an inverter 23 installed at the lower part of the vehicle body 26.
　図１１に示すように、インバータ２３の内部では、プリント基板（実装部材）２５上に複数のパワーモジュール２０が搭載され、さらにこれらのパワーモジュール２０を冷却する冷却装置２４が搭載されている。図１に示す本実施の形態のパワーモジュール２０では、半導体チップ１からの発熱量が多い。したがって、複数のパワーモジュール２０を冷却してインバータ２３の内部を冷却可能なように冷却装置２４が取り付けられている。 As shown in FIG. 11, a plurality of power modules 20 are mounted on a printed circuit board (mounting member) 25 inside the inverter 23, and a cooling device 24 for cooling these power modules 20 is mounted. In the power module 20 of the present embodiment shown in FIG. 1, the amount of heat generated from the semiconductor chip 1 is large. Therefore, the cooling device 24 is attached so that the plurality of power modules 20 can be cooled to cool the inside of the inverter 23.
　これにより、鉄道車両２１において、図１に示すモジュールの接合構造が用いられた複数のパワーモジュール２０を搭載したインバータ２３が設けられていることにより、インバータ２３内が高温環境となった場合であっても、インバータ２３およびそれが設けられた鉄道車両２１の信頼性を高めることができる。すなわち、高温環境下での動作安定性と高電流負荷にも耐え得るパワーモジュール２０およびこれを用いたインバータシステムを実現することができる。 As a result, in the railway vehicle 21, the inverter 23 equipped with the plurality of power modules 20 using the module joining structure shown in FIG. Even so, the reliability of the inverter 23 and the railway vehicle 21 provided with the inverter 23 can be improved. That is, it is possible to realize a power module 20 that can withstand operation stability under a high temperature environment and a high current load, and an inverter system using the same.
　次に、上記実施の形態のパワーモジュール２０を搭載した自動車について説明する。図１２は図１に示す半導体装置が搭載された自動車の一例を示す斜視図である。 Next, an automobile equipped with the power module 20 of the above embodiment will be described. 12 is a perspective view showing an example of an automobile on which the semiconductor device shown in FIG. 1 is mounted.
　図１２に示す自動車２７は、例えば、図１に示すパワーモジュール２０が搭載されたものであり、車体２８と、タイヤ２９と、パワーモジュール２０と、パワーモジュール２０を支持する実装部材である実装ユニット３０と、を備えている。 An automobile 27 shown in FIG. 12 is mounted with the power module 20 shown in FIG. 1, for example, and includes a vehicle body 28, a tire 29, the power module 20, and a mounting unit that is a mounting member that supports the power module 20. 30.
　自動車２７では、パワーモジュール２０は、実装ユニット３０に含まれるインバータに搭載されているが、実装ユニット３０は、例えば、エンジン制御ユニット等であり、その場合、実装ユニット３０はエンジンの近傍に配置されている。この場合には、実装ユニット３０は、高温環境下での使用となり、これにより、パワーモジュール２０も高温状態となる。 In the automobile 27, the power module 20 is mounted on an inverter included in the mounting unit 30. The mounting unit 30 is, for example, an engine control unit, and in this case, the mounting unit 30 is disposed in the vicinity of the engine. ing. In this case, the mounting unit 30 is used in a high temperature environment, and the power module 20 is also in a high temperature state.
　しかしながら、自動車２７において、図１に示すモジュールの接合構造が用いられた複数のパワーモジュール２０を搭載したインバータが設けられていることにより、実装ユニット３０が高温環境となった場合であっても、自動車２７の信頼性を高めることができる。つまり自動車２７においても、高温環境下での動作安定性と高電流負荷にも耐え得るパワーモジュール２０およびこれを用いたインバータシステムを実現することができる。 However, even if the mounting unit 30 is in a high temperature environment by providing an inverter in which a plurality of power modules 20 using the module joining structure shown in FIG. The reliability of the automobile 27 can be improved. That is, in the automobile 27 as well, it is possible to realize the power module 20 that can withstand operation stability under a high temperature environment and a high current load, and an inverter system using the same.
　以上、本発明者によってなされた発明を発明の実施の形態に基づき具体的に説明したが、本発明は前記発明の実施の形態に限定されるものではなく、その要旨を逸脱しない範囲で種々変更可能であることは言うまでもない。 As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments of the invention. However, the present invention is not limited to the embodiments of the invention, and various modifications can be made without departing from the scope of the invention. It goes without saying that it is possible.
　なお、本発明は上記した実施の形態に限定されるものではなく、様々な変形例が含まれる。例えば、上記した実施の形態は本発明を分かりやすく説明するために詳細に説明したものであり、必ずしも説明した全ての構成を備えるものに限定されるものではない。 Note that the present invention is not limited to the above-described embodiment, and includes various modifications. For example, the above-described embodiment has been described in detail for easy understanding of the present invention, and is not necessarily limited to one having all the configurations described.
　また、ある実施の形態の構成の一部を他の実施の形態の構成に置き換えることが可能であり、また、ある実施の形態の構成に他の実施の形態の構成を加えることも可能である。また、各実施の形態の構成の一部について、他の構成の追加、削除、置換をすることが可能である。なお、図面に記載した各部材や相対的なサイズは、本発明を分かりやすく説明するため簡素化・理想化しており、実装上はより複雑な形状となる。 Further, a part of the configuration of one embodiment can be replaced with the configuration of another embodiment, and the configuration of another embodiment can be added to the configuration of one embodiment. . In addition, it is possible to add, delete, and replace other configurations for a part of the configuration of each embodiment. In addition, each member and relative size which were described in drawing are simplified and idealized in order to demonstrate this invention clearly, and it becomes a more complicated shape on mounting.
　　１　半導体チップ
　１ａ　上面
　１ｂ　下面
　１ｃ　電極
　　２　はんだ
　　３　セラミック基板（配線基板）
　３ａ　上面
　３ｂ　下面
  ３ｃ，３ｃａ，３ｃｂ，３ｃｃ　電極
　　４　ベース板（金属板）
　　５　はんだ（接合材）
　５ａ　高融点接合材（第１接合材）
　５ｂ　低融点接合材（第２接合材）
　　６　ワイヤ
　　７　端子
　　８　ケース
　　９　ポーラス状接合部（多孔質接合材）
　１０　金属間化合物
　２０　パワーモジュール（半導体装置）
　２１　鉄道車両
　２２　パンタグラフ
　２３　インバータ
　２４　冷却装置
　２５　プリント基板
　２６　車両本体
　２７　自動車
　２８　車体
　２９　タイヤ
　３０　実装ユニット
　４０　Ｓｎ系はんだ
　４１，４２　亀裂
　５０　パワーモジュール DESCRIPTION OF SYMBOLS 1 Semiconductor chip 1a Upper surface 1b Lower surface 1c Electrode 2 Solder 3 Ceramic substrate (wiring board)
3a upper surface 3b lower surface 3c, 3ca, 3cb, 3cc electrode 4 base plate (metal plate)
5 Solder (joining material)
5a High melting point bonding material (first bonding material)
5b Low melting point bonding material (second bonding material)
6 Wire 7 Terminal 8 Case 9 Porous joint (porous joint material)
10 Intermetallic compounds 20 Power modules (semiconductor devices)
DESCRIPTION OF SYMBOLS 21 Rail vehicle 22 Pantograph 23 Inverter 24 Cooling device 25 Printed circuit board 26 Vehicle main body 27 Car 28 Car body 29 Tire 30 Mounting unit 40 Sn system solder 41, 42 Crack 50 Power module

Claims (13)

  1. 　半導体チップを支持し、前記半導体チップと電気的に接続された配線基板と、
    　前記配線基板を支持する金属板と、
    　前記配線基板と前記金属板との間に配置され、前記配線基板と前記金属板とを接合する接合材と、
    　を有し、
    　前記接合材は、前記半導体チップの直下において、前記半導体チップの平面サイズと同じかまたはそれより大きな平面サイズで形成された第１接合材と、平面視で前記第１接合材の周囲に配置された第２接合材とからなり、
    　前記第１接合材は、前記第２接合材より融点が高い、半導体装置。     A wiring board that supports the semiconductor chip and is electrically connected to the semiconductor chip;
    A metal plate that supports the wiring board;
    A bonding material disposed between the wiring board and the metal plate, and bonding the wiring board and the metal plate;
    Have
    The bonding material is disposed immediately below the semiconductor chip, around a first bonding material formed in a plane size equal to or larger than the planar size of the semiconductor chip and around the first bonding material in plan view. Second bonding material,
    The first bonding material is a semiconductor device having a higher melting point than the second bonding material.
  2. 　請求項１記載の半導体装置において、
    　前記第１接合材は、前記配線基板を介して前記半導体チップの直下に配置されている、半導体装置。     The semiconductor device according to claim 1,
    The semiconductor device, wherein the first bonding material is disposed directly below the semiconductor chip via the wiring board.
  3. 　請求項１記載の半導体装置において、
    　前記第１接合材は、金属粒子による焼結材であり、
    　前記第２接合材は、Ｓｎ系はんだ合金である、半導体装置。     The semiconductor device according to claim 1,
    The first bonding material is a sintered material made of metal particles,
    The semiconductor device, wherein the second bonding material is a Sn-based solder alloy.
  4. 　請求項１記載の半導体装置において、
    　前記第１接合材は、金属間化合物を含み、
    　前記第２接合材は、Ｓｎ系はんだ合金である、半導体装置。     The semiconductor device according to claim 1,
    The first bonding material includes an intermetallic compound,
    The semiconductor device, wherein the second bonding material is a Sn-based solder alloy.
  5. 　請求項１記載の半導体装置において、
    　前記第１接合材は、Ｚｎ系はんだ合金またはＡｕ系はんだ合金であり、
    　前記第２接合材は、Ｓｎ系はんだ合金である、半導体装置。     The semiconductor device according to claim 1,
    The first bonding material is a Zn-based solder alloy or an Au-based solder alloy,
    The semiconductor device, wherein the second bonding material is a Sn-based solder alloy.
  6. 　請求項１記載の半導体装置において、
    　鉄道の車両に設けられたインバータに搭載されている、半導体装置。     The semiconductor device according to claim 1,
    A semiconductor device mounted on an inverter provided in a railway vehicle.
  7. 　請求項１記載の半導体装置において、
    　自動車の車体に設けられたインバータに搭載されている、半導体装置。     The semiconductor device according to claim 1,
    A semiconductor device mounted on an inverter provided in the body of an automobile.
  8. 　（ａ）配線基板上に半導体チップを搭載する工程、
    　（ｂ）前記半導体チップが搭載された前記配線基板を、接合材を介して金属板上に搭載する工程、
    　を有し、
    　前記（ｂ）工程において、前記接合材を加熱溶融して前記配線基板と前記金属板とを接合し、
    　前記接合材は、前記半導体チップの直下において、前記半導体チップの平面サイズと同じかまたはそれより大きな平面サイズで形成された第１接合材と、平面視で前記第１接合材の周囲に配置された第２接合材とからなり、
    　前記第１接合材は、前記第２接合材より融点が高い、半導体装置の製造方法。     (A) mounting a semiconductor chip on a wiring board;
    (B) a step of mounting the wiring board on which the semiconductor chip is mounted on a metal plate via a bonding material;
    Have
    In the step (b), the bonding material is heated and melted to bond the wiring board and the metal plate,
    The bonding material is disposed immediately below the semiconductor chip, around a first bonding material formed in a plane size equal to or larger than the planar size of the semiconductor chip and around the first bonding material in plan view. Second bonding material,
    The method for manufacturing a semiconductor device, wherein the first bonding material has a higher melting point than the second bonding material.
  9. 　請求項８記載の半導体装置の製造方法において、
    　前記第１接合材は、金属粒子による焼結材であり、
    　前記（ｂ）工程において、前記配線基板上に配置された前記焼結材を加熱して前記配線基板上に多孔質接合材を形成し、その後、前記多孔質接合材および前記第２接合材を加熱溶融し、前記加熱溶融により形成された前記接合材を介して前記配線基板と前記金属板とを接合する、半導体装置の製造方法。     The method of manufacturing a semiconductor device according to claim 8.
    The first bonding material is a sintered material made of metal particles,
    In the step (b), the sintered material disposed on the wiring board is heated to form a porous bonding material on the wiring board, and then the porous bonding material and the second bonding material are formed. A method for manufacturing a semiconductor device, comprising: heating and melting, and bonding the wiring board and the metal plate through the bonding material formed by the heating and melting.
  10. 　請求項９記載の半導体装置の製造方法において、
    　前記（ｂ）工程で前記配線基板上に前記多孔質接合材を形成した後、前記多孔質接合材上に、前記多孔質接合材より平面サイズが大きな前記第２接合材である低融点金属箔を配置し、その後、前記多孔質接合材および前記低融点金属箔を加熱溶融し、前記加熱溶融により形成された前記接合材を介して前記配線基板と前記金属板とを接合する、半導体装置の製造方法。     In the manufacturing method of the semiconductor device according to claim 9,
    After forming the porous bonding material on the wiring board in the step (b), the low melting point metal foil which is the second bonding material having a larger planar size than the porous bonding material on the porous bonding material Of the semiconductor device, after which the porous bonding material and the low melting point metal foil are heated and melted, and the wiring board and the metal plate are bonded via the bonding material formed by the heating and melting. Production method.
  11. 　請求項１０記載の半導体装置の製造方法において、
    　前記（ｂ）工程で前記多孔質接合材および前記低融点金属箔を加熱溶融することで、金属間化合物を形成する、半導体装置の製造方法。     The method of manufacturing a semiconductor device according to claim 10.
    A method for manufacturing a semiconductor device, wherein an intermetallic compound is formed by heating and melting the porous bonding material and the low-melting-point metal foil in the step (b).
  12. 　請求項８記載の半導体装置の製造方法において、
    　前記第１接合材は、金属粒子による焼結材であり、
    　前記第２接合材は、Ｓｎ系はんだ合金である、半導体装置の製造方法。     The method of manufacturing a semiconductor device according to claim 8.
    The first bonding material is a sintered material made of metal particles,
    The method for manufacturing a semiconductor device, wherein the second bonding material is an Sn-based solder alloy.
  13. 　請求項８記載の半導体装置の製造方法において、
    　前記第１接合材は、Ｚｎ系はんだ合金またはＡｕ系はんだ合金であり、
    　前記第２接合材は、Ｓｎ系はんだ合金である、半導体装置の製造方法。     The method of manufacturing a semiconductor device according to claim 8.
    The first bonding material is a Zn-based solder alloy or an Au-based solder alloy,
    The method for manufacturing a semiconductor device, wherein the second bonding material is an Sn-based solder alloy.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019067976A (en) * 2017-10-03 2019-04-25 トヨタ自動車株式会社 Semiconductor device
WO2019097790A1 (en) * 2017-11-15 2019-05-23 パナソニックＩｐマネジメント株式会社 Semiconductor module and production method therefor

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10242356A (en) * 1997-02-27 1998-09-11 Kyocera Corp Manufacture of package for housing semiconductor device
JP2007243118A (en) * 2006-03-13 2007-09-20 Fuji Electric Holdings Co Ltd Semiconductor device
JP2009088215A (en) * 2007-09-28 2009-04-23 Dowa Metaltech Kk Semiconductor device
JP2015005571A (en) * 2013-06-19 2015-01-08 株式会社デンソー Semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10242356A (en) * 1997-02-27 1998-09-11 Kyocera Corp Manufacture of package for housing semiconductor device
JP2007243118A (en) * 2006-03-13 2007-09-20 Fuji Electric Holdings Co Ltd Semiconductor device
JP2009088215A (en) * 2007-09-28 2009-04-23 Dowa Metaltech Kk Semiconductor device
JP2015005571A (en) * 2013-06-19 2015-01-08 株式会社デンソー Semiconductor device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019067976A (en) * 2017-10-03 2019-04-25 トヨタ自動車株式会社 Semiconductor device
WO2019097790A1 (en) * 2017-11-15 2019-05-23 パナソニックＩｐマネジメント株式会社 Semiconductor module and production method therefor
JPWO2019097790A1 (en) * 2017-11-15 2020-10-08 パナソニックセミコンダクターソリューションズ株式会社 Semiconductor module and its manufacturing method
US10847702B2 (en) 2017-11-15 2020-11-24 Panasonic Semiconductor Solutions Co., Ltd. Semiconductor module
JP7201439B2 (en) 2017-11-15 2023-01-10 ヌヴォトンテクノロジージャパン株式会社 Semiconductor module and manufacturing method thereof

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