JP2020107627A - Semiconductor device and manufacturing method of semiconductor device - Google Patents

Abstract

To improve reliability of a semiconductor device.SOLUTION: A semiconductor device 10 comprises: a wiring board 3 having an upper face 3a and a lower face 3b that is located on the opposite side to the upper face 3a; wiring 3ab formed on the upper face 3a of the wiring board 3; wiring 3ba formed on the lower face 3b of the wiring board 3; a plurality of semiconductor chips 1 each mounted on the wiring 3ab via a bonding material 2; and a base plate 4 which is bonded via a bonding material 5 provided between itself and the wiring 3ba so as to support the wiring board 3. In plan view, the plurality of semiconductor chips 1 are disposed on ends A2 of the wiring board 3. In the wiring board 3, the ends A2 of the wiring board 3 are fixed in such a shape as to protrude toward the upper face 3a side whereas a central part A1 of the wiring board 3 is flat in plan view.SELECTED DRAWING: Figure 1

Description

The present invention relates to a semiconductor device and a method of manufacturing a semiconductor device.

In a power module (power semiconductor device), a semiconductor element (hereinafter, also referred to as a semiconductor chip or simply a chip) and a wiring board (insulating board), or a wiring board and a heat sink (metal plate for heat dissipation) are joined by a bonding material such as solder. Often has a bonded structure.

So far, lead (Pb)-containing solder has been used as a bonding material for semiconductor devices used in automobiles, construction machinery, railways, industrial fields, etc., which require high heat resistance. Equipment using free bonding materials has also been widely distributed.

In recent years, development of wide-gap semiconductors such as silicon carbide (SiC) and gallium nitride (GaN) that can operate at high temperatures and can reduce the size and weight of devices by simplifying a cooling system has been promoted. In general, the upper limit of the operating temperature of a Si semiconductor element is 150 to 175° C., whereas the SiC semiconductor element can be used at 175° C. or higher. When the operating temperature becomes high, various members used in the power module are also required to have heat resistance and reliability.

Therefore, a heat-resistant ceramic substrate is generally used as the wiring substrate of the power module. For example, in Patent Document 1, for the purpose of providing a ceramic substrate capable of obtaining a solder layer having a small porosity in the case of solder joining with a heat sink, metal heat radiation when heated to 230 to 300° C. A ceramic substrate is described, which is characterized in that it is curved in a convex shape on the plate side.

JP, 2006-245437, A

The inventor of the present invention is considering improving the bonding between the wiring board and the semiconductor chip or the bonding between the wiring board and the base plate (heat sink) in the power module. In the power module, it is desired to improve the reliability of the semiconductor device by devising the semiconductor device and the manufacturing method thereof.

Other problems and novel features will be apparent from the description of the present specification and the accompanying drawings.

A semiconductor device according to an embodiment is a wiring board having a first surface and a second surface opposite to the first surface; a first wiring formed on the first surface of the wiring board; A second bonding material between the second wiring formed on the second surface of the wiring board, a plurality of semiconductor chips mounted on the first wiring via a first bonding material, and the second wiring. And a base plate that supports the wiring board. The plurality of semiconductor chips are arranged on an end portion of the wiring board in a plan view, and the end portion of the wiring board in the wiring board in a plan view is convex toward the first surface side. The central portion of the wiring board is flat while being fixed in such a shape.

According to one embodiment, the reliability of the semiconductor device can be improved.

FIG. 3 is a main-portion cross-sectional view showing the semiconductor device of one embodiment. FIG. 3 is a main-portion cross-sectional view showing the semiconductor device of one embodiment. FIG. 3 is a main-portion plan view showing the semiconductor device of the embodiment; FIG. 7 is a main-portion cross-sectional view of the semiconductor device of the embodiment during the manufacturing process thereof. FIG. 5 is a main-portion cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 4; FIG. 6 is a main-portion cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 5; FIG. 7 is a main-portion cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 6; FIG. 8 is a main-portion cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 7; FIG. 9 is a main-portion cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 8; FIG. 10 is a main-portion cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 9; FIG. 6 is a main-portion cross-sectional view showing a semiconductor device in a first studied example. FIG. 6 is a main-portion plan view showing a semiconductor device of a first study example; FIG. 6 is a main-portion cross-sectional view of the semiconductor device of the first studied example during the manufacturing process thereof; FIG. 13 is a main-portion cross-sectional view of a semiconductor device in a second studied example during a manufacturing step thereof; FIG. 7 is a schematic cross-sectional view showing a state of a sink mark in the semiconductor devices of the first and second examination examples. It is a principal part top view which shows the semiconductor device of the 1st modification. FIG. 9 is a main-portion cross-sectional view showing a semiconductor device of a second embodiment. FIG. 2 is a partial side view showing an example of a railway vehicle equipped with the semiconductor device shown in FIG. 1. FIG. 19 is a plan view showing an example of the internal structure of the inverter installed in the railway vehicle shown in FIG. 18. FIG. 3 is a perspective view showing an example of an automobile equipped with the semiconductor device shown in FIG. 1.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In all the drawings for explaining the embodiments, members having the same function are designated by the same reference numeral, and the repeated description thereof will be omitted. In the following embodiments, the description of the same or similar portions will not be repeated in principle unless particularly necessary.

(Embodiment 1)
<Structure of semiconductor device>
1 and 2 are cross-sectional views of a main part showing a structure of a semiconductor device (power module) according to one embodiment (hereinafter, referred to as a first embodiment), and FIG. 3 shows a structure of the semiconductor device according to the first embodiment. It is a principal part top view. Note that FIG. 1 is a cross-sectional view of a main part viewed from the B direction in FIG. 3, and FIG. 2 is a cross-sectional view of the main part viewed from the C direction in FIG.

The configuration of the semiconductor device according to the first embodiment shown in FIGS. 1 to 3 will be described below. The semiconductor device 10 according to the first embodiment is configured as, for example, a power module (semiconductor module) mounted on a rail car, a car body, or the like. Specifically, the semiconductor device 10 includes a plurality of semiconductor chips 1, a wiring substrate (supporting substrate, insulating substrate) 3 that supports the semiconductor chips 1, a base plate (heat sink) 4 that supports the wiring substrate 3, and a semiconductor. It has a wire 6 for electrically connecting the chip 1 and the wiring board 3, and a terminal (lead) 7 for electrically connecting the wiring board 3 and an external device (not shown). The semiconductor chip 1 and the wiring board 3 are bonded via the bonding material 2. Then, the wiring board 3 and the base plate 4 are joined via the joining material 5.

The plurality of semiconductor chips 1 are power semiconductor chips (semiconductor elements). Each semiconductor chip 1 includes, for example, an IGBT (Insulated Gate Bipolar Transistor), a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), an FWD (Free Wheeling Diode), an SBD (Schottky Barrier Diode), etc., but is not limited thereto. Not something. The semiconductor chip 1 is made of Si, SiC, GaN, gallium oxide, diamond, or the like, preferably SiC or GaN that can operate at a high temperature of 175° C. or higher, but is not limited to this. Absent. Suitable examples of the semiconductor chip 1 include, for example, an IGBT (SiC-IGBT) or a MOSFET (SiC-MOSFET) using SiC as a substrate material, which is used as a silicon carbide switching element in a drive device for railway vehicles, and an SiC-. It includes a SiC diode which is a freewheeling element of an IGBT or a SiC-MOSFET. Each semiconductor chip 1 is formed in a rectangular shape in a plan view.

The wiring board 3 of the first embodiment is made of a ceramic substrate such as alumina (Al ₂ O ₃ ), aluminum nitride (AlN), silicon nitride (Si ₃ N ₄ ), or the like. A plurality of wirings (first wirings, conductor films, conductor patterns, electrodes, circuits) 3aa, 3ab, 3ac are arranged on the upper surface (first surface, main surface) 3a of the wiring board 3 and a lower surface (second surface) of the wiring board 3. Wiring (second wiring, conductor film, conductor pattern) 3ba is formed on each of the surface and the main surface 3b. The wirings 3aa, 3ab, 3ac, 3ba are made of, for example, a material containing copper (Cu) and aluminum (Al) as main components.

On the wiring 3ab provided on the upper surface 3a of the wiring board 3, a plurality of (for example, six) semiconductor chips 1 are mounted via a bonding material (first bonding material) 2. That is, the wiring board 3 supports the semiconductor chip 1 via the bonding material 2. Since the semiconductor chip 1 is bonded to the wiring 3ab on the upper surface 3a side of the wiring board 3 as described above, the upper surface 3a of the wiring board 3 may be hereinafter referred to as a semiconductor chip mounting surface 3a.

The bonding material 2 is made of a material that melts and forms an intermetallic compound at the interface with the material to be bonded and bonds the material, for example, a solder (alloy). As the solder, a solder containing tin (Sn) as a main component or a solder containing lead (Pb) as a main component is preferable, and specifically, Pb-Sn, Sn-Cu, Sn-Cu-Sb, Sn-Sb. , Sn-Ag, Sn-Ag-Cu and the like are preferable. The melting point of the material forming the bonding material 2 is about 220° C. in the case of solder containing tin (Sn) as a main component, and 290° C. or higher in the case of solder containing lead (Pb) as a main component. The melting point of the material forming the bonding material 2 is preferably 300° C. or less from the viewpoint of the heat resistance of the material to be bonded and the members around it and the residual stress during cooling.

As shown in FIGS. 1 and 3, the plurality of semiconductor chips 1 are arranged at the end portions of the wiring board 3 in plan view. Note that the “edge portion” refers to a region from the peripheral edge (outermost peripheral edge) of the wiring board 3 to the inside by one side (long side or short side) of the semiconductor chip 1 in plan view. ..

As shown in FIG. 3, the wiring board 3 according to the first embodiment is formed in a rectangular shape in plan view. Therefore, the central portion of the wiring board 3 in the long-side direction (longitudinal direction, length direction) is the area A1 (hereinafter, also referred to as the long-side central portion A1 or simply the central portion A1), and the long-side end is the area A2 (hereinafter referred to as the area A2). , Along side edge A2 or simply edge A2). Therefore, as shown in FIGS. 1 and 3, in semiconductor device 10 of the first embodiment, a plurality of semiconductor chips 1 are arranged at long-side end A2 of wiring board 3 in plan view. In particular, one of the sides of each of the plurality of semiconductor chips 1 is arranged along the peripheral edge of the wiring board 3.

It is not necessary that all of the plurality of semiconductor chips 1 be arranged at the end portions of the wiring board 3 in a plan view, and some of the plurality of semiconductor chips 1 may be arranged in the wiring board 3 in a plan view. It may be arranged in the central portion. However, it is preferable that one of the sides of each of the plurality of semiconductor chips 1 is arranged along the peripheral edge of the wiring board 3.

Further, in the first embodiment, the semiconductor chip 1 is described as an example in which it is arranged at the long side direction end portion A2 of the wiring board 3 in a plan view, but the present invention is not limited to this and will be described later. As shown in the modification example, the semiconductor chip 1 may be arranged at the end portion of the wiring board 3 in the short side direction (width direction, width direction) in plan view.

Further, although the wiring board 3 is described as an example in which it is formed in a rectangular shape in a plan view, the present invention is not limited to this. Also in this case, in plan view, the end portion of the wiring board 3 on which the semiconductor chip 1 is arranged has a length from the peripheral edge (outermost peripheral edge) of the wiring board 3 to one side (long side or short side) of the semiconductor chip 1. It can be defined as the area up to the inside.

Further, in the wiring board 3 according to the first embodiment, one end A2 of the wiring board 3 is fixed in a convex shape (warped) toward the upper surface (first surface) 3a side in plan view. The central portion A1 of the wiring board 3 is flat. In other words, the (closest) distance between the upper surface 3a of the wiring board 3 and the lower surface 3b of the wiring board 3 is substantially constant between the central portion A1 of the wiring board 3 and the end portion A2 of the wiring board 3, while The (closest) distance between the lower surface 3b of the end portion A2 of 3 and the upper surface of the base plate 4 is the (closest) distance between the lower surface 3b of the central portion A1 of the wiring board 3 and (the upper surface of) the base plate 4. Shorter than.

Further, the wiring board 3 of the first embodiment is deformed into a shape that becomes convex toward the semiconductor chip mounting surface (upper surface, first surface) 3a side of the wiring board 3 when heated to 200 to 350° C., for example. Do (warp). The amount of deformation (warpage) of the wiring board 3 is preferably 200 μm or less.

As one specific example of the structure of the wiring board 3, a material forming the wirings 3aa, 3ab and 3ac on the upper surface 3a side of the wiring board 3 and a material forming the wiring 3ba on the lower surface 3b side of the wiring board 3 are used. The wirings 3a, 3ab, 3ac on the upper surface 3a side of the wiring board 3 are thicker than the wirings 3ba on the lower surface 3b side of the wiring board 3 which are the same. By doing so, the thermal expansion amount of the wirings 3aa, 3ab, 3ac becomes larger than the thermal expansion amount of the wiring 3ba. As a result, when the wiring board 3 is heated, the wiring board 3 is deformed (warped) into a shape that is convex toward the upper surface 3a side of the wiring board 3.

Further, as another specific configuration example of the wiring board 3, the thickness of the wirings 3aa, 3ab, 3ac on the upper surface 3a side of the wiring board 3 is equal to the thickness of the wiring 3ba on the lower surface 3b side of the wiring board 3. And the linear expansion coefficient of the material forming the wirings 3aa, 3ab, 3ac is larger than the linear expansion coefficient of the material forming the wiring 3ba. By doing so, the thermal expansion amount of the wirings 3aa, 3ab, 3ac becomes larger than the thermal expansion amount of the wiring 3ba. As a result, when the wiring board 3 is heated, the wiring board 3 is deformed (warped) into a shape that is convex toward the upper surface 3a side of the wiring board 3. The coefficient of linear expansion of the main material forming the semiconductor chip 1 is smaller than the coefficient of linear expansion of the material forming the wirings 3aa, 3ab, 3ac, 3ba.

The base plate 4 of the first embodiment is a heat sink (heat dissipation metal plate), and is, for example, aluminum, Al—C, aluminum alloy, copper, Cu—C, Cu—Mo, copper alloy, or a composite of aluminum and SiC. Material or a composite material of magnesium (Mg) and SiC, and the surface thereof may be plated with nickel (Ni), gold (Au), silver (Ag), or the like. The base plate 4 is electrically connected to the wiring 3ba formed on the lower surface 3b of the wiring board 3 via a bonding material (second bonding material) 5. That is, the base plate 4 supports the wiring board 3 via the bonding material 5. Since the base plate 4 is bonded to the wiring 3ba on the lower surface 3b side of the wiring board 3 as described above, the lower surface 3b of the wiring board 3 may be hereinafter referred to as a base plate bonding surface 3b.

Like the bonding material 2, the bonding material 5 is made of a material that melts to form an intermetallic compound at the interface with the material to be bonded and bonds, and is, for example, a solder (alloy). The materials of the bonding material 2 and the bonding material 5 may be the same or different, but as described later, the melting point of the material forming the bonding material 5 is higher than the melting point of the material forming the bonding material 2. It is preferably low. That is, it is preferable that when the joining materials 2 and 5 which are melted at a certain temperature are cooled at the same rate, the joining material 2 is first solidified.

The wire 6 of the first embodiment is, for example, a metal wire such as an aluminum wire or a copper wire, and is formed of an electrode (for example, for a gate, not shown) provided on the upper surface of the semiconductor chip 1 and an upper surface 3 a of the wiring board 3. The wiring (conductor film, circuit) 3aa, 3ac is electrically connected.

The terminal 7 of the first embodiment is, for example, a metal wire, one end of which is connected to the wiring 3aa provided on the upper surface 3a of the wiring board 3, and the other end of which is drawn to the outside of the case 8 described later. Thus, the wiring 3aa and the external device (not shown) are electrically connected.

Further, a case 8 that covers the plurality of semiconductor chips 1, the plurality of wires 6 and the wiring board 3 is attached to the base plate 4 of the first embodiment. The area surrounded by the upper surface of the base plate 4 and the case 8 is filled with, for example, a sealing resin 11. As the resin 11, for example, a gel resin material can be used.

<Semiconductor device manufacturing process>
Next, the manufacturing process of the semiconductor device of the first embodiment will be described, and the structure of the semiconductor device of the first embodiment will be made clearer. 4 to 10 are main-portion cross-sectional views of the semiconductor device of First Embodiment during a manufacturing step, and show cross sections corresponding to FIG.

The method of manufacturing a semiconductor device according to the first embodiment includes a semiconductor chip bonding step (S1) and a base plate bonding step (S2). The semiconductor chip bonding step (S1) includes a step of heating the wiring board 3 to deform (warp) the wiring board 3 into a convex shape toward the semiconductor chip mounting surface (upper surface, first surface) 3a side, and wiring. The step of disposing and melting the bonding material (first bonding material) 2 on the wiring (first wiring) 3ab on the semiconductor chip mounting surface 3a side of the substrate 3 is included. Then, in the semiconductor chip bonding step (S1), a step of disposing the semiconductor chip 1 on the bonding material 2 arranged at the end portion A2 of the wiring board 3 in a plan view, cooling the wiring board 3, and The step of bringing the lower surface close to the upper surface 3a of the end portion A2 of the wiring board 3 and solidifying the bonding material 2 is included.

In the base plate bonding step (S2), the wiring board 3 is heated to deform (warp) the end portion A2 of the wiring board 3 into a shape that is convex toward the base plate bonding surface (lower surface, second surface) 3b side. The process includes a step and a step of disposing the bonding material (second bonding material) 5 on the base plate 4 and melting the bonding material. In the base plate bonding step (S2), the wiring board 3 is arranged on the bonding material 5 so that the wiring (second wiring) 3ba on the base plate bonding surface 3b side of the wiring board 3 contacts the bonding material 5. And the step of cooling the wiring board 3, bringing the upper surface of the base plate 4 and the lower surface 3b of the end portion of the wiring board 3 close to each other, and solidifying the bonding material 5. Hereinafter, each step will be described in detail.

First, the semiconductor chip joining step (S1) will be described. As shown in FIG. 4, the wiring board 3 is prepared. Subsequently, as shown in FIG. 5, the wiring board 3 is heated to a temperature at which the bonding material 2 is sufficiently melted, for example, 200 to 350° C. At this time, in the wiring board 3, as described above, the amount of thermal expansion of the wiring 3ab on the upper surface 3a side of the wiring board 3 is larger than the thermal expansion amount of the wiring 3ba on the lower surface 3b side of the wiring board 3 (in FIG. 5). Therefore, the wiring board 3 is deformed (warped) toward the upper surface 3a side of the wiring board 3.

Here, as shown in FIG. 6, the bonding material 2 is arranged on the wiring 3ab on the upper surface 3a side of the wiring substrate 3 and the bonding material 2 is melted. Further, the semiconductor chip 1 is arranged on the bonding material 2. At this time, the semiconductor chip 1 is arranged at the end portion A2 in the long side direction of the wiring board 3 in a plan view.

Then, as the wiring board 3 (and the semiconductor chip 1) is cooled, the melted bonding material 2 starts to solidify. At the same time, since the amount of heat shrinkage of the wiring 3ab on the upper surface 3a side of the wiring board 3 is larger than the amount of heat shrinkage of the wiring 3ba on the lower surface 3b side of the wiring board 3, the warped wiring board 3 tends to become flat. As a result, the lower surface of the semiconductor chip 1 and the upper surface 3a of the long-side end portion of the wiring board 3 approach each other (see the arrow in FIG. 6), and as shown in FIG. It solidifies in a state of being filled between the wiring board 3 and the wiring 3ab.

As shown in FIG. 7, when the wiring board 3 is cooled and the bonding material 2 is solidified, the long side end A2 of the wiring 3ab of the wiring board 3 is integrated with the semiconductor chip 1. Here, since the linear expansion coefficient of the main material forming the semiconductor chip 1 is smaller than the linear expansion coefficient of the material forming the wirings 3ab and 3ba, after the bonding material 2 solidifies, The end portion A2 is not completely flat. On the other hand, the central portion A1 in the long side direction of the wiring board 3 on which the semiconductor chip 1 is not mounted is completely flat. The above is the semiconductor chip joining step (S1).

As shown in FIG. 7, when the wiring board 3 is cooled and the bonding material 2 is solidified, the long side end A2 of the wiring 3ab of the wiring board 3 is integrated with the semiconductor chip 1. At this time, the bonding material 2 generates intermetallic compounds at the interface with the semiconductor chip 1 which is the material to be bonded and at the interface with the wiring 3ab of the wiring board 3 and is firmly bonded, so that the base plate shown below is used. Even if the bonding material 2 is melted during the bonding step (S2), it does not return to the state shown in FIG. If such a situation is to be reliably prevented, the melting point of the material forming the bonding material 5 may be set lower than the melting point of the material forming the bonding material 2. By doing so, in the base plate bonding step (S2) described below, if the wiring board 3 is heated to the melting point of the bonding material 5 or more and less than the melting point of the bonding material 2, the bonding material 5 can be in a molten state. On the other hand, the bonding material 2 can be maintained in the solidified state.

Next, the base plate bonding step (S2) will be described. As shown in FIG. 8, the wiring board 3 is heated to a temperature at which the bonding material 5 is sufficiently melted, for example, 200 to 350° C. At this time, as described above, the linear expansion coefficient of the main material forming the semiconductor chip 1 forms the wirings 3ab and 3ba at the end of the wiring 3ab of the wiring board 3 integrated with the semiconductor chip 1 in the long side direction. Since the coefficient of linear expansion of the material is smaller than that of the material, the amount of thermal expansion of the wiring 3ba on the lower surface 3b side of the wiring board 3 is larger than that of the wiring 3ab on the upper surface 3a side of the wiring board 3 (arrow in FIG. 8). reference). As a result, the long-side direction end portion A2 of the wiring board 3 is deformed (warped) to a shape convex toward the lower surface 3b side of the wiring board 3. On the other hand, in the central portion A1 of the wiring board 3 on which the semiconductor chip 1 is not mounted, the amount of thermal expansion of the wiring 3ab on the upper surface 3a side of the wiring board 3 is larger than that of the wiring 3ba on the lower surface 3b side of the wiring board 3. Since the amount is larger than the amount, it is deformed (warped) toward the upper surface 3a side of the wiring board 3.

Here, as shown in FIG. 9, the bonding material 5 is arranged on the upper surface of the base plate 4, and the bonding material 5 is melted. Further, the wiring board 3 is mounted on the bonding material 5. At this time, the wiring 3ba on the lower surface 3b side of the wiring board 3 is arranged so as to be in contact with the bonding material 5.

After that, when the wiring board 3 (and the base plate 4) is cooled, the melted bonding material 5 starts to solidify. At the same time, as described above, the central portion A1 in the long side direction of the wiring board 3 which is convexly warped toward the upper surface 3a side tends to be flat. On the other hand, in the long side end portion A2 of the wiring 3ab of the wiring board 3 integrated with the semiconductor chip 1, the amount of heat shrinkage of the wiring 3ba on the lower surface 3b side of the wiring board 3 is the wiring 3ab on the upper surface 3a side of the wiring board 3. Than the heat shrinkage of. Therefore, the upper surface of the base plate 4 and the lower surface 3b of the end portion of the wiring board 3 in the long side direction approach each other (see the arrow in FIG. 9), and as shown in FIG. It solidifies in a state of being filled with the wiring 3ba of the substrate 3.

As a result of the above steps, in the semiconductor device 10 of the first embodiment, the end portion A2 of the wiring board 3 is finally fixed in a convex shape (warped) toward the upper surface 3a in a plan view. On the other hand, the central portion A1 of the wiring board 3 becomes flat. In other words, the (closest) distance between the upper surface 3a of the wiring board 3 and the lower surface 3b of the wiring board 3 is substantially constant between the central portion A1 of the wiring board 3 and the end portion A2 of the wiring board 3, while The (closest) distance between the lower surface 3b of the end portion A2 of 3 and the upper surface of the base plate 4 is shorter than the (closest) distance between the lower surface 3b of the central portion A1 of the wiring board 3 and the upper surface of the base plate 4.

After that, although not shown, a step of connecting the semiconductor chip 1 and the wirings 3aa and 3ac of the wiring board 3 with the wires 6 (a wire bonding step), a step of connecting the terminals 7 to the wirings 3aa, and a case 8 are attached to the base plate 4. The semiconductor device 10 of the first embodiment is completed through the steps, the step of filling the region surrounded by the upper surface of the base plate 4 and the case 8 with the resin 11, and the like.

In the method of manufacturing the semiconductor device according to the first embodiment, as shown in FIGS. 6 and 7, when the semiconductor chip 1 and the wiring board 3 are joined, the lower surface of the semiconductor chip 1 and the long side of the wiring board 3 are joined. When the wiring board 3 and the base plate 4 are joined to each other, the upper surface 3a of the direction end approaches the upper surface 3a of the direction end, and the upper surface of the base board 4 and the long side direction end portion of the wiring board 3 are bonded to each other, as shown in FIGS. It is important that the lower surface 3b approaches. Therefore, as long as these conditions are satisfied, the process is not limited to the above process.

As an example, in addition to the semiconductor chip 1, the bonding material 2 and the wiring board 3 shown in FIG. 6, the bonding material 5 and the base plate 4 are also prepared and these are cooled at the same time. In this case, the melting point of the material forming the bonding material 5 is set lower than the melting point of the material forming the bonding material 2. By doing so, when the molten bonding materials 2 and 5 are cooled at the same rate, the bonding material 2 solidifies first, so that the solidification of the bonding material 2 proceeds in the semiconductor chip 1 and the wiring board 3. Accordingly, the state of FIG. 6 changes to the state of FIG. On the other hand, while the bonding material 2 is solidifying, the bonding material 5 is maintained in a molten state. Subsequent steps are as shown in FIGS. 9 and 10. In this way, the semiconductor chip bonding process (S1) and the base plate bonding process (S2) can be performed as one process, and the semiconductor device manufacturing process can be simplified.

<Background of the study>
Hereinafter, the semiconductor device (power module) of the first study example (hereinafter, study example 1) examined by the present inventor will be described. FIG. 11 is a cross-sectional view of an essential part showing the structure of the semiconductor device of Study Example 1, and FIG. 12 is a plan view of the essential part showing the structure of the semiconductor device of Study Example 1. Note that FIG. 11 is a cross-sectional view of the main parts as seen from the direction B in FIG. FIG. 13 is a cross-sectional view of essential parts in the process of manufacturing the semiconductor device of Study Example 1, and shows a cross section corresponding to FIG. 11. FIG. 14 is a cross-sectional view of essential parts in a manufacturing process of a semiconductor device of a second study example (hereinafter, study example 2) described later. FIG. 15 is a schematic diagram showing the appearance of the sink mark formed in the bonding material in the semiconductor devices of Study Example 1 and Study Example 2.

The semiconductor device 100 of the study example 1 shown in FIGS. 11 and 12 is similar to the semiconductor device 10 of the first embodiment shown in FIG. 1, and includes a plurality of semiconductor chips 1 and a wiring substrate 3 supporting the semiconductor chips 1. It has a base plate 4 that supports the wiring board 3.

However, in the semiconductor device 100 of Study Example 1, the plurality of semiconductor chips 1 are not the end portion (end portion in the long side direction) A2 of the wiring substrate 3 in plan view but the central portion (in the long side direction) of the wiring substrate 3. The semiconductor device 10 is arranged in the central portion A1 and this point is a difference from the semiconductor device 10 of the first embodiment. Note that, in FIGS. 11 and 12, the wire 6, the terminal 7, the case 8, the resin 11 and the like are omitted for simplicity of description. Although four semiconductor chips are shown in FIG. 12, the number of semiconductor chips is not particularly limited.

Here, the problem found by the present inventor in Study Example 1 will be described. As described above, the present inventor is considering improving the bonding between the wiring substrate and the semiconductor chip or the bonding between the wiring substrate and the base plate in the power module.

The wiring board 3 of Study Example 1 has wirings 3ca, 3cb, 3cc provided on the upper surface 3a side and a wiring 3d provided on the lower surface 3b side. Generally, the material forming the wirings 3ca, 3cb, 3cc on the upper surface 3a side is the same as the material forming the wiring 3d on the lower surface 3b side, and the thickness of the wirings 3ca, 3cb, 3cc is It is the same as the thickness of the wiring 3d.

Here, the wiring on the upper surface 3a side of the wiring board 3 is configured as wirings 3ca, 3cb, 3cc by partially removing it by etching or the like to form a circuit. On the other hand, the wiring 3d on the lower surface 3b side of the wiring board 3 is for joining with the base plate 4, and thus is not etched or the like. Therefore, in Study Example 1, since the volume of the wiring 3d is larger than the volume of the wirings 3ca, 3cb, 3cc, when the wiring board 3 is heated, the thermal expansion amount of the wiring 3d is 3ca, 3cb, 3cc. Is greater than the thermal expansion amount of. As a result, as shown in FIG. 13, when the wiring board 3 is heated, the wiring board 3 is deformed into a convex shape toward the upper surface 3a side of the wiring board 3.

First, the aforementioned semiconductor chip joining step (S1) will be examined. As shown in FIG. 13, after the wiring board 3 is heated, the bonding material 2 is arranged on the wiring 3cb on the upper surface 3a side of the wiring board 3 and the bonding material 2 is melted. Further, the semiconductor chip 1 is mounted on the molten bonding material 2. At this time, the semiconductor chip 1 is arranged in the central portion A1 in the long side direction of the wiring board 3 in a plan view.

After that, when the semiconductor chip 1 and the wiring board 3 are cooled, the melted bonding material 2 starts to solidify. At the same time, since the amount of heat shrinkage of the wiring 3d on the lower surface 3b side of the wiring board 3 is larger than the amount of heat shrinkage of the wiring 3cb on the upper surface 3a side of the wiring board 3, the warped wiring board 3 tends to become flat. As a result, the bonding material 2 is solidified while the lower surface of the semiconductor chip 1 and the upper surface 3a of the central portion of the wiring board 3 in the long side direction are separated (see the arrow in FIG. 13). Since the bonding material 2 shrinks while solidifying, as shown in FIG. 15, a local bonding material shortage occurs between the lower surface of the semiconductor chip 1 and the upper surface 3a of the wiring board 3 at the central portion in the long side direction, so that the bonding material A sink mark portion 101, which is a defective joint portion, which is open to the outside, is formed in the material 2. If such a sink portion 101 is present in the bonding material 2, it causes a decrease in heat dissipation of the heat generated in the semiconductor chip 1 and a void in the sealing resin, which causes deterioration of the characteristics as a power module.

Therefore, the present inventor studied the semiconductor device of Study Example 2 in order to solve the problem of the semiconductor device of Study Example 1. Like the wiring board 3 of the first embodiment, the wiring board 3 of Examination Example 2 employs a wiring board 3 that, when heated, is deformed into a convex shape toward the upper surface 3a side of the wiring board 3. .. Specifically, when the material forming the wirings 3ca, 3cb, 3cc on the upper surface 3a side of the wiring board 3 and the material forming the wiring 3d on the lower surface 3b side of the wiring board 3 are the same, the upper surface 3a side of the wiring board 3 The thickness of the wirings 3ca, 3cb, 3cc is set to be thicker than the thickness of the wiring 3d on the lower surface 3b side of the wiring board 3. Alternatively, when the thickness of the wirings 3ca, 3cb, 3cc on the upper surface 3a side of the wiring board 3 is the same as the thickness of the wiring 3d on the lower surface 3b side of the wiring board 3, the material forming the wirings 3ca, 3cb, 3cc The linear expansion coefficient is made larger than the linear expansion coefficient of the material forming the wiring 3d.

First, in the semiconductor chip bonding step (S1), as shown in FIG. 14, the bonding material 2 is arranged on the wiring 3cb on the upper surface 3a side of the heated wiring substrate 3, and the semiconductor chip is melted on the bonding material 2. Place 1

After that, when the semiconductor chip 1 and the wiring board 3 are cooled, the melted bonding material 2 starts to solidify. At the same time, since the amount of heat shrinkage of the wiring 3d on the lower surface 3b side of the wiring board 3 is larger than the amount of heat shrinkage of the wiring 3cb on the upper surface 3a side of the wiring board 3, the warped wiring board 3 tends to become flat. As a result, in Study Example 2, the lower surface of the semiconductor chip 1 and the upper surface 3a of the central portion of the wiring substrate 3 in the long-side direction approach each other (see the arrow in FIG. 14), and the bonding material 2 is used as in the first embodiment. Solidifies in a state of being filled between the semiconductor chip 1 and the wiring 3cb of the wiring board 3.

Next, in the base plate bonding step (S2), the bonding material 5 is arranged on the upper surface of the base plate 4, and the wiring board 3 is arranged on the melted bonding material 5.

Then, as the base plate 4 and the wiring board 3 are cooled, the melted bonding material 5 begins to solidify. At the same time, since the amount of heat shrinkage of the wiring 3d on the lower surface 3b side of the wiring board 3 is larger than the amount of heat shrinkage of the wiring 3cb on the upper surface 3a side of the wiring board 3, the warped wiring board 3 tends to become flat. As a result, in Study Example 2, the bonding material 5 is solidified while the upper surface of the base plate 4 and the lower surface 3b of the end portion in the long side direction of the wiring board 3 are separated (see the arrow in FIG. 14). Since the bonding material 5 shrinks while solidifying, as shown in FIG. 15, a local bonding material shortage occurs between the upper surface of the base plate 4 and the lower surface 3b at the central portion in the long side direction of the wiring board 3, and the bonding material 5 is bonded. The material 5 is provided with a sink portion 101 that is a defective joint portion and is open to the outside. If such a sink portion 101 is present in the bonding material 5, it causes a decrease in heat dissipation of the heat transferred from the semiconductor chip 1 to the wiring board 3 and causes voids in the sealing resin, which deteriorates the characteristics of the power module. Cause.

Therefore, in the semiconductor device of Study Example 2, the problem of the semiconductor device of Study Example 1 in the semiconductor chip joining step (S1) is solved, while another problem in the base plate joining step (S2) is solved. Will occur. As shown in FIG. 13, in the semiconductor device of Study Example 1, in the base plate bonding step (S2), the upper surface of the base plate 4 and the lower surface 3b of the long-side end of the wiring board 3 approach each other. However, since the bonding material 5 is solidified (see the arrow in FIG. 13), the problem of the semiconductor device of Study Example 2 does not occur.

From the above, in the semiconductor devices of Study Example 1 and Study Example 2, the formation of the sink portion 101 of the bonding material 2 existing between the semiconductor chip 1 and the wiring board 3 and the gap between the wiring board 3 and the base plate 4 It is not possible to prevent the formation of the sink mark portion 101 of the bonding material 5 existing in the above at the same time. Therefore, there is a demand for a semiconductor device that can prevent the formation of the sink mark portion 101 in the bonding materials 2 and 5 and improve the reliability of the semiconductor device, and a manufacturing method thereof.

<Main Features and Effects of First Embodiment>
One of the characteristics of the semiconductor device 10 according to the first embodiment shown in FIGS. 1 to 3 is that a plurality of semiconductor chips 1 are arranged at an end (long side direction end) A2 of the wiring board 3 in a plan view. That is what is being done. The end portion (end portion in the long side direction) A2 of the wiring board 3 is fixed in a shape that is convex (warped) toward the upper surface (first surface) 3a side of the wiring board 3, while being fixed. The central part (longitudinal direction central part) A1 of 3 is flat. Alternatively, the wiring board 3 is deformed (warped) into a shape that is convex toward the semiconductor chip mounting surface (upper surface) 3a side when heated.

Further, the semiconductor chip 1 and the wiring board 3 are bonded via a bonding material (first bonding material) 2, and the wiring board 3 and the base plate 4 are bonded via a bonding material (second bonding material) 5. Then, the bonding materials 2 and 5 are made of a material which is melted to form an intermetallic compound at the interface with the material to be bonded and bonded.

One of the features of the method of manufacturing the semiconductor device according to the first embodiment shown in FIGS. 4 to 10 is that the wiring board 3 is heated in the semiconductor chip bonding step (S1), and the wiring board 3 is mounted on the semiconductor chip mounting surface ( (Upper surface) 3a, a step of deforming to a convex shape, the wiring board 3 is cooled, the lower surface of the semiconductor chip 1 and the upper surface 3a of the long side end A2 of the wiring board 3 are brought close to each other, and And the step of solidifying the bonding material 2. Then, in the base plate bonding step (S2), a step of heating the wiring board 3 to deform the end portion A2 of the wiring board 3 into a convex shape toward the base plate bonding surface (lower surface) 3b side; 3 is cooled, the upper surface of the base plate 4 and the lower surface 3b at the end portion in the long side direction of the wiring board 3 are brought close to each other, and the bonding material 5 is solidified.

In the present embodiment, by adopting such a configuration and manufacturing method, it is possible to prevent the formation of the sink mark portion 101 in the bonding materials 2 and 5 in the power module and improve the reliability of the semiconductor device. The reason will be specifically described below.

As described above, in the semiconductor devices of Study Example 1 and Study Example 2, the formation of the sink portion 101 of the bonding material 2 existing between the semiconductor chip 1 and the wiring board 3, the wiring board 3, and the base plate 4 are formed. It is not possible to prevent the formation of the sink mark portion 101 of the bonding material 5 existing between the gaps at the same time.

Therefore, in the semiconductor device 10 according to the first embodiment, the wiring board 3 employs the wiring board 3 that is deformed to be convex toward the semiconductor chip mounting surface (upper surface) 3a when heated. Specifically, the material forming the wirings 3aa, 3ab, 3ac on the upper surface 3a side of the wiring board 3 and the material forming the wiring 3ba on the lower surface 3b side of the wiring board 3 are the same, and The thickness of the wirings 3aa, 3ab, 3ac on the upper surface 3a side is thicker than the thickness of the wiring 3ba on the lower surface 3b side of the wiring board 3. Alternatively, the thickness of the wirings 3aa, 3ab, 3ac on the upper surface 3a side of the wiring board 3 is the same as the thickness of the wiring 3ba on the lower surface 3b side of the wiring board 3, and the material forming the wirings 3aa, 3ab, 3ac Is larger than the linear expansion coefficient of the material forming the wiring 3ba. By doing so, as shown in FIGS. 6 and 7, when the semiconductor chip 1 and the wiring board 3 are joined, the lower surface of the semiconductor chip 1 and the upper surface 3a of the end portion of the wiring board 3 can be brought close to each other. .. As a result, there is no shortage of bonding material between the lower surface of the semiconductor chip 1 and the upper surface 3a at the end of the wiring board 3.

In the semiconductor device 10 according to the first embodiment, the plurality of semiconductor chips 1 are arranged at the end portion (end portion in the long side direction) A2 of the wiring board 3 in plan view. Since the linear expansion coefficient of the main material forming the semiconductor chip 1 is smaller than the linear expansion coefficient of the material forming the wirings 3ab and 3ba, by placing the semiconductor chip 1 at the end of the wiring board 3, the wiring board 3 It is possible to control the deformation of the ends of the. Specifically, as shown in FIGS. 9 and 10, the upper surface of the base plate 4 and the lower surface 3b at the end of the wiring board 3 are brought close to each other when the wiring board 3 and the base plate 4 are joined. You can As a result, there is no shortage of bonding material between the upper surface of the base plate 4 and the lower surface 3b at the end of the wiring board 3.

As described above, in the semiconductor device 10 of the first embodiment, the formation of the sink portion 101 of the bonding material 2 existing between the semiconductor chip 1 and the wiring board 3 and the gap between the wiring board 3 and the base plate 4 are performed. It is possible to prevent the formation of the sink mark portion 101 of the bonding material 5 existing at the same time, and it is possible to improve the reliability of the semiconductor device.

In particular, of the wiring board 3, the end portion A2 of the wiring board 3 is fixed in a convex shape toward the upper surface (first surface) 3a side in a plan view, while the central portion A1 of the wiring board 3 is fixed. Is flat, the adhesiveness between the wiring board 3 and the base plate 4 is enhanced as compared with the case where the entire wiring board 3 is convex (warped) toward the upper surface (first surface 3a) side. be able to.

In particular, in the semiconductor device 10 of the first embodiment, the plurality of semiconductor chips 1 include silicon carbide switching elements, the wiring substrate 3 is a ceramic substrate, and the bonding materials 2 and 5 are solders containing tin as a main component. In such a case, the semiconductor device 10 will be used in a high temperature environment. Therefore, since the semiconductor device 10 has the above-described characteristics, it is possible to provide the semiconductor device 10 that can withstand the operational stability under a high temperature environment and a high current load.

Further, in the semiconductor device of the first embodiment, one of the sides of each of the plurality of semiconductor chips 1 is arranged along the peripheral edge of wiring board 3. By doing so, as shown in FIGS. 9 and 10, when the wiring board 3 and the base plate 4 are joined together, the upper surface of the base board 4 and the lower surface 3b of the end portion of the wiring board 3 are surely brought close to each other. You can

Further, in the semiconductor device of the first embodiment, the semiconductor chip 1 is arranged at the end of the wiring board 3 in the long side direction in plan view. When the wiring board 3 is formed in a rectangular shape in a plan view, it is considered that the deformation amount at the long side direction end portion is larger than the deformation amount at the short side direction end portion. Therefore, in the semiconductor device of the first embodiment, it is possible to reliably prevent a shortage of the bonding material between the upper surface of the base plate 4 and the lower surface 3b at the end portion in the long side direction of the wiring board 3.

<Modification>
A semiconductor device of a modified example of the first embodiment will be described with reference to FIG. FIG. 16 is a plan view of relevant parts of a semiconductor device of a modification. In addition, in FIG. 16, the wire 6, the terminal 7, the case 8, the resin 11, and the like are omitted for simplification of description. Further, although eight semiconductor chips are shown in FIG. 16, the number of semiconductor chips is not particularly limited.

In the semiconductor device 15 of the modified example, the plurality of semiconductor chips 1 are common to the semiconductor device 10 of the first embodiment in that they are arranged at the end portions of the wiring board 3 in a plan view. However, in the semiconductor device 15 of the modified example, the plurality of semiconductor chips 1 are not limited to the long side (longitudinal direction, length direction) end portion A2 of the wiring board 3 but also the short side direction (short side) of the wiring board 3. Direction, width direction) is different from the first embodiment in that it is also arranged at the end portion.

Further, as shown in FIG. 16, in the semiconductor device 15 of the modified example, wirings 3ea, 3eb, 3ec are formed on the upper surface of the wiring board 3, and each of the wiring board 3 of the first embodiment shown in FIG. It corresponds to the wirings 3aa, 3ab, 3ac formed on the upper surface 3a. This shows an example in which the wiring layout is changed in order to arrange the semiconductor chip 1 at the end portion of the wiring board 3 in a plan view.

The other configuration of the semiconductor device 15 of the modified example is basically the same as the configuration of the semiconductor device 10 of the first embodiment, and therefore the repeated description is omitted. The method of manufacturing the semiconductor device of the modified example is also basically the same as the method of manufacturing the semiconductor device of the first embodiment, and therefore, repeated description will be omitted.

In the semiconductor device 15 of the modified example, as in the first embodiment, the plurality of semiconductor chips 1 are arranged at the end portions of the wiring board 3 in plan view. It is possible to prevent the sink mark portion 101 from being formed in the semiconductor device and improve the reliability of the semiconductor device. In particular, in the modified example, the semiconductor chip 1 is also arranged in the short side direction end portion of the wiring board 3 in a plan view, so that the upper surface of the base plate 4 and the long side direction end portion of the wiring board 3. Not only the lower surface 3b of the base plate 4 but also the upper surface of the base plate 4 and the lower surface 3b at the end portion in the short side direction of the wiring board 3 can be prevented from being insufficient. In this respect, the modified example is more advantageous than the first embodiment.

(Embodiment 2)
The semiconductor device of the second embodiment will be described with reference to FIG. FIG. 17 is a main-portion cross-sectional view of the semiconductor device in Embodiment 2. Note that FIG. 17 corresponds to a cross-sectional view of a main part as seen from the direction C in FIG.

As shown in FIG. 17, in the semiconductor device 20 of the second embodiment, the wiring board 3 has the wirings 3fa, 3fb, 3fc formed on the upper surface 3a and the wiring 3g including the wirings 3ga, 3gb, 3gc on the lower surface 3b. Has been formed. The wirings 3fb and 3gb are arranged in the central portion of the wiring board 3 in a plan view. The wiring (first portion) 3fb overlaps the wiring (third portion) 3gb in plan view. On the other hand, the wirings 3fa, 3fc, 3ga, 3gc are arranged at the end portions of the wiring board 3 in a plan view. The wirings (second portions) 3fa and 3fc overlap the wirings (fourth portions) 3ga and 3gc in a plan view.

In particular, the thickness of the wiring (first portion) 3fb on the upper surface 3a side of the wiring board 3 is thicker than the thickness of the wiring (third portion) 3gb on the lower surface 3b side. Further, the thickness of the wiring (second portion) 3ga, 3gc on the lower surface 3b side of the wiring board 3 is larger than the thickness of the wiring 3fa, 3fc overlapping the wiring (fourth portion) 3ga, 3gc on the upper surface 3a side in plan view. Too thick.

The plurality of semiconductor chips 1 are arranged on the wiring (first portion) 3fb on the upper surface 3a side with the bonding material 2 interposed therebetween. In particular, the plurality of semiconductor chips 1 are arranged along the peripheral edge (outermost peripheral edge) of the wiring 3fb.

The above-described configuration of the second embodiment is the difference from the semiconductor device 100 of Study Example 1. The materials forming the wirings 3fa, 3fb, 3fc, 3g are the same.

As shown in FIG. 17, in the semiconductor device 20 of the second embodiment, the configuration other than the wiring board 3 is the same as that of the semiconductor device 100 of the study example 1 shown in FIGS. The repeated description is omitted.

In the second embodiment, in plan view, the thickness of the wiring 3fb on the upper surface 3a side of the central portion of the wiring board 3 is made thicker than the thickness of the wiring 3gb on the lower surface 3b side of the wiring board 3. The thermal expansion amount of the wiring 3fb is larger than the thermal expansion amount of the wiring 3gb. As a result, the central portion of the wiring board 3 is deformed into a shape that is convex toward the semiconductor chip mounting surface (upper surface) 3a side of the wiring board 3 when heated.

On the other hand, in the second embodiment, in plan view, the thickness of the wirings 3ga and 3gc on the lower surface 3b side of the end portion of the wiring board 3 is equal to the thicknesses of the wirings 3fa and 3fc on the upper surface 3a side of the wiring board 3, respectively. By making the thickness thicker than this, the thermal expansion amount of the wirings 3ga and 3gc becomes larger than the thermal expansion amount of the wirings 3fa and 3fc. As a result, the end portion of the wiring board 3 is deformed into a shape that is convex toward the base plate bonding surface (lower surface) 3b side of the wiring board 3 when heated.

By doing so, in the semiconductor device 20 of the second embodiment, the lower surface of the semiconductor chip 1 and the upper surface 3a of the end portion of the wiring board 3 can be brought close to each other when the semiconductor chip 1 and the wiring board 3 are joined. In addition, the upper surface of the base plate 4 and the lower surface 3b at the end of the wiring board 3 can be brought close to each other when the wiring board 3 and the base board 4 are joined. As a result, similarly to the first embodiment, in the power module, formation of the sink portion 101 in the bonding materials 2 and 5 can be prevented, and the reliability of the semiconductor device can be improved. In particular, the second embodiment is more advantageous than the first embodiment in that the layout of the semiconductor chip 1 in plan view is not limited and the degree of freedom in layout is increased.

(Application example)
18 is a partial side view showing an example of a railway vehicle equipped with the semiconductor device shown in FIG. 1, and FIG. 19 is a plan view showing an example of the internal structure of the inverter installed in the railway vehicle shown in FIG.

In this application example, a railway vehicle equipped with the semiconductor device 10 of the first embodiment (or the semiconductor device 15 of the modified example, the semiconductor device 20 of the second embodiment, and the same applies hereinafter) will be described. A railroad vehicle 21 shown in FIG. 18 includes, for example, the semiconductor device 10 shown in FIG. 1 mounted therein, and includes a vehicle body 26, the semiconductor device 10, a mounting member that supports the semiconductor device 10, and a current collector. It has a certain pantograph 22 and an inverter 23. The semiconductor device 10 is mounted on the inverter 23 installed in the lower portion of the vehicle body 26.

As shown in FIG. 19, inside the inverter 23, a plurality of semiconductor devices 10 are mounted on a printed circuit board (mounting member) 25, and a cooling device 24 that cools these semiconductor devices 10 is also mounted. In the semiconductor device 10 of the present embodiment shown in FIG. 1, the amount of heat generated from the semiconductor chip 1 is large. Therefore, the cooling device 24 is attached so that the plurality of semiconductor devices 10 can be cooled to cool the inside of the inverter 23.

Here, according to this application example (an example in which the semiconductor device 10 is applied to the railway vehicle 21), the wiring board 3 and the semiconductor chip 1 are joined, or the wiring board 3 and the base plate (heat sink) 4 are joined. It is possible to improve the joint reliability of these joints. As a result, the resistance of the inverter 23 to the high temperature environment is increased, so that the cooling function for the inverter 23 can be simplified, and the cooling device 24 can be downsized, and in turn, the inverter 23 can be downsized.

As a result, since the railcar 21 is provided with the inverter 23 having the plurality of semiconductor devices 10 shown in FIG. 1, the inverter 23 and the inverter 23 The reliability of the provided railway vehicle 21 can be improved. That is, it is possible to realize the semiconductor device 10 that can withstand operation stability under a high temperature environment and a high current load, and an inverter system using the same.

Next, an automobile equipped with the semiconductor device 10 of the above embodiment will be described. 20 is a perspective view showing an example of an automobile in which the semiconductor device shown in FIG. 1 is mounted.

An automobile 27 shown in FIG. 20, for example, has the semiconductor device 10 shown in FIG. 1 mounted therein, and has a vehicle body 28, tires 29, semiconductor device 10, and a mounting unit that is a mounting member that supports the semiconductor device 10. 30 are provided.

In the automobile 27, the semiconductor device 10 is mounted on an inverter included in the mounting unit 30, and the mounting unit 30 is, for example, an engine control unit. In that case, the mounting unit 30 is arranged near the engine. ing. In this case, the mounting unit 30 is used in a high temperature environment, and the semiconductor device 10 is also in a high temperature state.

Here, according to this application example (example in which the semiconductor device 10 is applied to the automobile 27), as in the application example to the railroad vehicle 21, the wiring substrate 3 and the semiconductor chip 1 are bonded or the wiring substrate 3 is connected. Bonding with the base plate (heat sink) 4 can be improved, and the bonding reliability of these bonding portions can be improved.

As a result, since the vehicle 27 is provided with the inverter mounting the plurality of semiconductor devices 10 shown in FIG. 1, the reliability of the vehicle 27 is improved even when the mounting unit 30 is in a high temperature environment. be able to. That is, also in the automobile 27, it is possible to realize the semiconductor device 10 that can withstand the operational stability under a high temperature environment and a high current load, and the inverter system using the same.

Although the invention made by the inventor has been specifically described based on the embodiment, the invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

In addition, what corresponds to the contents described in the embodiments or a part thereof will be described below.

[Appendix 1]
A wiring board having a first surface and a second surface opposite to the first surface;
A first wiring formed on the first surface of the wiring board;
Second wiring formed on the second surface of the wiring board;
A plurality of semiconductor chips mounted on the first wiring via a first bonding material;
A base plate that is joined to the second wiring via a second joining material and supports the wiring board;
Have
The plurality of semiconductor chips are arranged at an end portion of the wiring board in a plan view,
In a plan view, the distance between the first surface of the wiring board and the second surface of the wiring board is substantially constant between the central portion of the wiring board and the end portion of the wiring board, while the wiring A distance between the second surface of the wiring board and the base plate at the end portion of the board is shorter than a distance between the second surface of the wiring board and the base plate at the central portion of the wiring board; Semiconductor device.

[Appendix 2]
In the semiconductor device according to attachment 1,
Each of the plurality of semiconductor chips is formed in a rectangular shape in plan view,
A semiconductor device in which one of the sides of each of the plurality of semiconductor chips is arranged along a peripheral edge of the wiring board.

[Appendix 3]
In the semiconductor device according to attachment 1,
The wiring board is formed in a rectangular shape in plan view,
The semiconductor device, wherein the plurality of semiconductor chips are arranged at end portions in the long side direction of the wiring board in a plan view.

[Appendix 4]
In the semiconductor device according to attachment 1,
A semiconductor device installed in an inverter installed in a railway vehicle.

[Appendix 5]
In the semiconductor device according to attachment 1,
A semiconductor device installed in an inverter installed in the body of an automobile.

[Appendix 6]
A wiring board having a first surface and a second surface opposite to the first surface;
A first wiring formed on the first surface of the wiring board;
Second wiring formed on the second surface of the wiring board;
A plurality of semiconductor chips mounted on the first wiring via a first bonding material;
A base plate that is joined to the second wiring via a second joining material and supports the wiring board;
Have
The first wiring includes a first portion arranged at a central portion of the wiring board and a second portion arranged at an end portion of the wiring board in a plan view,
The second wiring includes a third portion overlapping with the first portion in a plan view, and a fourth portion overlapping with the second portion in a plan view,
The plurality of semiconductor chips are arranged along a peripheral edge of the first portion,
The semiconductor device, wherein the thickness of the first portion is thicker than the thickness of the third portion, and the thickness of the fourth portion is thicker than the thickness of the second portion.

[Appendix 7]
In the semiconductor device according to attachment 6,
Each of the plurality of semiconductor chips is formed in a rectangular shape in plan view,
The semiconductor device, wherein one of the sides of each of the plurality of semiconductor chips is arranged along the peripheral edge of the first portion.

1 Semiconductor Chip 2, 5 Bonding Material 3 Wiring Board 4 Base Plate 6 Wire 7 Terminal 8 Case 10, 15, 20, 100 Semiconductor Device 11 Resin 21 Railway Vehicle 27 Automotive

Claims (15)

A wiring board having a first surface and a second surface opposite to the first surface;
A first wiring formed on the first surface of the wiring board;
Second wiring formed on the second surface of the wiring board;
A plurality of semiconductor chips mounted on the first wiring via a first bonding material;
A base plate that is joined to the second wiring via a second joining material and supports the wiring board;
Have
The plurality of semiconductor chips are arranged at an end portion of the wiring board in a plan view,
Of the wiring board, in plan view, the end portion of the wiring board is fixed in a shape that is convex toward the first surface side, while the central portion of the wiring board is flat. Semiconductor device. The semiconductor device according to claim 1,
Each of the plurality of semiconductor chips is formed in a rectangular shape in plan view,
A semiconductor device in which one of the sides of each of the plurality of semiconductor chips is arranged along a peripheral edge of the wiring board. The semiconductor device according to claim 1,
The wiring board is formed in a rectangular shape in plan view,
The semiconductor device, wherein the plurality of semiconductor chips are arranged at end portions in the long side direction of the wiring board in a plan view. The semiconductor device according to claim 1,
The plurality of semiconductor chips includes a silicon carbide switching element,
The wiring board is a ceramic substrate,
The semiconductor device in which the first bonding material and the second bonding material are solders containing tin as a main component. The semiconductor device according to claim 1,
A semiconductor device installed in an inverter installed in a railway vehicle. The semiconductor device according to claim 1,
A semiconductor device installed in an inverter installed in the body of an automobile. A wiring board having a first surface and a second surface opposite to the first surface;
A first wiring formed on the first surface of the wiring board;
Second wiring formed on the second surface of the wiring board;
A plurality of semiconductor chips mounted on the first wiring via a first bonding material;
A base plate that is joined to the second wiring via a second joining material and supports the wiring board;
Have
The plurality of semiconductor chips are arranged at an end portion of the wiring board in a plan view,
The semiconductor device, wherein the wiring board is deformed into a shape that is convex toward the first surface side when heated. The semiconductor device according to claim 7,
A semiconductor device in which a linear expansion coefficient of a main material forming the plurality of semiconductor chips is smaller than a linear expansion coefficient of a material forming the first wiring and a linear expansion coefficient of a material forming the second wiring. The semiconductor device according to claim 7,
The semiconductor device, wherein the thickness of the first wiring is thicker than the thickness of the second wiring. The semiconductor device according to claim 7,
A semiconductor device in which a linear expansion coefficient of a material forming the first wiring is larger than a linear expansion coefficient of a material forming the second wiring. (A) a step of heating a wiring board having a first surface and a second surface located on the opposite side of the first surface to deform the wiring board into a convex shape toward the first surface side;
(B) a step of disposing a first bonding material on the first wiring formed on the first surface of the wiring board and melting the first bonding material;
(C) a step of disposing a plurality of semiconductor chips on the first bonding material arranged at an end portion of the wiring board in a plan view,
(D) cooling the wiring board, bringing the lower surfaces of the plurality of semiconductor chips close to the first surface of the end portion of the wiring board, and solidifying the first bonding material;
(E) a step of heating the wiring board to deform the end portion of the wiring board into a convex shape toward the second surface side;
(F) disposing a second bonding material on the base plate and melting the second bonding material,
(G) disposing the wiring board on the second bonding material so that the second wiring formed on the second surface of the wiring board contacts the second bonding material,
(H) cooling the wiring board, bringing the upper surface of the base plate and the second surface of the end portion of the wiring board close to each other, and solidifying the second bonding material;
A method for manufacturing a semiconductor device, comprising: The method of manufacturing a semiconductor device according to claim 11,
The linear expansion coefficient of the main material forming the plurality of semiconductor chips is smaller than the linear expansion coefficient of the material forming the first wiring and the linear expansion coefficient of the material forming the second wiring,
In the step (d), the first wiring at the end of the wiring board and the plurality of semiconductor chips are integrated with each other,
In the step (e), when the wiring board is heated, the end portion of the wiring board is deformed into a shape protruding toward the second surface side. The method of manufacturing a semiconductor device according to claim 11,
The thickness of the first wiring is thicker than the thickness of the second wiring,
In the step (a), when the wiring board is heated, the wiring board is deformed into a convex shape toward the first surface side. The method of manufacturing a semiconductor device according to claim 11,
The linear expansion coefficient of the material forming the first wiring is larger than the linear expansion coefficient of the material forming the second wiring,
In the step (a), when the wiring board is heated, the wiring board is deformed into a convex shape toward the first surface side. The method of manufacturing a semiconductor device according to claim 11,
A method of manufacturing a semiconductor device, wherein a melting point of a material forming the first bonding material is higher than a melting point of a material forming the second bonding material.

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