JP2017103290A - Semiconductor device, manufacturing method thereof, power module, and vehicle - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which has high reliability under a high-temperature environment.SOLUTION: In a semiconductor device, a bonding part of a member 1 to be bonded and a semiconductor chip 4 includes: a plurality of porous metal layers 2 formed and spaced apart from one another on a top face of a chip-mount part 1b of the member 1 to be bonded; an intermetallic compound layer 8 made of a Cu-Sn compound and formed in contact with an Ni electrode 5 on the backside of the semiconductor chip 4; and an intermetallic compound layer 9 interposed between the top face of the chip-mount part 1b and the intermetallic compound layer 8, and including Sn as a primary component. The chip-mount part 1b is a member having a Cu film on its surface, or a member having, on its surface, a Cu film plated with Ag, Au or Ni. In addition, the plurality of porous metal layers 2 are each a porous layer including Ag, Cu, or Ag and Cu.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a semiconductor device, a manufacturing method thereof, a power module, and a vehicle.

  As background arts in this technical field, there are JP-A-2008-300792 (Patent Document 1) and JP-A-2015-082581 (Patent Document 2).

  Japanese Patent Application Laid-Open No. 2008-300792 (Patent Document 1) discloses a base layer formed by curing a metal particle paste at a high temperature and a layer of a high temperature metal brazing material formed by dispersing and absorbing metal particles in a low temperature metal brazing material. A semiconductor device is described in which the back side of the semiconductor chip and the copper wiring pattern are joined by a joining layer constituted by:

  Japanese Patent Laying-Open No. 2015-082581 (Patent Document 2) discloses a sintered metal layer of fine particles containing at least a first metal, a solidified metal layer containing at least a second metal, a sintered metal layer and a solidified metal. A power semiconductor device including a diffusion metal layer including at least a first metal and a second metal interposed between layers is described.

JP 2008-300792 A Japanese Patent Laying-Open No. 2015-082581

  One method of joining a member to be joined and a semiconductor chip is to react Sn-based solder with a metal particle paste containing nano- or micro-level metal particles to form a joint between the member to be joined and the semiconductor chip. There is a method of using a high melting point intermetallic compound.

  However, if the bonding portion between the member to be bonded and the semiconductor chip does not completely become an intermetallic compound and Sn having a low melting point remains, the heat resistance of the bonding portion may deteriorate.

  On the other hand, when the joint portion between the member to be joined and the semiconductor chip is completely an intermetallic compound, the intermetallic compound is brittle, and therefore, when a large impact is applied to the joint portion, the joint portion may be destroyed at once.

  In Patent Document 1 and Patent Document 2, consideration is not given to the nature of such an intermetallic compound.

  In order to solve the above problems, a semiconductor device according to the present invention includes a member to be bonded, a semiconductor chip, and a bonding portion that bonds the member to be bonded and the semiconductor chip. The bonding portion includes a plurality of porous metal layers formed on the upper surface of the chip mounting portion of the member to be bonded, and a Cu—Sn compound formed in contact with the Ni electrode on the back surface of the semiconductor chip. And a second layer made of an intermetallic compound containing Sn as a main component and covering the plurality of porous metal layers and interposed between the upper surface of the chip mounting portion and the first layer; Have.

  According to the present invention, a semiconductor device having high reliability in a high temperature environment can be provided.

  Problems, configurations, and effects other than those described above will be clarified by the following description of embodiments.

BRIEF DESCRIPTION OF THE DRAWINGS It is sectional drawing which shows the semiconductor device by Example 1, (a) is sectional drawing explaining the aspect of the semiconductor device before heat processing, (b) is sectional drawing explaining the aspect of the semiconductor device after heat processing. It is sectional drawing which expands and shows a part of junction part of the to-be-joined member and semiconductor chip by Example 1. FIG. FIG. 5 is an enlarged cross-sectional photograph showing a part of a bonded portion between a member to be bonded and a semiconductor chip when one porous metal layer is formed on the upper surface of a chip mounting portion without dividing the porous metal layer. . The cross section which expands and shows a part of joining part of a to-be-joined member and a semiconductor chip in the case where a porous metal layer is divided and a plurality of porous metal layers are formed apart from each other on the upper surface of the chip mounting part It is a photograph. FIG. 3 is a plan view showing a first arrangement example of a plurality of porous metal layers formed to be separated from each other according to Example 1. FIG. 6 is a plan view showing a second arrangement example of a plurality of porous metal layers formed apart from each other according to Example 1. FIG. 6 is a plan view showing a third arrangement example of a plurality of porous metal layers formed separately from each other according to Example 1. It is sectional drawing which expands and shows a part of junction part of the to-be-joined member and semiconductor chip by the modification 5 of Example 1. FIG. It is sectional drawing which expands and shows a part of junction part of the to-be-joined member and semiconductor chip by the modification 6 of Example 1. FIG. It is principal part sectional drawing of the power module by Example 2. FIG. FIG. 10 is a partial side view showing an example of a railway vehicle according to a third embodiment. It is a top view which shows an example of the internal structure of the inverter installed in the rail vehicle shown in FIG. FIG. 10 is a perspective view illustrating an example of an automobile according to a fourth embodiment.

  In the following embodiments, when necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other, and one is the other. There are some or all of the modifications, details, supplementary explanations, and the like.

  Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including element steps) are not necessarily indispensable unless otherwise specified and clearly considered essential in principle. Needless to say.

  In addition, when referring to “consisting of A”, “consisting of A”, “having A”, and “including A”, other elements are excluded unless specifically indicated that only that element is included. It goes without saying that it is not what you do. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.

  In all the drawings for explaining the following embodiments, components having the same function are denoted by the same reference numerals in principle, and repeated description thereof is omitted. Hereinafter, the present embodiment will be described in detail with reference to the drawings.

≪Detailed assignment explanation≫
A power module is used for an inverter that controls a high-output motor such as a motor for electric railway, industrial equipment, or an electric vehicle / hybrid vehicle (EV (Electric Vehicle) / HEV (Hybrid Electric Vehicle)). Until now, power semiconductor devices such as IGBTs (Insulated Gate Bipolar Transistors) using Si have been used for power modules. However, in recent years, power semiconductor devices using SiC or GaN, which are expected to save energy, are becoming popular.

  By the way, conventionally, in a power semiconductor device using Si, Pb—Sn solder has been used for a joint portion between a member to be joined and a semiconductor chip. However, since SiC or GaN can be driven at a higher temperature than Si, in the power semiconductor device using SiC or GaN, the bonded portion between the member to be bonded and the semiconductor chip is more powerful than the power semiconductor device using Si. May be exposed to high temperatures.

  In the case of bonding using Pb—Sn solder, if the temperature of the bonded portion between the member to be bonded and the semiconductor chip exceeds 200 ° C., the high temperature environment required for the power semiconductor device is insufficient due to insufficient heat resistance of the bonded portion. May not satisfy the operational stability and high current load tolerance.

  For example, when a member to be bonded and a semiconductor chip are bonded with Pb—Sn solder and held at a temperature of 250 ° C. for 500 hours, a Kirkendall void is formed and the heat resistance of the bonded portion deteriorates. For this reason, there is a need for a bonding material that can realize bonding with higher heat resistance than Pb—Sn solder.

  In recent years, it has been pointed out that the Pb component has an adverse effect on the human body, and solder containing Pb has been highlighted as a social problem. Furthermore, as represented by the EU (Restriction of Hazardous Substances Directive) directive of the EU (European Union), the movement to legally restrict the use of harmful substances including Pb has been activated.

  In recent years, instead of joining using Pd—Sn solder, sintered metal joining for sintering metal particle paste containing nano- or micro-level metal particles has been proposed. Sintered metal bonding is promising as a high-temperature bonding technique because it can handle high-temperature operation and does not contain Pb.

  However, in sintered metal bonding, the metal particle paste does not melt at the time of bonding. Therefore, in order to absorb warpage or unevenness of the members to be bonded, it is necessary to apply a load at the time of bonding to bring the metal particle paste into close contact with the members to be bonded.

  Since the sintered density after the bonding greatly depends on the load at this time, a large load of about 10 MPa is required to obtain a sintered density necessary for ensuring the bondability of the bonded portion.

  However, if the semiconductor chip is pressed with a large load, the semiconductor chip may be destroyed. For this reason, it is necessary to reduce the load at the time of joining as much as possible.

  As a method of reducing the load, in order to absorb warpage or unevenness of the member to be joined, Sn solder is used, and the metal particle paste and Sn solder are completely reacted to form a high melting point intermetallic compound. There is a method (see Patent Document 1 and Patent Document 2). By forming the intermetallic compound, in the power semiconductor device, it is possible to obtain a joint having high heat resistance between the material to be joined and the semiconductor chip.

  For example, when Ag particle paste and Sn-based solder are used as a bonding material, a reaction between Ag contained in the Ag particle paste and Sn contained in the Sn-based solder forms an Ag—Sn compound having a high melting point of 400 ° C. or higher. can do.

  However, long-time heat treatment is required to form all the joints between the member to be joined and the semiconductor chip with an intermetallic compound. For example, in order to make all the joints between the member to be joined and the semiconductor chip an Ag—Sn compound, heat treatment is required at a temperature of 300 ° C. for about 1.5 to 2 hours.

  When all the joint portions between the member to be joined and the semiconductor chip are not intermetallic compounds, Sn having a low melting point remains in the joint portions, and the desired heat resistance may not be obtained at the joint portions.

  On the other hand, when all the joints between the member to be joined and the semiconductor chip are formed of intermetallic compounds, the intermetallic compounds are brittle, so if a large impact is applied to the joints, the joints may be destroyed at once. .

  Therefore, the present invention provides a semiconductor device having high reliability in a high temperature environment by obtaining a good bond between a member to be bonded and a semiconductor chip.

  Note that in this specification, a highly reliable semiconductor device is a semiconductor device in which a bonded portion between a member to be bonded and a semiconductor chip has heat resistance, and has operational stability and high current load resistance in a high temperature environment. Say.

<< Structure of semiconductor device >>
The structure of the semiconductor device according to the first embodiment will be described with reference to FIG. 1A and 1B are cross-sectional views illustrating a semiconductor device according to the first embodiment, where FIG. 1A is a cross-sectional view illustrating an embodiment of the semiconductor device before heat treatment, and FIG. 1B is a cross-sectional view illustrating an embodiment of the semiconductor device after heat treatment. FIG.

  First, the configuration of the semiconductor device before the bonded member 1 and the semiconductor chip 4 are bonded by heat treatment will be described with reference to FIG.

  A chip mounting portion 1b is formed on the first main surface of the substrate 1a of the member 1 to be bonded, and a plurality of wiring patterns 1c are formed around the chip mounting portion 1b. A wiring pattern 1d is also formed on the second main surface opposite to the first main surface of the substrate 1a. In the first embodiment, the substrate 1a, the chip mounting portion 1b, the wiring pattern 1c, and the wiring pattern 1d are referred to as a member 1 to be joined. The chip mounting portion 1b, the wiring pattern 1c, and the wiring pattern 1d are made of, for example, a Cu film, and the thickness thereof is, for example, about 0.2 to 0.5 mm.

  On the upper surface of the chip mounting portion 1b, a plurality of porous metal layers 2 are formed apart from each other. The plurality of porous metal layers 2 are porous Ag layers containing nano- or micro-level Ag particles, and examples thereof include an Ag particle paste.

  Here, the separation means that the two members are arranged apart from each other and are not in direct contact with each other. Moreover, even if another member is disposed between the two members, the two members are said to be separated. That is, even if two members are connected via other members, these two members are said to be separated.

  That is, in FIG. 1B described later, the first porous metal layer 2 and the second porous metal layer 2 are covered with the intermetallic compound layer 6. Further, an intermetallic compound layer 9 is disposed between the first porous metal layer 2 and the second porous metal layer 2 with an intermetallic compound layer 6 interposed therebetween. As described above, the first porous metal 2 and the second porous metal 2 are electrically connected via the intermetallic compound layer 6 and the intermetallic compound layer 9. Even if it has such a relationship, it is said that the first porous metal 2 and the second porous metal 2 are separated.

  Further, Sn-based solder 3 is formed on the upper surface of the chip mounting portion 1b so as to cover the upper surfaces and side surfaces of the plurality of porous metal layers 2. The semiconductor chip 4 is mounted on the upper surface of the chip mounting portion 1b via the plurality of porous metal layers 2 and the Sn-based solder 3.

  The semiconductor chip 4 has a quadrangular planar shape that intersects its thickness direction, and has a front surface and a back surface opposite to the front surface. On the surface side of the semiconductor chip 4, a plurality of semiconductor elements, a multilayer wiring layer in which a plurality of insulating layers and wiring layers are stacked, a surface protection film covering the multilayer wiring layer, and the like are formed.

  Furthermore, a plurality of electrode pads electrically connected to a plurality of semiconductor elements are formed on the surface side of the semiconductor chip 4, and the plurality of electrode pads correspond to the respective electrode pads on the surface protective film. It is exposed to the formed opening.

  The back surface of the semiconductor chip 4 faces the member 1 to be joined, and a Ni electrode 5 is formed on the back surface of the semiconductor chip 4. The thickness of the Ni electrode 5 is, for example, about 0.2 to 1.0 μm, and a typical value is 0.5 μm.

  Next, the configuration of the semiconductor device after the bonded member 1 and the semiconductor chip 4 are bonded by heat treatment will be described with reference to FIG.

  By the heat treatment, Ag contained in the porous metal layer 2 reacts with Sn contained in the Sn-based solder 3 to form an intermetallic compound, that is, an Ag—Sn compound.

  Further, Cu constituting the chip mounting portion 1b diffuses into the Sn-based solder 3 from the chip mounting portion 1b exposed between the porous metal layers 2 adjacent to each other, and Sn contained in the Cu and Sn-based solder 3 React with each other to form an intermetallic compound, that is, a Cu-Sn compound.

Then, the upper and side surfaces of a plurality of porous metal layer 2, an intermetallic compound layer 6 made of mostly Ag-Sn compound (e.g. Ag 3 _Sn) are formed. Further, an intermetallic compound layer 7 mainly made of a Cu—Sn compound (for example, Cu ₃ Sn) is formed on the upper surface of the chip mounting portion 1b exposed between the porous metal layers 2 adjacent to each other. Further, an intermetallic compound layer 8 mainly made of a Cu—Sn compound (for example, Cu ₆ Sn ₅ ) is formed in contact with the Ni electrode 5 on the back surface of the semiconductor chip 4.

Then, between the chip mounting portion 1b and the intermetallic compound layer 8, specifically, the intermetallic compound layer 6 and the intermetallic compound layer 7 formed on the bonded member 1 side, and the semiconductor chip 4 side. Between the intermetallic compound layer 8, an intermetallic compound layer 9 made of an intermetallic compound containing Sn as a main component is formed. Examples of the intermetallic compound containing Sn as a main component include an Ag—Sn compound (for example, Ag ₃ Sn) and a Cu—Sn compound (for example, Cu ₆ Sn ₅ ).

Here, the main component refers to an element having the largest ratio among the joining members such as a compound and solder. For example, in the case of an Ag ₃ Sn compound, the main component is Ag, and in the case of a Su ₆ Sn ₅ compound, Su is the main component. If it is Sn-3Ag-0.5Cu solder, the main component is Sn.

  In Example 1, a porous Ag layer containing nano- or micro-level Ag particles was used for the porous metal layer 2. When the porous Ag layer is joined with the Sn-based solder 3, the wettability of the Sn-based solder 3 is very good, so that a good joint can be obtained. Moreover, since Ag contained in the porous Ag layer reacts with Sn contained in the Sn-based solder 3 to produce an Ag—Sn compound, it is easy to increase the melting point.

  Examples of means for forming the porous Ag layer include the following methods. A divided pattern of Ag particle paste composed of nano-sized Ag particles and a solvent is formed on the upper surface of the chip mounting portion 1b of the bonded member 1 by screen printing, and then sintered in a high-temperature bath. Alternatively, the porous Ag layer can be similarly formed by a method of transferring a divided pattern using a stamp or the like or a method of supplying by a dispenser instead of screen printing.

<< Characteristics and Effects of Semiconductor Device According to Embodiment 1 >>
Features and effects of the semiconductor device according to the first embodiment will be described with reference to FIGS. FIG. 2 is an enlarged cross-sectional view illustrating a part of the joint portion between the member to be joined and the semiconductor chip according to the first embodiment.

  FIG. 3 shows a bonded portion between a member to be bonded and a semiconductor chip when one porous metal layer having substantially the same area as the semiconductor chip is formed on the upper surface of the chip mounting portion without dividing the porous metal layer. It is a cross-sectional photograph which expands and shows a part.

  FIG. 4 is an enlarged view of a part of the bonded portion between the member to be bonded and the semiconductor chip when the porous metal layer is divided and a plurality of porous metal layers are formed on the upper surface of the chip mounting portion so as to be separated from each other. It is a cross-sectional photograph shown.

  In the following description, FIGS. 1A and 1B are referred to as appropriate.

1. Features of Semiconductor Device The semiconductor device according to the first embodiment includes a member to be bonded, a semiconductor chip, and a bonding portion that bonds the member to be bonded and the semiconductor chip. And the said joint part is the Cu-Sn compound formed in contact with the Ni electrode of the several porous metal layer formed on the upper surface of the chip | tip mounting part of the to-be-joined member spaced apart from each other, and the back surface of a semiconductor chip And a second layer made of an intermetallic compound containing Sn as a main component and covering the plurality of porous metal layers and interposed between the upper surface of the chip mounting portion and the first layer; It is characterized by having. Examples of the intermetallic compound containing Sn as a main component are an Ag—Sn compound and a Cu—Sn compound.

2. About heat resistance If Sn contained in the Sn-based solder used for bonding remains in the bonded portion between the member to be bonded and the semiconductor chip, the heat resistance of that portion is low, so the desired heat resistance may not be obtained at the bonded portion. There is sex.

  However, according to the first embodiment, the heat resistance of the joint portion between the member to be joined and the semiconductor chip can be improved. The reason will be described below.

  As shown in FIGS. 1A and 1B, in the bonded portion between the member 1 to be bonded and the semiconductor chip 4 according to the first embodiment, a plurality of porous materials are separated from each other on the upper surface of the chip mounting portion 1b. Since the metal layer 2 is formed, the porous metal in contact with the Sn-based solder 3 is compared with the case where one porous metal layer 2 having almost the same area as the semiconductor chip 4 is formed on the upper surface of the chip mounting portion 1b. The surface area of layer 2 is increased. Thus, since the surface area of the porous metal layer 2 in contact with the Sn-based solder 3 is increased, the reaction between Ag contained in the porous metal layer 2 and Sn contained in the Sn-based solder 3 is promoted.

  Further, as shown in FIG. 2, Cu constituting the chip mounting portion 1b diffuses into the Sn-based solder 3 from the chip mounting portion 1b exposed between the adjacent porous metal layers 2, and the Cu and Sn Sn contained in the system solder 3 reacts to form a Cu—Sn compound.

  As described above, in addition to the generation of the Ag—Sn compound, the Cu—Sn compound is generated, so that Sn contained in the Sn-based solder 3 is easily consumed, and the bonded portion between the member to be bonded 1 and the semiconductor chip 4 is consumed. It is possible to prevent the Sn contained in the Sn-based solder 3 from remaining. As a result, desired heat resistance can be obtained at the joint between the member 1 to be joined and the semiconductor chip 4, so that the semiconductor device can be driven at a high temperature.

3. About reliability (first effect)
Without dividing the porous metal layer, one porous metal layer having substantially the same area as the semiconductor chip is formed on the upper surface of the chip mounting portion, and Ag and Sn-based solder contained in the porous metal layer are formed by heat treatment. When Sn contained is reacted, an Ag—Sn compound is formed at the joint between the member to be joined and the semiconductor chip.

  However, for the Ag—Sn compound to grow from the porous metal layer and reach the Ni electrode on the back surface of the semiconductor chip, for example, heat treatment is required at a temperature of 300 ° C. for about 1.5 to 2 hours. During this time, as shown in FIG. 3, Ni constituting the Ni electrode reacts with Sn contained in the Sn-based solder to form a Ni—Sn compound. If all the Ni constituting the Ni electrode has reacted, the Ni—Sn compound may be peeled off from the back surface of the semiconductor chip and the semiconductor device may be broken.

  For this reason, it is required to perform the heat treatment for forming the intermetallic compound in a short time. However, as described above, the short-time heat treatment has a problem that Sn remains in the bonded portion between the member to be bonded and the semiconductor chip.

  However, according to the first embodiment, it is possible to avoid the destruction of the semiconductor device by suppressing the generation of the Ni—Sn compound. The reason will be described below.

  As shown in FIGS. 1A and 1B, in the bonded portion between the member 1 to be bonded and the semiconductor chip 4 according to the first embodiment, a plurality of porous materials are separated from each other on the upper surface of the chip mounting portion 1b. A metal layer 2 is formed. Thereby, Cu constituting the chip mounting portion 1b diffuses into the Sn-based solder 3 from the chip mounting portion 1b exposed between the adjacent porous metal layers 2, and is included in the Cu and Sn-based solder 3. Sn reacts to form a Cu-Sn compound.

  Further, the Cu diffuses in the Sn-based solder 3 toward the back surface of the semiconductor chip 4, and since the crystal structure of Ni is similar to the crystal structure of Cu, Cu is deposited on the surface of the Ni electrode 5. Then, as shown in FIG. 4, the Cu—Sn compound is formed in contact with the Ni electrode 5 by promoting the reaction between the deposited Cu and Sn contained in the Sn-based solder 3.

Thereby, as shown in FIG. 2, an intermetallic compound layer 6 mainly composed of an Ag—Sn compound (for example, Ag ₃ Sn) is formed on the upper surface and side surfaces of the plurality of porous metal layers 2. Further, an intermetallic compound layer 7 mainly made of a Cu—Sn compound (for example, Cu ₃ Sn) is formed on the upper surface of the chip mounting portion 1b exposed between the porous metal layers 2 adjacent to each other.

Further, an intermetallic compound layer 8 mainly made of a Cu—Sn compound (for example, Cu ₆ Sn ₅ ) is formed in contact with the Ni electrode 5 on the back surface of the semiconductor chip 4.

Then, between the chip mounting portion 1b and the intermetallic compound layer 8, specifically, the intermetallic compound layer 6 and the intermetallic compound layer 7 formed on the bonded member 1 side, and the semiconductor chip 4 side. Between the intermetallic compound layer 8, an intermetallic compound layer 9 made of an intermetallic compound containing Sn as a main component is formed. Examples of the intermetallic compound containing Sn as a main component include an Ag—Sn compound (for example, Ag ₃ Sn) and a Cu—Sn compound (for example, Cu ₆ Sn ₅ ).

  As described above, the formation of the Ni—Sn compound on the back surface of the semiconductor chip 4 can be suppressed by forming the intermetallic compound layer 8 made of the Cu—Sn compound in contact with the Ni electrode 5 on the back surface of the semiconductor chip 4. , Destruction of the semiconductor device due to the generation of the Ni—Sn compound can be avoided.

  As a result of studies by the present inventors, for example, an intermetallic compound layer 8 made of a Cu—Sn compound is formed in contact with the Ni electrode 5 on the back surface of the semiconductor chip 4 by a heat treatment at a temperature of 300 ° C. for about 30 minutes. An Ag—Sn compound and a Cu—Sn compound could be formed between the upper surface of the chip mounting portion 1 b and the intermetallic compound layer 8 made of a Cu—Sn compound so as to cover the porous metal layer 2.

(Second effect)
When all the joint portions between the member to be joined and the semiconductor chip are formed of an intermetallic compound, since the intermetallic compound is brittle, there is a possibility that the joint portion may be destroyed at once when a large impact is applied to the joint portion.

  However, according to the first embodiment, as shown in FIGS. 1A and 1B, the Ag—Sn compound and Cu are bonded to the bonded portion between the member to be bonded 1 and the semiconductor chip 4 by a short heat treatment. -Sn compounds can be formed.

  Therefore, before the porous metal layer 2 becomes an intermetallic compound, the reaction for generating the intermetallic compound stops, and a plurality of porous metal layers 2 can be left on the upper surface of the chip mounting portion 1b. Since the plurality of porous metal layers 2 remaining on the upper surface of the chip mounting portion 1b absorb the impact applied to the bonded portion between the member 1 to be bonded and the semiconductor chip 4, the breakage of the bonded portion can be suppressed.

  Moreover, even if a crack occurs in the intermetallic compound, the crack stops at the porous metal layer 2 and the destruction of the joint can be suppressed.

≪Plane pattern of porous metal layer≫
An example of a planar pattern of a plurality of porous metal layers is shown in FIGS. FIG. 5 is a plan view showing a first arrangement example of a plurality of porous metal layers formed apart from each other according to the first embodiment. FIG. 6 is a plan view showing a second arrangement example of the plurality of porous metal layers formed apart from each other according to the first embodiment. FIG. 7 is a plan view showing a third arrangement example of the plurality of porous metal layers formed apart from each other according to the first embodiment.

  The planar pattern of the plurality of porous metal layers formed in contact with the chip mounting portion on the main surface of the chip mounting portion of the member to be bonded must be fine so that the surface area in contact with the Sn-based solder increases. Is desirable. This is because when the surface area of the porous metal layer in contact with the Sn-based solder is small, the time for generating the intermetallic compound becomes long.

  In plan view, the area ratio of the plurality of porous metal layers to the semiconductor chip is preferably 40% or more and 80% or less. When the area ratio is less than 40%, the remaining portion is an intermetallic compound, so that the brittleness becomes strong as the characteristics of the bonded portion between the member to be bonded and the semiconductor chip, and the reliability may be lowered. On the other hand, when the area ratio is larger than 80%, the amount of Sn-based solder supplied at the time of bonding decreases, and it becomes difficult to satisfactorily bond the entire area of the bonded portion between the member to be bonded and the semiconductor chip.

  In the layout of the porous metal layer 2 shown in FIG. 5, the plurality of porous metal layers 2 arranged at the first interval along the X direction are along the Y direction orthogonal to the X direction on the surface of the chip mounting portion 1b. Are arranged at a second interval. The porous metal layer 2 has a quadrangular shape in plan view, and the dimension of one side is about 10 to 15 μm. The first interval and the second interval may be the same or different. Moreover, you may arrange | position so that it may become a staggered arrangement | sequence.

  In the layout of the porous metal layer 2 shown in FIG. 6, a plurality of porous metal layers 2 extending along the X direction are arranged apart from each other in the Y direction. A plurality of porous metal layers 2 are arranged in a so-called stripe shape. The width of the porous metal layer 2 in the Y direction is, for example, about 10 to 15 μm.

  In the layout of the porous metal layer 2 shown in FIG. 7, the plurality of porous metal layers 2 arranged at the first interval along the X direction are arranged at the second interval along the Y direction. The porous metal layer 2 has a circular shape in plan view and a diameter of about 10 to 15 μm. The first interval and the second interval may be the same or different. Moreover, you may arrange | position so that it may become a staggered arrangement | sequence.

<< Modification 1 >>
In Example 1 described above, Sn-based solder is used as the solder, but In-based solder can also be used.

  The joint portion according to the modified example 1 includes a plurality of porous metal layers formed on the upper surface of the chip mounting portion of the member to be joined and Cu-In formed in contact with the Ni electrode on the back surface of the semiconductor chip. A first layer made of a compound, and a second layer made of an intermetallic compound containing In as a main component and covering the plurality of porous metal layers and interposed between the upper surface of the chip mounting portion and the first layer It is characterized by having.

  Thereby, substantially the same effects as those of the first embodiment can be obtained.

<< Modification 2 >>
In the first embodiment described above, the chip mounting portion of the member to be bonded is configured by the Cu film. However, the chip mounting portion can also be configured by a member having a Cu film formed on the surface.

  The joint portion according to the modified example 2 includes a plurality of porous metal layers formed on the upper surface of the chip mounting portion of the member to be joined and Cu—Sn formed in contact with the Ni electrode on the back surface of the semiconductor chip. A first layer made of a compound and a second layer made of an intermetallic compound containing Sn as a main component and covering the plurality of porous metal layers and interposed between the upper surface of the chip mounting portion and the first layer And having. Further, the chip mounting portion is formed of a member having a Cu film formed on the surface.

  Since Cu diffuses from the Cu film constituting the chip mounting portion to the Sn-based solder and reacts with it, a Cu—Sn compound can be formed, and therefore, substantially the same effect as in Example 1 can be obtained. it can.

  Note that the solder is not limited to Sn solder, and may be In solder, for example. Moreover, the wiring patterns formed on the first main surface and the second main surface of the substrate, which constitute the member to be bonded, may also be formed of a member having a Cu film on the surface.

<< Modification 3 >>
In the above-described first embodiment, the chip mounting portion of the member to be bonded is configured by the Cu film. However, the chip mounting portion is configured by a member having a Cu film formed on the surface, and further, the surface of the Cu film is Ag plated. May be applied.

  The joint portion according to the modified example 3 includes a plurality of porous metal layers formed on the upper surface of the chip mounting portion of the member to be joined, and Cu—Sn formed in contact with the Ni electrode on the back surface of the semiconductor chip. A first layer made of a compound and a second layer made of an intermetallic compound containing Sn as a main component and covering the plurality of porous metal layers and interposed between the upper surface of the chip mounting portion and the first layer And having. Further, the chip mounting portion is made of a member having a Cu film formed on the surface, and Ag plating is applied to the surface of the Cu film.

  When the chip mounting portion is a member having a Cu film subjected to Ag plating on the surface, the bonding strength of the porous metal layer can be increased.

  For example, when a plurality of porous metal layers are made of Ag, the plurality of porous metal layers are obtained by printing and sintering paste-like Ag on the upper surface of the Cu member subjected to Ag plating by a screen printing method. It is formed. In this case, higher bonding strength can be obtained than in the case of a Cu member not subjected to Ag plating. Further, at the time of the sintering, the chip mounting portion can be prevented from being oxidized because Ag covers the surface of the Cu member even in a non-oxidizing atmosphere. If the chip mounting portion is oxidized, there is a possibility that a bonding failure may occur when bonding with Sn-based solder. However, in Modification 3, this bonding failure can be avoided.

  The thickness of the Ag plating is desirably 3 μm or less. When the Ag plating thickness is thicker than 3 μm, the Ag plating does not melt into the Sn-based solder from the exposed chip mounting portion when joining with Sn-based solder, and the underlying Cu of the Ag plating becomes Sn-based solder May not spread. When Cu does not diffuse into Sn-based solder, it becomes difficult to form an intermetallic compound layer made of a Cu—Sn compound in contact with the Ni electrode on the back surface of the semiconductor chip.

  When the Ag plating must be thicker than 3 μm, the plurality of porous metal layers are made of a metal containing Cu (see Modifications 6 and 7 described later), or the Ni electrode on the back surface of the semiconductor chip Cu for forming an intermetallic compound layer made of a Cu—Sn compound is supplied in contact with the Ni electrode by a method such as providing a Cu layer in contact with the electrode.

  Note that the solder is not limited to Sn solder, and may be In solder, for example. Further, the wiring patterns formed on the first main surface and the second main surface of the substrate constituting the member to be bonded may also be formed of a member having a Cu film with Ag plating on the surface.

<< Modification 4 >>
In Example 1 described above, the chip mounting portion of the member to be bonded is configured by the Cu film. However, the chip mounting portion is configured by a member having a Cu film formed on the surface, and further, the surface of the Cu film is Au plated. May be applied.

  The joint part according to the modified example 4 is a Cu-Sn formed in contact with a plurality of porous metal layers formed on the upper surface of the chip mounting part of the member to be joined and spaced apart from each other and the Ni electrode on the back surface of the semiconductor chip. A first layer made of a compound and a second layer made of an intermetallic compound containing Sn as a main component and covering the plurality of porous metal layers and interposed between the upper surface of the chip mounting portion and the first layer And having. Further, the chip mounting portion is made of a member having a Cu film formed on the surface, and the surface of the Cu film is Au plated.

  Since the chip mounting portion is a member having a Cu film plated with Au on the surface, the bonding strength of the porous metal layer can be increased.

  For example, when a plurality of porous metal layers are made of Ag, the plurality of porous metal layers are obtained by printing and sintering paste-like Ag on the upper surface of a Cu member subjected to Au plating by a screen printing method. It is formed. In this case, higher bonding strength can be obtained than in the case of a Cu member not subjected to Au plating. Further, at the time of the sintering, even if the atmosphere is not a non-oxidizing atmosphere, the chip mounting portion can be prevented from being oxidized because Au covers the surface of the Cu member. If the chip mounting portion is oxidized, there is a risk of joining failure when joining with Sn-based solder. However, in Modification 4, this joining failure can be avoided.

  If the thickness of the Au plating is 1 μm or less, the Au plating melts into the Sn-based solder from the exposed chip mounting portion when joining with Sn-based solder, and the underlying Cu of the Au plating diffuses into the Sn-based solder To do. When Cu reacts with the Sn-based solder, an intermetallic compound layer made of a Cu—Sn compound can be formed in contact with the Ni electrode on the back surface of the semiconductor chip.

  Note that the solder is not limited to Sn solder, and may be In solder, for example. Further, the wiring patterns formed on the first main surface and the second main surface of the substrate, which constitute the member to be bonded, may also be configured by members having a Cu film plated with Au on the surface.

<< Modification 5 >>
In the above-described first embodiment, the chip mounting portion of the member to be bonded is configured by the Cu film. However, the chip mounting portion is configured by a member having a Cu film formed on the surface, and the surface of the Cu film is Ni-plated. May be applied.

  The joint portion according to the modified example 5 includes a plurality of porous metal layers formed on the upper surface of the chip mounting portion of the member to be joined and Cu-Sn formed in contact with the Ni electrode on the back surface of the semiconductor chip. A first layer made of a compound and a second layer made of an intermetallic compound containing Sn as a main component and covering the plurality of porous metal layers and interposed between the upper surface of the chip mounting portion and the first layer And having. Furthermore, the chip mounting portion is made of a member having a Cu film formed on the surface, and Ni plating is applied to the surface of the Cu film.

  Among semiconductor devices that are always used in a high temperature environment, when the chip mounting portion of the member to be bonded is exposed, Cu may be discolored due to oxidation. However, discoloration can be prevented by applying Ni plating to the surface of the Cu film.

  If the thickness of the Ni plating is 1 μm or less, the Ni plating melts into the Sn-based solder from the exposed chip mounting portion when joining with the Sn-based solder, and the underlying Cu of the Ni plating diffuses into the Sn-based solder To do. When Cu reacts with the Sn-based solder, an intermetallic compound layer made of a Cu—Sn compound can be formed in contact with the Ni electrode on the back surface of the semiconductor chip.

  Note that the solder is not limited to Sn solder, and may be In solder, for example. Further, the wiring patterns formed on the first main surface and the second main surface of the substrate, which constitute the member to be joined, may also be configured by members having a Cu film plated with Ni on the surface.

  FIG. 8 is an enlarged cross-sectional view illustrating a part of the joint portion between the member to be joined and the semiconductor chip according to the fifth modification of the first embodiment.

  As shown in FIG. 8, the chip mounting portion 1b includes a base 1b1, a Cu film 1b2 formed on the base 1b1, and a Ni plating 1b3 applied to the surface of the Cu film 1b2. The chip mounting portion 1b including the base material 1b1 and the Cu film 1b2 not subjected to the Ni plating 1b3 is the second modification. Further, the chip mounting portion 1b in which the surface of the Cu film 1b2 is subjected to Ag plating instead of the Ni plating 1b3 is the modified example 3, and the chip mounting in which the surface of the Cu film 1b2 is subjected to Au plating instead of the Ni plating 1b3 is mounted. The part is the fourth modification.

<< Modification 6 >>
In Example 1 described above, the plurality of porous metal layers are made of Ag, but may be made of Cu.

  The joint portion according to the modified example 6 includes a plurality of porous metal layers formed on the upper surface of the chip mounting portion of the member to be joined and Cu-Sn formed in contact with the Ni electrode on the back surface of the semiconductor chip. A first layer made of a compound and a second layer made of an intermetallic compound containing Sn as a main component and covering the plurality of porous metal layers and interposed between the upper surface of the chip mounting portion and the first layer And having. Further, the plurality of porous metal layers are made of Cu.

  A porous Cu layer containing nano- or micro-level Cu particles is used as the porous metal layer. When the porous Cu layer is joined with the Sn-based solder, the wettability of the Sn-based solder is very good, so that a good joint can be obtained. Moreover, since Cu contained in the porous Cu layer reacts with Sn contained in the Sn-based solder to produce a Cu—Sn compound at a high speed, it is easy to increase the melting point.

  Cu diffuses not only from the chip mounting portion but also from the polycrystalline Cu layer into the Sn-based solder, and the Cu and Sn contained in the Sn-based solder react to form a Cu—Sn compound. . Therefore, even when the chip mounting portion of the member to be bonded is constituted by a member having a Cu film having a Ni plating thickness of, for example, 1 μm or more on the surface, the member to be bonded and the semiconductor chip can be formed in a short time. A Cu—Sn compound can be formed at the joint.

  FIG. 9 is an enlarged cross-sectional view illustrating a part of the bonded portion between the member to be bonded and the semiconductor chip according to the sixth modification of the first embodiment.

As shown in FIG. 9, Cu—Sn compounds having different composition ratios are formed depending on the joint portion. For example, a Cu—Sn compound 11 whose composition ratio is mainly Cu ₃ Sn is formed on the upper surface and side surfaces of the porous Cu layer 10, and similarly, the chip mounting portion 1 b exposed between the adjacent porous Cu layers 10. A Cu—Sn compound 11 whose composition ratio is mainly Cu ₃ Sn is formed on the upper surface of the film, and a Cu—Sn compound 12 whose composition ratio is mainly Cu ₆ Sn ₅ is formed on the other portions.

  Examples of means for forming the porous Cu layer include the following methods. A divided pattern of Cu particle paste composed of nano-sized Cu particles and a solvent is formed on the upper surface of the chip mounting portion of the bonded member by screen printing, and then sintered in a high-temperature bath. Alternatively, the porous Cu layer can be similarly formed by a method of transferring a divided pattern using a stamp or the like or a method of supplying by a dispenser instead of screen printing.

  Note that the solder is not limited to Sn solder, and may be In solder, for example.

<< Modification 7 >>
In Example 1 described above, the plurality of porous metal layers are made of Ag, but may be made of Ag and Cu.

  The joint portion according to the modified example 7 includes a plurality of porous metal layers formed on the upper surface of the chip mounting portion of the member to be joined and Cu-Sn formed in contact with the Ni electrode on the back surface of the semiconductor chip. A first layer made of a compound and a second layer made of an intermetallic compound containing Sn as a main component and covering the plurality of porous metal layers and interposed between the upper surface of the chip mounting portion and the first layer And having. Further, the plurality of porous metal layers are characterized by comprising Ag and Cu.

  A porous Ag-Cu layer containing nano- or micro-level Ag particles and Cu particles is used for the porous metal layer. When the porous Ag—Cu layer is joined with the Sn-based solder, the Sn-based solder has very good wettability, so that a good joint can be obtained. In addition, Cu contained in the porous Ag—Cu layer reacts with Sn contained in the Sn-based solder to generate a Cu—Sn compound at a high speed, so that it is easy to increase the melting point.

  In addition, Cu diffuses not only from the chip mounting portion but also from the polycrystalline Ag—Cu layer into the Sn-based solder, and the Cu and Sn contained in the Sn-based solder react to form a Cu—Sn compound. Is done. Therefore, even when the chip mounting portion of the member to be bonded is constituted by a member having a Cu film having a Ni plating thickness of, for example, 1 μm or more on the surface, the member to be bonded and the semiconductor chip can be formed in a short time. A Cu—Sn compound can be formed at the joint.

  Examples of means for forming the porous Ag—Cu layer include the following methods. A division pattern of Ag-Cu particle paste composed of nano-sized Ag particles, Cu particles, and a solvent is formed on the upper surface of the chip mounting portion of the bonded member by screen printing, and then sintered in a high-temperature bath. Alternatively, the porous Ag—Cu layer can be similarly formed by a method of transferring a divided pattern using a stamp or the like or a method of supplying by a dispenser instead of screen printing.

  Note that the solder is not limited to Sn solder, and may be In solder, for example.

  As described above, the bonding portion between the member to be bonded and the semiconductor chip according to the first embodiment includes a plurality of porous metal layers formed on the upper surface of the chip mounting portion of the member to be bonded and separated from each other, and the semiconductor chip. A first layer made of a Cu—Sn compound formed in contact with the Ni electrode on the back surface and a plurality of porous metal layers, Sn interposed between the upper surface of the chip mounting portion and the first layer; And a second layer made of an intermetallic compound as a main component. Thereby, a lead-free semiconductor device having high reliability in a high temperature environment can be realized.

  A power module according to the second embodiment will be described. The power module according to the second embodiment is a power module to which the semiconductor device according to the first embodiment is applied. FIG. 10 is a cross-sectional view of a main part of the power module according to the second embodiment.

  The power module 30 includes a base 107, a bonded member 105 bonded to the base 107 via an Sn-based solder sheet 106, and semiconductor chips 103 and 104 bonded to the bonded member 105 via a bonded portion 108. And a terminal 102 bonded to a position different from the semiconductor chips 103 and 104 on the member 105 to be bonded.

  The bonded member 105 has a size in a plan view of, for example, a ceramic substrate 105a having a size of about 40 mm × 20 mm, and a chip mounting portion 105b formed on the first main surface (surface on the semiconductor chips 103 and 104 side) of the ceramic substrate 105a. And a terminal mounting portion 105c and a Cu plate 105d formed on the second main surface (surface on the base 107 side) of the ceramic substrate 105a.

  The chip mounting part 105b and the terminal mounting part 105c are made of, for example, a member made of silicon nitride having a Cu film on the surface. Further, the surface of the Cu film constituting the chip mounting portion 105b may be subjected to Au plating, Ag plating, or Ni plating. The surface of the Cu plate 105d may be plated with Ni.

  The joint portion 108 is composed of a plurality of porous metal layers formed on the upper surface of the chip mounting portion 105b so as to be spaced apart from each other, and a Cu—Sn compound formed in contact with the Ni electrodes on the back surfaces of the semiconductor chips 103 and 104. A first layer; and a second layer made of an intermetallic compound containing Sn as a main component and interposed between the chip mounting portion 105b and the first layer so as to cover the plurality of porous metal layers. . The plurality of porous metal layers are, for example, a porous Ag layer, a porous Cu layer, or a porous Ag—Cu layer. The intermetallic compound containing Sn as a main component is, for example, a Cu—Sn compound and an Ag—Sn compound, or a Cu—Sn compound. As the layout of the plurality of porous metal layers, for example, the layout shown in FIG. 5, FIG. 6, or FIG. 7 can be applied.

  Below, an example of the manufacturing method of a power module is demonstrated.

  First, the member to be bonded 105 is prepared, and a metal particle paste (for example, Ag particle paste or Cu particle paste) is screen-printed on the upper surface of the chip mounting portion 105b of the member to be bonded 105. At this time, as shown in FIG. 5, FIG. 6, or FIG. 7, screen printing is performed so that the pattern made of the metal particle paste becomes a plurality of patterns separated from each other. Subsequently, a plurality of porous metal layers including metal particles (for example, Ag particles or Cu particles) are formed apart from each other by sintering at a temperature of 250 ° C., for example.

  Next, an Sn-based solder sheet, for example, an Sn-3Ag-0.5Cu-based solder sheet or an Sn-In-based solder sheet is placed on the upper surface of the chip mounting portion 105b so as to cover the plurality of porous metal layers. Subsequently, the semiconductor chips 103 and 104 are placed on the Sn-based solder sheet so that the back surfaces of the semiconductor chips 103 and 104 and the top surface of the chip mounting portion 105b are opposed to each other. Put the weight of.

Next, for example, a heat treatment at a peak temperature of 300 ° C. is performed for about 15 minutes in a reducing atmosphere of (N ₂ + 15% H ₂ ) to form an intermetallic compound at the joint 108.

  Next, the plurality of electrode pads formed on the surface side of the semiconductor chips 103 and 104 and the terminal mounting portion 105c are connected using the bonding wire 101, and the terminal 102 is connected on the upper surface of the terminal mounting portion 105c. Subsequently, the bonded member 105 to which the semiconductor chips 103 and 104 and the terminal 102 are connected is mounted on the upper surface of the base 107 via the Sn-based solder sheet 106. Thereafter, the power module 30 is substantially completed by sealing the periphery of the joint 108 with silicone resin or the like.

  Table 1 summarizes various specifications of the joint portion between the bonded member and the semiconductor chip examined by the present inventors and the evaluation results thereof.

  As the bondability of the bonding portion, the bonding state of the bonding portion of the power module is confirmed by an ultrasonic flaw detection image, and the case where the bonding portion is 10% or more of the area of the semiconductor chip is defined as “x”, and less than 10% Was defined as “○”. Further, the cross section of the joint was observed, and the case where unreacted Sn-based solder remained was defined as “x”, and the case where it did not remain was defined as “◯”. With respect to the bondability of the joint portion according to the second embodiment, all are “◯”, which indicates that the joint is good.

  As the reliability of the joint, a temperature cycle test of −40 ° C. to 200 ° C. was performed on the power module. A case where the bonding area is 80% or more with respect to the initial bonding area at the time of 1,000 cycles is defined as “◯”, and a case where the bonding area is less than 80% is defined as “X”. Defined. As for the reliability of the joint portion according to the second embodiment, both are “◯” and it can be seen that the joint is good.

  As a comparative example, a power module similar to the power module shown in FIG. 10 is assembled using one porous metal layer without dividing the porous metal layer, and a bonded portion between the member to be bonded and the semiconductor chip. The bondability and reliability of the were evaluated. Table 2 summarizes the evaluation results.

  In Comparative Examples 1 and 2, unreacted Sn-based solder remained in the joint, and it was confirmed that the joint was not completely heat-resistant. In addition, when a temperature cycle test was performed in the joined state, in Comparative Examples 1 and 2, cracks developed in the remaining portion of the low melting point Sn-based solder, and the joining area was less than the initial 80%. . In particular, in Comparative Example 1, the Ni electrode on the back surface of the semiconductor chip disappeared, and bonding peeling was observed at that portion.

  A railway vehicle according to the third embodiment will be described. The railway vehicle according to the third embodiment is a railway vehicle equipped with the power module according to the second embodiment. FIG. 11 is a partial side view showing an example of a railway vehicle according to the third embodiment. 12 is a plan view showing an example of an internal structure of an inverter installed in the railway vehicle shown in FIG.

  A railway vehicle 31 shown in FIG. 11 is mounted with, for example, the power module 30 of the above-described second embodiment, and includes a vehicle main body 36, a power module 30, a mounting member that supports the power module 30, and a current collector. The pantograph 32 and the inverter 33 are provided. And the power module 30 is mounted in the inverter 33 installed in the lower part of the vehicle main body 36.

  As shown in FIG. 12, inside the inverter 33, a plurality of power modules 30 are mounted on a printed circuit board (mounting member) 35, and a cooling device 34 for cooling these power modules 30 is mounted. In the power module 30 of Example 2 described above, the amount of heat generated from the semiconductor chip is large. Therefore, the cooling device 34 is attached so that the plurality of power modules 30 can be cooled to cool the inside of the inverter 33.

  Thereby, in the railway vehicle 31, the inverter 33 equipped with the plurality of power modules 30 using the module joining structure is provided. 33 and the reliability of the railway vehicle 31 provided with the same can be improved. That is, it is possible to realize a power module 30 that can withstand operation stability under a high temperature environment and a high current load, and an inverter system using the same.

  A vehicle according to the fourth embodiment will be described. The vehicle according to the fourth embodiment is a vehicle on which the power module according to the second embodiment described above is mounted. FIG. 13 is a perspective view showing an example of an automobile according to the fourth embodiment.

  13 includes, for example, a power module 30 and includes a vehicle body 38, tires 39, a power module 30, and a mounting unit 40 that is a mounting member that supports the power module 30. ing.

  In the automobile 37, the power module 30 is mounted on an inverter included in the mounting unit 40. The mounting unit 40 is, for example, an engine control unit. In this case, the mounting unit 40 is disposed in the vicinity of the engine. ing. In this case, the mounting unit 40 is used in a high temperature environment, and thus the power module 30 is also in a high temperature state.

  However, even if the mounting unit 40 is in a high-temperature environment due to the provision of the inverter in which the plurality of power modules 30 using the module joining structure is provided in the automobile 37, the reliability of the automobile 37 is improved. Can increase the sex. That is, also in the automobile 37, it is possible to realize a power module 30 that can withstand operational stability under a high temperature environment and a high current load, and an inverter system using the same.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The present invention is not limited to the above-described embodiment, and includes various modifications. For example, the above-described embodiment has been described in detail for easy understanding of the present invention, and is not necessarily limited to the one having all the configurations described.

  In addition, part of the configuration of one embodiment can be replaced with the configuration of another embodiment, and the configuration of another embodiment can be added to the configuration of one embodiment. . In addition, it is possible to add, delete, and replace other configurations for a part of the configuration of each embodiment. In addition, each member and relative size which were described in drawing are simplified and idealized in order to demonstrate this invention clearly, and become a more complicated shape on mounting.

DESCRIPTION OF SYMBOLS 1 To-be-joined member 1a Board | substrate 1b Chip mounting part 1b1 Base material 1b2 Cu film 1b3 Ni plating 1c, 1d Wiring pattern 2 Porous metal layer 3 Sn system solder 4 Semiconductor chip 5 Ni electrode 6, 7, 8, 9 Intermetallic compound layer DESCRIPTION OF SYMBOLS 10 Porous Cu layer 11,12 Cu-Sn compound 30 Power module 31 Railway vehicle 32 Pantograph 33 Inverter 34 Cooling device 35 Printed circuit board (mounting member)
36 Vehicle body 37 Car 38 Car body 39 Tire 40 Mounting unit 101 Wire 102 Terminal 103, 104 Semiconductor chip 105 Joined member 105a Ceramic substrate 105b Chip mounting portion 105c Terminal mounting portion 105d Cu plate 106 Sn-based solder sheet 107 Base 108 Bonding portion

Claims (15)

A substrate having a first main surface and a second main surface opposite to the first main surface;
A chip mounting portion formed on the first main surface of the substrate;
A semiconductor chip having a front surface and a back surface opposite to the front surface, and an electrode formed on the back surface;
A joint formed between the upper surface of the chip mounting portion and the electrode on the back surface of the semiconductor chip;
With
The joint is
A plurality of porous metal layers formed on the top surface of the chip mounting portion and spaced apart from each other;
A first layer made of a Cu-Sn compound formed in contact with the electrode on the back surface of the semiconductor chip;
A second layer made of an intermetallic compound containing Sn as a main component, covering the plurality of porous metal layers and interposed between the upper surface of the chip mounting portion and the first layer;
A semiconductor device. The semiconductor device according to claim 1,
The chip mounting portion is a semiconductor device made of a Cu film or a member having a Cu film on the surface. The semiconductor device according to claim 1,
The chip mounting portion is a semiconductor device comprising a Cu film on which Ag plating, Au plating, or Ni plating is applied, or a member having a Cu film on which Ag plating, Au plating, or Ni plating is applied on the surface. The semiconductor device according to claim 1,
The plurality of porous metal layers are semiconductor devices that are Ag, Cu, or a porous layer made of Ag and Cu. The semiconductor device according to claim 1,
The semiconductor device, wherein a planar area of the plurality of porous metal layers is 40% or more and 80% or less of a planar area of the semiconductor chip. A substrate having a first main surface and a second main surface opposite to the first main surface;
A chip mounting portion formed on the first main surface of the substrate;
A semiconductor chip having a front surface and a back surface opposite to the front surface, and an electrode formed on the back surface;
A joint formed between the upper surface of the chip mounting portion and the electrode on the back surface of the semiconductor chip;
With
The joint is
A plurality of porous metal layers formed on the top surface of the chip mounting portion and spaced apart from each other;
A first layer made of a Cu-In compound formed in contact with the electrode on the back surface of the semiconductor chip;
A second layer made of an intermetallic compound containing In as a main component, covering the plurality of porous metal layers and interposed between the upper surface of the chip mounting portion and the first layer;
A semiconductor device. The semiconductor device according to claim 6.
The chip mounting portion is a semiconductor device made of a Cu film or a member having a Cu film on the surface. The semiconductor device according to claim 6.
The chip mounting portion is a semiconductor device comprising a Cu film on which Ag plating, Au plating, or Ni plating is applied, or a member having a Cu film on which Ag plating, Au plating, or Ni plating is applied on the surface. The semiconductor device according to claim 6.
The plurality of porous metal layers are semiconductor devices that are Ag, Cu, or a porous layer made of Ag and Cu. The semiconductor device according to claim 6.
The semiconductor device, wherein a planar area of the plurality of porous metal layers is 40% or more and 80% or less of a planar area of the semiconductor chip. (A) preparing a bonded member having a substrate and a chip mounting portion formed on the main surface of the substrate;
(B) a step of preparing a semiconductor chip having a front surface and a back surface opposite to the front surface and having electrodes formed on the back surface;
(C) a step of forming a plurality of porous metal layers containing metal particles on the upper surface of the chip mounting portion apart from each other;
(D) A step of placing a semiconductor chip on the Sn-based solder after forming Sn-based solder on the upper surface of the chip mounting portion so as to cover the plurality of porous metal layers;
(E) a step of heating while applying pressure between the member to be joined and the semiconductor chip;
Including
The chip mounting portion is made of a Cu film or a member having a Cu film on the surface,
In the step (e),
A first layer made of a Cu-Sn compound is formed in contact with the electrode on the back surface of the semiconductor chip;
A semiconductor that covers the plurality of porous metal layers, and a second layer made of an intermetallic compound containing Sn as a main component is formed between the upper surface of the chip mounting portion and the first layer. Device manufacturing method. The method of manufacturing a semiconductor device according to claim 11.
The chip mounting portion is made of a Cu film subjected to Ag plating, Au plating, or Ni plating, or a member having a Cu film subjected to Ag plating, Au plating, or Ni plating on the surface thereof. Method. The method of manufacturing a semiconductor device according to claim 11.
The semiconductor device manufacturing method, wherein the plurality of porous metal layers are Ag, Cu, or a porous layer made of Ag and Cu.   A power module comprising the semiconductor device according to claim 1.   The vehicle which drives a wheel with the system provided with the power module of Claim 14.