JP2012129330A - Semiconductor device and manufacturing method of the same - Google Patents

Semiconductor device and manufacturing method of the same Download PDF

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Publication number
JP2012129330A
JP2012129330A JP2010278744A JP2010278744A JP2012129330A JP 2012129330 A JP2012129330 A JP 2012129330A JP 2010278744 A JP2010278744 A JP 2010278744A JP 2010278744 A JP2010278744 A JP 2010278744A JP 2012129330 A JP2012129330 A JP 2012129330A
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Japan
Prior art keywords
substrate
porous metal
solder
semiconductor device
bonding material
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Application number
JP2010278744A
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Japanese (ja)
Inventor
Eiji Sakamoto
英次 坂本
Shinichi Fujiwara
伸一 藤原
Takehide Yokozuka
剛秀 横塚
Kaoru Uchiyama
内山　　薫
Shiro Yamashita
志郎 山下
Tokihito Suwa
時人 諏訪
Masahiko Asano
雅彦 浅野
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Hitachi Astemo Ltd
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Hitachi Automotive Systems Ltd
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Priority to JP2010278744A priority Critical patent/JP2012129330A/en
Priority to PCT/JP2011/006416 priority patent/WO2012081167A1/en
Publication of JP2012129330A publication Critical patent/JP2012129330A/en
Pending legal-status Critical Current

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Abstract

PROBLEM TO BE SOLVED: To provide a highly reliable semiconductor device which controls the thickness of a joined part even if a part of a second substrate 4, which is joined to a first substrate 1, is curved.SOLUTION: A joining material joining a fist substrate to a second substrate is composed of a porous metal and solder. The porous metal ranges to both sides in the thickness direction and adjusts a gap between the both substrates in a peripheral part. In a center part, the porous metal exists not in the entire part in the thickness direction. This structure allows a design error caused by a curvature of the substrate to be absorbed with the solder in the center part.

Description

本発明は、多孔質金属とはんだを用いた接合部を有する半導体装置に関する。   The present invention relates to a semiconductor device having a joint using a porous metal and solder.

従来の接合部の厚さ制御としては、接合部にＮｉボール入りのはんだが用いられている（特許文献１参照）、多孔質金属の空孔より大きな空隙のない多孔質金属とはんだが用いられている（特許文献２参照）、金属基板に凹凸形状を設けている（特許文献３参照）ことが知られている。特許文献１は、Niボール入りのシート状のはんだで接合することで、接合部の厚さを制御している。特許文献２は、多孔質金属の空孔より大きな空隙のない多孔質金属とはんだを用いて接合部の厚さを制御している。特許文献３は、金属基板上に凹凸形状を形成し、接合部の厚さを制御している。   As the conventional thickness control of the joint, Ni ball-containing solder is used in the joint (see Patent Document 1), and a porous metal and solder without voids larger than the pores of the porous metal are used. (See Patent Document 2), it is known that the metal substrate is provided with an uneven shape (see Patent Document 3). In Patent Document 1, the thickness of the joint is controlled by joining with a sheet-like solder containing Ni balls. In Patent Document 2, the thickness of the joint is controlled by using a porous metal having no void larger than the pores of the porous metal and solder. In Patent Document 3, a concavo-convex shape is formed on a metal substrate, and the thickness of the joint is controlled.

特許第４３０２６０７号公報Japanese Patent No. 4302607 特開２０００−３４９１００号公報JP 2000-349100 A 特許第３８５３５６６号公報Japanese Patent No. 3853566

ハイブリッド自動車および電気自動車など、動力に電気を使う車両には、電流を制御し高効率な走行を実現するためにインバーターモジュールが搭載されている。インバーターモジュールには、電気を制御するための１０ｍｍ角程度の比較的大きな半導体素子が搭載されているため、接合部の厚さバラつきが大きくなりやすい。接合厚の薄い箇所には応力が集中するため、クラック進展速度が大きくなる。   Vehicles that use electricity for power, such as hybrid vehicles and electric vehicles, are equipped with an inverter module in order to control current and achieve highly efficient driving. Since a relatively large semiconductor element of about 10 mm square for controlling electricity is mounted on the inverter module, the thickness variation of the joint portion tends to increase. Since stress concentrates at the thin joint thickness, the crack growth rate increases.

インバーターモジュールの更なる小型化・ハイパワー化が求められており、ハイパワー化すると素子から多くの熱が放出されるため、高放熱なモジュール構造が必要で、モジュールの小型化・ハイパワー化を実現可能な素子の表裏面から冷却可能な構造（両面冷却構造）が開発されている。両面冷却構造では、半導体素子の表裏をＣｕ、Ｃｕ合金、Ａｌ、Ａｌ合金等の金属基板とはんだで接合する必要があり、接合部の厚さばらつきが大きいと接合厚の薄い箇所ではんだが接合部の外にはみ出し、他方の金属基板と接することで短絡する可能性がある。また、接合厚に大きな差があると、薄い箇所に応力が集中し、クラック進展が促進される。   There is a need for further downsizing and higher power of the inverter module, and when high power is used, a lot of heat is released from the element, so a high heat dissipation module structure is required, and miniaturization and high power of the module are required. A structure that can be cooled from the front and back surfaces of a feasible element (double-side cooling structure) has been developed. In the double-sided cooling structure, it is necessary to join the front and back of the semiconductor element with a metal substrate such as Cu, Cu alloy, Al, Al alloy, etc. with solder. There is a possibility of short-circuiting by protruding outside the part and contacting the other metal substrate. Further, if there is a large difference in the joining thickness, stress concentrates on a thin portion and the crack progress is promoted.

そこで、接合部の厚さを制御できる技術が求められている。ただし、半導体素子や基板は湾曲していることがあるため、湾曲した半導体素子および基板の接合部の厚さを制御する技術が必要である。基板が湾曲している場合接合部全域の厚さを均一にすることは困難なので、接合部の端部から生じるクラックの進展を抑制するために端部の厚さを制御することが重要になる。   Therefore, a technique capable of controlling the thickness of the joint is demanded. However, since the semiconductor element and the substrate may be curved, a technique for controlling the thickness of the junction between the curved semiconductor element and the substrate is necessary. When the substrate is curved, it is difficult to make the thickness of the entire joint portion uniform, so it is important to control the thickness of the end portion in order to suppress the progress of cracks generated from the end portion of the joint portion. .

本発明の目的は、上記課題を解決すべく、接合部の厚さを制御でき、高信頼な半導体装置を提供することにある。   SUMMARY OF THE INVENTION An object of the present invention is to provide a highly reliable semiconductor device that can control the thickness of a bonding portion in order to solve the above problems.

上記目的を達成するために、例えば特許請求の範囲に記載の構成を採用する。本願は上記課題を解決する手段を複数含んでいるが、その一例を挙げるならば、第１及び第２の基板を接合する接合材は、多孔質金属とはんだで構成し、この多孔質金属は、周辺部では厚さ方向の両端まで存在して両基板間の間隔を調整するとともに、、中心部では、厚さ方向全体にわたっては存在しないようにする。   In order to achieve the above object, for example, the configuration described in the claims is adopted. The present application includes a plurality of means for solving the above-described problems. To give an example, the bonding material for bonding the first and second substrates is composed of a porous metal and solder, The peripheral portion exists up to both ends in the thickness direction to adjust the distance between the two substrates, and the central portion does not exist over the entire thickness direction.

本発明によれば、基板や半導体素子が湾曲しているかどうかにかかわらず、接合部を所定の厚さに制御することができる。   According to the present invention, the junction can be controlled to a predetermined thickness regardless of whether the substrate or the semiconductor element is curved.

本発明にかかる実施例１の第１の基板１と第２の基板４を、多孔質金属５を挟持してはんだ３を使って接合した後の接合部の断面図である。It is sectional drawing of the junction part after joining the 1st board | substrate 1 and the 2nd board | substrate 4 of Example 1 concerning this invention using the solder 3 while pinching the porous metal 5. FIG. 本発明にかかる実施例１の第２の基板４の上に多孔質金属５を乗せた後の第１の基板１を接合する側からの平面図である。It is a top view from the side which joins the 1st substrate 1 after putting porous metal 5 on the 2nd substrate 4 of Example 1 concerning the present invention. 本発明にかかる実施例１の第１の基板と第２の基板を、多孔質金属５を挟持してはんだ３を使って接合した後の接合部端部の断面図である。It is sectional drawing of the junction part edge part after joining the 1st board | substrate and 2nd board | substrate of Example 1 concerning this invention using the solder 3 with the porous metal 5 pinched. 本発明にかかる実施例２の多孔質金属５を含んだはんだシートを第２の基板の上に乗せた後の第１の基板１を接合する側からの平面図である。It is a top view from the side which joins the 1st board | substrate 1 after putting the solder sheet containing the porous metal 5 of Example 2 concerning this invention on a 2nd board | substrate. 本発明にかかる実施例３の基板及び発泡金属の平面図である。It is a top view of the board | substrate and foam metal of Example 3 concerning this invention. 本発明にかかる実施例３の基板及び発泡金属の平面図である。It is a top view of the board | substrate and foam metal of Example 3 concerning this invention. 本発明にかかる実施例３の基板及び発泡金属の平面図である。It is a top view of the board | substrate and foam metal of Example 3 concerning this invention. 本発明にかかる実施例４の第１の基板１の表裏面を第２の基板４、第３の基板７で接合した後の接合部の断面図である。It is sectional drawing of the junction part after joining the front and back of the 1st board | substrate 1 of Example 4 concerning this invention with the 2nd board | substrate 4 and the 3rd board | substrate 7. FIG.

以下に実施例を用いて本発明の内容を詳細に説明する。   The contents of the present invention will be described in detail below using examples.

本発明に係る第１の実施の形態について、図１乃至図３を用いて説明する。図１は、第１の基板１と第２の基板４を、接合する領域に多孔質金属５を挟持してはんだ３を使って接合した後の接合部の断面図である。図２は、第２の基板４の上に図１記載の多孔質金属５を置いた後の第１の基板１を接合する側からの平面図である。図３は第１の基板１と第２の基板４を、接合する領域に多孔質金属５を挟持してはんだ３を使って接合した後の接合部端部の断面図である。第１の基板１は、例えば半導体素子であり、ＭＯＳ（Ｍｅｔａｌ Ｏｘｉｄｅ Ｓｅｍｉｃｏｎｄｕｃｔｏｒ）やＩＧＢＴ（Ｉｎｓｕｌａｔｅｄ Ｇａｔｅ Ｂｉｐｏｌａｒ Ｔｒａｎｓｉｓｔｏｒ）、サイリスタ等のパワー半導体素子や、若しくはＦＷＤ（Ｆｒｅｅ Ｗｈｅｅｌｉｎｇ Ｄｉｏｄｅ）等の半導体素子が考えられる。半導体素子は、例えば厚さ０．１ｍｍから０．２ｍｍ程度の薄板状であり、湾曲しており完全な水平基板ではないことが多い。   A first embodiment according to the present invention will be described with reference to FIGS. FIG. 1 is a cross-sectional view of a joint portion after a first substrate 1 and a second substrate 4 are joined using a solder 3 while sandwiching a porous metal 5 in a joining region. FIG. 2 is a plan view from the side where the first substrate 1 is joined after the porous metal 5 shown in FIG. 1 is placed on the second substrate 4. FIG. 3 is a cross-sectional view of the end portion of the joint portion after the first substrate 1 and the second substrate 4 are joined using the solder 3 while sandwiching the porous metal 5 in the joining region. The first substrate 1 is a semiconductor element, for example, a power semiconductor element such as a MOS (Metal Oxide Semiconductor), an IGBT (Insulated Gate Bipolar Transistor), or a thyristor, or a semiconductor element such as a FWD (Free Wheeling Diode). . The semiconductor element is, for example, a thin plate having a thickness of about 0.1 mm to 0.2 mm, is curved, and is often not a complete horizontal substrate.

第１の基板１の接合面側には導体層２が形成されている。導体層２は、３層構造となっており、基板１側から最下層、中層、最上層で構成されている。導体層２における最下層は第１の基板と接触するので、接着力を考慮してＴｉによって形成される。Ｔｉの厚さは約１００ｎｍである。中層は、Ｎｉ、Ｎｉ合金、Ｐｔ、Ｐｔ合金等によって形成され、厚さは約０・５μｍから６μｍである。なお、中層は、基板１がセラミック基板等、半導体素子ではない場合、Ｃｕ合金、Ａｌ合金等によって形成される場合もある。導体層２の最上層は、はんだ接合を可能とするために、Ａｇ、Ａｇ合金、Ａｕ、Ａｕ合金等が使用される。最上層の厚さは約１００ｎｍ〜２００ｎｍの厚さである。   A conductor layer 2 is formed on the bonding surface side of the first substrate 1. The conductor layer 2 has a three-layer structure, and is composed of a lowermost layer, a middle layer, and an uppermost layer from the substrate 1 side. Since the lowermost layer in the conductor layer 2 is in contact with the first substrate, it is formed of Ti in consideration of the adhesive force. The thickness of Ti is about 100 nm. The middle layer is made of Ni, Ni alloy, Pt, Pt alloy or the like, and has a thickness of about 0.5 μm to 6 μm. The intermediate layer may be formed of a Cu alloy, an Al alloy, or the like when the substrate 1 is not a semiconductor element such as a ceramic substrate. The uppermost layer of the conductor layer 2 is made of Ag, Ag alloy, Au, Au alloy or the like in order to enable solder bonding. The thickness of the uppermost layer is about 100 nm to 200 nm.

第２の基板４は、Ｃｕ、Ｃｕ合金、Ａｌ、Ａｌ合金等の金属基板、若しくはＡｌ２Ｏ３、ＡｌＮ、ＳｉＣのいずれかが主成分のセラミック基板である。第２の基板４がＣｕ、Ｃｕ合金、Ａｌ、Ａｌ合金等の金属基板の場合、必ずしも表面に導体層を形成する必要はないが、セラミック基板の場合、接合面側に導体層２と同様の導体層を形成する必要がある。導体層２の表面は、最上層であるＡｇもしくはＡｇ合金、またはＡｕもしくはＡｕ合金のうち少なくとも１種以上の金属が存在していることになるので、第１の基板１と第２の基板４をはんだによって接続することが出来る。 The second substrate 4 is a metal substrate such as Cu, Cu alloy, Al, Al alloy or the like, or a ceramic substrate whose main component is one of Al 2 O 3 , AlN, and SiC. When the second substrate 4 is a metal substrate such as Cu, Cu alloy, Al, Al alloy or the like, it is not always necessary to form a conductor layer on the surface, but in the case of a ceramic substrate, the same as the conductor layer 2 on the bonding surface side It is necessary to form a conductor layer. Since the surface of the conductor layer 2 contains at least one metal of Ag or Ag alloy, which is the uppermost layer, or Au or Au alloy, the first substrate 1 and the second substrate 4 are present. Can be connected by soldering.

第１の基板１と第２の基板４は、はんだ３で接合されており、その接合部の一部には、多孔質金属５が存在している。接合部の多孔質金属５には、はんだ３が含浸され、多孔質金属が元々有する孔は全てはんだ３で充填されている。はんだ３には、Ｓｎを９０ｗｔ％以上含有しているSn系はんだ、若しくはＺｎ−Ａｌ、Ｚｎ−Ａｌ−Ｃｕのはんだが使用される。多孔質金属５には、Ｃｕ、Ｃｕ合金、Ｎｉ、Ｎｉ合金、Ｆｅ、Ｆｅ合金、Ａｌ、Ａｌ合金、Ｍｇ、Ｍｇ合金、Ｔｉ、Ｔｉ合金等の金属が使用される。多孔質金属のはんだと接する面の最表面には、Ｃｕ、Ｃｕ合金、Ｎｉ、Ｎｉ合金、Ａｇ、Ａｇ合金、若しくはＡｕ、Ａｕ合金が形成されている。   The 1st board | substrate 1 and the 2nd board | substrate 4 are joined by the solder 3, and the porous metal 5 exists in a part of the junction part. The porous metal 5 at the joint is impregnated with the solder 3, and all the holes originally possessed by the porous metal are filled with the solder 3. As the solder 3, Sn-based solder containing 90 wt% or more of Sn, or Zn—Al, Zn—Al—Cu solder is used. For the porous metal 5, metals such as Cu, Cu alloy, Ni, Ni alloy, Fe, Fe alloy, Al, Al alloy, Mg, Mg alloy, Ti, Ti alloy and the like are used. Cu, Cu alloy, Ni, Ni alloy, Ag, Ag alloy, Au, or Au alloy is formed on the outermost surface in contact with the porous metal solder.

接合部は、中心部とその周囲の周辺部で構成される。多孔質金属５は、その中心部に、多孔質の孔よりも大きな空洞５ａを有しており、その上に第１の基板１の中心部が位置している。第１の基板及び接合部の周辺部において、多孔質金属５は、接合材厚さ方向の全体（一端から他端まで）にわたって存在しており、第１の基板１は、多孔質金属５及びはんだ３で支持されている。第１の基板１及び接合部の中心部では多孔質金属５が無いため、第１の基板ははんだ３で支持されており、多孔質金属５の上面よりも低い位置まで位置している。すなわち、第1の基板１が湾曲しても、接合部の中心部には多孔質金属５が存在していないため、接合部の厚さには影響を与えない。このため、周辺部における多孔質金属５の厚さに基づいて、第1の基板１の位置及び接合部の厚さが決定される。   The joint portion includes a central portion and a peripheral portion around the central portion. The porous metal 5 has a cavity 5a larger than the porous hole at the center thereof, and the center of the first substrate 1 is positioned thereon. In the peripheral part of the first substrate and the joint part, the porous metal 5 exists over the whole of the joining material thickness direction (from one end to the other end). It is supported by solder 3. Since there is no porous metal 5 at the center of the first substrate 1 and the joint, the first substrate is supported by the solder 3 and is located to a position lower than the upper surface of the porous metal 5. That is, even if the first substrate 1 is curved, the porous metal 5 does not exist at the center of the joint, and therefore the thickness of the joint is not affected. For this reason, the position of the 1st board | substrate 1 and the thickness of a junction part are determined based on the thickness of the porous metal 5 in a peripheral part.

次に、本実施例に係る半導体装置の形成プロセスの概略について説明する。まず、第１の基板１に電極となる導体層２をフォトリソグラフィー技術を用いた半導体プロセスにより形成する。   Next, an outline of a process for forming a semiconductor device according to this embodiment will be described. First, the conductor layer 2 to be an electrode is formed on the first substrate 1 by a semiconductor process using a photolithography technique.

第１の基板１の厚さは例えば、０．０５ｍｍから０．２ｍｍ程度であり、第１の基板１の接合面側に形成された導体層２の厚さは約０・５〜６μｍである。導体層２は、積層構造として、第１の基板１と接触する部分には、第１の基板１との接着性を向上させるために、Ｔｉが１００ｎｍ程度形成される場合もある。第２の基板４の厚さは例えば、１ｍｍから２ｍｍ程度であり、第２の基板４がＣｕ、Ｃｕ合金、Ａｌ、Ａｌ合金等の金属基板の場合、必ずしも表面に導体層を形成する必要はない。   The thickness of the first substrate 1 is, for example, about 0.05 mm to 0.2 mm, and the thickness of the conductor layer 2 formed on the bonding surface side of the first substrate 1 is about 0.5 to 6 μm. . The conductor layer 2 has a laminated structure, and Ti may be formed to a thickness of about 100 nm in a portion in contact with the first substrate 1 in order to improve the adhesion to the first substrate 1. The thickness of the second substrate 4 is, for example, about 1 mm to 2 mm. When the second substrate 4 is a metal substrate such as Cu, Cu alloy, Al, Al alloy, etc., it is not always necessary to form a conductor layer on the surface. Absent.

次に、例えば図２のような枠状の多孔質金属５を第２の基板４上に置く。それを加熱プレートなどの上に配置し、はんだ３の融点以上に加熱しておく。次に、アクチュエータが備わったシリンジでピストンにより、溶融状態のはんだ３が入ったはんだ槽からはんだ３が吸い上げられ、シリンジ内に貯えられる。次に、多孔質金属５を乗せた範囲内にシリンジが移動され、ピストンによりシリンジ内のはんだ３が多孔質金属５の枠内に塗出される。その上から第１の基板１を乗せる。塗出されたはんだ３は第１の基板１と第２の基板４間で濡れ拡がる。その際、塗出されたはんだ３は多孔質金属５の空孔内部に含浸される。その後、冷却してはんだが凝固し、接合完了となる。このはんだ接合プロセスでは、はんだの酸化を抑制するためＮ２等の不活性ガス、Ｈ２等の還元ガス、若しくはその混合ガスで満たされた酸素濃度１００ｐｐｍ以下の雰囲気で行うことが望ましい。接合した状態におけるはんだ３の厚さは例えば、５０μｍから２００μｍである。 Next, for example, a frame-like porous metal 5 as shown in FIG. 2 is placed on the second substrate 4. It is placed on a heating plate or the like and heated above the melting point of the solder 3. Next, the solder 3 is sucked up from the solder tank containing the molten solder 3 by the piston with the syringe provided with the actuator, and stored in the syringe. Next, the syringe is moved within a range where the porous metal 5 is placed, and the solder 3 in the syringe is applied to the frame of the porous metal 5 by the piston. A first substrate 1 is placed thereon. The coated solder 3 spreads between the first substrate 1 and the second substrate 4. At that time, the coated solder 3 is impregnated inside the pores of the porous metal 5. Thereafter, the solder is solidified by cooling, and the joining is completed. This solder bonding process is preferably performed in an atmosphere filled with an inert gas such as N 2 , a reducing gas such as H 2 , or a mixed gas thereof with an oxygen concentration of 100 ppm or less in order to suppress solder oxidation. The thickness of the solder 3 in the joined state is, for example, 50 μm to 200 μm.

なお、本実施例では、多孔質金属５は接合部の中心部において存在せず空洞となっているが、これに限らず、多孔質金属５の中心部を周辺部より薄く形成し、厚さ方向の両端のいずれかに存在しないようにしても足りる。   In the present embodiment, the porous metal 5 does not exist in the central portion of the joint portion and is a cavity. However, the present invention is not limited to this, and the central portion of the porous metal 5 is formed to be thinner than the peripheral portion. It is sufficient that it does not exist at either end of the direction.

以上、本実施例によれば、第１の基板１と第２の基板４の接合部に中心が空洞５ａになった多孔質金属５を挟持し、多孔質金属５の中心付近を空洞５ａとしているため、基板が湾曲していても接合部の端部の厚さを制御できる。   As described above, according to this embodiment, the porous metal 5 having the center of the cavity 5a is sandwiched between the joint portions of the first substrate 1 and the second substrate 4, and the vicinity of the center of the porous metal 5 is defined as the cavity 5a. Therefore, even if the substrate is curved, the thickness of the end of the joint can be controlled.

また、接合部の端部から生じるクラック６の進展を、はんだ３より硬い多孔質金属５で抑制できる。   Further, the progress of the crack 6 generated from the end of the joint can be suppressed by the porous metal 5 that is harder than the solder 3.

また、接合部の多孔質金属５挟持部では、はんだ３より熱伝導率の高い金属を多孔質金属５に採用することで、はんだ３のみで接合する場合より接合部の熱伝導率を上げることができる。   Further, in the sandwiched portion of the porous metal 5, a metal having a higher thermal conductivity than that of the solder 3 is used for the porous metal 5, thereby increasing the thermal conductivity of the joined portion as compared with the case of joining only with the solder 3. Can do.

また、多孔質金属５を使うため、多孔質でなく多孔質金属５と同じ金属を使う場合より接合部のヤング率をはんだ３と同等にできる。   Further, since the porous metal 5 is used, the Young's modulus of the joint can be made equal to that of the solder 3 compared to the case where the same metal as the porous metal 5 is used instead of the porous metal 5.

次に本発明に係わる第２の実施の形態について図４を用いて説明する。第２の実施の形態において、実施例１と相違する点は、第１の基板１と第２の基板４の接合部に挟持する多孔質金属５にあらかじめはんだ３を含浸させておき、図４のような多孔質金属を含んだはんだシート９を作成し、これを接合に使うことである。他の点は、実施例１と同じであり、同様の作用効果を奏する。   Next, a second embodiment according to the present invention will be described with reference to FIG. The second embodiment is different from the first embodiment in that the porous metal 5 sandwiched between the joint portions of the first substrate 1 and the second substrate 4 is impregnated with the solder 3 in advance. The solder sheet 9 containing a porous metal such as that described above is prepared and used for joining. Other points are the same as those of the first embodiment, and the same effects are obtained.

次に、本実施例に係わる半導体装置の形成プロセスの概略について説明する。まず、第１の基板１に電極となる導体層２をフォトリソグラフィー技術を用いた半導体プロセスにより形成する。   Next, an outline of a process for forming a semiconductor device according to this embodiment will be described. First, the conductor layer 2 to be an electrode is formed on the first substrate 1 by a semiconductor process using a photolithography technique.

第１の基板１の厚さは例えば、０．０５ｍｍから０．２ｍｍ程度であり、第１の基板１の接合面側に形成された導体層２の厚さは約０・５〜６μｍである。導体層２は、積層構造として、第１の基板１と接触する部分には、第１の基板１との接着性を向上させるために、Ｔｉが１００ｎｍ程度形成される場合もある。第２の基板４の厚さは例えば、１ｍｍから２ｍｍ程度であり、第２の基板４がＣｕ、Ｃｕ合金、Ａｌ、Ａｌ合金等の金属基板の場合、必ずしも表面に導体層を形成する必要はない。   The thickness of the first substrate 1 is, for example, about 0.05 mm to 0.2 mm, and the thickness of the conductor layer 2 formed on the bonding surface side of the first substrate 1 is about 0.5 to 6 μm. . The conductor layer 2 has a laminated structure, and Ti may be formed to a thickness of about 100 nm in a portion in contact with the first substrate 1 in order to improve the adhesion to the first substrate 1. The thickness of the second substrate 4 is, for example, about 1 mm to 2 mm. When the second substrate 4 is a metal substrate such as Cu, Cu alloy, Al, Al alloy, etc., it is not always necessary to form a conductor layer on the surface. Absent.

次に、図４のような多孔質金属５を含んだシート状のはんだ９を第２の基板４上に乗せる。それを加熱プレートなどの上に配置し、その上に第１の基板１を乗せる。次に、はんだ３の融点以上に加熱する。その後、冷却してはんだが凝固し、接合完了となる。このはんだ接合プロセスでは、はんだの酸化を抑制するためＮ２等の不活性ガス、Ｈ２等の還元ガス、若しくはその混合ガスで満たされた酸素濃度１００ｐｐｍ以下の雰囲気で行うことが望ましい。接合した状態におけるはんだ３の厚さは例えば、５０μｍから２００μｍである。 Next, a sheet-like solder 9 including the porous metal 5 as shown in FIG. 4 is placed on the second substrate 4. It is placed on a heating plate or the like, and the first substrate 1 is placed thereon. Next, the solder 3 is heated to a melting point or higher. Thereafter, the solder is solidified by cooling, and the joining is completed. This solder bonding process is preferably performed in an atmosphere filled with an inert gas such as N 2 , a reducing gas such as H 2 , or a mixed gas thereof with an oxygen concentration of 100 ppm or less in order to suppress solder oxidation. The thickness of the solder 3 in the joined state is, for example, 50 μm to 200 μm.

多孔質金属５は、接合前にあらかじめはんだシート内に含まれるため、多少複雑な形状の多孔質金属５を使うことができる。したがって、上記のような第２の実施の形態とすることで、第１の基板１の水平方向の形状が多少複雑に湾曲していても、接合部の厚さを制御することができる。また、基板の形状に合わせ、はんだが濡れやすく、ボイド率を低減できる形状の多孔質金属５を容易に採用できる。   Since the porous metal 5 is contained in advance in the solder sheet before joining, the porous metal 5 having a somewhat complicated shape can be used. Therefore, by adopting the second embodiment as described above, the thickness of the bonding portion can be controlled even if the horizontal shape of the first substrate 1 is slightly complicated. In addition, the porous metal 5 having a shape that can easily wet the solder and reduce the void ratio can be easily adopted in accordance with the shape of the substrate.

次に本発明に係わる第３の実施の形態について図５乃至図７を用いて説明する。第３の実施の形態において、実施例１と相違する点は、図５乃至図７に示すように、枠状のように連続しておらず、不連続な形状の多孔質金属５を用いることである。本実施例に係わる半導体装置の形成プロセスは、実施例１、実施例２と同様である。   Next, a third embodiment according to the present invention will be described with reference to FIGS. The third embodiment differs from the first embodiment in that a porous metal 5 having a discontinuous shape is used as shown in FIGS. It is. The formation process of the semiconductor device according to this example is the same as that of Example 1 and Example 2.

上記のような第３の実施の形態とすることで、接合時にボイドが接合部の外部に排出されやすくなる。また、第１の基板の湾曲状況に応じ、接合部の厚さを制御できるようになる。   By setting it as the above 3rd Embodiment, it becomes easy to discharge | emit a void to the exterior of a junction part at the time of joining. In addition, the thickness of the joint can be controlled according to the bending state of the first substrate.

次に本発明に係わる第４の実施の形態について図８を用いて説明する。第３の実施の形態は、第１の基板の表裏面と第２の基板４、第３の基板７をはんだ３を使い、多孔質金属５を挟持して接合することである。第３の基板７は第２の基板４と同じ材料を用いるのが好ましいが、必ずしも同じ材料を用いる必要はない。   Next, a fourth embodiment according to the present invention will be described with reference to FIG. In the third embodiment, the front and back surfaces of the first substrate, the second substrate 4 and the third substrate 7 are joined by using the solder 3 and sandwiching the porous metal 5 therebetween. Although it is preferable to use the same material as the second substrate 4 for the third substrate 7, it is not always necessary to use the same material.

第１の基板１と第２の基板４の半導体装置の形成プロセスは、実施例１、実施例２と同様である。第１の基板１と第２の基板４接合後、第３の基板７の半導体装置の形成プロセスは、実施例１、実施例２と同様のプロセスを適用することで、図８の半導体装置を作製できる。ただし、第３の基板７の接合に使うはんだ８の融点は、第１の基板１と第２の基板４の接合に用いたはんだ３の融点以下とする。また、第１の基板１と第２の基板４接合後、第３の基板７を接合する際、第１の基板１の上に第３の基板７を積み重ねて接合してもいいし、第３の基板の上に、第１の基板１で第２の基板４と接合されていない面を乗せて接合してもよい。   The process for forming the semiconductor devices on the first substrate 1 and the second substrate 4 is the same as in the first and second embodiments. After the bonding of the first substrate 1 and the second substrate 4, the semiconductor device of FIG. 8 is formed by applying the same process as that of the first and second embodiments to the process of forming the semiconductor device of the third substrate 7. Can be made. However, the melting point of the solder 8 used for joining the third substrate 7 is not more than the melting point of the solder 3 used for joining the first substrate 1 and the second substrate 4. In addition, when the third substrate 7 is bonded after the first substrate 1 and the second substrate 4 are bonded, the third substrate 7 may be stacked on the first substrate 1 and bonded. A surface of the first substrate 1 that is not bonded to the second substrate 4 may be placed on the third substrate and bonded.

上記のような第４の実施の形態とすることで、半導体装置の放熱性を向上でき、半導体装置の小型化・エネルギーの高密度化を実現できる。   By adopting the fourth embodiment as described above, the heat dissipation of the semiconductor device can be improved, and the semiconductor device can be downsized and the energy density can be increased.

１・・・第１の基板、２・・・導体層、３・・・はんだ（第１の基板と第２の基板の接合部）、４・・・第２の基板、５・・・多孔質金属、６・・・クラック、７・・・第３の基板、８・・・はんだ（第１の基板と第３の基板の接合部）、９・・・多孔質金属を含んだシート状のはんだ。 DESCRIPTION OF SYMBOLS 1 ... 1st board | substrate, 2 ... Conductor layer, 3 ... Solder (joining part of a 1st board | substrate and a 2nd board | substrate), 4 ... 2nd board | substrate, 5 ... Porous 6 ... Crack, 7 ... 3rd substrate, 8 ... Solder (joint part of 1st substrate and 3rd substrate), 9 ... Sheet form containing porous metal Solder.

Claims (10)

第１の基板と、第２の基板と、それらを接合する第１の接合材とを備えた半導体装置において、
前記第１の接合材は、多孔質金属と、前記多孔質金属の内部及び周囲に設けられたはんだとを有し、
前記第１の接合材は、中心部と周辺部とを有し、
前記多孔質金属は、前記第１の接合材の周辺部でその厚さ方向に一端から他端まで延在するするとともに、中心部では、厚さ方向の前記一端または他端のいずれかで存在しておらず、
前記はんだは、前記第１の接合材の中心部及び周辺部に存在していることを特徴とする半導体装置。 In a semiconductor device comprising a first substrate, a second substrate, and a first bonding material for bonding them,
The first bonding material includes a porous metal and solder provided in and around the porous metal,
The first bonding material has a central portion and a peripheral portion;
The porous metal extends from one end to the other end in the thickness direction at the periphery of the first bonding material, and exists at either the one end or the other end in the thickness direction at the center. Not
2. The semiconductor device according to claim 1, wherein the solder is present in a central portion and a peripheral portion of the first bonding material. 請求項１において、
前記第１の接合材の中心部では、前記多孔質金属は存在していないことを特徴とする半導体装置。 In claim 1,
The semiconductor device is characterized in that the porous metal does not exist in the central portion of the first bonding material. 請求項２において、
前記多孔質金属は、枠状に形成されていることを特徴とする半導体装置。 In claim 2,
The semiconductor device, wherein the porous metal is formed in a frame shape. 請求項２において、
前記第１の接合材は、その周辺部に並べられた複数の前記多孔質金属を有していることを特徴とする半導体装置。 In claim 2,
The semiconductor device according to claim 1, wherein the first bonding material includes a plurality of the porous metals arranged in a peripheral portion thereof. 請求項１乃至４のいずれかにおいて、
前記多孔質金属を有する接合部のヤング率が、多孔質金属の母材金属のヤング率より低いことを特徴とする半導体装置。 In any one of Claims 1 thru | or 4,
A semiconductor device characterized in that the Young's modulus of the joint having the porous metal is lower than the Young's modulus of the base metal of the porous metal. 請求項１乃至５において、
前記はんだとして、Ｓｎを９０ｗｔ％以上含有しているはんだ、Ｚｎ−Ａｌ、またはＺｎ−Ａｌ−Ｃｕのはんだを用いることを特徴とする半導体装置。 In claims 1 to 5,
A semiconductor device using a solder containing 90 wt% or more of Sn, Zn—Al, or Zn—Al—Cu solder as the solder. 請求項１乃至６のいずれかにおいて、
第１の基板がＳｉ、ＳｉＮ、ＧａＮ、ＳｉＣが主成分の半導体素子であることを特徴とする半導体装置。 In any one of Claims 1 thru | or 6.
A semiconductor device, wherein the first substrate is a semiconductor element mainly composed of Si, SiN, GaN, and SiC. 請求項１乃至７のいずれかにおいて、多孔質金属のはんだと接する面の最表面に、Ｃｕ、Ｃｕ合金、Ｎｉ、Ｎｉ合金、Ａｇ、Ａｇ合金、若しくはＡｕ、Ａｕ合金が形成されていることを特徴とする半導体装置。   8. The method according to claim 1, wherein Cu, Cu alloy, Ni, Ni alloy, Ag, Ag alloy, or Au, Au alloy is formed on the outermost surface of the surface in contact with the porous metal solder. A featured semiconductor device. 請求項１乃至８のいずれかにおいて、
前記第１の基板の前記第２の基板とは反対側に設けられた第３の基板と、
前記第１の基板と前記第３の基板の基板とを接合する接合材とを備え、
前記第２の接合材は、多孔質金属とはんだとを有し、
その多孔質金属は、その中心部が周辺部より薄い、または中心部に多孔質金属がない空洞部を有している、または、前記第２の接合材の面方向の中心部には、前記多孔質金属が存在していないことを特徴とする半導体装置。 In any one of Claims 1 thru | or 8.
A third substrate provided on the opposite side of the first substrate from the second substrate;
A bonding material for bonding the first substrate and the substrate of the third substrate;
The second bonding material has a porous metal and solder,
The porous metal has a hollow portion in which the central portion is thinner than the peripheral portion or has no porous metal in the central portion, or in the central portion in the surface direction of the second bonding material, A semiconductor device characterized in that no porous metal is present. 第２の基板上に、多孔質金属と溶融したはんだとを有する接合材を設ける工程と、
前記接合材上に第１の基板を設ける工程と、
前記接合材を凝固させて、前記第１の基板と前記第２の基板とを接合する工程とを有する半導体装置の製造方法において、
前記接合材は、中心部と周辺部を有し、
前記多孔質金属は、前記接合材の周辺部でその厚さ方向に一端から他端まで延在するするとともに、中心部では、厚さ方向の前記一端または他端のいずれかで存在しておらず、
前記はんだは、前記接合材の中心部及び周辺部に存在していることを特徴とする半導体装置の製造方法。 Providing a bonding material having a porous metal and molten solder on the second substrate;
Providing a first substrate on the bonding material;
In the method for manufacturing a semiconductor device, comprising solidifying the bonding material and bonding the first substrate and the second substrate.
The bonding material has a central portion and a peripheral portion,
The porous metal extends from one end to the other end in the thickness direction at the periphery of the bonding material, and is present at either the one end or the other end in the thickness direction at the center. Without
The method of manufacturing a semiconductor device, wherein the solder is present in a central portion and a peripheral portion of the bonding material.
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