JP2007201314A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
JP2007201314A
JP2007201314A JP2006020221A JP2006020221A JP2007201314A JP 2007201314 A JP2007201314 A JP 2007201314A JP 2006020221 A JP2006020221 A JP 2006020221A JP 2006020221 A JP2006020221 A JP 2006020221A JP 2007201314 A JP2007201314 A JP 2007201314A
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Prior art keywords
semiconductor element
mounting substrate
bonded
semiconductor device
region
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JP2006020221A
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Japanese (ja)
Inventor
Masanori Usui
正則 臼井
Yasushi Yamada
靖 山田
Koji Hotta
幸司 堀田
Masaki Konishi
正樹 小西
Satoshi Kuwano
聡 桑野
Hiroaki Tanaka
宏明 田中
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Toyota Motor Corp
Toyota Central R&D Labs Inc
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Toyota Motor Corp
Toyota Central R&D Labs Inc
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Priority to JP2006020221A priority Critical patent/JP2007201314A/en
Publication of JP2007201314A publication Critical patent/JP2007201314A/en
Pending legal-status Critical Current

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Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device decreased in difference in an electric resistivity due to positions within a semiconductor element provided in the semiconductor device. <P>SOLUTION: The semiconductor device comprises the semiconductor element 10 having a peripheral part R and a central part C, a mounting substrate 20 of the element 10, and a joint layer 30 for jointing the element 10 to the substrate 20. At least one of the substrate 20 and the layer 30 is nonuniformly structured in a region corresponding to the part R of the element 10 and in a region corresponding to the part C of the element 10. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、半導体素子が接合層によって実装基板に接合されている半導体装置に関し、特に、半導体素子内の位置による電気抵抗率のばらつきが小さい半導体装置に関する。   The present invention relates to a semiconductor device in which a semiconductor element is bonded to a mounting substrate by a bonding layer, and more particularly to a semiconductor device in which variation in electrical resistivity due to a position in the semiconductor element is small.

半導体装置は、一般的に、スイッチング素子等を構成する半導体素子が接合層によって実装基板に接合されている。
例えば、図２２に示すように、特許文献１の半導体装置１００では、半導体素子１１０が接合層１３０によって実装基板１２０に接合されている。実装基板１２０には、半導体素子１１０の冷却を促進するために、熱伝導率の高いＣｕ又はＡｌ等の金属基板が用いられ、接合層１３０には、はんだが用いられる。なお、接合層１３０に、はんだ以外の金属や接着剤等が用いられる場合もある。
特開２００４−８７７３５号公報 Generally, in a semiconductor device, a semiconductor element constituting a switching element or the like is bonded to a mounting substrate by a bonding layer.
For example, as shown in FIG. 22, in the semiconductor device 100 of Patent Document 1, the semiconductor element 110 is bonded to the mounting substrate 120 by the bonding layer 130. For the mounting substrate 120, a metal substrate such as Cu or Al having high thermal conductivity is used to promote cooling of the semiconductor element 110, and solder is used for the bonding layer 130. Note that a metal other than solder, an adhesive, or the like may be used for the bonding layer 130.
JP 200487735 A

半導体素子１１０を接合層１３０によって実装基板１２０に接合する際には、加熱接合することが多い。また、実装基板１２０の主材料（Ｃｕ，Ａｌ等）の線膨張係数は、半導体素子１１０の主材料（Ｓｉ，ＧａＮ等）の線膨張係数よりも大きい場合が多い。接合層１３０の厚みは、半導体素子１１０や実装基板１２０の厚みと比較して薄いので、実装基板１２０と半導体素子１１０の線膨張係数の差が、実装基板１２０と半導体素子１１０の接合状態に影響を及ぼす。半導体素子１１０を実装基板１２０に加熱接合した後に、動作温度（例えば、２０〜３０℃）にまで温度を下げると、半導体素子１１０よりも実装基板１２０の線膨張係数が大きいため、半導体素子１１０に半導体素子１１０を中央部に向けて圧縮する熱応力が発生する。
この場合、半導体素子１１０に発生する熱応力は、半導体素子１１０の周辺部において相対的に小さく、中央部において相対的に大きくなりやすい。半導体素子１１０内の位置によって熱応力の値がばらつくと、ピエゾ抵抗効果によって半導体素子１１０を構成する材料の電気抵抗率が変化することから、半導体素子１１０内の位置によって電気抵抗率がばらついてしまう。すると、半導体素子がオンした際に、電気抵抗率が低い部分に電流が集中し、この部分が局所的に発熱し易い。
本発明は、上記の問題点を解決するために創案された。本発明では、実装基板に接合されている半導体素子の電気抵抗率が半導体素子内の位置によってばらつく度合いが小さい半導体装置を提供する。 When the semiconductor element 110 is bonded to the mounting substrate 120 by the bonding layer 130, it is often heat bonded. Further, the linear expansion coefficient of the main material (Cu, Al, etc.) of the mounting substrate 120 is often larger than the linear expansion coefficient of the main material (Si, GaN, etc.) of the semiconductor element 110. Since the thickness of the bonding layer 130 is thinner than the thickness of the semiconductor element 110 or the mounting substrate 120, the difference in the linear expansion coefficient between the mounting substrate 120 and the semiconductor element 110 affects the bonding state between the mounting substrate 120 and the semiconductor element 110. Effect. After the semiconductor element 110 is thermally bonded to the mounting substrate 120, when the temperature is lowered to an operating temperature (for example, 20 to 30 ° C.), the linear expansion coefficient of the mounting substrate 120 is larger than that of the semiconductor element 110. Thermal stress is generated that compresses the semiconductor element 110 toward the center.
In this case, the thermal stress generated in the semiconductor element 110 is relatively small at the periphery of the semiconductor element 110 and tends to be relatively large at the center. If the value of the thermal stress varies depending on the position in the semiconductor element 110, the electrical resistivity of the material constituting the semiconductor element 110 changes due to the piezoresistive effect, so that the electrical resistivity varies depending on the position in the semiconductor element 110. . Then, when the semiconductor element is turned on, current concentrates on a portion where the electrical resistivity is low, and this portion tends to generate heat locally.
The present invention has been devised to solve the above problems. The present invention provides a semiconductor device in which the electrical resistivity of a semiconductor element bonded to a mounting substrate has a small degree of variation depending on the position in the semiconductor element.

（請求項１に記載の発明）
本発明の半導体装置では、半導体素子が接合層によって実装基板に接合されている。本発明の半導体装置では、接合層と実装基板の少なくとも一方が、半導体素子の周辺部に接合している領域と半導体素子の中央部に接合している領域とで、材料組成が異なっていることを特徴とする。
ここでいう「半導体素子の周辺部」は、半導体素子の周囲の全範囲を意味する場合もあれば、半導体素子の周囲の一部の範囲を意味する場合もある。たとえば、半導体素子の平面形状が略四角形に形成されている場合には、四辺に隣接する範囲であることもあれば、対向する二辺に隣接する範囲のみであることもある。「半導体素子の中央部」は、半導体素子の周辺部に囲まれている範囲を意味する場合もあれば、中心を含む範囲であって上記した「周辺部」以外の全ての範囲を意味する場合もあれば、「周辺部」以外の一部の範囲を意味する場合もある。典型的には、「中央部」には、半導体素子の主動作領域が配設されており、「周辺部」には、主動作領域が配設されていない。「周辺部」には、例えば周辺耐圧領域やワイヤ等とのボンディング領域が形成されている。 (Invention of Claim 1)
In the semiconductor device of the present invention, the semiconductor element is bonded to the mounting substrate by the bonding layer. In the semiconductor device of the present invention, the material composition of at least one of the bonding layer and the mounting substrate is different between the region bonded to the peripheral portion of the semiconductor element and the region bonded to the central portion of the semiconductor element. It is characterized by.
The “peripheral portion of the semiconductor element” as used herein may mean the entire range around the semiconductor element, or it may mean a partial range around the semiconductor element. For example, when the planar shape of the semiconductor element is formed in a substantially square shape, it may be a range adjacent to four sides or only a range adjacent to two opposite sides. “Central part of the semiconductor element” may mean a range surrounded by the peripheral part of the semiconductor element, or may mean a range including the center and other than the above “peripheral part” In other cases, it may mean a part of the range other than the “peripheral portion”. Typically, the main operation region of the semiconductor element is disposed in the “central portion”, and the main operation region is not disposed in the “peripheral portion”. In the “peripheral portion”, for example, a peripheral pressure-resistant region or a bonding region with a wire or the like is formed.

従来の技術の欄で記載したように、一般的に、半導体素子を接合層によって実装基板に加熱接合した後に温度を下げると、半導体素子に熱応力が発生する。実装基板の材料組成が一様であり、接合層の材料組成が一様であると、半導体素子の中心に近いほど半導体素子に発生する熱応力が大きくなる。
本発明の半導体装置の場合、接合層と実装基板の少なくとも一方では、半導体素子の周辺部に接合している領域と半導体素子の中央部に接合している領域とで、材料組成が変えてある。材料組成を変えることによって、熱応力が集中しやすい半導体装置の中央部では実装基板による機械的拘束力を弱め、熱応力が集中しづらい半導体装置の周辺部では実装基板による機械的拘束力を強めることができる。これにより、半導体素子は周辺部において相対的に強固に実装基板に固定され、中央部では相対的にフリーな状態におかれる。これによって、半導体素子を実装基板に確実に接合するとともに、中心に近い程大きくなっていた熱応力の分布を一様化することができる。したがって、ピエゾ抵抗効果によって、電気抵抗率が半導体素子内の位置によってばらついてしまう現象の発生を抑制することができる。半導体素子がオン状態の際に、応力集中とピエゾ抵抗効果によって、電気抵抗率が低くなった部分に電流が集中し、この部分が局所的に発熱するのを防止することができる。 As described in the section of the prior art, generally, when the temperature is lowered after the semiconductor element is heated and bonded to the mounting substrate with the bonding layer, thermal stress is generated in the semiconductor element. If the material composition of the mounting substrate is uniform and the material composition of the bonding layer is uniform, the closer to the center of the semiconductor element, the greater the thermal stress generated in the semiconductor element.
In the case of the semiconductor device of the present invention, at least one of the bonding layer and the mounting substrate has a different material composition between the region bonded to the peripheral portion of the semiconductor element and the region bonded to the central portion of the semiconductor element. . By changing the material composition, the mechanical restraint force due to the mounting substrate is weakened at the center of the semiconductor device where thermal stress is likely to concentrate, and the mechanical restraint force due to the mounting substrate is strengthened at the periphery of the semiconductor device where thermal stress is difficult to concentrate. be able to. Thereby, the semiconductor element is relatively firmly fixed to the mounting substrate in the peripheral portion, and is relatively free in the central portion. As a result, the semiconductor element can be reliably bonded to the mounting substrate, and the distribution of thermal stress that has become larger as it is closer to the center can be made uniform. Therefore, it is possible to suppress the occurrence of the phenomenon that the electric resistivity varies depending on the position in the semiconductor element due to the piezoresistance effect. When the semiconductor element is in the ON state, current can be prevented from being concentrated in a portion where the electrical resistivity is low due to stress concentration and the piezoresistive effect, and this portion can be prevented from generating heat locally.

（請求項２に記載の発明）
半導体素子と実装基板を接合する接合層が、半導体素子の周辺部を実装基板に接合している領域では引っ張り強度が高い材料組成を有し、半導体素子の中央部を実装基板に接合している領域では引っ張り強度が低い材料組成を有していてもよい。
この場合、半導体素子は、周辺部において強く拘束され、中央部では弱く拘束される。従って、半導体素子は、周辺部において強く拘束された状態で実装基板に接合される。この場合、半導体素子の中心に近づくほど熱応力が発達する現象が抑制される。半導体素子内の位置によって熱応力が大きく分布する現象を抑制することができる。 (Invention of Claim 2)
The bonding layer for bonding the semiconductor element and the mounting substrate has a material composition having high tensile strength in the region where the peripheral portion of the semiconductor element is bonded to the mounting substrate, and the central portion of the semiconductor element is bonded to the mounting substrate. The region may have a material composition with low tensile strength.
In this case, the semiconductor element is strongly restrained at the peripheral portion and weakly restrained at the central portion. Therefore, the semiconductor element is bonded to the mounting substrate in a state of being strongly restrained at the peripheral portion. In this case, a phenomenon in which thermal stress develops as the position approaches the center of the semiconductor element is suppressed. A phenomenon in which thermal stress is largely distributed depending on the position in the semiconductor element can be suppressed.

（請求項３に記載の発明）
半導体素子と実装基板を接合する接合層が、半導体素子の周辺部を実装基板に接合している領域では融点が高い材料組成を有し、半導体素子の中央部を実装基板に接合している領域では融点が低い材料組成を有していてもよい。
この場合、半導体素子の周辺部は高い温度状態で実装基板に拘束され、中央部は低い温度状態で実装基板に拘束される。すなわち、半導体素子の周辺部が実装基板に拘束される時の温度と半導体素子の動作温度の差に比して、半導体素子の中央部が実装基板に拘束される時の温度と半導体素子の動作温度の差は小さい。半導体素子に加わる熱応力は、前記の温度差が小さいほど小さい。従って、半導体素子の中央部において、大きな熱応力が発達することを防止できる。半導体素子内の位置によって熱応力が大きく分布する現象を抑制することができる。 (Invention of Claim 3)
A region in which the bonding layer for bonding the semiconductor element and the mounting substrate has a material composition with a high melting point in the region where the peripheral portion of the semiconductor element is bonded to the mounting substrate, and the central portion of the semiconductor element is bonded to the mounting substrate Then, you may have a material composition with low melting | fusing point.
In this case, the peripheral portion of the semiconductor element is restrained by the mounting substrate at a high temperature state, and the central portion is restrained by the mounting substrate at a low temperature state. That is, the temperature when the central part of the semiconductor element is restrained by the mounting substrate and the operation of the semiconductor element, compared to the difference between the temperature when the peripheral part of the semiconductor element is restrained by the mounting substrate and the operating temperature of the semiconductor element. The difference in temperature is small. The thermal stress applied to the semiconductor element is smaller as the temperature difference is smaller. Therefore, it is possible to prevent a large thermal stress from developing in the central portion of the semiconductor element. A phenomenon in which thermal stress is largely distributed depending on the position in the semiconductor element can be suppressed.

（請求項４に記載の発明）
実装基板が、接合層によって半導体素子の周辺部に接合している領域では線膨張係数が大きい材料組成を有し、接合層によって半導体素子の中央部を接合している領域では線膨張係数が小さい材料組成を有していてもよい。
この場合、半導体素子を実装基板に加熱接合してから半導体素子の動作温度にまで温度を下げた場合に、半導体素子の中央部が接合される実装基板では収縮率が小さいに対し、半導体素子の周辺部が接合される実装基板では収縮率が大きい。従って、半導体素子の中央部において熱応力が発達する程度が低減される。半導体素子内の位置によって熱応力が大きく分布する現象を抑制することができる。 (Invention of Claim 4)
The region where the mounting substrate is bonded to the peripheral portion of the semiconductor element by the bonding layer has a material composition having a large linear expansion coefficient, and the region where the central portion of the semiconductor element is bonded by the bonding layer is small. It may have a material composition.
In this case, when the temperature is lowered to the operating temperature of the semiconductor element after the semiconductor element is heated and bonded to the mounting substrate, the shrinkage rate is small in the mounting substrate to which the central portion of the semiconductor element is bonded, whereas The shrinkage rate is large in the mounting substrate to which the peripheral part is bonded. Therefore, the degree to which the thermal stress develops in the central portion of the semiconductor element is reduced. A phenomenon in which thermal stress is largely distributed depending on the position in the semiconductor element can be suppressed.

（請求項５に記載の発明）
実装基板を多孔質の母材で構成することができ、多孔質の母材の孔に母材とは相違する線膨張係数を有する部材を配設することができる。この場合、接合層によって半導体素子の周辺部に接合されている領域と、接合層によって半導体素子の中央部に接合されている領域とで、前記孔に配設されている部材の量を相違させることによって、半導体素子の周辺部に接合されている実装基板の線膨張係数の方が、半導体素子の中央部に接合されている実装基板の線膨張係数よりも大きくすることができる。
本発明の半導体装置によれば、半導体素子の周辺部に接合されている実装基板の線膨張係数と中央部に接合されている実装基板の線膨張係数の関係を簡単に調節することができる。 (Invention of Claim 5)
The mounting substrate can be formed of a porous base material, and a member having a linear expansion coefficient different from that of the base material can be disposed in the hole of the porous base material. In this case, the amount of the member disposed in the hole is different between the region bonded to the peripheral portion of the semiconductor element by the bonding layer and the region bonded to the central portion of the semiconductor element by the bonding layer. Accordingly, the linear expansion coefficient of the mounting substrate bonded to the peripheral portion of the semiconductor element can be made larger than the linear expansion coefficient of the mounting substrate bonded to the central portion of the semiconductor element.
According to the semiconductor device of the present invention, the relationship between the linear expansion coefficient of the mounting substrate bonded to the peripheral portion of the semiconductor element and the linear expansion coefficient of the mounting substrate bonded to the central portion can be easily adjusted.

多孔質の母材の孔に、母材よりも大きな線膨張係数を有する部材を配設してもよいし、小さな線膨張係数を有する部材を配設してもよい。小さな線膨張係数を有する部材を配設する場合には、例えば以下の構成を採用することができる。
典型的には、母材の孔は基本的に同じサイズとし、半導体素子の周辺部に対応する領域では孔の密度を低くし、中央部に対応する領域では孔の密度を高くする。この場合、全ての孔に母材よりも小さい線膨張係数を有する部材を含浸すると、半導体素子の周辺部が接合される領域では小さな線膨張係数を有する部材が少量存在するのに対し、半導体素子の中央部が接合される領域では小さな線膨張係数を有する部材が多量に存在する関係を得ることができる。
あるいは、母材の孔は基本的に同じサイズとし、孔の密度を実装基板の全体に亘って均一としてもよい。この場合、半導体素子の周辺部に対応する領域では少ない孔に母材よりも小さい線膨張係数を有する部材を配設し、中央部に対応する領域では多くの孔に母材よりも小さい線膨張係数を有する部材を配設する。こうしても、半導体素子の周辺部が接合される領域では小さな線膨張係数を有する部材が少量存在するのに対し、半導体素子の中央部が接合される領域では小さな線膨張係数を有する部材が多量に存在する関係を得ることができる。
あるいは、孔の密度を実装基板の全体に亘って均一とする一方、半導体素子の周辺部に対応する領域では孔のサイズを小さくし、中央部に対応する領域では孔のサイズを大きくする。こうしても、半導体素子の周辺部が接合される領域では小さな線膨張係数を有する部材が少量存在するのに対し、半導体素子の中央部が接合される領域では小さな線膨張係数を有する部材が多量に存在する関係を得ることができる。
いずれによっても、半導体素子の周辺部に接合されている実装基板の線膨張係数の方が、半導体素子の中央部に接合されている実装基板の線膨張係数よりも大きいという関係を得ることができる。 A member having a larger linear expansion coefficient than that of the base material may be disposed in the hole of the porous base material, or a member having a smaller linear expansion coefficient may be disposed. In the case of disposing a member having a small linear expansion coefficient, for example, the following configuration can be employed.
Typically, the holes in the base material are basically the same size, and the hole density is lowered in the region corresponding to the peripheral portion of the semiconductor element, and the hole density is increased in the region corresponding to the central portion. In this case, when all the holes are impregnated with a member having a linear expansion coefficient smaller than that of the base material, there is a small amount of a member having a small linear expansion coefficient in the region where the peripheral portion of the semiconductor element is joined. It is possible to obtain a relationship in which a large amount of members having a small linear expansion coefficient exist in the region where the central portions of the two are joined.
Alternatively, the holes in the base material may be basically the same size, and the density of the holes may be uniform over the entire mounting board. In this case, a member having a smaller linear expansion coefficient than that of the base material is disposed in a small number of holes in the region corresponding to the peripheral portion of the semiconductor element, and a smaller linear expansion than that of the base material is provided in many holes in the region corresponding to the central portion. A member having a coefficient is disposed. Even in this case, there are a small number of members having a small linear expansion coefficient in the region where the peripheral portion of the semiconductor element is bonded, whereas there are a large number of members having a small linear expansion coefficient in the region where the central portion of the semiconductor element is bonded. An existing relationship can be obtained.
Alternatively, the hole density is made uniform over the entire mounting substrate, while the hole size is reduced in the region corresponding to the peripheral portion of the semiconductor element, and the hole size is increased in the region corresponding to the central portion. Even in this case, there are a small number of members having a small linear expansion coefficient in the region where the peripheral portion of the semiconductor element is bonded, whereas there are a large number of members having a small linear expansion coefficient in the region where the central portion of the semiconductor element is bonded. An existing relationship can be obtained.
In any case, it is possible to obtain a relationship that the linear expansion coefficient of the mounting substrate bonded to the peripheral portion of the semiconductor element is larger than the linear expansion coefficient of the mounting substrate bonded to the central portion of the semiconductor element. .

本発明によれば、半導体素子内の位置による電気抵抗率のばらつきが小さな半導体装置を提供することができる。   ADVANTAGE OF THE INVENTION According to this invention, the semiconductor device with a small dispersion | variation in the electrical resistivity by the position in a semiconductor element can be provided.

以下に説明する実施例の主要な特徴を列記しておく。
（第１実施形態）半導体素子は上面略四角形であって、半導体素子の周辺部とは、半導体素子の四辺に隣接する範囲を示す。
（第２実施形態）半導体素子は上面略四角形であって、半導体素子の周辺部とは、半導体素子の対向する二辺に隣接する範囲を示す。
（第３実施形態）半導体素子の最周辺部と周辺部と中央部とでは、異なる融点を有する接合部材で実装基板に接合されている。
（第４実施形態）半導体素子の周辺部を実装基板に接合する接合部材の融点は、半導体素子の最周辺部を実装基板に接合する接合部材の融点よりも低く、半導体素子の中央部を実装基板に接合する接合部材の融点よりも高い。
（第５実施形態）半導体素子の周辺部と中央部は、実装基板の異なる線膨張係数を有する領域に接合されている。
（第６実施形態）実装基板は、異なる線膨張係数を有する基板部材が組み合わされて形成され、領域によって異なる線膨張係数を有している。半導体素子の周辺部は実装基板の線膨張係数が大きい領域に接合されており、半導体素子の中央部は実装基板の線膨張係数が小さい領域に接合されている。 The main features of the embodiments described below are listed.
(First Embodiment) The semiconductor element has a substantially rectangular top surface, and the peripheral portion of the semiconductor element indicates a range adjacent to the four sides of the semiconductor element.
Second Embodiment A semiconductor element has a substantially rectangular top surface, and the peripheral portion of the semiconductor element indicates a range adjacent to two opposing sides of the semiconductor element.
(Third Embodiment) The outermost peripheral portion, the peripheral portion, and the central portion of the semiconductor element are bonded to the mounting substrate with bonding members having different melting points.
(Fourth Embodiment) The melting point of a joining member that joins the peripheral part of a semiconductor element to a mounting substrate is lower than the melting point of a joining member that joins the outermost peripheral part of the semiconductor element to the mounting substrate, and the central part of the semiconductor element is mounted. It is higher than the melting point of the bonding member bonded to the substrate.
(Fifth Embodiment) A peripheral portion and a central portion of a semiconductor element are joined to regions having different linear expansion coefficients of a mounting substrate.
(Sixth Embodiment) A mounting board is formed by combining board members having different linear expansion coefficients, and has different linear expansion coefficients depending on regions. The peripheral portion of the semiconductor element is bonded to a region where the linear expansion coefficient of the mounting substrate is large, and the central portion of the semiconductor element is bonded to a region where the linear expansion coefficient of the mounting substrate is small.

（第１実施例）
以下に第１実施例の半導体装置１を図１〜図６を参照して説明する。第１実施例の半導体装置には、スイッチング素子等を構成する半導体素子が設けられている。そして、半導体素子の周辺部を実装基板に接合する接合部材と、半導体素子の中央部を実装基板に接合する接合部材の引っ張り強度が相違する。
図１には、半導体装置１の要部分解図が模式的に示されている。図２〜図４は、半導体素子が実装基板に接合される工程を示す。図５は、実装基板に接合した半導体素子に発生する熱応力を示す斜視図である。図６では、半導体装置１の上面図と、半導体素子内の位置に対応する熱応力の分布を示す。 (First embodiment)
The semiconductor device 1 according to the first embodiment will be described below with reference to FIGS. The semiconductor device of the first embodiment is provided with a semiconductor element constituting a switching element or the like. And the tensile strength of the joining member which joins the peripheral part of a semiconductor element to a mounting substrate, and the joining member which joins the center part of a semiconductor element to a mounting board differ.
FIG. 1 schematically shows an exploded view of the main part of the semiconductor device 1. 2 to 4 show a process in which the semiconductor element is bonded to the mounting substrate. FIG. 5 is a perspective view showing thermal stress generated in the semiconductor element bonded to the mounting substrate. FIG. 6 shows a top view of the semiconductor device 1 and a distribution of thermal stress corresponding to the position in the semiconductor element.

図１に示すように、半導体装置１では、上面略正方形の半導体素子１０が接合層３０によって実装基板２０に接合されている。接合層３０は、上面から見て、半導体素子１０よりも若干大きい略正方形となっている。
本実施例の半導体素子１０は、主にＳｉ（シリコン）により構成されている。半導体素子１０の中央部Ｃには、図示していないが、半導体素子１０の主動作領域が配設されている。半導体素子１０の四辺に隣接する周辺部Ｒには、電極パッド等が配設されている。
実装基板２０は、主にＣｕ（銅）又はＡｌ（アルミニウム）等の熱伝導率の高い金属で構成されている。
接合層３０は２種類の材料からなり、略正方形の四辺に沿って、枠形状の第１接合部材３１が設けられている。第１接合部材３１の中央の開口には、第２接合部材３２が設けられている。第１接合部材３１の引っ張り強度Ｔ１（Ｐａ）は、第２接合部材３２の引っ張り強度Ｔ２（Ｐａ）よりも大きい（Ｔ１＞Ｔ２）。第１接合部材３１の引っ張り強度Ｔ１（Ｐａ）は、２００（ＭＰａ）以上であることが好ましい。第１接合部材３１としては、ＡｕＳｎ，ＡｕＳｉ，ＡｕＧｅ等の材料が用いられる。第２接合部材３２の引っ張り強度Ｔ２（Ｐａ）は、１０（ＭＰａ）以下であることが好ましい。第２接合部材３２には、Ａｇ系のエポキシ導電性接着材（Ａｇ：８５％〜９０％、エポキシ：１５％〜１０％）等が用いられる。 As shown in FIG. 1, in the semiconductor device 1, the semiconductor element 10 having a substantially square top surface is bonded to the mounting substrate 20 by the bonding layer 30. The bonding layer 30 has a substantially square shape that is slightly larger than the semiconductor element 10 when viewed from above.
The semiconductor element 10 of the present embodiment is mainly composed of Si (silicon). Although not shown, a main operation region of the semiconductor element 10 is disposed in the central portion C of the semiconductor element 10. In the peripheral portion R adjacent to the four sides of the semiconductor element 10, electrode pads and the like are disposed.
The mounting substrate 20 is mainly made of a metal having high thermal conductivity such as Cu (copper) or Al (aluminum).
The bonding layer 30 is made of two kinds of materials, and a frame-shaped first bonding member 31 is provided along the substantially square four sides. A second joint member 32 is provided in the central opening of the first joint member 31. The tensile strength T1 (Pa) of the first joining member 31 is greater than the tensile strength T2 (Pa) of the second joining member 32 (T1> T2). The tensile strength T1 (Pa) of the first joining member 31 is preferably 200 (MPa) or more. A material such as AuSn, AuSi, or AuGe is used for the first bonding member 31. The tensile strength T2 (Pa) of the second bonding member 32 is preferably 10 (MPa) or less. For the second bonding member 32, an Ag-based epoxy conductive adhesive (Ag: 85% to 90%, epoxy: 15% to 10%) or the like is used.

次に図２〜図４を用いて、半導体素子１０を実装基板２０に接合する工程を説明する。図２〜図４は、図１のII−II線に対応する半導体装置１０の断面図である。
まず図２に示すように、実装基板２０の上面に、枠形状の第１接合部材３１と枠内に嵌まる第２接合部３２を載置する。
次に図３に示すように、半導体素子１０の中央部Ｃを第２接合部材３２の上に配置するとともに、半導体素子１０の周辺部Ｒを第１接合部材３１の上に配置する。そして、温度を、第１接合部材３１の融点と第２接合部材３２の融点のいずれよりも高い温度にまで上昇させる。
すると図４に示すように、第１接合部材３１と第２接合部材３２は溶融する。その後に温度が下げられることによって、第１接合部材３１と第２接合部材３２は再び固化する。これにより、半導体素子１０は接合層３０によって実装基板２０に接合（加熱接合）される。 Next, the process of joining the semiconductor element 10 to the mounting substrate 20 will be described with reference to FIGS. 2 to 4 are cross-sectional views of the semiconductor device 10 corresponding to the line II-II in FIG.
First, as shown in FIG. 2, a frame-shaped first bonding member 31 and a second bonding portion 32 that fits in the frame are placed on the upper surface of the mounting substrate 20.
Next, as shown in FIG. 3, the central portion C of the semiconductor element 10 is disposed on the second bonding member 32, and the peripheral portion R of the semiconductor element 10 is disposed on the first bonding member 31. Then, the temperature is raised to a temperature higher than both the melting point of the first bonding member 31 and the melting point of the second bonding member 32.
Then, as shown in FIG. 4, the first joining member 31 and the second joining member 32 are melted. Thereafter, the temperature is lowered, whereby the first joining member 31 and the second joining member 32 are solidified again. As a result, the semiconductor element 10 is bonded (heat bonded) to the mounting substrate 20 by the bonding layer 30.

ここで、実装基板の線膨張係数をＴＣＥｓｕｂ、Ｓｉの線膨張係数をＴＣＥｓｉ、半導体素子を実装基板に実装する際の加熱温度をＴｐａｃｋ、半導体装置の動作温度をＴｏｐ、Ｓｉのヤング率をＹｓｉとすると、図５に示す半導体素子１０のｘ方向及び−ｘ方向に発生する熱応力σｘと、ｙ方向及び−ｙ方向に作用する熱応力σｙの絶対値は、それぞれ（式１）によって算出される。
σｘ，σｙの絶対値＝ＡＢＳ［（ＴＣＥｓｕｂ−ＴＣＥｓｉ）×（Ｔｐａｃｋ−Ｔｏｐ）×Ｙｓｉ］
・・・（式１） Here, the linear expansion coefficient of the mounting substrate is TCE sub , the linear expansion coefficient of Si is TCE si , the heating temperature when mounting the semiconductor element on the mounting substrate is T pack , the operating temperature of the semiconductor device is T op , and the Si Young When the rate is Y si , the absolute values of the thermal stress σ x generated in the x direction and the −x direction and the thermal stress σ y acting in the y direction and the −y direction of the semiconductor element 10 shown in FIG. Calculated by equation 1).
Absolute value of σ x , σ y = ABS [(TCE sub −TCE si ) × (T pack −T op ) × Y si ]
... (Formula 1)

本実施例の実装基板２０を構成している金属は、半導体素子１０を構成しているＳｉよりも線膨張係数ＴＣＥが大きい（ＴＣＥｓｕｂ＞ＴＣＥｓｉ）。この場合、熱応力σｘ，σｙは負の値となり、図５に示すように、半導体素子１０を中心方向に圧縮する圧縮応力が発生する。
なお、実際の半導体素子１０では、接合層が一様な場合には、半導体素子の中心に近い程、機械的拘束力が強くなる。これに対応して、接合層が一様な場合には、図６の太い破線（σｘ２，σｙ２）で示すように、実際の熱応力の絶対値は、半導体素子１０の中心に近い程大きくなる。
半導体素子に応力が発生すると、ピエゾ抵抗効果によって、応力の大きさに応じて半導体素子の電気抵抗率が変化することが知られている。
例えば図５に示すように、電流が−ｚ方向に流れる半導体素子１０（縦型半導体素子）の場合、熱応力σｘ，σｙが発生すると、−ｚ方向の電気抵抗率は、下記の（式２）に示す変化割合で変化する。
電気抵抗率が変化割合＝［（ピエゾ抵抗係数５３．４×１０−１１）×（σｘ＋σｙ）］
・・・（式２）
熱応力σｘ，σｙが、図５、図６に示すような圧縮応力である場合（熱応力σｘ，σｙが負の値となる場合）、熱応力σｘと熱応力σｙの絶対値が大きくなる程、−ｚ方向の電気抵抗率は（式２）で算出される割合をもって小さくなる。したがって、接合層が一様な場合には、実際の電気抵抗率は、半導体素子の中心に近い程小さくなる。そこで、−ｚ方向に流れる電流は、半導体素子の中央部に集中し、中央部が集中的に発熱する現象が生じる。 The metal constituting the mounting substrate 20 of the present example has a linear expansion coefficient TCE larger than that of the Si constituting the semiconductor element 10 (TCE sub > TCE si ). In this case, the thermal stresses σ x and σ y have negative values, and as shown in FIG. 5, a compressive stress that compresses the semiconductor element 10 in the central direction is generated.
In the actual semiconductor element 10, when the bonding layer is uniform, the closer to the center of the semiconductor element, the stronger the mechanical binding force. Correspondingly, when the bonding layer is uniform, the absolute value of the actual thermal stress is closer to the center of the semiconductor element 10 as shown by the thick broken lines (σ x2 , σ y2 ) in FIG. growing.
When stress is generated in a semiconductor element, it is known that the electrical resistivity of the semiconductor element changes according to the magnitude of the stress due to the piezoresistive effect.
For example, as shown in FIG. 5, in the case of the semiconductor element 10 (vertical semiconductor element) in which current flows in the −z direction, when thermal stresses σ x and σ y are generated, the electrical resistivity in the −z direction is It changes at the change rate shown in Equation 2).
Electric resistivity change rate = [(piezoresistance coefficient 53.4 × 10 −11 ) × (σ x + σ y )]
... (Formula 2)
When the thermal stresses σ x and σ y are compressive stresses as shown in FIGS. 5 and 6 (when the thermal stresses σ x and σ y are negative values), the thermal stress σ x and the thermal stress σ y As the absolute value increases, the electrical resistivity in the −z direction decreases with the ratio calculated by (Equation 2). Therefore, when the bonding layer is uniform, the actual electrical resistivity becomes smaller as it is closer to the center of the semiconductor element. Therefore, a current flowing in the −z direction is concentrated in the central portion of the semiconductor element, and a phenomenon occurs in which the central portion generates heat intensively.

一方、実施例１の半導体装置１を用いれば、半導体素子１０の周辺部Rが、引っ張り強度の大きい第１接合部材３１によって、実装基板２０に強く拘束された状態となっている。これに対応して、図６の太い実線（σｘ１，σｙ１）で示すように、第１接合部材３１によって実装基板２０に接合されている領域（周辺部Ｒ）では、熱応力σｘ１，σｙ１の絶対値が半導体素子の中心に近づくほど大きくなっているものの、第２接合部材３２によって実装基板２０に接合されている領域（中央部Ｃ）では、熱応力σｘ１，σｙ１の絶対値が半導体素子内の位置に無関係にほぼ一定値に維持されている。
熱応力が分布していなければ、電気抵抗率も分布しない。したがって、半導体装置１を用いれば、半導体素子１０内の中央部Ｃにおいて電気抵抗率が局所的に減少し、大電流が局所的に流れて局所的に発熱する現象の発生を抑制することができる。 On the other hand, when the semiconductor device 1 according to the first embodiment is used, the peripheral portion R of the semiconductor element 10 is strongly restrained by the mounting substrate 20 by the first bonding member 31 having a high tensile strength. Correspondingly, as indicated by thick solid lines (σ x1 , σ y1 ) in FIG. 6, in the region (peripheral portion R) bonded to the mounting substrate 20 by the first bonding member 31, the thermal stress σ x1 , Although the absolute value of σ y1 increases as it approaches the center of the semiconductor element, the absolute values of the thermal stresses σ x1 and σ y1 in the region (central portion C) bonded to the mounting substrate 20 by the second bonding member 32. The value is maintained at a substantially constant value regardless of the position in the semiconductor element.
If the thermal stress is not distributed, the electrical resistivity is not distributed. Therefore, if the semiconductor device 1 is used, it is possible to suppress the occurrence of a phenomenon in which the electrical resistivity is locally reduced at the central portion C in the semiconductor element 10 and a large current flows locally to generate heat locally. .

前述したように、中央部Ｃに半導体素子１０の主動作領域が配設されている。周辺部Ｒには、電極パッド等が配設されている。したがって、周辺部Ｒでは、その位置によって電気抵抗率が変化していても、半導体素子１０の動作には影響が少ない。本実施例の半導体装置１によれば、半導体素子１０の周辺部Ｒが集中的に拘束された状態で実装基板２０に確実に接合されるとともに、中央部Ｃの機械的拘束力が弱められることで、中央部Ｃの中心に近づくほど発達していた熱応力が発達するのを抑制することができる。これにより、中央部Ｃでは、位置によって電気抵抗率が相違する度合いを低減することができる。したがって、半導体素子１０がオン状態の際に、主動作領域の電気抵抗率が低い部分に電流が集中し、この部分が局所的に発熱するのを防止することができる。   As described above, the main operation region of the semiconductor element 10 is disposed in the central portion C. In the peripheral portion R, electrode pads and the like are disposed. Therefore, in the peripheral portion R, even if the electric resistivity changes depending on the position, the operation of the semiconductor element 10 is less affected. According to the semiconductor device 1 of the present embodiment, the peripheral portion R of the semiconductor element 10 is reliably bonded to the mounting substrate 20 in a state of being intensively constrained, and the mechanical constraining force of the central portion C is weakened. Thus, it is possible to suppress the development of the thermal stress that has been developed as it approaches the center of the central portion C. Thereby, in the center part C, the degree to which an electrical resistivity changes with positions can be reduced. Therefore, when the semiconductor element 10 is in the ON state, it is possible to prevent current from concentrating on a portion having a low electrical resistivity in the main operation region and locally generating heat.

（第２実施例）
次に第２実施例の半導体装置１ａを図７、図８を参照して説明する。
半導体装置１ａでは、半導体素子１０の対向する二辺に隣接する範囲が集中的に拘束された状態で実装基板２０に接合されている。
図７には、半導体装置１ａの要部分解図が模式的に示されている。図８では、半導体装置１ａの上面図と、半導体素子１０内の位置に対応する熱応力の分布を示す。 (Second embodiment)
Next, a semiconductor device 1a according to a second embodiment will be described with reference to FIGS.
In the semiconductor device 1a, the range adjacent to the two opposite sides of the semiconductor element 10 is bonded to the mounting substrate 20 in a state of being intensively constrained.
FIG. 7 schematically shows an essential part exploded view of the semiconductor device 1a. FIG. 8 shows a top view of the semiconductor device 1 a and a distribution of thermal stress corresponding to the position in the semiconductor element 10.

図７に示すように、半導体装置１ａでは、上面略正方形の半導体素子１０が接合層３０ａによって実装基板２０に接合されている。
本実施例の半導体素子１０は、主にＳｉ（シリコン）により構成されている。半導体素子１０の中央部Ｃａには、スイッチング素子等が配設され、半導体素子１０の主動作領域が構成されている。半導体素子１０の対向する二辺に隣接する周辺部Ｒａには、電極パッド等が配設されている。本実施例の半導体素子１０と実装基板２０は、実施例１の半導体装置１と同様の構成であるので説明を省略し、図７，８中では同じ符号を用いている。
接合層３０ａは、半導体素子１０のｙ方向に伸びる対向する二辺に沿って伸びるストライプ状の第１接合部材３１ａを備えている。第１接合部材３１ａの間には、第２接合部材３２ａが設けられている。第１接合部材３１ａの引っ張り強度Ｔ１（Ｐａ）は、第２接合部材３２ａの引っ張り強度Ｔ２（Ｐａ）よりも大きい（Ｔ１＞Ｔ２）。
半導体装置１ａについて、半導体素子１０を実装基板２０に接合する工程は、実装基板２０に載置する接合層３０ａの構成が相違するだけで、あとは実施例１の半導体装置１と同様であるので、説明を省略する。
第１接合部材３１ａによって半導体素子１０ａの周辺部Ｒａが実装基板２０に接合される。また、第２接合部材３２ａによって半導体素子１０ａの中央部Ｃａが実装基板２０に接合される。 As shown in FIG. 7, in the semiconductor device 1a, the semiconductor element 10 having a substantially square top surface is bonded to the mounting substrate 20 by the bonding layer 30a.
The semiconductor element 10 of the present embodiment is mainly composed of Si (silicon). A switching element or the like is disposed in the central portion Ca of the semiconductor element 10, and a main operation region of the semiconductor element 10 is configured. An electrode pad or the like is disposed in the peripheral portion Ra adjacent to the two opposite sides of the semiconductor element 10. Since the semiconductor element 10 and the mounting substrate 20 of the present embodiment have the same configuration as the semiconductor device 1 of the first embodiment, description thereof is omitted, and the same reference numerals are used in FIGS.
The bonding layer 30 a includes a stripe-shaped first bonding member 31 a extending along two opposing sides extending in the y direction of the semiconductor element 10. A second bonding member 32a is provided between the first bonding members 31a. The tensile strength T1 (Pa) of the first joining member 31a is greater than the tensile strength T2 (Pa) of the second joining member 32a (T1> T2).
Regarding the semiconductor device 1a, the process of bonding the semiconductor element 10 to the mounting substrate 20 is the same as the semiconductor device 1 of the first embodiment except that the configuration of the bonding layer 30a placed on the mounting substrate 20 is different. The description is omitted.
The peripheral portion Ra of the semiconductor element 10a is bonded to the mounting substrate 20 by the first bonding member 31a. Further, the central portion Ca of the semiconductor element 10 a is bonded to the mounting substrate 20 by the second bonding member 32 a.

実施例２の半導体装置１ａを用いれば、半導体素子１０は、引っ張り強度の大きい第１接合部材３１ａによって対向する二辺に隣接する周辺部Ｒａが集中的に拘束された状態となっている。これに対応して、ｘ方向及び−ｘ方向では、図８の太い実線（σｘ１ａ）で示すように、第１接合部材３１ａによって実装基板２０に接合されている領域（周辺部Ｒａ）では、熱応力σｘ１ａの絶対値が半導体素子の中心に近づくほど大きくなっているのに対し、第２接合部材３２ａによって実装基板２０に接合されている領域（中央部Ｃａ）では、熱応力σｘ１ａの絶対値は半導体素子内の位置に無関係にほぼ一定値に維持されている。
また、ｘ方向での中央部Ｃａにおけるｙ方向に沿った断面では、半導体素子１０ａの周辺部Ｒｚは第２接合部材３２ａで実装基板に接合されており、周辺部Ｒｚで集中的に拘束されているわけでない。しかしながら、第２接合部材３２ａの引っ張り強度Ｔ２が低いので、図８の太い実線（σｙ１ａ）で示すように、大きな熱応力は発生しない。なお、周辺部Ｒａにおけるｙ方向に沿った断面では、全てが第１接合部材３１ａで接合されており、強固に拘束されている。したがって、図８の太い破線（σｙ２）で示すような熱応力σｙ２が発生する。しかしながら、その部分は半導体素子１０の主動作領域でなく、大きな熱応力が作用しても特段の問題は生じない。
図８に示す中央部Ｃａのように、熱応力σｘ１ａに変化がない部分では、電気抵抗率の変化はない。したがって、半導体装置１ａを用いれば、半導体素子１０ａの中央部Ｃａ内の位置によって電気抵抗率が分布する度合いを低減することができる。また、図８に示す中央部Ｃａのように、ｙ方向の熱応力（σｙ１ａ）が小さければ、電気抵抗率はほとんど変化しない。 If the semiconductor device 1a according to the second embodiment is used, the semiconductor element 10 is in a state where the peripheral portion Ra adjacent to the two opposite sides is intensively restrained by the first bonding member 31a having a high tensile strength. Correspondingly, in the x direction and the −x direction, as shown by the thick solid line (σ x1a ) in FIG. 8, in the region (peripheral portion Ra) bonded to the mounting substrate 20 by the first bonding member 31a, Whereas the absolute value of the thermal stress σ x1a increases toward the center of the semiconductor element, the thermal stress σ x1a of the region (center portion Ca) bonded to the mounting substrate 20 by the second bonding member 32a is larger . The absolute value is maintained at a substantially constant value regardless of the position in the semiconductor element.
In the cross section along the y direction at the central portion Ca in the x direction, the peripheral portion Rz of the semiconductor element 10a is bonded to the mounting substrate by the second bonding member 32a, and is intensively restrained by the peripheral portion Rz. I'm not there. However, since the tensile strength T2 of the second joining member 32a is low, no large thermal stress is generated as shown by the thick solid line (σ y1a ) in FIG. In addition, in the cross section along the y direction in the peripheral portion Ra, all are joined by the first joining member 31a and are firmly restrained. Therefore, a thermal stress σ y2 as shown by a thick broken line (σ y2 ) in FIG. 8 is generated. However, that portion is not the main operating region of the semiconductor element 10, and no particular problem occurs even if a large thermal stress is applied.
As in the central portion Ca shown in FIG. 8, there is no change in the electrical resistivity in the portion where the thermal stress σ x1a is not changed. Therefore, if the semiconductor device 1a is used, it is possible to reduce the degree of distribution of electrical resistivity depending on the position in the central portion Ca of the semiconductor element 10a. Moreover, if the thermal stress (σ y1a ) in the y direction is small as in the central portion Ca shown in FIG. 8, the electrical resistivity hardly changes.

図１の半導体装置１と図７の半導体装置１ａは、ｚ方向に電流が流れる縦型の半導体素子であるが、本発明は、図９に示すように、ｘ方向に電流が流れる横型の半導体装置１ｂにも適用することができる。半導体装置１ｂの接合層３０ｂは、半導体装置１ａの接合層３０ａと同様に構成されている。接合層３０ｂは、半導体素子のｘ方向に伸びる対向する二辺に沿って伸びるストライプ状の第１接合部材３１ｂを備えている。第１接合部材３１ｂの間には、第２接合部材３２ｂが設けられている。半導体素子１０ｂは、ｙ方向の両端に位置する周辺部Ｒｂが、集中的に拘束された状態となっている。これによって、ｙ方向及び−ｙ方向の熱応力σｙ１ｂが発生し、ｘ方向及び−ｘ方向の熱応力はほとんど発生しない。 The semiconductor device 1 in FIG. 1 and the semiconductor device 1a in FIG. 7 are vertical semiconductor elements in which current flows in the z direction. However, the present invention is a lateral semiconductor in which current flows in the x direction as shown in FIG. The present invention can also be applied to the device 1b. The bonding layer 30b of the semiconductor device 1b is configured similarly to the bonding layer 30a of the semiconductor device 1a. The bonding layer 30b includes a stripe-shaped first bonding member 31b extending along two opposing sides extending in the x direction of the semiconductor element. A second joining member 32b is provided between the first joining members 31b. The semiconductor element 10b is in a state where peripheral portions Rb located at both ends in the y direction are intensively restrained. As a result, thermal stress σ y1b in the y direction and −y direction is generated, and almost no thermal stress in the x direction and −x direction is generated.

一般的に、接合層や実装基板が一様であれば、ｘ方向とｙ方向に熱応力σｘ，σｙが発生する。この応力によって、ｘ方向の電気抵抗率が変化する割合が、下記の（式３）で算出される。
電気抵抗率が変化する割合＝ピエゾ抵抗係数（−１０２．２×１０−１１）×σｘ
＋ピエゾ抵抗係数（５３．４×１０−１１）×σｙ・・・（式３）
これは、熱応力σｘと熱応力σｙが、図９に示すように圧縮応力である場合（熱応力σｘとσｙが負の値の場合）、熱応力σｘの絶対値が大きくなる程、ｘ方向の電気抵抗率は（式３）で算出される割合をもって大きくなることを示している。また、熱応力σｙの絶対値が大きくなる程、ｘ方向の電気抵抗率は、（式３）で算出される割合をもって小さくなることを示している。 In general, if the bonding layer and the mounting substrate are uniform, thermal stresses σ x and σ y are generated in the x and y directions. The rate at which the electrical resistivity in the x direction changes due to this stress is calculated by the following (Equation 3).
Ratio of change in electrical resistivity = piezoresistance coefficient (−102.2 × 10 −11 ) × σ x
+ Piezoresistance coefficient (53.4 × 10 −11 ) × σ y (Expression 3)
This is because when the thermal stress σ x and the thermal stress σ y are compressive stresses as shown in FIG. 9 (when the thermal stresses σ x and σ y are negative values), the absolute value of the thermal stress σ x is large. As shown, the electrical resistivity in the x direction increases with the ratio calculated by (Equation 3). Further, it is shown that the electrical resistivity in the x direction decreases with the ratio calculated by (Equation 3) as the absolute value of the thermal stress σ y increases.

半導体装置１ｂでは、図９に示すようにｙ方向の熱応力σｙ１ｂが、半導体素子１０ｂを圧縮する方向に発生する。ｘ方向の熱応力σｘ１ｂは小さい。
したがって、図９に示す半導体装置１ｂの場合には、下記式が得られる。
ｘ方向の電気抵抗率が変化する割合＝ピエゾ抵抗係数（５３．４×１０−１１）×σｙ１ｂ
半導体装置１ｂでは、この割合をもって、熱応力σｙ１ｂの絶対値が大きくなる程、ｘ方向の電気抵抗率が小さくなる。これにより、半導体装置１ｂは、周辺部Ｒｂで確実に実装基板２０に接合されているとともに、通電方向であるｘ方向の抵抗が大きくなることがなく、オン状態の際の損失が少ない。このように、半導体装置１ｂでは、一方向に発生する熱応力を積極的に利用している。 In the semiconductor device 1b, as shown in FIG. 9, a thermal stress σ y1b in the y direction is generated in a direction in which the semiconductor element 10b is compressed. The thermal stress σ x1b in the x direction is small.
Therefore, in the case of the semiconductor device 1b shown in FIG. 9, the following equation is obtained.
Ratio of change in electrical resistivity in x direction = piezoresistance coefficient (53.4 × 10 −11 ) × σ y1b
In the semiconductor device 1b, the electrical resistivity in the x direction decreases as the absolute value of the thermal stress σ y1b increases with this ratio. As a result, the semiconductor device 1b is reliably bonded to the mounting substrate 20 at the peripheral portion Rb, the resistance in the x direction, which is the energization direction, does not increase, and the loss in the on state is small. Thus, in the semiconductor device 1b, the thermal stress generated in one direction is actively used.

また、本発明は、図１０に示すようなｘ方向に電流が流れる横型の半導体装置１ｃにも適用することができる。半導体装置１ｃの接合層３０ｃは、半導体装置１ａの接合層３０ａと同様に構成されている。接合層３０ｃは、半導体素子のｙ方向に伸びる対向する二辺に沿って伸びるストライプ状の第１接合部材３１ｃを備えている。第１接合部材３１ｃの間には、第２接合部材３２ｃが設けられている。半導体素子１０ｃは、ｘ方向の両端に存在する周辺部Ｒｃで、集中的に拘束された状態となっている。これによって、ｘ方向及び−ｘ方向の熱応力σｘ１ｃが発生し、ｙ方向及び−ｙ方向の熱応力はほとんど発生しない。 The present invention can also be applied to a lateral semiconductor device 1c in which current flows in the x direction as shown in FIG. The bonding layer 30c of the semiconductor device 1c is configured similarly to the bonding layer 30a of the semiconductor device 1a. The bonding layer 30c includes first stripe-shaped bonding members 31c extending along two opposing sides extending in the y direction of the semiconductor element. A second joining member 32c is provided between the first joining members 31c. The semiconductor element 10c is in a state of being intensively constrained at the peripheral portion Rc existing at both ends in the x direction. As a result, thermal stress σ x1c in the x direction and −x direction is generated, and thermal stress in the y direction and −y direction is hardly generated.

したがって、図１０に示す半導体装置１ｃの場合には、下記式が得られる。
ｘ方向の電気抵抗率が変化する割合＝ピエゾ抵抗係数（−１０２．２×１０−１１）×σｘ１ｃ
半導体装置１ｃでは、この割合をもって、熱応力σｘ１ｃの絶対値が大きくなる程、ｘ方向の電気抵抗率が大きくなる。これにより、半導体装置１ｃは、周辺部Ｒｃで確実に実装基板２０に接合されているとともに、通電方向であるｘ方向の抵抗が大きくなり、短絡負荷時の破壊耐量が高い。このように、半導体装置１ｃでは、一方向に発生する熱応力を積極的に利用している。 Therefore, in the case of the semiconductor device 1c shown in FIG.
Ratio of change in electric resistivity in x direction = piezoresistance coefficient (−102.2 × 10 −11 ) × σ x1c
In the semiconductor device 1c, with this ratio, the electrical resistivity in the x direction increases as the absolute value of the thermal stress σ x1c increases. As a result, the semiconductor device 1c is reliably bonded to the mounting substrate 20 at the peripheral portion Rc, the resistance in the x direction, which is the energization direction, is increased, and the breakdown resistance during a short-circuit load is high. Thus, in the semiconductor device 1c, the thermal stress generated in one direction is actively used.

（第３実施例）
次に第３実施例の半導体装置１ｄを図１１〜図１８を参照して説明する。
半導体装置１ｄでは、半導体素子１０の周辺部Ｒを実装基板２０に接合する接合部材の融点と、半導体素子１０の中央部Ｃを実装基板２０に接合する接合部材の融点が相違している。
図１１には、半導体装置１ｄの要部分解図が模式的に示されている。図１２〜図１７には、半導体素子が実装基板に接合される工程を示す。図１８では、半導体装置１ｄ内の位置に対応する電気抵抗率の分布を示す。 (Third embodiment)
Next, a semiconductor device 1d according to a third embodiment will be described with reference to FIGS.
In the semiconductor device 1d, the melting point of the bonding member that bonds the peripheral portion R of the semiconductor element 10 to the mounting substrate 20 is different from the melting point of the bonding member that bonds the central portion C of the semiconductor element 10 to the mounting substrate 20.
FIG. 11 schematically shows an essential part exploded view of the semiconductor device 1d. 12 to 17 show a process in which the semiconductor element is bonded to the mounting substrate. FIG. 18 shows a distribution of electrical resistivity corresponding to a position in the semiconductor device 1d.

図１１に示すように、半導体装置１ｄには、上面略正方形の半導体素子１０が接合層３０ｄによって実装基板２０に接合されている。接合層３０ｄは、上面から見て、半導体素子１０よりも若干大きい略正方形となっている。
本実施例の半導体素子１０、実装基板２０は、第１実施例の半導体装置１と同様であるので、説明を省略する。
接合層３０ｄには、略枠状であるとともに、1辺に間隔ｄの開口部を有する第３接合部材３１ｄが設けられている。第３接合部材３１ｄの中央部には、第４接合部材３２ｄが設けられている。第３接合部材３１ｄの融点Ｔｍ１（℃）は、第４接合部材３２ｄの融点Ｔｍ２（℃）よりも高い（Ｔｍ１（℃）＞Ｔｍ２（℃））。第３接合部材３１ｄには、ＡｕＳｎ，ＡｕＳｉ，ＡｕＧｅ等の部材が用いられる。第４接合部材３２ｄには、ＳｎＡｇ，ＰｂＳｎ（Ｐｂは５０パーセント以下），ＳｎＣｕ，ＳｎＩｎ，ＳｎＢｉ等の部材が用いられる。 As shown in FIG. 11, in the semiconductor device 1d, the semiconductor element 10 having a substantially square top surface is bonded to the mounting substrate 20 by the bonding layer 30d. The bonding layer 30d has a substantially square shape that is slightly larger than the semiconductor element 10 when viewed from above.
Since the semiconductor element 10 and the mounting substrate 20 of this embodiment are the same as those of the semiconductor device 1 of the first embodiment, description thereof is omitted.
The bonding layer 30d is provided with a third bonding member 31d having a substantially frame shape and having an opening with a distance d on one side. A fourth bonding member 32d is provided at the center of the third bonding member 31d. The melting point Tm1 (° C.) of the third bonding member 31d is higher than the melting point Tm2 (° C.) of the fourth bonding member 32d (Tm1 (° C.)> Tm2 (° C.)). A member such as AuSn, AuSi, or AuGe is used for the third bonding member 31d. A member such as SnAg, PbSn (Pb is 50% or less), SnCu, SnIn, SnBi, or the like is used for the fourth bonding member 32d.

次に、図１２〜図１７を用いて、半導体素子１０を実装基板２０に接合する工程を説明する。
図１２に示すように、まず、実装基板２０の上面にソルダーレジスト４０をパターンニングして配設する。ソルダーレジスト４０は、第３接合部材３１ｄと第４接合部材３２ｄと同じ厚みか、あるいはそれ以上の厚み（図１２に示す上下方向の寸法）に形成する。ソルダーレジスト４０には、第３接合部材３１ｄの形状に対応する溝４１が設けられている。
次に、図１３に示すように、溝４１に第３接合部材３１ｄを配置する。第３接合部材３１ｄには、間隔ｄのゲートＧが設けられている。そして、その上に半導体素子１０を載置する。
この状態で、第３接合部材３１ｄの融点よりも高い温度にまで加熱し、図１４に示すように、半導体素子１０を実装基板２０に加熱接合する。
次に図１５に示すように、ソルダーレジスト４０を除去する。これにより、第４接合部材３２ｄの溶融材料が注入される中空部が形成されるとともに、第４接合部材３２ｄの溶融材料を注入可能なゲートＧ(幅ｄ)が形成される。
そして図１６に示すように、ゲートＧから、第４接合部材３２ｄの融点よりも高い温度にまで加熱することで溶融させた第４接合部材３２ｄを注入する。溶融材料は毛細管現象によって中空部に広がる。その後温度を下げることによって、第４接合部材３２ｄが固化する。以上によって熱接合が完成する。 Next, the process of joining the semiconductor element 10 to the mounting substrate 20 will be described with reference to FIGS.
As shown in FIG. 12, first, a solder resist 40 is patterned and disposed on the upper surface of the mounting substrate 20. The solder resist 40 is formed to have the same thickness as or larger than the third bonding member 31d and the fourth bonding member 32d (the vertical dimension shown in FIG. 12). The solder resist 40 is provided with a groove 41 corresponding to the shape of the third bonding member 31d.
Next, as shown in FIG. 13, the third bonding member 31 d is disposed in the groove 41. The third bonding member 31d is provided with a gate G having a distance d. And the semiconductor element 10 is mounted on it.
In this state, heating is performed to a temperature higher than the melting point of the third bonding member 31d, and the semiconductor element 10 is heat bonded to the mounting substrate 20 as shown in FIG.
Next, as shown in FIG. 15, the solder resist 40 is removed. Thereby, a hollow portion into which the molten material of the fourth bonding member 32d is injected is formed, and a gate G (width d) into which the molten material of the fourth bonding member 32d can be injected is formed.
Then, as shown in FIG. 16, the fourth bonding member 32d melted by heating from the gate G to a temperature higher than the melting point of the fourth bonding member 32d is injected. The molten material spreads in the hollow part by capillary action. Thereafter, the fourth bonding member 32d is solidified by lowering the temperature. Thus, the thermal bonding is completed.

ここで、実装基板の線膨張係数をＴＣＥｓｕｂ、Ｓｉの線膨張係数をＴＣＥｓｉ、第３接合部材３１ｄの融点をＴｍ１、第４接合部材３２ｄの融点をＴｍ２、半導体装置の動作時の温度をＴｏｐ（２０℃〜３０℃程度）、Ｓｉのヤング率をＹｓｉとすると、第３接合部材３１ｄにより接合された周辺部Ｒ（４辺の周辺）に作用する熱応力σ１、第４接合部材３２ｄにより接合された中央部Ｃに作用する熱応力σ２の絶対値は、それぞれ下記（式４）によって算出される。熱応力σ１及び熱応力σ２は、半導体素子１０を圧縮する方向に発生する。
熱応力σｉの絶対値＝ＡＢＳ［（ＴＣＥｓｕｂ−ＴＣＥｓｉ）×（Ｔｍｉ−Ｔｏｐ）×Ｙｓｉ］
ここで、ｉは１または２である （式４）
前述したように、融点Ｔｍ１（℃）＞融点Ｔｍ２（℃）であるので、（式４）より、熱応力σ１の絶対値＞熱応力σ２の絶対値となる。したがって、接合層３０ｄを、一様に第３接合部材３１ｄによって形成した場合と比較して、半導体素子１０の中央部Ｃに発生する熱応力の絶対値を低減することができる。 Here, the linear expansion coefficient of the mounting substrate is TCE sub , the linear expansion coefficient of Si is TCE si , the melting point of the third bonding member 31d is Tm1 , the melting point of the fourth bonding member 32d is Tm2, and the temperature during operation of the semiconductor device is If T op (about 20 ° C. to 30 ° C.) and the Si Young's modulus is Y si , the thermal stress σ 1 acting on the peripheral portion R (around the four sides) joined by the third joining member 31d, the fourth joining The absolute value of the thermal stress σ 2 acting on the central portion C joined by the member 32d is calculated by the following (Equation 4). The thermal stress σ 1 and the thermal stress σ 2 are generated in the direction in which the semiconductor element 10 is compressed.
Absolute value of thermal stress σ i = ABS [(TCE sub −TCE si ) × (T m i−T op ) × Y si ]
Here, i is 1 or 2 (Formula 4)
As described above, since melting point Tm1 (° C.)> Melting point Tm2 (° C.), from Equation 4, the absolute value of thermal stress σ 1 > the absolute value of thermal stress σ 2 . Therefore, the absolute value of the thermal stress generated in the central portion C of the semiconductor element 10 can be reduced as compared with the case where the bonding layer 30d is uniformly formed by the third bonding member 31d.

半導体素子１０は、−ｚ方向に電流が流れる縦型半導体素子であるので、熱応力σ１，σ２が発生すると、−ｚ方向の電気抵抗率が変化する。その割合が、（式５）で算出される。
−ｚ方向の電気抵抗率が変化する割合＝［（ピエゾ抵抗係数５３．４×１０−１１）×σｉ］
ここで、ｉは１または２である （式５）
これにより、熱応力σ１の絶対値＞熱応力σ２の絶対値の場合、図１８に示すように、中央部Ｃの電気抵抗率の変化を低減することができる。 Since the semiconductor element 10 is a vertical semiconductor element in which a current flows in the −z direction, when the thermal stresses σ 1 and σ 2 are generated, the electrical resistivity in the −z direction changes. The ratio is calculated by (Equation 5).
Ratio of change in electrical resistivity in −z direction = [(piezoresistance coefficient 53.4 × 10 −11 ) × σ i ]
Here, i is 1 or 2 (Formula 5)
Thereby, when the absolute value of the thermal stress σ 1 > the absolute value of the thermal stress σ 2 , as shown in FIG. 18, the change in the electrical resistivity of the central portion C can be reduced.

このように、第３実施例の半導体装置１ｄを用いれば、半導体素子１０の中央部Ｃ内の位置による電気抵抗率の変化の度合いを低減することができる。したがって、半導体素子１０がオン状態の際に、主動作領域の電気抵抗率が低い部分に電流が集中し、この部分が局所的に発熱するのを防止することができる。   Thus, if the semiconductor device 1d of the third embodiment is used, the degree of change in electrical resistivity due to the position in the central portion C of the semiconductor element 10 can be reduced. Therefore, when the semiconductor element 10 is in the ON state, it is possible to prevent current from concentrating on a portion having a low electrical resistivity in the main operation region and locally generating heat.

第３実施例では、接合層３０ｄに、融点が相違する２種類の接合部材、すなわち第３接合部材３１ｄと第４接合部材３２ｄが設けられている場合について説明した。接合層には、融点が相違する３種類以上の接合部材が設けられていてもよい。例えば、接合層に３種類の接合部材が設けられている場合、図１１に示す接合層３０ｄのように二重ではなく、三重（最周辺部対応領域、周辺部対応領域、中央部対応領域）に構成される。そして、外側ほど融点が高い材料で接合部材が形成される。この構成によれば、半導体素子１０が接合層によって実装基板２０に接合される際の機械的拘束力（クランプ力）、及び半導体素子１０に発生する熱応力の大きさの両者を満足する値に調整し易い。   In the third embodiment, the case where the bonding layer 30d is provided with two types of bonding members having different melting points, that is, the third bonding member 31d and the fourth bonding member 32d has been described. The bonding layer may be provided with three or more types of bonding members having different melting points. For example, when three types of bonding members are provided in the bonding layer, they are not double like the bonding layer 30d shown in FIG. 11 but triple (most peripheral area corresponding area, peripheral area corresponding area, central area corresponding area). Configured. And a joining member is formed with the material whose melting | fusing point is so high that it is an outer side. According to this configuration, the value satisfies both the mechanical restraint force (clamping force) when the semiconductor element 10 is bonded to the mounting substrate 20 by the bonding layer and the magnitude of the thermal stress generated in the semiconductor element 10. Easy to adjust.

（第４実施例）
次に第４実施例の半導体装置１ｅを図１９を参照して説明する。
半導体装置１ｅでは、半導体素子１０の周辺部Ｒが接合される実装基板の領域（周辺部対応領域）の線膨張係数が、中央部Ｃが接合される実装基板の領域（中央部対応領域）の線膨張係数と相違する。
図１９には、半導体装置１ｅの要部断面図と、実装基板２０ｅの位置に対応する線膨張係数ＴＣＥの分布を示す。 (Fourth embodiment)
Next, a semiconductor device 1e according to a fourth embodiment will be described with reference to FIG.
In the semiconductor device 1e, the linear expansion coefficient of the mounting substrate region (peripheral portion corresponding region) to which the peripheral portion R of the semiconductor element 10 is bonded is equal to that of the mounting substrate region (central portion corresponding region) to which the central portion C is bonded. It is different from the linear expansion coefficient.
FIG. 19 shows a cross-sectional view of the main part of the semiconductor device 1e and the distribution of the linear expansion coefficient TCE corresponding to the position of the mounting substrate 20e.

図１９に示すように、半導体装置１ｅには、上面略正方形の半導体素子１０が実装基板２０ｅに接合層３０ｅで接合されている。接合層３０ｅは、上面から見て、半導体素子１０よりも若干大きく形成されている。
本実施例の半導体素子１０は、第１実施例と同様であるので、説明を省略する。本実施例の接合層３０ｅは、一様な部材で形成されている。
実装基板２０ｅは、周辺部Ｒ側ほど、多数の孔２１ｅが形成された多孔体の孔２１ｅに多孔体と異なる材料を含浸させた材料で構成されている。含浸させた材料は多孔体の材料よりも、線膨張係数が大きい。多孔体の材料には、タングステン、Ｍｏ，ＳｉＣ等が用いられる。多孔体の孔２１ｅに含浸させる材料には、Ｃｕ，Ａｌ等が用いられる。多孔体に設ける孔２１ｅの数は、作業温度や、冷却条件、雰囲気等により制御可能であることが知られている。この実施例では、２種類の材料を組み合わせて用いる点では、半導体素子の周辺部に接合している領域と半導体素子の中央部に接合している領域とで異ならない。ただし、組成比が相違する。これもまた、半導体素子の周辺部に接合している領域と半導体素子の中央部に接合している領域とで材料組成が異なることに相当する。 As shown in FIG. 19, in the semiconductor device 1e, the semiconductor element 10 having a substantially square top surface is bonded to the mounting substrate 20e with a bonding layer 30e. The bonding layer 30e is formed to be slightly larger than the semiconductor element 10 when viewed from above.
Since the semiconductor element 10 of this embodiment is the same as that of the first embodiment, description thereof is omitted. The bonding layer 30e of the present embodiment is formed of a uniform member.
The mounting substrate 20e is made of a material obtained by impregnating a material different from the porous body into the porous hole 21e in which a large number of holes 21e are formed toward the peripheral portion R side. The impregnated material has a larger linear expansion coefficient than the porous material. Tungsten, Mo, SiC or the like is used as the porous material. Cu, Al or the like is used as a material to be impregnated into the pores 21e of the porous body. It is known that the number of holes 21e provided in the porous body can be controlled by operating temperature, cooling conditions, atmosphere, and the like. In this embodiment, the combination of two kinds of materials does not differ between the region bonded to the peripheral portion of the semiconductor element and the region bonded to the central portion of the semiconductor element. However, the composition ratio is different. This also corresponds to the difference in material composition between the region bonded to the peripheral portion of the semiconductor element and the region bonded to the central portion of the semiconductor element.

一般的に、一様な実装基板に一様な接合層で接合された半導体素子には、半導体素子の中心に近い程熱応力による影響が大きくなる。本実施例の半導体装置１ｅでは、周辺部対応領域と中央部対応領域とで、単位体積あたりの実装基板に配設する材料（多孔体の材料よりも線膨張係数の大きい）の量を異ならせることによって、周辺部対応領域の線膨張係数の方が中央部対応領域の線膨張係数よりも大きくなるように構成している。
この実施例では、半導体素子１０の周辺部Ｒ側を接合する領域ほど、実装基板２０ｅの線膨張係数が大きい。したがって、周辺部Ｒ側と比較して中央部Ｃの方が機械的拘束力が小さく、周辺部Ｒで集中的にクランプされた状態となって実装基板２０ｅに接合されている。これにより、半導体素子１０の中央部Ｃ内の位置による熱応力の変化の度合いを低減することができる。熱応力の変化の度合いが低減されれば、電気抵抗率の変化の度合いも低減される。したがって、半導体装置１ｅを用いれば、半導体素子１０内の位置による電気抵抗率の相違を低減することができる。
また、第４実施例の半導体装置１ｅによれば、実装基板の周辺部対応領域と中央部対応領域の線膨張係数を簡単に調節することができる。 In general, a semiconductor element bonded to a uniform mounting substrate with a uniform bonding layer is more affected by thermal stress as it is closer to the center of the semiconductor element. In the semiconductor device 1e of this embodiment, the amount of material (having a larger linear expansion coefficient than that of the porous material) per unit volume is made different between the peripheral portion corresponding region and the central portion corresponding region. Thus, the linear expansion coefficient of the peripheral corresponding region is configured to be larger than the linear expansion coefficient of the central corresponding region.
In this embodiment, the linear expansion coefficient of the mounting substrate 20e is larger in the region where the peripheral portion R side of the semiconductor element 10 is joined. Therefore, the central portion C has a smaller mechanical restraining force than the peripheral portion R side, and is joined to the mounting substrate 20e in a state of being intensively clamped at the peripheral portion R. Thereby, the degree of change of thermal stress due to the position in the central portion C of the semiconductor element 10 can be reduced. If the degree of change in thermal stress is reduced, the degree of change in electrical resistivity is also reduced. Therefore, if the semiconductor device 1e is used, the difference in electrical resistivity depending on the position in the semiconductor element 10 can be reduced.
Moreover, according to the semiconductor device 1e of the fourth embodiment, the linear expansion coefficients of the peripheral portion corresponding region and the central portion corresponding region of the mounting substrate can be easily adjusted.

第４実施例では、単位体積あたりの実装基板２０ｅに空けられている同じ大きさの孔２１ｅの数が、中央部対応領域よりも周辺部対応領域の方が多く、全ての孔２１ｅに実装基板２０ｅよりも大きい線膨張係数を有する材料を含浸する場合について説明した。周辺部対応領域の線膨張係数を中央部対応領域の線膨張係数よりも大きくする構成は本実施例に限定されるものではない。
例えば、単位体積あたりの実装基板に空けられている同じ大きさの孔の数は、中央部対応領域も周辺部対応領域も同じであって、孔に選択的に実装基板よりも大きい線膨張係数を有する材料を配設してもよい。この場合、中央部対応領域に設けられている孔よりも周辺部対応領域に設けられている孔に多くの材料を含浸する。あるいは、単位体積あたりの実装基板に空けられている孔の数は同じであって、周辺部対応領域では中央部対応領域よりも大きい孔が設けられていてもよい。
また、多孔質の実装基板の孔に、実装基板よりも小さい線膨張係数を有する材料を配設する場合としては以下の構成が考えられる。
例えば、単位体積あたりの実装基板に空けられている同じ大きさの孔の数が、周辺部対応領域よりも中央部対応領域の方が多く、全ての孔に実装基板よりも小さい線膨張係数を有する材料を含浸する。あるいは、単位体積あたりの実装基板に空けられている孔の数と大きさは同じであって、孔に選択的に実装基板よりも小さい線膨張係数を有する材料を配設してもよい。この場合、周辺部対応領域に設けられている孔よりも中央部対応領域に設けられている孔に多くの材料を含浸する。あるいは、単位体積あたりの実装基板に空けられている孔の数は同じであって、中央部対応領域では周辺部対応領域よりも大きい孔が設けられていてもよい。
これらによって、周辺部対応領域の線膨張係数の方が中央部対応領域の線膨張係数よりも大きくなるように構成することができる。 In the fourth embodiment, the number of holes 21e of the same size per unit volume that are vacated in the mounting board 20e is larger in the peripheral area corresponding area than in the central area, and all the holes 21e are mounted on the mounting board. The case where the material having a linear expansion coefficient larger than 20e is impregnated has been described. The configuration in which the linear expansion coefficient in the peripheral area corresponding region is larger than the linear expansion coefficient in the central area is not limited to the present embodiment.
For example, the number of holes of the same size vacated in the mounting board per unit volume is the same in both the central area and the peripheral area, and the linear expansion coefficient is selectively larger than the mounting board. You may arrange | position the material which has these. In this case, more material is impregnated in the hole provided in the peripheral area corresponding region than in the hole provided in the central area. Alternatively, the number of holes vacated in the mounting substrate per unit volume may be the same, and the peripheral part corresponding region may be provided with a larger hole than the central part corresponding region.
Further, the following configuration is conceivable when a material having a smaller linear expansion coefficient than that of the mounting substrate is disposed in the hole of the porous mounting substrate.
For example, the number of holes of the same size per unit volume that are vacated in the mounting board is larger in the center area than in the peripheral area, and all holes have a smaller linear expansion coefficient than the mounting board. Impregnated with material. Alternatively, the number and size of the holes vacated in the mounting substrate per unit volume may be the same, and a material having a smaller linear expansion coefficient than the mounting substrate may be selectively disposed in the hole. In this case, a larger amount of material is impregnated into the hole provided in the center corresponding region than the hole provided in the peripheral corresponding region. Alternatively, the number of holes vacated in the mounting substrate per unit volume may be the same, and a larger hole may be provided in the center corresponding region than in the peripheral corresponding region.
Accordingly, the linear expansion coefficient in the peripheral corresponding region can be configured to be larger than the linear expansion coefficient in the central corresponding region.

また、図２０に示すように、線膨張係数の大きい材料と線膨張係数の小さい材料を貼り合わせることで、実装基板を形成してもよい。
図２０に示す実装基板２０ｆでは、母材２２ｆに、半導体素子１０の中心が接合される領域程深く形成した上面開口の穴を設ける。そして、この穴に母材２２ｆよりも線膨張係数の小さい材料で形成されているとともに穴を埋める形状の部材２３ｆを、ろう付け等で張り合わせる。母材２２ｆとしては、Ｃｕ，Ａｌ等が用いられる。部材２３ｆとしては、Ｗ，Ｍｏ等が用いられる。このように構成された実装基板２０ｆは、図１９に示した実装基板２０ｅと同様、半導体素子１０の周辺部対応領域ほど線膨張係数が大きい。したがって、実装基板２０ｅと同様、半導体素子１０中央部の位置による熱応力の変化を低減することができる。また、母体である多孔体の孔に材料を含浸させる方法と比較して、母体の構成、及び製造方法が簡単であるので、製造コストを抑制することができる。
また、図２１に示す実装基板２０ｇでは、母材２２ｇに、半導体素子１０の中心が接合される領域程深く形成した上面開口の階段上の穴を設ける。そして、この穴に母材２２ｇよりも線膨張係数の小さい材料で形成されているとともに穴を埋める形状の部材２３ｇを張り合わせる。母材２２ｇとしては、Ｃｕ，Ａｌ等が用いられる。部材２３ｇとしては、Ｗ，Ｍｏ等が用いられる。このように構成された実装基板２０ｇは、図１９に示した実装基板２０ｅと同様、半導体素子１０の周辺部対応領域ほど線膨張係数が大きい。したがって、実装基板２０ｅと同様、半導体素子１０中央部の位置による熱応力の変化を低減することができる。また、母体である多孔体の孔に材料を含浸させる方法と比較して、母体の構成、及び製造方法が簡単であるので、製造コストを抑制することができる。
以上の実施例では、２種類の材料を張り合わせて用いる点では、半導体素子の周辺部に接合している領域と半導体素子の中央部に接合している領域とで異ならない。ただし、厚み(それが組成比となる)が相違する。これもまた、半導体素子の周辺部に接合している領域と半導体素子の中央部に接合している領域とで材料組成が異なることに相当する。 Further, as shown in FIG. 20, the mounting substrate may be formed by bonding a material having a large linear expansion coefficient and a material having a small linear expansion coefficient.
In the mounting substrate 20f shown in FIG. 20, the base material 22f is provided with a hole having an upper opening formed deeper in a region where the center of the semiconductor element 10 is bonded. Then, a member 23f that is formed of a material having a smaller linear expansion coefficient than the base material 22f and that fills the hole is bonded to the hole by brazing or the like. Cu, Al, etc. are used as the base material 22f. W, Mo or the like is used as the member 23f. The mounting substrate 20f configured as described above has a larger linear expansion coefficient in the peripheral area corresponding region of the semiconductor element 10, like the mounting substrate 20e illustrated in FIG. Therefore, similarly to the mounting substrate 20e, changes in thermal stress due to the position of the central portion of the semiconductor element 10 can be reduced. In addition, since the structure of the base material and the manufacturing method are simpler than the method of impregnating the material of the pores of the porous body, which is the base material, the manufacturing cost can be suppressed.
Further, in the mounting substrate 20g shown in FIG. 21, the base material 22g is provided with a stepped hole having a top opening formed deeper in a region where the center of the semiconductor element 10 is bonded. Then, a member 23g that is formed of a material having a smaller linear expansion coefficient than the base material 22g and fills the hole is bonded to the hole. Cu, Al or the like is used as the base material 22g. W, Mo, or the like is used as the member 23g. The mounting substrate 20g configured as described above has a larger linear expansion coefficient in the peripheral area corresponding region of the semiconductor element 10 like the mounting substrate 20e shown in FIG. Therefore, similarly to the mounting substrate 20e, changes in thermal stress due to the position of the central portion of the semiconductor element 10 can be reduced. In addition, since the structure of the base material and the manufacturing method are simpler than the method of impregnating the material of the pores of the porous body, which is the base material, the manufacturing cost can be suppressed.
In the above-described embodiments, the two types of materials are used together, and the region bonded to the peripheral portion of the semiconductor element is not different from the region bonded to the central portion of the semiconductor element. However, the thickness (which is the composition ratio) is different. This also corresponds to the difference in material composition between the region bonded to the peripheral portion of the semiconductor element and the region bonded to the central portion of the semiconductor element.

また、第１実施例〜第４実施例では、半導体素子が上面略正方形である場合について説明した。本発明は、半導体素子が上面略長方形等、他の形状の半導体素子が設けられた半導体装置についても適用することができる。例えば、半導体素子が上面略長方形の形状である場合、対向する短辺の周りを集中的にクランプするように構成すれば、四辺の周りや対向する長辺の周りを集中的にクランプする場合と比較して、機械的拘束力が弱まるとともに、半導体素子に発生する熱応力が低減する。一方、対向する長辺の周りを集中的にクランプするように構成すれば、四辺の周りを集中的にクランプする場合と比較して、機械的拘束力が弱まるとともに半導体素子に発生する熱応力が低減するが、対向する短辺の周りを集中的にクランプする場合と比較すれば、機械的拘束力が強く半導体素子に発生する熱応力が大きい。
このように、不均一な接合層や不均一な実装基板を用いて、半導体素子を集中的にクランプする領域の位置や面積等を調節することで、半導体素子の機械的拘束力、半導体素子に発生する熱応力、半導体素子の電気抵抗率等を調節することができる。 In the first to fourth embodiments, the case where the semiconductor element has a substantially square top surface has been described. The present invention can also be applied to a semiconductor device in which a semiconductor element is provided with a semiconductor element having another shape such as a substantially rectangular top surface. For example, when the semiconductor element has a substantially rectangular shape on the upper surface, if it is configured to intensively clamp around the short sides facing each other, it may be clamped around the four sides or around the long sides facing each other. In comparison, the mechanical restraining force is weakened, and the thermal stress generated in the semiconductor element is reduced. On the other hand, if it is configured to intensively clamp around the opposite long sides, the mechanical restraining force is weakened and the thermal stress generated in the semiconductor element is reduced compared to the case of intensively clamping around the four sides. Although it is reduced, the mechanical restraint force is stronger and the thermal stress generated in the semiconductor element is larger than in the case of intensive clamping around the opposing short sides.
In this way, by using a non-uniform bonding layer or a non-uniform mounting substrate and adjusting the position and area of the region where the semiconductor element is clamped intensively, the mechanical restraining force of the semiconductor element can be reduced. The generated thermal stress, the electrical resistivity of the semiconductor element, and the like can be adjusted.

以上、本発明の具体例を詳細に説明したが、これらは例示にすぎず、特許請求の範囲を限定するものではない。特許請求の範囲に記載の技術には、以上に例示した具体例を様々に変形、変更したものが含まれる。
また、本明細書または図面に説明した技術要素は、単独であるいは各種の組合せによって技術的有用性を発揮するものであり、出願時の請求項記載の組合せに限定されるものではない。また、本明細書または図面に例示した技術は複数目的を同時に達成するものであり、そのうちの一つの目的を達成すること自体で技術的有用性を持つものである。 Specific examples of the present invention have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above.
In addition, the technical elements described in the present specification or drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology illustrated in the present specification or the drawings achieves a plurality of objects at the same time, and has technical utility by achieving one of the objects.

第１実施例の半導体装置１の要部分解図を示す。The principal part exploded view of the semiconductor device 1 of 1st Example is shown. 半導体装置１で、半導体素子１０が実装基板２０に接合される工程を示す。A process in which the semiconductor element 10 is bonded to the mounting substrate 20 in the semiconductor device 1 is shown. 半導体装置１で、半導体素子１０が実装基板２０に接合される工程を示す。A process in which the semiconductor element 10 is bonded to the mounting substrate 20 in the semiconductor device 1 is shown. 半導体装置１で、半導体素子１０が実装基板２０に接合される工程を示す。A process in which the semiconductor element 10 is bonded to the mounting substrate 20 in the semiconductor device 1 is shown. 実装基板２０に接合した半導体素子１０に作用する熱応力を示す斜視図である。4 is a perspective view showing thermal stress acting on the semiconductor element 10 bonded to the mounting substrate 20. FIG. 半導体装置１の上面図と、半導体素子内の位置に対応する熱応力の分布を示す。The top view of the semiconductor device 1 and the distribution of the thermal stress corresponding to the position in the semiconductor element are shown. 第２実施例の半導体装置１ａの要部分解図を示す。The principal part exploded view of the semiconductor device 1a of 2nd Example is shown. 半導体装置１ａの上面図と、半導体素子内の位置に対応する熱応力の分布を示す。The top view of the semiconductor device 1a and the distribution of thermal stress corresponding to the position in the semiconductor element are shown. 半導体装置１ｂで、実装基板２０に接合した半導体素子１０に作用する熱応力を示す斜視図である。FIG. 6 is a perspective view showing thermal stress acting on the semiconductor element 10 bonded to the mounting substrate 20 in the semiconductor device 1b. 半導体装置１ｃで、実装基板２０に接合した半導体素子１０に作用する熱応力を示す斜視図である。FIG. 6 is a perspective view showing thermal stress acting on the semiconductor element 10 bonded to the mounting substrate 20 in the semiconductor device 1c. 第３実施例の半導体装置１ｄの要部分解図を示す。The principal part exploded view of the semiconductor device 1d of 3rd Example is shown. 半導体装置１ｄで、半導体素子１０が実装基板２０に接合される工程を示す。A process of bonding the semiconductor element 10 to the mounting substrate 20 in the semiconductor device 1d is shown. 半導体装置１ｄで、半導体素子１０が実装基板２０に接合される工程を示す。A process of bonding the semiconductor element 10 to the mounting substrate 20 in the semiconductor device 1d is shown. 半導体装置１ｄで、半導体素子１０が実装基板２０に接合される工程を示す。A process of bonding the semiconductor element 10 to the mounting substrate 20 in the semiconductor device 1d is shown. 半導体装置１ｄで、半導体素子１０が実装基板２０に接合される工程を示す。A process of bonding the semiconductor element 10 to the mounting substrate 20 in the semiconductor device 1d is shown. 半導体装置１ｄで、半導体素子１０が実装基板２０に接合される工程を示す。A process of bonding the semiconductor element 10 to the mounting substrate 20 in the semiconductor device 1d is shown. 半導体装置１ｄで、半導体素子１０が実装基板２０に接合される工程を示す。A process of bonding the semiconductor element 10 to the mounting substrate 20 in the semiconductor device 1d is shown. 半導体装置１ｄの位置に対応する熱応力の分布を示す。The distribution of thermal stress corresponding to the position of the semiconductor device 1d is shown. 第４実施例の半導体装置１ｅの要部断面図と、実装基板２０ｅの位置に対応する線膨張係数ＴＣＥを示す。Sectional drawing of the principal part of the semiconductor device 1e of 4th Example and the linear expansion coefficient TCE corresponding to the position of the mounting substrate 20e are shown. 半導体装置１ｆの要部断面図を示す。The principal part sectional view of semiconductor device 1f is shown. 半導体装置１ｇの要部断面図を示す。The principal part sectional view of semiconductor device 1g is shown. 従来の半導体装置１００の断面図を示す。A cross-sectional view of a conventional semiconductor device 100 is shown.

符号の説明Explanation of symbols

１，１ａ，１ｂ，１ｃ，１ｄ，１ｅ，１ｆ，１ｇ 半導体装置
１０，１０ａ 半導体素子
２０，２０ｅ，２０ｆ，２０ｇ 実装基板
２１ｅ 孔
２２ｆ，２２ｇ 母材
２３ｆ，２３ｇ 部材
３０，３０ａ，３０ｂ，３０ｃ，３０ｄ，３０ｅ 接合層
３１，３１ａ，３１ｂ，３１ｃ 第１接合部材
３２，３２ａ，３２ｂ，３２ｃ 第２接合部材
３１ｄ 第３接合部材
３２ｄ 第４接合部材
４０ ソルダーレジスト
Ｃ，Ｃａ，Ｃｂ 中央部
Ｇ ゲート
Ｒ，Ｒａ、Ｒｂ 周辺部 1, 1a, 1b, 1c, 1d, 1e, 1f, 1g Semiconductor device 10, 10a Semiconductor element 20, 20e, 20f, 20g Mounting substrate 21e Hole 22f, 22g Base material 23f, 23g Member 30, 30a, 30b, 30c, 30d, 30e Joining layers 31, 31a, 31b, 31c First joining members 32, 32a, 32b, 32c Second joining member 31d Third joining member 32d Fourth joining member 40 Solder resist C, Ca, Cb Central portion G Gate R , Ra, Rb periphery

Claims (5)

半導体素子が接合層によって実装基板に接合されている半導体装置であり、
接合層と実装基板の少なくとも一方は、半導体素子の周辺部に接合している領域と半導体素子の中央部に接合している領域とで、材料組成が異なっていることを特徴とする半導体装置。 A semiconductor device in which a semiconductor element is bonded to a mounting substrate by a bonding layer,
At least one of the bonding layer and the mounting substrate has a material composition different between a region bonded to the peripheral portion of the semiconductor element and a region bonded to the central portion of the semiconductor element. 前記接合層は、半導体素子の周辺部を実装基板に接合している領域では引っ張り強度が高い材料組成を有し、半導体素子の中央部を実装基板に接合している領域では引っ張り強度が低い材料組成を有することを特徴とする請求項１の半導体装置。   The bonding layer has a material composition having a high tensile strength in a region where the peripheral portion of the semiconductor element is bonded to the mounting substrate, and a material having a low tensile strength in a region where the central portion of the semiconductor element is bonded to the mounting substrate. 2. The semiconductor device according to claim 1, wherein the semiconductor device has a composition. 前記接合層は、半導体素子の周辺部を実装基板に接合している領域では融点が高い材料組成を有し、半導体素子の中央部を実装基板に接合している領域では融点が低い材料組成を有することを特徴とする請求項１の半導体装置。   The bonding layer has a material composition having a high melting point in the region where the peripheral portion of the semiconductor element is bonded to the mounting substrate, and has a material composition having a low melting point in the region where the central portion of the semiconductor element is bonded to the mounting substrate. The semiconductor device according to claim 1, comprising: 前記実装基板は、接合層によって半導体素子の周辺部に接合されている領域では線膨張係数が大きい材料組成を有し、接合層によって半導体素子の周辺部に接合されている領域では線膨張係数が小さい材料組成を有することを特徴とする請求項１の半導体装置。   The mounting substrate has a material composition having a large linear expansion coefficient in the region bonded to the peripheral portion of the semiconductor element by the bonding layer, and has a linear expansion coefficient in the region bonded to the peripheral portion of the semiconductor element by the bonding layer. 2. The semiconductor device according to claim 1, wherein the semiconductor device has a small material composition. 前記実装基板は、多孔質の母材の孔に、母材とは相違する線膨張係数を有する部材が配設された材料で形成されており、接合層によって半導体素子の周辺部に接合されている領域と、接合層によって半導体素子の中央部に接合されている領域とで、前記孔に配設されている部材の量が相違していることを特徴とする請求項４の半導体装置。   The mounting substrate is formed of a material in which a member having a linear expansion coefficient different from that of the base material is disposed in a hole of the porous base material, and is bonded to the peripheral portion of the semiconductor element by a bonding layer. 5. The semiconductor device according to claim 4, wherein an amount of a member disposed in the hole is different between a region where the hole is present and a region where the bonding layer is bonded to the central portion of the semiconductor element.
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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008277335A (en) * 2007-04-25 2008-11-13 Fuji Electric Device Technology Co Ltd Semiconductor device and its manufacturing process
JP2012004171A (en) * 2010-06-14 2012-01-05 Nissan Motor Co Ltd Semiconductor device
WO2012081167A1 (en) * 2010-12-15 2012-06-21 日立オートモティブシステムズ株式会社 Semiconductor device and method for manufacturing same
CN102646650A (en) * 2011-02-22 2012-08-22 富士通株式会社 Semiconductor device and method for manufacturing semiconductor device
US20160064350A1 (en) * 2012-02-09 2016-03-03 Robert Bosch Gmbh Connection arrangement of an electric and/or electronic component

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06326141A (en) * 1993-05-17 1994-11-25 Mitsubishi Electric Corp Base material for semiconductor-chip bonding and solder material for semiconductor-chip bonding as well as manufacture of solder material for semiconductor-chip bonding
WO1998043288A1 (en) * 1997-03-24 1998-10-01 Seiko Epson Corporation Semiconductor device and method for manufacturing the same
JP2002299522A (en) * 2002-03-28 2002-10-11 Mitsubishi Electric Corp Semiconductor device
JP2005050886A (en) * 2003-07-29 2005-02-24 Kyocera Corp Compound substrate and its manufacturing method
JP2007044699A (en) * 2005-08-05 2007-02-22 Nissan Motor Co Ltd Joined structure
JP2007110001A (en) * 2005-10-17 2007-04-26 Fuji Electric Holdings Co Ltd Semiconductor device

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06326141A (en) * 1993-05-17 1994-11-25 Mitsubishi Electric Corp Base material for semiconductor-chip bonding and solder material for semiconductor-chip bonding as well as manufacture of solder material for semiconductor-chip bonding
WO1998043288A1 (en) * 1997-03-24 1998-10-01 Seiko Epson Corporation Semiconductor device and method for manufacturing the same
JP2002299522A (en) * 2002-03-28 2002-10-11 Mitsubishi Electric Corp Semiconductor device
JP2005050886A (en) * 2003-07-29 2005-02-24 Kyocera Corp Compound substrate and its manufacturing method
JP2007044699A (en) * 2005-08-05 2007-02-22 Nissan Motor Co Ltd Joined structure
JP2007110001A (en) * 2005-10-17 2007-04-26 Fuji Electric Holdings Co Ltd Semiconductor device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008277335A (en) * 2007-04-25 2008-11-13 Fuji Electric Device Technology Co Ltd Semiconductor device and its manufacturing process
JP2012004171A (en) * 2010-06-14 2012-01-05 Nissan Motor Co Ltd Semiconductor device
WO2012081167A1 (en) * 2010-12-15 2012-06-21 日立オートモティブシステムズ株式会社 Semiconductor device and method for manufacturing same
CN102646650A (en) * 2011-02-22 2012-08-22 富士通株式会社 Semiconductor device and method for manufacturing semiconductor device
US20160064350A1 (en) * 2012-02-09 2016-03-03 Robert Bosch Gmbh Connection arrangement of an electric and/or electronic component

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