JP7400293B2 - Semiconductor device and semiconductor device manufacturing method - Google Patents

Description

The present invention relates to a semiconductor device and a method for manufacturing a semiconductor device.

The semiconductor device includes, for example, a semiconductor chip such as an IGBT (Insulated Gate Bipolar Transistor) or a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor). In addition, there are semiconductor devices such as intelligent power switches for the purpose of making semiconductor devices smaller and more intelligent. An intelligent power switch is equipped with a semiconductor chip that includes a transistor section that includes a vertical power semiconductor element, and a control circuit section that includes a horizontal semiconductor element that constitutes a control and protection circuit for the vertical power semiconductor element. (For example, see Patent Document 1).

In order to achieve high reliability in such semiconductor devices even in environments with large temperature differences and temperature changes, it is necessary to increase the strength of the solder that joins the semiconductor chip and the die pad to prevent the semiconductor chip from peeling off. be. For this reason, attempts have been made to increase the amount of solder and make the solder thicker to increase the strength of the solder and improve the reliability of semiconductor devices against temperature changes (for example, see Patent Document 2).

Re-publication No. 2015-174197 Japanese Patent Application Publication No. 2002-353378

With the miniaturization of semiconductor devices and the reduction in the size of semiconductor chips, the area to which solder is applied also needs to be reduced. However, if the solder is made thicker in order to increase the strength of the solder, the amount of solder increases accordingly, and the application area also becomes wider, which hinders the miniaturization of semiconductor devices.

Additionally, thicker solder tends to cause variations in its thickness. As a result, the semiconductor chip mounted on the solder may also be tilted. When a bonding wire is bonded to a tilted semiconductor chip, ultrasonic waves for bonding are not properly transmitted to the semiconductor chip, the wire cannot be reliably bonded, and the bonding wire is likely to peel off.

The present invention has been made in view of these points, and an object of the present invention is to provide a semiconductor device and a method for manufacturing a semiconductor device that can maintain reliability while suppressing an increase in solder thickness. do.

According to one aspect of the present invention, there is provided a semiconductor chip including a transistor portion including a transistor configured at one end in a plan view, and a control circuit portion including a control circuit configured in the remaining portion; a die pad to which the semiconductor chip is bonded to a bonding area; and a solder provided between a back surface of the semiconductor chip and the bonding area to bond the semiconductor chip and the bonding area, the solder being A semiconductor device is provided, comprising a first portion that overlaps the transistor section in a plan view, and a second portion that overlaps only the control circuit section and includes a cavity.

According to one aspect of the present invention, the semiconductor chip is bonded to a semiconductor chip including a transistor portion including a transistor configured at one end in plan view and a control circuit portion including a control circuit configured in the remaining portion. a die pad having a bonding area set on the front surface thereof; and a step of preparing a die pad having a bonding area set on the front surface thereof; Provided is a method for manufacturing a semiconductor device, comprising: a water repellent treatment step of forming a water repellent region only in one of the regions corresponding to the above, and a step of bonding the semiconductor chip to the die pad via solder.

According to one aspect of the present invention, there is provided a semiconductor chip including a transistor portion including a transistor configured at one end in a plan view, and a control circuit portion including a control circuit configured in the remaining portion; a die pad to which the semiconductor chip is bonded to a bonding area; and a solder provided between a back surface of the semiconductor chip and the bonding area to bond the semiconductor chip and the bonding area, the solder being A semiconductor device is provided, comprising a first portion that overlaps the transistor portion in a plan view, and a second portion that overlaps the control circuit portion and has a larger porosity of solder than the first portion.

The semiconductor device and the method for manufacturing the semiconductor device having the above configuration can maintain reliability while suppressing increase in solder thickness.

1 is a diagram for explaining the appearance of a semiconductor device according to a first embodiment; FIG. 1 is a perspective plan view of a semiconductor device according to a first embodiment; FIG. 1 is a side sectional view of a semiconductor device according to a first embodiment; FIG. 3 is a flowchart showing a method for manufacturing a semiconductor device according to the first embodiment. FIG. 3 is a diagram for explaining a method for manufacturing a semiconductor device according to a first embodiment. FIG. 3 is a diagram for explaining a lead frame setting process included in the semiconductor device manufacturing method of the first embodiment. FIG. 3 is a diagram for explaining a water repellent treatment step included in the method of manufacturing a semiconductor device according to the first embodiment. FIG. 3 is a diagram for explaining a solder application step included in the method for manufacturing a semiconductor device according to the first embodiment. FIG. 3 is a diagram for explaining a semiconductor chipset step included in the method for manufacturing a semiconductor device according to the first embodiment. FIG. 3 is a diagram for explaining a sealing step included in the method for manufacturing a semiconductor device according to the first embodiment. FIG. 3 is a diagram for explaining a formation region of a water-repellent region for a die pad in the semiconductor device of the first embodiment. FIG. 7 is a diagram for explaining a method of manufacturing a semiconductor device according to a second embodiment. FIG. 7 is a perspective plan view of a semiconductor device according to a third embodiment. FIG. 7 is a side cross-sectional view of a semiconductor device according to a third embodiment. FIG. 7 is a diagram (part 1) for explaining a water repellent treatment step included in the method for manufacturing a semiconductor device according to the third embodiment; FIG. 7 is a diagram (part 2) for explaining a water repellent treatment step included in the method for manufacturing a semiconductor device according to the third embodiment; FIG. 7 is a perspective plan view of a semiconductor device according to a fourth embodiment. FIG. 7 is a side sectional view of a semiconductor device according to a fourth embodiment. FIG. 7 is a diagram for explaining a water repellent treatment step included in a method for manufacturing a semiconductor device according to a fourth embodiment. FIG. 7 is a diagram for explaining a method of manufacturing a semiconductor device according to a fifth embodiment.

[First embodiment]
Hereinafter, a semiconductor device according to a first embodiment will be described using FIGS. 1 to 3 with reference to the drawings. FIG. 1 is a diagram for explaining the appearance of a semiconductor device according to a first embodiment. FIG. 2 is a perspective plan view of the semiconductor device of the first embodiment, and FIG. 3 is a side sectional view of the semiconductor device of the first embodiment. Note that FIG. 2 shows a perspective plan view of the semiconductor device 10 of FIG. 1. Further, FIG. 3(A) shows a cross-sectional view taken along the dashed-dotted line X1-X1 in FIG. 2, and FIG. 3(B) shows a cross-sectional view taken along the dashed-dotted line X2-X2 in FIG.

Further, in the first and second embodiments, the front surface is the surface on which the semiconductor device 10 in FIG. 1 faces upward, and for example, on the die pad 20 in FIG. The surface is the front. The back surface refers to the surface facing downward in the semiconductor device 10 of FIG. For example, in the die pad 20 of FIG. 3, the surface opposite to the surface on which the semiconductor chip 50 is mounted is the back surface. The front surface and the back surface have the same directionality in other drawings as well.

The semiconductor device 10 includes a die pad 20, a plurality of connection terminals 30, a semiconductor chip 50 disposed on the die pad 20 via a solder 40, and a plurality of bonding wires 60 that electrically connect the semiconductor chip 50 and the connection terminals 30. We are prepared. The semiconductor device 10 is configured such that these members are sealed in a substantially cubic shape by a sealing member 70. The semiconductor device 10 only needs to include at least one die pad 20 and one semiconductor chip 50. In the semiconductor device 10 having such a configuration, the length of the sealing side surfaces 71 and 72 is 2.5 mm or more and 6 mm or less, and the thickness is 0.5 mm or more and 2 mm or less.

The die pad 20 is made of a metal having excellent thermal conductivity such as aluminum, iron, silver, copper, or an alloy containing at least one of these. Furthermore, a bonding region 21 (described later) to which a semiconductor chip 50 is bonded is set on the front surface of the die pad 20, as will be described later. Furthermore, a water-repellent region 23 (FIG. 3(B)) is formed in this bonding region 21. The water-repellent region 23 is a region in the bonding region 21 of the die pad 20 that has poor solder wettability compared to regions other than the water-repellent region 23 . Therefore, when solder 40 is applied to the bonding area 21 of the die pad 20 as described later, when the solder melts, the solder 40 is repelled in the water-repellent area 23 and the solder 40 flows to the bonding area 21 other than the water-repellent area 23. . Therefore, when the solder 40 is applied to the entire surface of the bonding area 21 of the die pad 20, although the solder 40 is present in areas other than the water-repellent area 23 after the solder 40 is melted, there is no solder 40 on the water-repellent area 23. 40 does not exist, and a void (cavity portion 43) is generated. In FIG. 2, the position of the cavity 43 included in the solder 40 facing the control circuit section 52 of the semiconductor chip 50 is indicated by a broken line.

A hanging pin portion 22 that supported the die pad 20 from a cut-off frame portion (described later) is formed on the opposite short side of the die pad 20. Two hanging pin portions 22 may be formed on each opposing short side of the die pad 20 . Although not shown, the back surface of the die pad 20 is exposed from the main sealing surface, which is the back surface of the sealing member 70, and is flush with the main sealing surface. Further, the end surfaces of the hanging pin portions 22 of the die pad 20 are exposed from two opposing sealing side surfaces 72 of the sealing member 70.

The connection terminal 30 has a flat plate shape to which the bonding wire 60 is bonded, and has a T-shape or an I-shape when viewed from above (note that FIG. 2 shows a T-shape). . Four connection terminals 30 are arranged on each side of the die pad 20 . Note that the number of connection terminals 30 is an example, and is not limited to this case. Furthermore, although not shown, the back surface of the connection terminal 30 is exposed from the main sealing surface of the sealing member 70 and is flush with the main sealing surface and the back surface of the die pad 20 . The connection terminal 30 is made of a metal such as copper or copper alloy, which has excellent conductivity. In order to improve corrosion resistance, the surface is formed by a plating process using a material made of, for example, tin, silver, a tin alloy, or a silver alloy as a plating film.

For example, the solder 40 is mainly made of at least one of the following alloys: an alloy consisting of tin-silver-copper, an alloy consisting of tin-zinc-bismuth, an alloy consisting of tin-copper, and an alloy consisting of tin-silver-indium-bismuth. Consists of lead-free solder as a component. Additionally, additives such as nickel, germanium, cobalt or silicon may be included. Further, the solder 40 includes a first portion 41 and a second portion 42, as shown in FIG. 8 later.

The semiconductor chip 50 includes a transistor section 51 that is made of silicon or silicon carbide and includes switching elements such as IGBTs and power MOSFETs. Such a semiconductor chip 50 has, for example, an input electrode (drain electrode or collector electrode) as a main electrode on the back surface, a control electrode (gate electrode) and an output electrode (source electrode or emitter electrode) as the main electrode on the front surface. ). The semiconductor chip 50 further includes a control circuit section 52 including a control circuit for controlling each of such switching elements. For example, as shown in FIG. 2, the semiconductor chip 50 includes a transistor portion 51 at one end and a control circuit portion 52 at the remaining portion in plan view. Further, the long side of such a semiconductor chip 50 is 1.5 cm or more and 4 cm or less, and the short side is 1 cm or more and 3.2 cm or less.

The back side of the semiconductor chip 50 described above is bonded onto the die pad 20 by solder 40. At this time, the solder 40 includes a first portion 41 (FIG. 3A) that overlaps with the transistor portion 51 of the semiconductor chip 50 in plan view, and a cavity portion 43 that overlaps with the control circuit portion 52 of the semiconductor chip 50. A second portion 42 (FIG. 3(B)). Further, the thickness of the solder 40 that joins the semiconductor chip 50 and the die pad 20 in this way is 10 μm or more and 100 μm or less. Furthermore, preferably it is 20 μm or more and 100 μm or less. If it is too thin or too thick than this range, the strength of the solder 40 will decrease and the semiconductor chip 50 will easily peel off.

The bonding wire 60 is made of a highly conductive metal such as aluminum or copper, or an alloy containing at least one of these metals. Note that the bonding wire 60 of the semiconductor device 10 is made of copper or a copper alloy. Moreover, it is preferable that this diameter is 100 μm or more and 1 mm or less. Furthermore, instead of the bonding wire 60, a connecting member such as a plate-shaped lead frame or a thin strip-shaped ribbon may be used. For the sealing member 70, thermosetting resin such as epoxy resin and phenol resin can be used, for example.

Next, a method for manufacturing such a semiconductor device 10 will be explained using FIGS. 4 to 10 and FIGS. 1 to 3. FIG. 4 is a flowchart showing the method for manufacturing the semiconductor device according to the first embodiment, and FIG. 5 is a diagram for explaining the method for manufacturing the semiconductor device according to the first embodiment. FIG. 6 is a diagram for explaining a lead frame setting step included in the semiconductor device manufacturing method of the first embodiment, and FIG. 7 is a diagram for explaining a lead frame setting step included in the semiconductor device manufacturing method of the first embodiment. It is a figure for explaining the water repellent treatment process included. FIG. 8 is a diagram for explaining a solder application process included in the method for manufacturing a semiconductor device according to the first embodiment, and FIG. 9 is a diagram for explaining a solder application step included in the method for manufacturing a semiconductor device according to the first embodiment. FIG. 3 is a diagram for explaining a semiconductor chipset process. FIG. 10 is a diagram for explaining a sealing process included in the method for manufacturing a semiconductor device according to the first embodiment. FIG. 5 shows a cross-sectional view taken along the dashed line XX in FIGS. 7 and 9, respectively. 6 to 10 each represent the main parts of the plane.

[Step S1] A lead frame (described later) including a die pad 20 and connection terminals 30, a semiconductor chip 50, a sealing member 70, and the like are prepared in advance. As for the semiconductor chip 50 and the sealing member 70, those already described are prepared. The lead frame is made of copper or a copper alloy, for example.

[Step S2] Set the lead frame at a predetermined position. For example, the lead frame 80 shown in FIG. 6 connects a pair of frame parts 81 to which the die pad 20 is connected via the hanging pin part 22, and a plurality of connection terminals 30 are connected to the pair of frame parts 81. It has a tie bar 82. In this way, in the lead frame 80, the die pad 20 and the plurality of connection terminals 30 are integrated. Such a lead frame 80 can be formed by punching a metal plate using a predetermined mold.

[Step S3] Water repellent treatment is performed on the bonding region 21 of the die pad 20 included in the lead frame 80, as shown in FIG. 7, for example, to form a water repellent region 23. The water-repellent region 23 is formed in a region corresponding to the control circuit portion 52 when the semiconductor chip 50 is bonded to the bonding region 21 later. Furthermore, the surface roughness of the water-repellent region 23 of the die pad 20 may be configured to be rougher than the surface roughness of the other bonding regions 21 . Such a water-repellent region 23 is formed in the region by laser processing, for example, as shown in FIG. 5(A). Laser processing can increase surface roughness. Alternatively, an oxide film may be formed in the region by laser processing in air or oxygen. Alternatively, a resin such as polyimide may be applied.

[Step S4] As shown in FIG. 8, solder 40 is applied to the entire surface of the bonding region 21 including the water-repellent region 23 of the die pad 20 included in the lead frame 80. The solder 40 at this time is conveniently divided into a first portion 41 that overlaps with the transistor portion 51 when the semiconductor chip 50 is bonded later, and a second portion 42 that similarly overlaps with the control circuit portion 52. Note that in FIG. 8, the portions of the second portion 42 corresponding to the water-repellent regions 23 are shown with broken lines.

[Step S5] The semiconductor chip 50 is aligned on the solder 40 applied on the die pad 20 included in the lead frame 80 (FIG. 5(B)), and the semiconductor chip 50 is bonded to the solder 40 while heating to form the die pad. Press it to the 20 side to set it. The transistor portion 51 of the semiconductor chip 50 is bonded to the die pad 20 by solder 40 (first portion 41). On the other hand, the solder 40 (second portion 42) cannot sufficiently wet the water-repellent region 23 of the bonding region 21 of the die pad 20, and can sufficiently wet the bonding region 21 other than the water-repellent region 23. . Therefore, as shown in FIG. 5C, the solder 40 (second portion 42) includes a cavity 43 in a portion facing the water-repellent region 23, and is connected to the control circuit portion 52 of the semiconductor chip 50. The die pad 20 is bonded to the die pad 20. The thickness of the solder 40 at this time is 10 μm or more and 100 μm or less. In addition, in FIG. 9, the portion corresponding to the cavity 43 in the control circuit section 52 of the semiconductor chip 50 is shown by a broken line.

If the second portion 42 of the solder 40 that joins the semiconductor chip 50 and the die pad 20 does not include the cavity 43, thermal stress will be generated in the solder 40 due to thermal cycles and the corners of the solder 40 will be damaged. Cracks will occur. This causes a decrease in the reliability of the semiconductor device 10. In order to suppress the occurrence of cracks at the corners of the solder 40, it is possible to make the solder 40 thicker. Although increasing the thickness of the solder 40 suppresses the occurrence of cracks in the solder 40, as described above, the thickness of the solder 40 becomes uneven, which may cause the semiconductor chip 50 placed on the solder 40 to tilt. , miniaturization becomes difficult as the amount of solder increases.

On the other hand, since the second portion 42 of the solder 40 that joins the semiconductor chip 50 and the die pad 20 includes the cavity 43 as in the first embodiment, the occurrence of cracks at the corners of the solder 40 can be suppressed. I can do it. The length from the edge of the cavity 43 to the corner of the solder 40 (indicated by the dashed arrow in FIG. 9) is shorter than the length of the diagonal line of the solder 40 that does not include the cavity 43. Therefore, thermal stress caused to the solder 40 due to thermal cycles can be reduced, and cracks at the corners of the solder 40 can be prevented from occurring. Therefore, the thickness of such solder 40 can be reduced, and the semiconductor device 10 can be made smaller. Furthermore, since variations in the thickness of the solder 40 can be suppressed, the inclination of the semiconductor chip 50 bonded onto the solder 40 is also suppressed. Therefore, wire bonding to the semiconductor chip 50 can be performed appropriately. Therefore, the reliability of the semiconductor device 10 is maintained. Further, in the semiconductor chip 50, the transistor section 51 generates a larger amount of heat than the control circuit section 52. Particularly in recent years, silicon carbide has been increasingly used in the transistor section 51. Semiconductor elements using silicon carbide allow more current to flow than when silicon carbide is used, and therefore generate more heat. For this reason, the transistor portion 51 of the semiconductor chip 50 is required to have high heat dissipation properties, and it is not preferable for the first portion 41 of the solder 40 to include the cavity portion 43. For this reason, it is desirable that the cavity 43 be included in the second portion 42 of the solder 40 rather than in the first portion 41 .

Note that the hollow portion 43 included in the second portion 42 of the solder 40 does not actually contain any solder 40, but rather has a certain range of regions with higher porosity than other portions of the solder 40. is occupying. The porosity is the total volume of voids in the solder 40 divided by the volume of the solder 40. The porosity of the second portion 42 of the solder 40 is 10% or more and 30% or less. If the porosity is smaller than this range, no stress relaxation effect can be obtained. Furthermore, if the porosity is larger than this range, the remaining area of the solder 40 will be too small and cracks will easily occur. Generally, the solder 40 that has been applied and solidified includes naturally occurring voids. However, the porosity of the first portion 41 of the solder 40 is sufficiently lower than the porosity of the second portion, which is 1% or more and less than 10%.

[Step S6] The semiconductor chip 50 bonded to the die pad 20 of the lead frame 80 by the solder 40 and the tie bar 82 are electrically connected by the bonding wire 60 (not shown). The semiconductor chip 50, the connection terminals 30, and the bonding wires 60 arranged on the die pad 20 of the lead frame 80 are molded and sealed in a predetermined mold using a sealing member 70, as shown in FIG. It is sealed with a member 70.

[Step S7] The die pad 20 and the connection terminals 30 sealed with the sealing member 70 are separated from the frame portion 81 of the lead frame 80 and the tie bars 82. For this separation, for example, the tie bar 82 and the hanging pin part 22 are punched out with a die, or diced with a dicing blade. Through the above steps, the semiconductor device 10 shown in FIGS. 1 to 3 is obtained.

The semiconductor device 10 includes a semiconductor chip 50 including a transistor section 51 including a transistor configured at one end in a plan view, and a control circuit section 52 including a control circuit configured at the remaining portion, and a semiconductor chip 50 on the front surface. It has a die pad 20 to which a semiconductor chip 50 is bonded to a bonding region 21 . Furthermore, it has a solder 40 that is provided between the back surface of the semiconductor chip 50 and the bonding area 21 and that bonds the semiconductor chip 50 and the bonding area 21. At this time, the solder 40 includes a first portion 41 that overlaps with the transistor portion 51 in a plan view, and a second portion 42 that overlaps with the control circuit portion 52 and includes a cavity portion 43. Alternatively, the solder 40 includes a first portion 41 that overlaps the transistor section 51 in a plan view, and a second portion 42 that overlaps the control circuit section 52 and has a larger porosity than the first section 41 . Such a semiconductor device 10 can reduce the thermal stress caused to the solder 40 due to thermal cycles, and prevent the occurrence of cracks at the corners of the solder 40. Therefore, the thickness of the solder 40 can be reduced, and the size of the semiconductor device 10 can be reduced. Furthermore, since variations in the thickness of the solder 40 can be suppressed, the inclination of the semiconductor chip 50 bonded onto the solder 40 is also suppressed. Therefore, wire bonding to the semiconductor chip 50 can be performed appropriately. Therefore, the reliability of the semiconductor device 10 is maintained.

Next, when creating the cavity 43 included in the second portion 42 of the solder 40, the formation range of the water-repellent region 23 with respect to the die pad 20 will be described using FIG. 11. FIG. 11 is a diagram for explaining the formation region of the water-repellent region for the die pad in the semiconductor device of the first embodiment. Note that the semiconductor device 10 shown in FIG. 11 corresponds to FIG. 2, and shows the case in which the semiconductor chip 50 is removed from FIG.

As described above, the semiconductor device 10 includes the cavity 43 in the second portion 42 of the solder 40, so that the length from the edge of the cavity 43 to the corner of the solder 40 (dashed line arrow in FIG. 9) is shortened, thereby suppressing the occurrence of cracks at the corners of the solder 40. Therefore, it is required that the water-repellent region 23 formed on the die pad 20 be maximized within the region corresponding to the second portion 42 of the solder 40. On the other hand, if the water-repellent region 23 is made too wide, the heat dissipation of the control circuit section 52 of the semiconductor chip 50 will be excessively reduced. Therefore, as shown in FIG. 11, a water-repellent region 23 is formed inward from the edge of the bonding region 21 of the die pad 20 within the maximum region 23a that is surrounded by 10% of the length of the side of the bonding region 21. It is necessary to form a water-repellent region 23 having the same width as the maximum region 23a. Note that the shape of the water-repellent region 23 in plan view is not limited to the circular shape of the first embodiment, but may be any shape such as a rectangular shape or an elliptical shape.

[Second embodiment]
In the second embodiment, a case where a water-repellent region is formed on the semiconductor chip 50 side and a cavity 43 is included in the solder 40 will be described with reference to FIG. 12 (and FIG. 4). FIG. 12 is a diagram for explaining a method of manufacturing a semiconductor device according to the second embodiment. Even in this case, steps S1 and S2 are performed in the same way as in the manufacturing method shown in FIG. In the water repellent treatment process of step S3, a water repellent region 53 is formed on the back surface of the control circuit section 52 of the semiconductor chip 50. Such a water-repellent region 53 may be formed by applying a resin such as polyimide to the region. Alternatively, an oxide film may be formed. Alternatively, a plating film containing aluminum or nickel may be formed. Then, in step S4, solder 40 is applied to the bonding area 21 of the die pad 20.

Then, the step of setting the semiconductor chip 50 in step S5 is performed. That is, the semiconductor chip 50 on which the water-repellent region 53 is formed in this way is aligned on the solder 40 applied on the die pad 20 included in the lead frame 80 (FIG. 12(A)), and the semiconductor chip is heated while being heated. 50 to the solder 40 and press it against the die pad 20 side to set it. The transistor portion 51 of the semiconductor chip 50 is bonded to the die pad 20 by solder 40 (first portion 41). On the other hand, the solder 40 (second portion 42) cannot sufficiently wet the water repellent area 53 of the semiconductor chip 50, but can sufficiently wet areas other than the water repellent area 53. Therefore, as shown in FIG. 12(B), the solder 40 (second portion 42) includes a cavity 43 in a portion facing the water-repellent region 53, and is connected to the control circuit portion 52 of the semiconductor chip 50. The die pad 20 is bonded to the die pad 20. The thickness of the solder 40 at this time is 10 μm or more and 100 μm or less, similar to the first embodiment. After this, the semiconductor device 10 is obtained by performing steps similar to steps S6 and S7 in FIG.

Similarly to the first embodiment, the semiconductor device 10 thus obtained can also reduce the thermal stress caused to the solder 40 due to thermal cycles, and prevent the occurrence of cracks at the corners of the solder 40. . Therefore, the thickness of the solder 40 can be reduced, and the size of the semiconductor device 10 can be reduced. Furthermore, since variations in the thickness of the solder 40 can be suppressed, the inclination of the semiconductor chip 50 bonded onto the solder 40 is also suppressed. Therefore, wire bonding to the semiconductor chip 50 can be performed appropriately. Therefore, the reliability of the semiconductor device 10 is maintained.

[Third embodiment]
In the third embodiment, a case where a protrusion is formed in the die pad 20 together with the water repellent region 23 in the semiconductor device 10 of the first embodiment will be described with reference to FIGS. 13 and 14. FIG. 13 is a perspective plan view of the semiconductor device of the third embodiment, and FIG. 14 is a side sectional view of the semiconductor device of the third embodiment. Note that FIG. 13 shows a perspective plan view of the semiconductor device 10. Further, FIG. 14 shows a cross-sectional view taken along the dashed line XX in FIG. In the third embodiment, the same components as the semiconductor device 10 of the first embodiment are given the same reference numerals, and their descriptions will be omitted.

As shown in FIGS. 13 and 14, the semiconductor device 10 includes a die pad 20, a plurality of connection terminals 30, a semiconductor chip 50 disposed on the die pad 20 via a solder 40, and a semiconductor chip 50 and the connection terminals 30 connected together. A bonding wire 60 is provided for connection. The semiconductor device 10 is configured such that these members are sealed in a substantially cubic shape by a sealing member 70 (see FIG. 1).

As described above, the die pad 20 has a water-repellent region 23 formed in a region facing the control circuit portion 52 of the semiconductor chip 50 in the bonding region 21 (see FIG. 15 described later) to which the semiconductor chip 50 is bonded. . Furthermore, a protrusion 24 is formed in the bonding region 21 of the die pad 20 of the third embodiment. The protrusion 24 maintains a constant gap between the semiconductor chip 50 and the die pad 20. Note that the protrusion 24 shown in FIGS. 13 and 14 has a cylindrical shape.

In the first embodiment, the water-repellent region 23 is formed in the region of the bonding region 21 of the die pad 20 that corresponds to the control circuit section 52 of the semiconductor chip 50. As a result, the solder 40 applied to the bonding region 21 of the die pad 20 includes a cavity 43 above the water-repellent region 23 . As a result, the length from the edge of the cavity 43 to the corner of the solder 40 is shortened, and the occurrence of cracks at the corner of the solder 40 can be suppressed. This water-repellent region 23 is formed within the maximum region 23a of the die pad 20, as shown in FIG. At this time, when the solder 40 is applied on the die pad 20 and the semiconductor chip 50 is placed, the side of the semiconductor chip 50 that includes the cavity 43 of the solder 40 is tilted, causing variations in the thickness of the solder 40. Put it away. When the center point of the water-repellent region 23 is formed to be shifted from the center of gravity of the die pad 20 and the area of the water-repellent region 23 is formed to be relatively large, the water repellent region 23 is included in the solder 40 corresponding to the water-repellent region 23. The cavity 43 creates a region within the solder 40 with a small volume. When the semiconductor chip 50 is placed on such solder 40, the cavity 43 side of the solder 40 cannot support the semiconductor chip 50, and the semiconductor chip 50 is tilted. In this way, when the thickness of the solder 40 varies, the heat dissipation performance for the semiconductor chip 50 also varies, which may cause a defect in the semiconductor chip 50.

Therefore, in the third embodiment, as described above, the protrusion 24 is provided on the side of the die pad 20 on which the semiconductor chip 50 is inclined. As a result, the semiconductor chip 50 on the solder 40 including the cavity 43 at the location corresponding to the water-repellent region 23 is supported by the protrusion 24, thereby preventing the semiconductor chip 50 from tilting. Therefore, the thickness of the solder 40 is also maintained substantially uniform, suppressing variations in heat dissipation with respect to the semiconductor chip 50, and preventing a decrease in reliability of the semiconductor device 10. For this reason, the protrusion 24 is not limited to a cylindrical shape, but must have a shape that can maintain a constant gap between the semiconductor chip 50 and the die pad 20. Examples of such a shape include a convex shape, a prismatic shape, a semi-elliptical shape, and a rod shape. Further, a plurality of protrusions 24 may be arranged in a scattered manner, or protrusions 24 having a rectangular shape in plan view may be appropriately arranged. The height of the protrusion 24 is preferably 10 μm or more and 100 μm or less so that the gap between the semiconductor chip 50 and the die pad 20 is a desired distance. Further, the number and formation position of the protrusions 24 are merely an example, and the number and formation position may be such that the protrusions 24 are formed at a location that can reliably support the semiconductor chip 50 placed on the solder 40 and prevent it from tilting. Bye.

Next, a method for manufacturing a semiconductor device 10 including a die pad 20 having such a protrusion 24 will be described with reference to FIGS. 15 and 16 and FIGS. 4 to 10. 15 and 16 are diagrams for explaining a water repellent treatment step included in the method of manufacturing a semiconductor device according to the third embodiment. Note that FIG. 16(A) is a cross-sectional view taken along the dashed line XX in FIG. 15. FIG. 16(B) is a plan view of the die pad 20 on which the water-repellent region 23 and the protrusion 24 are formed. FIG. 16B shows a center line C1 that is parallel to the lateral direction of the die pad 20 and passes through the center of the long side, and a center line C2 that is parallel to the longitudinal direction and passes through the center of the short side. Further, the intersection of the center lines C1 and C2 is the center of gravity G of the die pad 20.

The semiconductor device 10 of the third embodiment is also manufactured according to the flowchart shown in FIG. Even in this case, steps S1 and S2 are performed in the same way as in the manufacturing method shown in FIG. In the water repellent treatment step of step S3, water repellent treatment is performed on the bonding region 21 of the die pad 20 included in the lead frame 80 to form a water repellent region 23. Then, press working is performed on a predetermined location of the die pad 20 to form a protrusion 24 on the front surface of the die pad 20, as shown in FIGS. 15 and 16(A). Note that the protrusion 24 may be formed at the time of forming the lead frame 80 in step S2. Furthermore, the protrusions 24 are not limited to being formed by pressing the die pad 20, but may be formed by applying resin. Note that thermosetting resins such as maleimide-modified epoxy resins, maleimide-modified phenol resins, and maleimide resins can be used as such resins. Moreover, such a protrusion 24 needs to be formed at a location where it can reliably support the semiconductor chip 50 that will be placed on the solder 40 later. Therefore, the protruding portion 24 is formed in the region corresponding to the control circuit portion 52 of the die pad 20 shown in FIG. 16(B).

Further, when the area of the water-repellent region 23 occupies 10% or more and 30% or less of the area of the front surface of the die pad 20, and the center P of the water-repellent region 23 is displaced from the center of gravity G of the die pad 20, The protrusion 24 is preferably formed in a region corresponding to the control circuit section 52 on the lower side in FIG. 16 than the center line C1 (center of gravity G). In order to more reliably support the semiconductor chip 50, the protrusion 24 is preferably formed within a region corresponding to the control circuit section 52 from the center P of the water repellent region 23. Furthermore, it is more preferable that the protrusion 24 be formed near the lower side in FIG. 16 that is farthest from the center of gravity G. After this step S3, the steps S4 to S7 of the flowchart shown in FIG. 4 are performed, thereby manufacturing the semiconductor device 10 shown in FIGS. 13 and 14.

Similarly to the first and second embodiments, the semiconductor device 10 obtained in this manner can also reduce the thermal stress caused to the solder 40 due to thermal cycles, and can prevent the occurrence of cracks at the corners of the solder 40. Prevented. Furthermore, the protrusion 24 allows the gap between the semiconductor chip 50 and the die pad 20 to be kept constant. Therefore, the thickness of the solder 40 can be made thin and substantially uniform, and the semiconductor device 10 can be made smaller. Moreover, since variations in the thickness of the solder 40 can be suppressed more reliably, the inclination of the semiconductor chip 50 bonded onto the solder 40 is also suppressed. Therefore, wire bonding to the semiconductor chip 50 can be performed appropriately, and a decrease in heat dissipation performance to the semiconductor chip 50 can be suppressed. Therefore, the reliability of the semiconductor device 10 is maintained.

[Fourth embodiment]
In the fourth embodiment, a modification of the semiconductor device 10 of the third embodiment will be described with reference to FIGS. 17 and 18. FIG. 17 is a perspective plan view of the semiconductor device of the fourth embodiment, and FIG. 18 is a side sectional view of the semiconductor device of the fourth embodiment. Note that in the fourth embodiment as well, the same components as those in the semiconductor device 10 of the third embodiment are denoted by the same reference numerals, and a description thereof will be omitted.

As shown in FIGS. 17 and 18, the semiconductor device 10 includes a die pad 20, a plurality of connection terminals 30, a semiconductor chip 50 disposed on the die pad 20 via a solder 40, and a semiconductor chip 50 and the connection terminals 30 connected to each other with electricity. A bonding wire 60 is provided for connection. The semiconductor device 10 is configured such that these members are sealed in a substantially cubic shape by a sealing member 70.

Similarly to the third embodiment, the die pad 20 has a water-repellent region 63 in a region facing the control circuit portion 52 of the semiconductor chip 50 in the bonding region 21 (see FIG. 19 described later) to which the semiconductor chip 50 is bonded. and a protrusion 24 are formed. The protrusion 24 maintains a constant gap between the semiconductor chip 50 and the die pad 20. Note that the protrusion 24 shown in FIGS. 17 and 18 has a cylindrical shape. Further, in the die pad 20 of the fourth embodiment, a bank portion 25 is formed surrounding the water-repellent region 63. At this time, the height of the bank portion 25 (from the main surface of the die pad 20 ) is higher than the main surface of the water-repellent region 63 . The water repellent region 63 and the bank portion 25 are integrally made of resin. Note that thermosetting resins such as maleimide-modified epoxy resin, maleimide-modified phenol resin, and maleimide resin can be used as this resin. In such a die pad 20, a cavity 43 is defined by the water-repellent region 63, the bank 25, and the back surface of the semiconductor chip 50.

In the first to third embodiments, the water-repellent region 23 is formed in the region of the bonding region 21 of the die pad 20 that corresponds to the control circuit section 52 of the semiconductor chip 50. As a result, the solder 40 applied to the die pad 20 is made to repel water in the water-repellent region 23, and the hollow portion 43 is included in the portion of the solder 40 that corresponds to the water-repellent region 23. However, it is difficult to reliably make the solder 40 water repellent in the water-repellent region 23, and a certain amount of the solder 40 remains on the water-repellent region 23. That is, the density of the solder 40 is lower in the portion of the solder 40 corresponding to the water-repellent region 23 than in other portions of the solder 40. In particular, the solder 40 tends to adhere to the edges of the water-repellent region 23. That is, the cavity 43 cannot be reliably formed, and the area of the water-repellent region 23 may become substantially smaller. Accordingly, the cavity 43 also becomes smaller, and the length from the edge of the cavity 43 to the corner of the solder 40 becomes longer than the actual cavity 43. Therefore, it may not be possible to reliably suppress the occurrence of cracks at the corners of the solder 40.

Therefore, in the fourth embodiment, a bank portion 25 is formed to surround the water-repellent region 63 of the die pad 20. This ensures that the solder 40 includes the cavity 43 at a location corresponding to the water-repellent region 63, and it is possible to maintain the cavity 43 corresponding to the area of the water-repellent region 63. Therefore, the length from the edge of the cavity 43 to the corner of the solder 40 can be maintained, the thermal stress caused to the solder 40 due to thermal cycles can be reduced, and the occurrence of cracks at the corner of the solder 40 can be reduced. This can be prevented more reliably.

Next, a method for manufacturing the semiconductor device 10 including the die pad 20 having such a bank portion 25 will be described with reference to FIG. 19 and FIGS. 4 to 10. FIG. 19 is a diagram for explaining a water repellent treatment step included in the method of manufacturing a semiconductor device according to the fourth embodiment.

The semiconductor device 10 of the fourth embodiment is also manufactured according to the flowchart shown in FIG. Even in this case, steps S1 and S2 are performed in the same way as in the manufacturing method shown in FIG. In the water repellent treatment process of step S3, a resin is applied to the bonding region 21 of the die pad 20 included in the lead frame 80 to form the water repellent region 63 and the bank portion 25. At this time, a water-repellent region 63 and a bank portion 25 surrounding the water-repellent region 63 are formed from resin applied to a predetermined region of the front surface of the die pad 20 (see FIG. 18). Note that the bank portion 25 may be formed of resin to surround the water-repellent region 23 formed on the die pad 20 by laser in the first embodiment. After forming the water-repellent region 63 and the bank portion 25, the die pad 20 is pressed to form a protrusion 24 on the front surface of the die pad 20, as shown in FIG. Note that the protrusion 24 is formed in the same manner as in the third embodiment. Furthermore, the protrusion 24 may be formed when the lead frame 80 is formed in step S2. After this step S3, the steps S4 to S7 of the flowchart shown in FIG. 4 are performed, thereby manufacturing the semiconductor device 10 shown in FIGS. 17 and 18.

The semiconductor device 10 thus obtained has a water-repellent region 63 and a bank portion 25 surrounding the water-repellent region 63 on the die pad 20 . Therefore, the solder 40 reliably includes the cavity 43 at a location corresponding to the water-repellent region 63, and the cavity 43 corresponding to the area of the water-repellent region 63 can be maintained. Therefore, the length from the edge of the cavity 43 to the corner of the solder 40 can be maintained, the thermal stress caused to the solder 40 due to thermal cycles can be reduced, and the occurrence of cracks at the corner of the solder 40 can be reduced. This can be prevented more reliably. Further, in the semiconductor device 10, since the protrusion 24 is formed on the die pad 20, the gap between the semiconductor chip 50 and the die pad 20 can be kept constant and thin, similarly to the third embodiment. Therefore, wire bonding to the semiconductor chip 50 can be performed appropriately. Therefore, the reliability of the semiconductor device 10 is maintained.

[Fifth embodiment]
In the fifth embodiment, a water-repellent region 63, a bank 25, and a protrusion 24 are formed on the semiconductor chip 50 side, and the solder 40 includes a cavity 43 in FIG. 20 (and FIG. ). FIG. 20 is a diagram for explaining a method for manufacturing a semiconductor device according to the fifth embodiment. Even in this case, steps S1 and S2 are performed in the same way as in the manufacturing method shown in FIG. In the water repellent treatment step of step S3, a resin is applied to the back surface of the control circuit section 52 of the semiconductor chip 50 to form the water repellent region 63 and the bank section 25. Although not shown in FIG. 20, a protrusion 24 is formed on the die pad 20. Note that the protrusion 24 is formed in the same manner as in the third embodiment. Furthermore, the protrusion 24 may be formed when the lead frame 80 is formed in step S2. Then, in step S4, solder 40 is applied to the bonding area 21 of the die pad 20.

Then, the step of setting the semiconductor chip 50 in step S5 is performed. That is, the semiconductor chip 50 on which the water-repellent region 63 and the bank portion 25 are formed in this way is aligned on the solder 40 applied on the die pad 20 included in the lead frame 80 (FIG. 20(A)), and heated. While doing so, the semiconductor chip 50 is bonded to the solder 40 and pressed against the die pad 20 side to set it. The transistor portion 51 of the semiconductor chip 50 is bonded to the die pad 20 by solder 40 (first portion 41). On the other hand, the solder 40 (second portion 42) cannot sufficiently wet the water-repellent region 63 and the bank portion 25 of the semiconductor chip 50, but can sufficiently wet the portions other than the water-repellent region 63 and the bank portion 25. Therefore, as shown in FIG. 20(B), the solder 40 (second portion 42) includes a cavity 43 in a portion facing the water-repellent region 63 and the bank portion 25, and controls the semiconductor chip 50. The circuit portion 52 and the die pad 20 are joined. The thickness of the solder 40 at this time is 50 μm or more and 100 μm or less, similar to the first embodiment. After this, the semiconductor device 10 is obtained by performing steps similar to steps S6 and S7 shown in FIG.

The semiconductor device 10 thus obtained also has a water-repellent region 63 and a bank portion 25 surrounding the water-repellent region 63 on the die pad 20, as in the fourth embodiment. Therefore, the solder 40 reliably includes the cavity 43 at a location corresponding to the water-repellent region 63, and the cavity 43 corresponding to the area of the water-repellent region 63 can be maintained. Therefore, the length from the edge of the cavity 43 to the corner of the solder 40 can be maintained, the thermal stress caused to the solder 40 due to thermal cycles can be reduced, and the occurrence of cracks at the corner of the solder 40 can be reduced. This can be prevented more reliably. Furthermore, in the semiconductor device 10, since the protrusion 24 is formed on the die pad 20, the gap between the semiconductor chip 50 and the die pad 20 can be kept constant and thin, similarly to the fourth embodiment. Therefore, wire bonding to the semiconductor chip 50 can be performed appropriately. Therefore, the reliability of the semiconductor device 10 is maintained.

10 Semiconductor device 20 Die pad 21 Bonding area 22 Hanging pin portion 23, 53, 63 Water repellent area 23a Maximum area 24 Projection 25 Bank portion 30 Connection terminal 40 Solder 41 First portion 42 Second portion 43 Cavity portion 50 Semiconductor chip 51 Transistor Part 52 Control circuit part 60 Bonding wire 70 Sealing member 71, 72 Sealing side surface 80 Lead frame 81 Frame part 82 Tie bar

Claims (22)

a semiconductor chip including a transistor section including a transistor configured at one end in a plan view and a control circuit section including a control circuit configured in the remaining portion;
a die pad to which the semiconductor chip is bonded to a bonding area on a front surface;
a solder provided between the back surface of the semiconductor chip and the bonding region to bond the semiconductor chip and the bonding region;
has
The solder includes a first portion that overlaps the transistor portion in a plan view, and a second portion that overlaps only the control circuit portion and includes a cavity portion.
Semiconductor equipment. The second portion includes the hollow portion in a region surrounded by 10% of the length of the side of the bonding region inwardly from the edge of the bonding region.
The semiconductor device according to claim 1. The second portion includes the hollow portion, which is circular in plan view, in a central portion of the second portion.
The semiconductor device according to claim 1 or 2. The die pad has a water-repellent region formed at a location corresponding to the cavity in the bonding region.
A semiconductor device according to any one of claims 1 to 3. The surface roughness in the water-repellent region is rougher than the surface roughness of the bonding region other than the water-repellent region.
The semiconductor device according to claim 4. The water repellent region has an oxide film formed thereon.
The semiconductor device according to claim 4 or 5. The water-repellent area is coated with resin.
The semiconductor device according to claim 4 or 5. The semiconductor chip has a water-repellent region formed at a location corresponding to the cavity on the back surface.
A semiconductor device according to any one of claims 1 to 3. The water-repellent area is coated with resin.
The semiconductor device according to claim 8. A protrusion is formed on a side of the area where the second portion of the bonding area is coated, spaced apart from the center of gravity of the bonding area of the die pad;
A semiconductor device according to any one of claims 4 to 9. The protrusion is spaced apart from the center of the water-repellent area and is formed on the side of the area where the second portion of the bonding area is applied.
The semiconductor device according to claim 10. The die pad has a bank portion surrounding the water repellent region and having a height higher than the water repellent region from the main surface of the die pad.
A semiconductor device according to any one of claims 4 to 11. The bank portion is formed of resin.
The semiconductor device according to claim 12. A semiconductor chip including a transistor portion including a transistor configured at one end and a control circuit portion including a control circuit configured at the remaining portion in a plan view, and a bonding region to which the semiconductor chip is bonded is a front surface. a preparation process of preparing a die pad set to
a water-repellent treatment step of forming a water-repellent region only on either the back surface of the control circuit portion of the semiconductor chip or a region of the bonding region of the die pad that corresponds to the control circuit portion of the semiconductor chip;
a step of joining the semiconductor chip to the die pad via solder;
A method for manufacturing a semiconductor device having the following. In the water repellent treatment step, laser processing is performed on the die pad to form the water repellent region.
The method for manufacturing a semiconductor device according to claim 14. In the water repellent treatment step, a resin is applied to the back surface of the control circuit section of the semiconductor chip to form the water repellent region.
The method for manufacturing a semiconductor device according to claim 15. A protrusion is formed from the center of gravity of the bonding region of the die pad to a side of the bonding region corresponding to the control circuit portion,
The method for manufacturing a semiconductor device according to claim 14. In the water repellent treatment step, forming the water repellent region and a bank portion surrounding the water repellent region and having a higher height from the die pad than the water repellent region;
The method for manufacturing a semiconductor device according to claim 14 or 16. The water repellent region and the bank are formed of resin.
The method for manufacturing a semiconductor device according to claim 18. a semiconductor chip including a transistor section including a transistor configured at one end in a plan view and a control circuit section including a control circuit configured in the remaining portion;
a die pad to which the semiconductor chip is bonded to a bonding area on a front surface;
a solder provided between the back surface of the semiconductor chip and the bonding region to bond the semiconductor chip and the bonding region;
has
The solder includes a first portion that overlaps the transistor portion in plan view and a second portion that overlaps the control circuit portion and has a larger porosity of the solder than the first portion.
Semiconductor equipment. The porosity of the second portion is 1% or more and less than 10%.
The semiconductor device according to claim 20. The porosity of the first portion is 10% or more and 30% or less,
The semiconductor device according to claim 20 or 21.

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