JP7263792B2 - Semiconductor device and its manufacturing method - Google Patents

Semiconductor device and its manufacturing method Download PDF

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JP7263792B2
JP7263792B2 JP2019008265A JP2019008265A JP7263792B2 JP 7263792 B2 JP7263792 B2 JP 7263792B2 JP 2019008265 A JP2019008265 A JP 2019008265A JP 2019008265 A JP2019008265 A JP 2019008265A JP 7263792 B2 JP7263792 B2 JP 7263792B2
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semiconductor element
electrode
semiconductor device
protrusion
semiconductor
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JP2020119948A (en
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創一 坂元
純司 藤野
洋暁 一戸
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Mitsubishi Electric Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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Description

本発明は、半導体素子をヒートシンク等の基材に接合する半導体装置に関するものである。 The present invention relates to a semiconductor device in which a semiconductor element is bonded to a base material such as a heat sink.

半導体装置は、半導体素子に設けられた電極に、例えば半導体素子を制御する回路基板が電気的に接続されるとともに、接合部材によって放熱用のヒートシンク等の基材と接合される。このとき、半導体素子、接合部材、ヒートシンク等の構成部材はそれぞれ熱膨張係数が異なることから、温度変化によって歪みが生じ、その歪みは接合部材に亀裂を発生させることもある。
この亀裂の発生を防止するために、接合部材の供給量を増やし、半導体素子と基材との接合部を厚く形成して歪みを緩和する技術が知られている。しかし、無加圧で接合を行う半導体装置においては、接合部材の供給量を増やすことにより接合部の厚さが不均一となるため、熱衝撃試験時の信頼性が低下するおそれがあった。
この対策の一つとして、はんだに濡れない金属ワイヤ等を金属板上に配置して接合部の厚さを確保する技術が開示されている（例えば、特許文献１参照）。 A semiconductor device is electrically connected to, for example, a circuit board that controls the semiconductor element, to electrodes provided on the semiconductor element, and is joined to a base material such as a heat sink for heat dissipation by a joining member. At this time, since the constituent members such as the semiconductor element, the bonding member, and the heat sink have different coefficients of thermal expansion, strain occurs due to temperature changes, and the strain may cause cracks in the bonding member.
In order to prevent the occurrence of cracks, a technique is known in which the amount of bonding material supplied is increased and the bonding portion between the semiconductor element and the substrate is formed thicker to alleviate the strain. However, in a semiconductor device that is bonded without pressure, increasing the supply amount of the bonding material makes the thickness of the bonding portion uneven, which may reduce the reliability during the thermal shock test.
As one of countermeasures against this problem, a technique has been disclosed in which a metal wire or the like that is not wetted by solder is placed on a metal plate to ensure the thickness of the joint (see, for example, Japanese Patent Application Laid-Open No. 2002-200013).

特開平１１－１８６３３１号公報JP-A-11-186331

しかしながら、はんだに濡れない金属ワイヤを接合部に設けることによって接合部の厚さは確保できるものの、接合部材と金属ワイヤとの接合性が悪いため、未接合領域が形成され、この未接合領域が熱衝撃試験時の亀裂のきっかけとなるおそれがあるという課題があった。 However, although the thickness of the joint can be ensured by providing the joint with a metal wire that does not get wet with solder, the bondability between the joint member and the metal wire is poor. There was a problem that it might trigger cracks during the thermal shock test.

本発明は、上述の課題を解決するためになされたもので、接合部の厚さの均一性を確保できるとともに、接合性を向上できる半導体装置及び半導体装置の製造方法を提供することを目的とする。 SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor device and a method of manufacturing a semiconductor device that can ensure uniformity in the thickness of the joint and improve the joint property. do.

本発明にかかる半導体装置は、基材と、前記基材上に搭載され、前記基材側の面に電極を有する半導体素子と、前記半導体素子のパターンが形成された面から前記電極が形成された面に向かって、前記電極を切断する切断加工によって形成され、前記電極の端面に前記基材方向に突出し、対向して少なくとも一対となる突起と、前記突起及び前記電極を覆うように金属焼結材によって前記基材上に形成された接合部とを備えたものである。
A semiconductor device according to the present invention comprises a substrate, a semiconductor element mounted on the substrate and having an electrode on a surface facing the substrate, and the electrode formed from a patterned surface of the semiconductor element. At least one pair of protrusions formed by cutting the electrode toward the surface of the electrode, protruding in the direction of the base material on the end surface of the electrode and facing each other, and a metal firing so as to cover the protrusion and the electrode. and a joint formed on the base material by a binder.

また、本発明にかかる半導体装置の製造方法は、ウェハの一方の面に半導体素子のパターンを形成するパターン形成工程と、前記ウェハの他方の面に前記半導体素子の電極を形成する電極形成工程と、前記半導体素子のパターン側から前記電極の手前まで前記半導体素子及び前記ウェハを溝加工して溝を形成する溝形成工程と、前記溝形成工程より加工速度を上げて前記溝から前記電極を切断加工し突起を形成する突起形成工程と、前記突起を有する前記半導体素子を取り出す工程と、基材上に金属焼結材ペーストを塗布し、前記金属焼結材ペースト上に前記突起を配置させて取り出した前記半導体素子を搭載する半導体素子搭載工程と、前記金属焼結材ペーストを加熱し、前記金属焼結材ペーストが焼結された金属焼結材を前記突起の内側に充填して前記基材と前記半導体素子の前記電極とを接合する接合工程と、前記半導体素子のパターンをリードフレームと接続する接続工程と、前記半導体素子を前記リードフレーム及び前記基材の少なくとも一部とともに封止する封止工程とを備えたものである。 A method of manufacturing a semiconductor device according to the present invention includes a pattern forming step of forming a pattern of semiconductor elements on one surface of a wafer, and an electrode forming step of forming electrodes of the semiconductor elements on the other surface of the wafer. a groove forming step of forming a groove by processing the semiconductor element and the wafer from the pattern side of the semiconductor element to the front of the electrode; and cutting the electrode from the groove at a higher processing speed than the groove forming step. a projection forming step of forming projections by processing; a step of taking out the semiconductor element having the projection; applying a sintered metal material paste on a base material; a semiconductor element mounting step of mounting the semiconductor element taken out; heating the metal sintered material paste; a bonding step of bonding the material and the electrodes of the semiconductor element; a connecting step of connecting the pattern of the semiconductor element to a lead frame; and sealing the semiconductor element together with at least part of the lead frame and the base material. and a sealing step.

本発明によれば、接合部の厚さ、及び厚さの均一性を確保できるとともに、接合性を向上できる。 ADVANTAGE OF THE INVENTION According to this invention, while the thickness of a junction part and the uniformity of thickness can be ensured, bondability can be improved.

本発明の実施の形態１にかかる半導体装置を示す概略構成図である。1 is a schematic configuration diagram showing a semiconductor device according to a first embodiment of the invention; FIG. 本発明の実施の形態１にかかる半導体素子の電極に設けた突起の例を示す概略構成図である。FIG. 4 is a schematic configuration diagram showing an example of protrusions provided on electrodes of the semiconductor element according to the first embodiment of the present invention; 本発明の実施の形態１にかかる半導体装置の一部の断面を示す概略構成図である。1 is a schematic configuration diagram showing a cross section of part of a semiconductor device according to a first embodiment of the present invention; FIG. 本発明の実施の形態１にかかる半導体素子の電極に設けた突起の例を示す概略構成図である。4 is a schematic configuration diagram showing an example of protrusions provided on electrodes of the semiconductor element according to the first embodiment of the present invention; FIG. 本発明の実施の形態２にかかる半導体装置の一部の断面を示す概略構成図である。It is a schematic configuration diagram showing a cross section of part of a semiconductor device according to a second embodiment of the present invention. 本発明の実施の形態２にかかる半導体装置の一部の断面を示す概略構成図である。It is a schematic configuration diagram showing a cross section of part of a semiconductor device according to a second embodiment of the present invention. 本発明の実施の形態３にかかる半導体素子の突起の形成方法の例を示すイメージ図である。FIG. 10 is an image diagram showing an example of a method for forming protrusions of a semiconductor element according to a third embodiment of the present invention; 本発明の実施の形態３にかかる半導体装置の製造方法の工程図である。It is process drawing of the manufacturing method of the semiconductor device concerning Embodiment 3 of this invention.

実施の形態１．
上述のとおり、はんだに濡れない金属ワイヤと接合部材の接合性が悪いため、本発明の実施の形態１においては、長辺及び短辺を有する半導体素子１の一方の面に形成された電極９の短辺側の端面に、一対となるよう２つの突起８をめっき処理により形成し、金属焼結材ペーストを用いて無加圧で基材４と焼結接合した。 Embodiment 1.
As described above, since the bondability between the metal wire that does not get wet with solder and the bonding member is poor, in the first embodiment of the present invention, the electrode 9 formed on one surface of the semiconductor element 1 having long sides and short sides A pair of protrusions 8 were formed by plating on the end face on the short side of the substrate 4, and were sinter-bonded to the substrate 4 without pressure using a metal sintering material paste.

図１は、本発明の実施の形態１にかかる半導体装置を示す概略構成図であり、図１（ａ）はリードフレーム６上にモールド樹脂７を備えた半導体装置１００、図１（ｂ）は、図１（ａ）の半導体装置１００からモールド樹脂７を取り除いた半導体装置１００内部、及び図１（ｃ）は図１（ａ）のＡ－Ａ断面を示す。 1A and 1B are schematic configuration diagrams showing a semiconductor device according to a first embodiment of the present invention, FIG. , the inside of the semiconductor device 100 from which the mold resin 7 has been removed from the semiconductor device 100 of FIG. 1(a), and FIG. 1(c) shows the AA cross section of FIG.

図１（ｂ）に示すように、基材４となるＣｕ製のヒートシンクと、半導体素子１、例えばＳｉ製のＬＤＭＯＳ（Ｌａｔｅｒａｌ Ｄｏｕｂｌｅ Ｄｉｆｆｕｓｅｄ Ｍｅｔａｌ－Ｏｘｉｄｅ－Ｓｅｍｉｃｏｎｄｕｃｔｏｒ Ｆｉｅｌｄ－Ｅｆｆｅｃｔ Ｔｒａｎｓｉｓｔｏｒ）の裏面に形成された後述するＡｕ製の電極９とが、Ａｇ焼結材等の金属焼結材ペーストを焼結させて金属焼結材とした接合部３を介して接続される。また、例えば高周波通信用半導体装置において高周波特性の整合を取るための回路基板２、例えばＭＩＣ（Ｍｉｃｒｏｗａｖｅ Ｉｎｔｅｇｒａｔｅｄ Ｃｉｒｃｕｉｔ）基板も接合部３を介して基材４に接続される。 As shown in FIG. 1B, a heat sink made of Cu as a base material 4 and a semiconductor element 1, for example, formed on the back surface of a LDMOS (Lateral Double Diffused Metal-Oxide-Semiconductor Field-Effect Transistor) made of Si. An electrode 9 made of Au, which will be described later, is connected via a joint portion 3 made of a metal sintered material by sintering a metal sintered material paste such as an Ag sintered material. A circuit board 2 , for example, a MIC (Microwave Integrated Circuit) board for matching high frequency characteristics in a semiconductor device for high frequency communication, for example, is also connected to the base material 4 via a joint portion 3 .

半導体素子１の電極パターン及び回路基板２は、リードフレーム６を介してそれぞれボンディングワイヤ５により外部基板（図示せず）に電気的に接続される。
さらに、半導体装置１００を外部の湿気、汚染、熱、電磁界等の影響から隔離し、絶縁性を確保するため、半導体素子１、回路基板２は、例えばトランスファーモールドによるモールド樹脂７によって覆われている（図１（ｃ））。 The electrode pattern of the semiconductor element 1 and the circuit board 2 are electrically connected to an external substrate (not shown) through a lead frame 6 and bonding wires 5, respectively.
Furthermore, in order to isolate the semiconductor device 100 from external influences such as humidity, contamination, heat, and electromagnetic fields and to ensure insulation, the semiconductor element 1 and the circuit board 2 are covered with a mold resin 7 by, for example, transfer molding. (Fig. 1(c)).

図２は、半導体素子の電極に設けた突起の例を示す概略構成図である。図２に示すように、半導体素子１の一方の面に形成された電極９の短辺側の端面に、一対となるように、且つ半導体素子１から基材４方向に突出するように、Ａｕ、Ａｇ、Ｃｕ、又はこれらの合金により突起８を形成する。例えば高周波通信用の半導体素子１で、長辺と短辺の比であるアスペクト比が１～１０の形状であれば、突起８は対向する短辺にそれぞれ形成される。
このように、一対となるように形成された突起８は、図３に示すように、突起８の高さによって接合部３の厚さを確保でき、接合部３の厚さの均一性を確保することができる。
そして、金属焼結材により接合部３を形成するため、Ａｕ、Ａｇ、Ｃｕ、又はこれらの合金により形成した突起８との界面において、焼結反応又は焼成反応による接合界面を形成できるため、接合性が向上し、未接合領域に起因する亀裂を防止できる。 FIG. 2 is a schematic configuration diagram showing an example of protrusions provided on electrodes of a semiconductor element. As shown in FIG. 2 , Au is applied to the end surface of the short side of the electrode 9 formed on one surface of the semiconductor element 1 so as to form a pair and protrude from the semiconductor element 1 toward the substrate 4 . , Ag, Cu, or an alloy thereof. For example, if the semiconductor element 1 for high-frequency communication has a shape with an aspect ratio of 1 to 10, the protrusions 8 are formed on the opposite short sides.
As shown in FIG. 3, the projections 8 formed to form a pair in this way can ensure the thickness of the joint 3 by the height of the projection 8, and ensure the uniformity of the thickness of the joint 3. can do.
Since the joint portion 3 is formed of a metal sintered material, a joint interface can be formed by a sintering reaction or a firing reaction at the interface with the protrusion 8 formed of Au, Ag, Cu, or an alloy thereof. The strength is improved and cracks caused by unbonded areas can be prevented.

金属焼結材ペーストは、例えば溶剤にＡｇ焼結材を分散させ５Ｐａ・ｓ以上２００Ｐａ・ｓ以下の粘度とし、ディスペンサで基材４上に塗布すればよい。突起８で規制されて電極９と基材４との間に広げられるとともに突起８の外側へ回り込み、接合部３の厚さと厚さの均一性、接合性を確保できる。
また、はんだを用いないため、溶融、凝固により生じる脆くて壊れやすい金属間化合物を形成しない。
また、短辺に突起８を形成すれば、溶剤成分を含む金属焼結材ペーストの焼結時に、溶剤成分を長辺側から揮発できるため、接合部３の過度な多孔質化を防止できる。 The metal sintered material paste may be obtained by, for example, dispersing Ag sintered material in a solvent so as to have a viscosity of 5 Pa·s or more and 200 Pa·s or less, and applying the paste onto the substrate 4 with a dispenser. It is regulated by the projection 8 and spreads between the electrode 9 and the base material 4, and also wraps around the outside of the projection 8, so that the thickness of the joint 3, the uniformity of the thickness, and the bondability can be ensured.
In addition, since no solder is used, no brittle and fragile intermetallic compounds caused by melting and solidification are formed.
Moreover, if the projections 8 are formed on the short sides, the solvent component can be volatilized from the long side during sintering of the metal sintering material paste containing the solvent component, so that the joint 3 can be prevented from becoming excessively porous.

また、図４（ａ）に示すように長辺側の端面に突起８を形成してもよい。この構成により、突起８と接合部３との接合面積を大きくでき、接合強度を向上できる。
また、図４（ｂ）に示すように、抜け穴１０を設けるとともに電極９の端面を囲むように突起８を形成してもよい。この構成により、接合面積を大きくできる。溶剤成分が揮発できれば、電極９の端面の全周に形成してもよい。
また、図４（ｃ）に示すように、突起８を電極９の角部のみに設けてもよい。溶剤成分を突起８が形成されていない部分から揮発させることができ、接合部３の過度な多孔質化を防止できる。突起８を対角となる一対の角部にのみ形成してもよい。
また、図４（ｄ）に示すように、突起８を角部及び端面の辺上に形成してもよい。溶剤成分が揮発しやすく、接合面積を大きくできる。図示しないが、隣り合った角部に突起８を形成するとともに、これと対向する端面の辺上に突起８を設けることもできる。突起８が対になり、均一に電極９を支えることができればよい。
また、図４（ｅ）に示すように、突起８を電極９の端面の長辺の一部に部分的に形成してもよい。短辺の一部に形成してもよく、長辺と短辺の双方に形成してもよい。少なくとも１つの対となるように突起８があればよく、この構成により、溶剤成分の揮発と、突起８と接合部３との接合面積を制御できる。 Moreover, as shown in FIG. 4A, protrusions 8 may be formed on the end faces on the long sides. With this configuration, the bonding area between the protrusion 8 and the bonding portion 3 can be increased, and the bonding strength can be improved.
Moreover, as shown in FIG. 4(b), a loophole 10 may be provided and a protrusion 8 may be formed so as to surround the end surface of the electrode 9. FIG. This configuration can increase the bonding area. If the solvent component can be volatilized, it may be formed on the entire circumference of the end surface of the electrode 9 .
Moreover, as shown in FIG. 4(c), the protrusions 8 may be provided only at the corners of the electrodes 9. FIG. The solvent component can be volatilized from the portion where the projections 8 are not formed, and the joint portion 3 can be prevented from becoming excessively porous. The protrusions 8 may be formed only on a pair of diagonal corners.
Moreover, as shown in FIG. 4(d), protrusions 8 may be formed on the corners and the sides of the end faces. The solvent component is easily volatilized, and the bonding area can be increased. Although not shown, it is also possible to form protrusions 8 at adjacent corners and to provide protrusions 8 on the side of the end face opposite thereto. It suffices if the projections 8 form a pair and support the electrodes 9 uniformly.
Moreover, as shown in FIG. 4(e), the protrusion 8 may be partially formed on a part of the long side of the end surface of the electrode 9. FIG. It may be formed on a part of the short sides, or may be formed on both the long sides and the short sides. At least one pair of protrusions 8 is sufficient, and this configuration can control the volatilization of the solvent component and the bonding area between the protrusions 8 and the joint portion 3 .

また、接合部３の厚さは、半導体素子１の厚さの１／２０以上の厚さを確保することが好ましく、よりヒートサイクル性を向上できる。より好ましくは半導体素子１の１／１０以上、さらに１／５以上である。 Moreover, it is preferable that the thickness of the joint portion 3 should be 1/20 or more of the thickness of the semiconductor element 1, so that the heat cycle property can be further improved. It is more preferably 1/10 or more, more preferably 1/5 or more of the semiconductor element 1 .

なお、金属焼結材は、Ａｇ焼結材、Ｃｕ焼結材、Ａｕ焼結材、Ｐｄ焼結材、Ｐｔ焼結材等の貴金属に分類される純金属をベースにした焼結材、Ａｇ－Ｐｄ焼結材、Ａｕ－Ｓｉ焼結材、Ａｕ－Ｇｅ焼結材、Ａｕ－Ｃｕ焼結材等の合金をベースにした焼結材等を用いればよい。 The sintered metal material includes sintered materials based on pure metals classified as precious metals such as Ag sintered materials, Cu sintered materials, Au sintered materials, Pd sintered materials, and Pt sintered materials. A sintered material based on an alloy such as a Pd sintered material, an Au--Si sintered material, an Au--Ge sintered material, and an Au--Cu sintered material may be used.

また、本実施の形態において、突起８をめっき処理により形成する例を示したが、マスキングしてスパッタにより積層成膜してもよい。また、電極９を厚く形成し、エッチング、研磨によって一部を除去して、突起８を形成してもよい。 Moreover, in the present embodiment, an example of forming the projections 8 by plating is shown, but they may be formed by sputtering after masking. Also, the electrode 9 may be formed thick and the protrusion 8 may be formed by partially removing the electrode 9 by etching and polishing.

また、長辺と短辺の長さが異なる高周波通信用の半導体素子１の例を示したが、長辺と短辺の長さが等しい半導体素子１を使用してもよい。 Moreover, although the example of the semiconductor element 1 for high-frequency communication with different lengths of the long sides and the short sides has been shown, a semiconductor element 1 with the same length of the long sides and the short sides may be used.

また、基材４としてＣｕ製のヒートシンクを用いた例を示したが、半導体素子１の動作による熱を逃がす機能があるヒートシンク材であればよい。例えば、鉄、タングステン、モリブデン、ニッケル、コバルト、これらの合金、又はこれらの複合材料を用いてもよい。熱伝導率の高いヒートシンク材を用いることにより、半導体素子１から発生する熱を効率よく外に逃がすことができ、接合部３に加わる歪みを低減できる。
上記の基材４の表面に酸化防止膜を形成してもよい。半導体素子１と回路基板２と接合部３の接合性を向上させるために、金、銀等のめっき層を形成してもよい。
また、基材４の形状は、四角柱の他、多角柱、円柱、楕円柱、これらの一部に段を設けた形状であってもよい。 Moreover, although an example of using a heat sink made of Cu as the base material 4 has been shown, any heat sink material having a function of releasing heat generated by the operation of the semiconductor element 1 may be used. For example, iron, tungsten, molybdenum, nickel, cobalt, alloys thereof, or composite materials thereof may be used. By using a heat sink material with high thermal conductivity, the heat generated from the semiconductor element 1 can be efficiently released to the outside, and the strain applied to the joint portion 3 can be reduced.
An antioxidant film may be formed on the surface of the substrate 4 described above. In order to improve the bondability between the semiconductor element 1, the circuit board 2, and the joint portion 3, a plated layer of gold, silver, or the like may be formed.
Moreover, the shape of the base material 4 may be a polygonal prism, a circular cylinder, an elliptical cylinder, or a shape in which a step is provided on a part of these, in addition to the square prism.

また、回路基板２を実装する例を示したが、少なくとも半導体素子１が実装されればよい。 Also, although an example in which the circuit board 2 is mounted has been shown, at least the semiconductor element 1 may be mounted.

すなわち、本実施の形態にかかる半導体装置１００は、基材４と、基材４側の面に電極９を有する半導体素子１と、電極９の端面に基材４方向に突出して形成され、対向して少なくとも一対となる突起８と、突起８及び電極９を覆うように金属焼結材により形成された接合部３とを備える構成によって、接合部３の厚さ、及び厚さの均一性を確保して半導体素子１と基材４を接合できるとともに、突起８と接合部３との界面に未接合領域が形成されにくく、接合性を向上できる。 That is, the semiconductor device 100 according to the present embodiment includes a substrate 4, a semiconductor element 1 having an electrode 9 on the surface on the side of the substrate 4, and an end surface of the electrode 9 formed so as to protrude in the direction of the substrate 4. The thickness of the joint portion 3 and the uniformity of the thickness can be improved by the structure including at least a pair of protrusions 8 and the joint portion 3 formed of a metal sintered material so as to cover the protrusion 8 and the electrode 9. The semiconductor element 1 and the base material 4 can be securely bonded to each other, and an unbonded region is less likely to be formed at the interface between the projection 8 and the bonding portion 3, thereby improving bondability.

実施の形態２．
図５は、本発明の実施の形態２にかかる半導体装置の一部を示す概略構成図である。図５において、図３と同じ符号を付けたものは、同一または対応する構成を示しており、その説明を省略する。 Embodiment 2.
FIG. 5 is a schematic configuration diagram showing part of a semiconductor device according to a second embodiment of the present invention. In FIG. 5, the same reference numerals as in FIG. 3 denote the same or corresponding configurations, and the description thereof will be omitted.

図５に示す突起８は、電極９の端面に形成されるとともに、先端部８１が先細りとなっており、三角柱形状となっている。このように、突起８の先端部８１を先細りにすることにより、高さの制御ができ、接合部３の厚さ、及び厚さの均一性を確保できる。また、接合部３に埋め込むことにより、突起８と接合部３との接合をより強固にできる。 The protrusion 8 shown in FIG. 5 is formed on the end surface of the electrode 9 and has a tapered tip portion 81 to form a triangular prism shape. By tapering the tip portion 81 of the protrusion 8 in this manner, the height can be controlled, and the thickness of the joint portion 3 and the uniformity of the thickness can be ensured. Moreover, by embedding in the joint portion 3, the joint between the projection 8 and the joint portion 3 can be made stronger.

また、図６（ａ）に示すように、突起８を電極９の端面より内側に向かって形成すれば、アンカー効果により、より強固に接合できる。また、熱膨張係数差による歪みに起因する応力が集中する位置を半導体素子１の端面から突起８の先端部８１へと内側に移動させることができ、亀裂の発生、進展を防止できる。 Further, as shown in FIG. 6(a), if the protrusion 8 is formed toward the inner side from the end surface of the electrode 9, the bonding can be made stronger due to the anchor effect. In addition, the position where the stress due to the strain due to the difference in thermal expansion coefficient concentrates can be moved inward from the end surface of the semiconductor element 1 to the tip 81 of the projection 8, thereby preventing the occurrence and propagation of cracks.

さらに、図６（ｂ）に示すように、三角柱の突起８の先端部８１をさらに内側に屈曲させた屈曲部８０を形成することよって、突起８が接合部３に深く食い込むため、いっそうアンカー効果が得られ、突起８と接合部３との接合を強固にできる。さらに、突起８の先端部８１を電極９に向かうように複数回屈曲させて屈曲部８０を設けてもよい。屈曲部８０を複数設ければ、アンカー効果により突起８と接合部３との接合を強固にできる。 Furthermore, as shown in FIG. 6(b), by forming a bent portion 80 in which the distal end portion 81 of the triangular prismatic projection 8 is further bent inward, the projection 8 deeply bites into the joint portion 3, so that the anchoring effect is enhanced. is obtained, and the joint between the projection 8 and the joint portion 3 can be strengthened. Further, the bent portion 80 may be provided by bending the distal end portion 81 of the protrusion 8 toward the electrode 9 multiple times. By providing a plurality of bent portions 80, the joint between the projection 8 and the joint portion 3 can be strengthened by the anchor effect.

また、突起８の表面は平滑でもよいが、粗化めっき等によって表面に凹凸を有するように粗化すれば、より接合部３との接合強度を確保できる。 The surface of the protrusion 8 may be smooth, but if the surface is roughened by roughening plating or the like so as to have unevenness on the surface, the bonding strength with the joint portion 3 can be secured.

また、突起８の先端部８１を半導体素子１の端面より内側に形成する例を示したが、電極９の外側の接合部３で覆うようにして、突起８の先端部８１を半導体素子１の端面より外側に形成してもよい。 Also, although an example in which the tip 81 of the projection 8 is formed inside the end face of the semiconductor element 1 has been shown, the tip 81 of the projection 8 is formed on the semiconductor element 1 by covering it with the bonding portion 3 outside the electrode 9 . It may be formed outside the end face.

突起８の先端部８１を先細りにすることにより、高さの制御ができ、接合部３の厚さ、及び厚さの均一性を確保できとともに、突起８と接合部３との接合をより強固にできる。 By tapering the tip portion 81 of the projection 8, the height can be controlled, the thickness of the joint portion 3 and the uniformity of the thickness can be secured, and the joint between the projection 8 and the joint portion 3 can be made stronger. can be

実施の形態３．
実施の形態１では、突起８を電極９の端面にめっき処理、積層成膜、エッチング、及び研磨によって形成する例を示したが、半導体素子１のパターン及び電極９を形成したウェハを切削して突起８を形成する方法について説明する。図７は、本発明の実施の形態３にかかる半導体素子の突起の形成方法の例を示すイメージ図であり、図８は、本発明の実施の形態３にかかる半導体装置の製造方法の工程図である。 Embodiment 3.
In the first embodiment, an example is shown in which the projections 8 are formed on the end surfaces of the electrodes 9 by plating, layered film formation, etching, and polishing. A method of forming the protrusion 8 will be described. FIG. 7 is an image diagram showing an example of a method for forming protrusions of a semiconductor element according to the third embodiment of the present invention, and FIG. 8 is a process diagram of a method for manufacturing a semiconductor device according to the third embodiment of the present invention. be.

まず、ウェハの一方の面に半導体素子１のパターンを形成し（パターン形成工程）、ウェハの他方の面に半導体素子１の電極９を形成する（電極形成工程）。
次に、半導体素子１のパターン側から電極９の手前まで半導体素子１及びウェハを切削刃１１による切削加工によって溝１２を形成し（溝形成工程）、溝形成工程より切削の加工速度を上げて溝１２から電極９を切削加工し突起８を形成する（突起形成工程）。
例えば、電極９の短辺側の端面にのみ突起８を形成する場合、短辺側を切削するときは上記の溝形成工程及び突起形成工程を行い、長辺側を切削するときは半導体素子１のパターン側から電極９まで同じ速度で切削する。 First, a pattern of the semiconductor elements 1 is formed on one surface of the wafer (pattern forming step), and the electrodes 9 of the semiconductor elements 1 are formed on the other surface of the wafer (electrode forming step).
Next, a groove 12 is formed by cutting the semiconductor element 1 and the wafer from the pattern side of the semiconductor element 1 to the front of the electrode 9 with a cutting blade 11 (groove forming step), and the cutting speed is increased from the groove forming step. The electrode 9 is cut from the groove 12 to form the protrusion 8 (protrusion forming step).
For example, when the projections 8 are formed only on the end faces of the short sides of the electrodes 9, the groove forming step and the projection forming step are performed when cutting the short sides, and the semiconductor element 1 is cut when cutting the long sides. from the pattern side to the electrode 9 at the same speed.

前記突起形成工程において形成された突起８を有する半導体素子１を取り出し、基材４上に塗布された金属焼結材ペースト上に突起８を配置させて、取り出した半導体素子１を搭載する（半導体素子搭載工程）。半導体素子１が搭載された金属焼結材ペーストは加熱、焼結され金属焼結材となり、突起８の内側に充填され基材４と半導体素子１の電極９とを接合する（接合工程）。
半導体素子１のパターンをリードフレーム６と接続し（接続工程）、半導体素子１をリードフレーム６及び基材４の少なくとも一部とともに封止する（封止工程）。 The semiconductor element 1 having the protrusions 8 formed in the protrusion forming step is taken out, the protrusions 8 are arranged on the metal sintered material paste applied on the base material 4, and the taken out semiconductor element 1 is mounted (semiconductor device mounting process). The sintered metal material paste on which the semiconductor element 1 is mounted is heated and sintered to form a sintered metal material, which fills the inside of the projection 8 and joins the base material 4 and the electrode 9 of the semiconductor element 1 (joining step).
The pattern of the semiconductor element 1 is connected to the lead frame 6 (connecting step), and the semiconductor element 1 is sealed together with the lead frame 6 and at least part of the base material 4 (sealing step).

また、突起８の高さは、切削刃１１の速度、切削刃１１の材質、電極９の厚さ等によって制御できる。 Also, the height of the protrusion 8 can be controlled by the speed of the cutting blade 11, the material of the cutting blade 11, the thickness of the electrode 9, and the like.

なお、溝形成工程における溝加工及び突起形成工程における電極の切断加工を、切削刃１１を用いた切削加工とする例を示したが、レーザを用いたレーザ加工としてもよい。 Although an example in which the cutting process using the cutting blade 11 is used for the groove processing in the groove forming process and the electrode cutting process in the projection forming process has been shown, laser processing using a laser may be used.

このように、半導体素子１のパターン及び電極９を形成したウェハを切削又は切断して突起８を形成し半導体装置１００を製造することにより、接合部３の厚さ、及び厚さの均一性を確保して半導体素子１と基材４を接合できるとともに、突起８と接合部３との界面に未接合領域が形成されることを防止できるため、これらの接合性を向上できる。 In this way, by cutting or cutting the wafer on which the patterns of the semiconductor elements 1 and the electrodes 9 are formed to form the protrusions 8 and manufacturing the semiconductor device 100, the thickness of the joint portion 3 and the uniformity of the thickness can be improved. The semiconductor element 1 and the base material 4 can be securely bonded to each other, and the formation of an unbonded region at the interface between the projection 8 and the bonding portion 3 can be prevented, so that the bondability between them can be improved.

なお、実施の形態１～３において半導体素子１としてＬＤＭＯＳを用いた例を示したが、電力増幅機能を有するものだけでなく、高周波信号のスイッチング機能を有するもの等も適用可能である。例えば、Ｓｉ製のＭＯＳＦＥＴ、化合物半導体であるガリウム砒素リンによるＧａＡｓ－ＨＦＥＴ（Ｈｅｔｅｒｏｓｔｒｕｃｔｕｒｅ Ｆｉｅｌｄ Ｅｆｆｅｃｔ Ｔｒａｎｓｉｓｔｏｒ）、ＧａＡｓ－ＨＢＴ（Ｈｅｔｅｒｏｊｕｎｃｔｉｏｎ Ｂｉｐｏｌａｒ Ｔｒａｎｓｉｓｔｏｒ）、窒化ガリウムによるＧａＮ－ＨＦＥＴ（Ｈｅｔｅｒｏｓｔｒｕｃｔｕｒｅ Ｆｉｅｌｄ Ｅｆｆｅｃｔ Ｔｒａｎｓｉｓｔｏｒ）等を用いてもよい。 In the first to third embodiments, an example of using LDMOS as the semiconductor element 1 is shown, but not only those having a power amplification function but also those having a high-frequency signal switching function can be applied. For example, Si MOSFET, GaAs-HFET (Heterostructure Field Effect Transistor) by gallium arsenide phosphide which is a compound semiconductor, GaAs-HBT (Heterojunction Bipolar Transistor), GaN-HFET (Heterostructure Field Effect Transistor) by gallium nitride, etc. good too.

本発明は、発明の範囲内において、各実施の形態を自由に組み合わせることや、各実施の形態を適宜、変形、省略することが可能である。 Within the scope of the invention, each embodiment can be freely combined, and each embodiment can be appropriately modified or omitted.

１ 半導体素子、２ 回路基板、３ 接合部、４ 基材、５ ボンディングワイヤ、
６ リードフレーム、７ モールド樹脂、８ 突起、９ 電極、１０ 抜け穴、
１１ 切削刃、１２ 溝、８０ 屈曲部、８１ 先端部、
１００ 半導体装置。 1 semiconductor element, 2 circuit board, 3 junction, 4 base material, 5 bonding wire,
6 lead frame, 7 mold resin, 8 projection, 9 electrode, 10 loophole,
11 cutting edge, 12 groove, 80 bend, 81 tip,
100 semiconductor devices.

Claims (10)

基材と、
前記基材上に搭載され、前記基材側の面に電極を有する半導体素子と、
前記半導体素子のパターンが形成された面から前記電極が形成された面に向かって、前記電極を切断する切断加工によって形成され、前記電極の端面に前記基材方向に突出し、対向して少なくとも一対となる突起と、
前記突起及び前記電極を覆うように金属焼結材によって前記基材上に形成された接合部と
を備えたことを特徴とする半導体装置。 a substrate;
a semiconductor element mounted on the base material and having an electrode on the surface facing the base material;
The electrodes are formed by cutting the electrodes from the pattern-formed surface of the semiconductor element toward the electrode-formed surface . and a protrusion that becomes
A semiconductor device comprising: a joint portion formed on the base material with a sintered metal material so as to cover the projection and the electrode. 前記突起は、前記電極の前記端面の短辺及び長辺の少なくとも一方に形成されることを特徴とする請求項１に記載の半導体装置。 2. The semiconductor device according to claim 1, wherein said protrusion is formed on at least one of the short side and the long side of said end face of said electrode. 前記突起は、前記電極の前記短辺及び前記長辺の少なくとも一方の一部に対となるように形成されることを特徴とする請求項２に記載の半導体装置。 3. The semiconductor device according to claim 2, wherein said protrusions are formed in pairs on a part of at least one of said short side and said long side of said electrode. 前記突起は、前記半導体素子の前記電極の対角となる少なくとも一対の角部に形成されることを特徴とする請求項１に記載の半導体装置。 2. The semiconductor device according to claim 1, wherein said protrusions are formed on at least a pair of corners that are diagonal to said electrodes of said semiconductor element. 前記突起の先端部は、先細りに形成されることを特徴とする請求項１～４のいずれか一項に記載の半導体装置。 5. The semiconductor device according to claim 1, wherein the tip of said protrusion is tapered. 前記突起の前記先端部は、前記電極の前記端面よりも内側に形成されることを特徴とする請求項５に記載の半導体装置。 6. The semiconductor device according to claim 5, wherein said tip portion of said protrusion is formed inside said end face of said electrode. 前記突起の前記先端部は、内側に屈曲させた屈曲部を有することを特徴とする請求項５又は６に記載の半導体装置。 7. The semiconductor device according to claim 5, wherein said tip portion of said projection has an inwardly bent portion. ウェハの一方の面に半導体素子のパターンを形成するパターン形成工程と、
前記ウェハの他方の面に前記半導体素子の電極を形成する電極形成工程と、
前記半導体素子のパターン側から前記電極の手前まで前記半導体素子及び前記ウェハを溝加工して溝を形成する溝形成工程と、
前記溝形成工程より加工速度を上げて前記溝から前記電極を切断加工し、対向する少なくとも一対の突起を形成する突起形成工程と、
前記突起を有する前記半導体素子を取り出す工程と、
基材上に金属焼結材ペーストを塗布し、前記金属焼結材ペースト上に前記突起を配置させて取り出した前記半導体素子を搭載する半導体素子搭載工程と、
前記金属焼結材ペーストを加熱し、前記金属焼結材ペーストが焼結された金属焼結材を前記突起の内側に充填して前記基材と前記半導体素子の前記電極とを接合する接合工程と、
前記半導体素子のパターンをリードフレームと接続する接続工程と、
前記半導体素子を前記リードフレーム及び前記基材の少なくとも一部とともに封止する封止工程と、
を備えた半導体装置の製造方法。 a pattern forming step of forming a pattern of semiconductor elements on one surface of the wafer;
an electrode forming step of forming an electrode of the semiconductor element on the other surface of the wafer;
a groove forming step of forming a groove by processing the semiconductor element and the wafer from the pattern side of the semiconductor element to the front of the electrode;
a protrusion forming step of cutting the electrode from the groove at a higher processing speed than the groove forming step to form at least a pair of opposing protrusions;
taking out the semiconductor element having the protrusion;
A semiconductor element mounting step of applying a metal sintered material paste on a base material and mounting the semiconductor element taken out by arranging the protrusions on the metal sintered material paste;
A joining step of heating the metal sintered material paste and filling the metal sintered material obtained by sintering the metal sintered material paste into the inside of the protrusion to join the base material and the electrode of the semiconductor element. and,
a connecting step of connecting the pattern of the semiconductor element to a lead frame;
a sealing step of sealing the semiconductor element together with at least part of the lead frame and the base;
A method of manufacturing a semiconductor device comprising 前記溝形成工程における前記溝加工は、切削加工又はレーザ加工であることを特徴とする請求項８に記載の半導体装置の製造方法。 9. The method of manufacturing a semiconductor device according to claim 8, wherein said groove processing in said groove forming step is cutting processing or laser processing. 前記突起形成工程における前記電極の切断加工は、切削加工又はレーザ加工であることを特徴とする請求項８に記載の半導体装置の製造方法。 9. The method of manufacturing a semiconductor device according to claim 8, wherein the cutting of the electrode in the projection forming step is cutting or laser processing.
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