JP2008021716A - Power module substrate and method of manufacturing the same, and power module - Google Patents

Power module substrate and method of manufacturing the same, and power module Download PDF

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JP2008021716A
JP2008021716A JP2006190266A JP2006190266A JP2008021716A JP 2008021716 A JP2008021716 A JP 2008021716A JP 2006190266 A JP2006190266 A JP 2006190266A JP 2006190266 A JP2006190266 A JP 2006190266A JP 2008021716 A JP2008021716 A JP 2008021716A
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power module
circuit layer
outer peripheral
module substrate
brazing material
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Shinsuke Aoki
慎介 青木
Toshiyuki Nagase
敏之 長瀬
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Mitsubishi Materials Corp
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Mitsubishi Materials Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

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Abstract

<P>PROBLEM TO BE SOLVED: To prevent a melted brazing material from riding on a surface to be bonded with a semiconductor chip along the side face of a circuit layer when the circuit layer is brazed on the surface of a ceramics board. <P>SOLUTION: When manufacturing the power module substrate, a brazing material foil 20 is arranged in a laminated body 14a, and it is provided with an outer circumference 20a wherein the outer circumference edge of a circuit layer 12 is arranged on its surface and an inside 20b surrounded by the outer circumference 20a. The outer circumference 20a is made of a material with higher liquid phase temperature than that of a material forming the inside 20b. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

この発明は、大電流、高電圧を制御する半導体装置に用いられるパワーモジュール用基板の製造方法およびパワーモジュール用基板並びにパワーモジュールに関するものである。   The present invention relates to a power module substrate manufacturing method, a power module substrate, and a power module used in a semiconductor device that controls a large current and a high voltage.

この種のパワーモジュールは一般に、セラミックス板の表面に回路層がろう付けされたパワーモジュール用基板と、回路層の表面にはんだ接合された半導体チップとを備えている。このうちパワーモジュール用基板は、セラミックス板の表面にろう材箔と回路層とをこの順に配置して積層体とした後に、この積層体を積層方向に加圧した状態で加熱しろう材箔を溶融させて、セラミックス板の表面に回路層をろう付けすることにより形成されている。そして、このろう付けには、例えば下記特許文献１に示されるように、回路層の平面視形状と略同形同大で、かつ全体が同一の材質からなるろう材箔が用いられている。
実公平８−１０２０２号公報 This type of power module generally includes a power module substrate having a circuit layer brazed to the surface of a ceramic plate, and a semiconductor chip soldered to the surface of the circuit layer. Of these, the power module substrate is formed by arranging a brazing material foil and a circuit layer in this order on the surface of the ceramic plate to form a laminate, and then heating the brazing material foil in a state of being pressed in the laminating direction. It is formed by melting and brazing the circuit layer on the surface of the ceramic plate. For this brazing, for example, as shown in Patent Document 1 below, a brazing material foil that is substantially the same shape and size as the planar view of the circuit layer and is entirely made of the same material is used.
No. 8-10202

しかしながら、前記従来のパワーモジュール用基板の製造方法では、ろう材箔を溶融させるのに前記積層体を加熱炉内に置いて加熱すると、ろう材箔はまず、その外周縁部に加熱炉内の熱が伝わって溶融し始め、その後徐々に沿面方向の内方に向けて熱が伝導し溶融が進んでいくので、ろう材箔の沿面方向における中央部を溶融させるまで加熱しようとすると、その前に、ろう材箔の外周縁部を構成していた既に溶融したろう材が、回路層とセラミックス板との間から染み出し、さらにその表面張力で凝集することによって、回路層の側面を伝って半導体チップがはんだ接合される表面に乗り上がるおそれがあった。
このようにして回路層の表面に乗り上げたろう材は視認することができ、外観品質を低減させるおそれがある。特に、Ｓｉを含有する例えばＡｌ−Ｓｉ系のろう材箔を用いて、純Ａｌ若しくはＡｌ合金からなる回路層をセラミックス板にろう付する場合には、溶融後に硬化したろう材は、回路層よりも硬い上にパワーモジュールを使用する過程における熱サイクルでさらに加工硬化させられることによって、回路層に対してその表面および側面から大きな外力が作用して、回路層とセラミックス板との接合界面に大きな応力が作用し、回路層がセラミックス板の表面から剥離し易くなり、パワーモジュールの熱サイクル寿命を低下させるおそれがある。さらに、上記と同様の材質からなるろう材箔および回路層を用いた場合において、回路層の表面のうちろう材が乗り上げた部分にワイヤボンディングが施されると、ろう材は前記のように回路層と比べて硬いので、この部分とワイヤボンディングとの接合部における熱サイクル寿命を低下させるおそれもある。 However, in the conventional method for manufacturing a power module substrate, when the laminated body is heated in a heating furnace to melt the brazing material foil, the brazing material foil is first placed on the outer peripheral edge of the heating furnace. Heat is transmitted and begins to melt, and then heat gradually conducts toward the inside of the creeping direction, and melting progresses.Therefore, when trying to heat until the center part in the creeping direction of the brazing foil is melted, In addition, the already melted brazing material constituting the outer peripheral edge of the brazing material foil oozes out from between the circuit layer and the ceramic plate, and further aggregates by the surface tension, thereby traveling along the side surface of the circuit layer. There is a possibility that the semiconductor chip may run on the surface to be soldered.
In this way, the brazing material riding on the surface of the circuit layer can be visually recognized, and the appearance quality may be reduced. In particular, when a circuit layer made of pure Al or an Al alloy is brazed to a ceramic plate using, for example, an Al-Si brazing foil containing Si, the brazing material cured after melting is more difficult than the circuit layer. In addition to being hard, it is further hardened by heat cycle in the process of using the power module, so that a large external force acts on the circuit layer from its surface and side surface, resulting in a large interface at the interface between the circuit layer and the ceramic plate. The stress acts, the circuit layer is easily peeled off from the surface of the ceramic plate, and the thermal cycle life of the power module may be reduced. Further, in the case where the brazing material foil and the circuit layer made of the same material as described above are used, when wire bonding is applied to the portion of the surface of the circuit layer where the brazing material has run over, the brazing material becomes a circuit as described above. Since it is harder than the layer, the thermal cycle life at the joint between this part and wire bonding may be reduced.

本発明はこのような事情を考慮してなされたもので、セラミックス板の表面に回路層をろう付けする際に、溶融したろう材が回路層の側面を伝って、半導体チップが接合される表面に乗り上がるのを抑制することができるパワーモジュール用基板の製造方法およびパワーモジュール用基板並びにパワーモジュールを提供することを目的とする。   The present invention has been made in view of such circumstances, and when brazing the circuit layer to the surface of the ceramic plate, the surface to which the semiconductor chip is joined by the molten brazing material traveling along the side surface of the circuit layer An object of the present invention is to provide a power module substrate manufacturing method, a power module substrate, and a power module that can suppress the boarding.

このような課題を解決して、前記目的を達成するために、本発明のパワーモジュール用基板の製造方法は、セラミックス板の表面にろう材箔と回路層とをこの順に配置して積層体とした後に、この積層体を積層方向に加圧した状態で加熱してろう材箔を溶融させることにより、セラミックス板の表面に回路層がろう付けされてなり、この回路層の表面に半導体チップがはんだ接合されるパワーモジュール用基板を形成するパワーモジュール用基板の製造方法であって、前記ろう材箔は、前記積層体において、表面に前記回路層の外周縁部が配置される外周部分と、この外周部分に囲まれた内側部分とを備え、前記外周部分は前記内側部分を形成する材質と比べて液相温度が高い材質で形成されていることを特徴とする。
この発明では、ろう材箔の外周部分が、前記内側部分を形成する材質よりも液相温度の高い材質で形成されているので、前記積層体を加熱したときに、まず、ろう材箔の前記内側部分を溶融させて、その後、前記外周部分を溶融させることが可能になる。したがって、ろう材箔の前記内側部分が溶融し、この溶融したろう材がろう材箔の外周縁に向けて拡がるように流れようとしても、その流れを、ろう材箔の前記外周部分でせき止めることができる。また、前記加熱してセラミックス板と回路層とをろう付けする過程において、ろう材箔の前記外周部分が溶融する時点を、前記従来のように全体が同一の材質からなるろう材箔を用いるのと比べて遅らせることが可能になり、この外周部分が溶融状態となっている時間を短縮することができる。
以上より、セラミックス板の表面に回路層をろう付けする際に、溶融したろう材が回路層の側面を伝って、半導体チップが接合される表面に乗り上がるのを抑制することができる。 In order to solve such problems and achieve the above object, a method for manufacturing a power module substrate according to the present invention includes a laminated body in which a brazing material foil and a circuit layer are arranged in this order on the surface of a ceramic plate. After that, the laminated body is heated in a state of being pressed in the laminating direction to melt the brazing material foil, whereby the circuit layer is brazed to the surface of the ceramic plate, and the semiconductor chip is formed on the surface of the circuit layer. A power module substrate manufacturing method for forming a power module substrate to be soldered, wherein the brazing material foil has an outer peripheral portion in which an outer peripheral edge portion of the circuit layer is disposed on a surface of the laminate, And an inner portion surrounded by the outer peripheral portion, wherein the outer peripheral portion is formed of a material having a higher liquidus temperature than the material forming the inner portion.
In this invention, since the outer peripheral portion of the brazing material foil is formed of a material having a higher liquidus temperature than the material forming the inner portion, when the laminate is heated, It is possible to melt the inner part and then melt the outer peripheral part. Therefore, even if the inner part of the brazing filler metal is melted and the molten brazing material tries to flow so as to spread toward the outer peripheral edge of the brazing filler metal foil, the flow is stopped at the outer peripheral part of the brazing filler metal foil. Can do. Further, in the process of brazing the ceramic plate and the circuit layer by heating, the time when the outer peripheral portion of the brazing material foil is melted is used by using the brazing material foil which is entirely made of the same material as in the prior art. It is possible to delay compared to the above, and the time during which the outer peripheral portion is in a molten state can be shortened.
As described above, when the circuit layer is brazed to the surface of the ceramic plate, it is possible to suppress the molten brazing material from traveling onto the surface to which the semiconductor chip is bonded along the side surface of the circuit layer.

ここで、前記外周部分は前記内側部分を形成する材質よりも液相温度が１０℃以上３０℃以下高い材質で形成されてもよい。
この場合、前記の作用効果が確実に奏効されることになる。すなわち、両液相温度の差が１０℃より小さいと、ろう付け時の加熱温度を加熱炉内の全域にわたってばらつき少なく均一にしなければ、ろう材箔の前記外周部分が前記内側部分と略同時に溶融し始めたり、あるいは前記外周部分が溶融した後に、前記内側部分が溶融したりするおそれがある。また、両液相温度の差が３０℃より大きいと、ろう材箔において、前記内側部分を溶融させた後、前記外周部分を溶融させるまでに、この内側部分のろう材を熱により変質させたり、あるいは前記外周部分および内側部分の各組成が互いに大きく異なったことに起因して、ろう付け時に互いが反応し合い例えばろう付けの接合強度を低下させる等し、さらには、加熱炉の温度制御が困難になる等のおそれがある。 Here, the outer peripheral portion may be formed of a material having a liquidus temperature higher by 10 ° C. or higher and 30 ° C. or lower than a material forming the inner portion.
In this case, the above-described effects are surely achieved. That is, if the difference between the two liquid phase temperatures is less than 10 ° C., the outer peripheral portion of the brazing material foil is melted substantially simultaneously with the inner portion unless the heating temperature during brazing is uniform with little variation over the entire area in the heating furnace. Or the inner part may melt after the outer peripheral part melts. Further, if the difference between the two liquid phase temperatures is larger than 30 ° C., after the inner portion of the brazing material foil is melted, the inner portion of the brazing material is altered by heat before the outer peripheral portion is melted. Or, because the respective compositions of the outer peripheral portion and the inner portion are greatly different from each other, they react with each other at the time of brazing, for example, the bonding strength of the brazing is reduced, and further, the temperature control of the heating furnace May become difficult.

また、本発明のパワーモジュール用基板は、セラミックス板の表面に回路層がろう付けされてなり、この回路層の表面に半導体チップがはんだ接合されるパワーモジュール用基板であって、本発明のパワーモジュール用基板の製造方法により形成されたことを特徴とする。
さらに、本発明のパワーモジュールは、セラミックス板の表面に回路層がろう付けされたパワーモジュール用基板と、回路層の表面にはんだ接合された半導体チップとを備えたパワーモジュールであって、前記パワーモジュール用基板は、本発明のパワーモジュール用基板の製造方法により形成されたことを特徴とする。 The power module substrate of the present invention is a power module substrate in which a circuit layer is brazed to the surface of a ceramic plate, and a semiconductor chip is soldered to the surface of the circuit layer. It is formed by a method for manufacturing a module substrate.
Furthermore, the power module of the present invention is a power module comprising a power module substrate having a circuit layer brazed to the surface of a ceramic plate, and a semiconductor chip solder-bonded to the surface of the circuit layer. The module substrate is formed by the method for manufacturing a power module substrate of the present invention.

この発明に係るパワーモジュール用基板の製造方法およびパワーモジュール用基板並びにパワーモジュールによれば、セラミックス板の表面に回路層をろう付けする際に、溶融したろう材が回路層の側面を伝って、半導体チップが接合される表面に乗り上がるのを抑制することができる。   According to the power module substrate manufacturing method and the power module substrate and the power module according to the present invention, when the circuit layer is brazed to the surface of the ceramic plate, the molten brazing material travels along the side surface of the circuit layer, It is possible to suppress climbing onto the surface to which the semiconductor chip is bonded.

以下、図面を参照し、この発明の実施の形態について説明する。図１はこの発明の一実施形態に係るパワーモジュール用基板を適用したパワーモジュールを示す全体図である。
このパワーモジュール１０は、セラミックス板１１の表面に回路層１２がろう付けされたパワーモジュール用基板１４と、回路層１２の表面にはんだ層１７を介してはんだ接合された半導体チップ１５とを備えている。 Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is an overall view showing a power module to which a power module substrate according to an embodiment of the present invention is applied.
This power module 10 includes a power module substrate 14 having a circuit layer 12 brazed to the surface of a ceramic plate 11 and a semiconductor chip 15 soldered to the surface of the circuit layer 12 via a solder layer 17. Yes.

図示の例では、パワーモジュール用基板１４には、回路層１２と同じ材質からなる金属層１８が、セラミックス板１１の裏面にろう付けされて備えられている。さらに、パワーモジュール１０には、冷却器１６が、金属層１８の裏面にろう付けや拡散接合により接合されて備えられている。
なお、セラミックス板１１は、例えばＡｌＮ、Ａｌ２Ｏ３、Ｓｉ３Ｎ４若しくはＳｉＣ等で形成され、回路層１２および金属層１８はそれぞれ、例えば純Ａｌ若しくはＡｌ合金で形成され、冷却器１６は、純Ａｌ、純Ｃｕ、Ａｌ合金若しくはＣｕ合金で形成され、はんだ層１７は、例えばＳｎ−Ａｇ−Ｃｕ系若しくはＺｎ−Ａｌ系のはんだ材とされ、さらに、セラミックス板１１と回路層１２および金属層１８とは、厚さが例えば１０μｍ〜３０μｍのＡｌ系のろう材箔２０を用いてろう付けされている。 In the illustrated example, the power module substrate 14 is provided with a metal layer 18 made of the same material as the circuit layer 12 by being brazed to the back surface of the ceramic plate 11. Further, the power module 10 is provided with a cooler 16 bonded to the back surface of the metal layer 18 by brazing or diffusion bonding.
The ceramic plate 11 is made of, for example, AlN, Al 2 O 3 , Si 3 N 4, or SiC, and the circuit layer 12 and the metal layer 18 are made of, for example, pure Al or Al alloy, and the cooler 16 is , Pure Al, pure Cu, Al alloy or Cu alloy, and the solder layer 17 is made of, for example, Sn—Ag—Cu-based or Zn—Al-based solder material. Further, the ceramic plate 11, the circuit layer 12, and the metal The layer 18 is brazed using an Al-based brazing material foil 20 having a thickness of, for example, 10 μm to 30 μm.

ここで、本実施形態では、回路層１２および金属層１８はそれぞれ、純Ａｌ若しくはＡｌ合金からなる母材を打ち抜いたり、あるいは鋳造により形成されており、回路層１２および金属層１８の各外表面のうち、セラミックス板１１の表裏面から立上がる側面はそれぞれ、セラミックス板１１の表裏面に対して略垂直に延在している。   Here, in the present embodiment, each of the circuit layer 12 and the metal layer 18 is formed by stamping or casting a base material made of pure Al or an Al alloy, and each outer surface of the circuit layer 12 and the metal layer 18. Among these, the side surfaces rising from the front and back surfaces of the ceramic plate 11 respectively extend substantially perpendicular to the front and back surfaces of the ceramic plate 11.

次に、以上のように構成されたパワーモジュール用基板１４の製造方法について説明する。
まず、図２に示されるように、セラミックス板１１の表面に、Ａｌ系のろう材箔２０と回路層１２とをこの順に配置するとともに、セラミックス板１１の裏面に、Ａｌ系のろう材箔２０と金属層１８とをこの順に配置して積層体１４ａを形成する。そして、この積層体１４ａを、加熱炉内に置いて積層方向に加圧した状態で加熱し、ろう材箔２０を溶融させることによって、セラミックス板１１の表面に回路層１２をろう付けするとともに、セラミックス板１１の裏面に金属層１８をろう付けし、パワーモジュール用基板１４を形成する。 Next, a method for manufacturing the power module substrate 14 configured as described above will be described.
First, as shown in FIG. 2, the Al-based brazing material foil 20 and the circuit layer 12 are arranged in this order on the surface of the ceramic plate 11, and the Al-based brazing material foil 20 is disposed on the back surface of the ceramic plate 11. And the metal layer 18 are arranged in this order to form the laminate 14a. Then, the laminated body 14a is heated in a state of being placed in a heating furnace and pressurized in the laminating direction, and the brazing material foil 20 is melted to braze the circuit layer 12 to the surface of the ceramic plate 11, A metal layer 18 is brazed to the back surface of the ceramic plate 11 to form a power module substrate 14.

ここで、本実施形態では、ろう材箔２０は、図２および図３に示されるように、積層体１４ａにおいて、表面に回路層１２の外周縁部が配置される外周部分２０ａと、この外周部分２０ａに囲まれた内側部分２０ｂとを備えている。そして、外周部分２０ａは内側部分２０ｂを形成する材質と比べて液相温度が高い材質で形成されている。例えば、外周部分２０ａは内側部分２０ｂを形成する材質よりも液相温度が１０℃以上３０℃以下高い材質で形成されている。図示の例では、金属層１８とセラミックス板１１との間に配置されたろう材箔２０も、回路層１２とセラミックス板１１との間に配置されたろう材箔２０と同様に、外周部分２０ａと内側部分２０ｂとを備えている。なお、本実施形態では、ろう材箔２０は、回路層１２の裏面の、セラミックス板１１の表面への投影面における略全域に配置されるとともに、金属層１８の裏面の、セラミックス板１１の裏面への投影面における略全域にも配置されている。   Here, in this embodiment, as shown in FIG. 2 and FIG. 3, the brazing filler metal foil 20 includes an outer peripheral portion 20 a in which the outer peripheral edge portion of the circuit layer 12 is disposed on the surface of the laminate 14 a, and this outer periphery. And an inner portion 20b surrounded by the portion 20a. And the outer peripheral part 20a is formed with the material whose liquidus temperature is high compared with the material which forms the inner part 20b. For example, the outer peripheral portion 20a is made of a material whose liquidus temperature is higher by 10 ° C. or more and 30 ° C. or less than the material forming the inner portion 20b. In the example shown in the drawing, the brazing material foil 20 disposed between the metal layer 18 and the ceramic plate 11 is also similar to the brazing material foil 20 disposed between the circuit layer 12 and the ceramic plate 11. And a portion 20b. In the present embodiment, the brazing filler metal foil 20 is disposed in substantially the entire area of the back surface of the circuit layer 12 on the projection surface onto the surface of the ceramic plate 11, and the back surface of the ceramic plate 11 on the back surface of the metal layer 18. It is also arranged over substantially the entire area on the projection plane.

これらの外周部分２０ａおよび内側部分２０ｂはそれぞれ、例えば、Ａｌ−Ｓｉ系、Ａｌ−Ｓｉ−Ｍｇ系、Ａｌ−Ｓｉ−Ｃｕ−Ｍｇ系、Ａｌ−Ｆｅ−Ｎｉ系、Ａｌ−Ｓｉ−Ｆｅ―Ｎｉ系、Ａｌ−Ｓｉ−Ｍｇ−Ｆｅ系、Ａｌ−Ｓｉ−Ｃｕ系、Ａｌ−Ｓｉ−Ｆｅ系、およびＡｌ−Ｓｉ−Ｍｇ−Ｆｅ−Ｍｎ系等のろう材箔のうちの１つで、かつ外周部分２０ａの液相温度が、内側部分２０ｂの液相温度よりも１０℃以上３０℃以下高くなる組合わせのろう材箔とされている。   Each of the outer peripheral portion 20a and the inner portion 20b is, for example, Al-Si-based, Al-Si-Mg-based, Al-Si-Cu-Mg-based, Al-Fe-Ni-based, Al-Si-Fe-Ni-based, respectively. , Al—Si—Mg—Fe, Al—Si—Cu, Al—Si—Fe, and Al—Si—Mg—Fe—Mn, etc. The brazing material foil is a combination in which the liquid phase temperature of 20a is higher by 10 ° C. or more and 30 ° C. or less than the liquid phase temperature of the inner portion 20b.

また、図示の例では、外周部分２０ａは、回路層１２の裏面の外周縁に沿ってその全周にわたって延在し、その沿面方向における内側に内側部分２０ｂが配置されている。なお、前記沿面方向は、積層体１４ａの積層方向に直交する方向のことをいう。さらに、内側部分２０ｂの外周縁は、外周部分２０ａの内周縁と同形同大とされており、内側部分２０ｂの外周縁と、外周部分２０ａの内周縁との間には略隙間のない状態となっている。   In the illustrated example, the outer peripheral portion 20a extends over the entire periphery along the outer peripheral edge of the back surface of the circuit layer 12, and the inner portion 20b is disposed on the inner side in the creeping direction. The creeping direction means a direction orthogonal to the stacking direction of the stacked body 14a. Further, the outer peripheral edge of the inner portion 20b is the same shape and size as the inner peripheral edge of the outer peripheral portion 20a, and there is substantially no gap between the outer peripheral edge of the inner portion 20b and the inner peripheral edge of the outer peripheral portion 20a. It has become.

このようなろう材箔２０を用いて積層体１４ａを加熱する際、まず、内側部分２０ｂの液相温度になるまで加熱した後に、その温度を内側部分２０ｂが全て液相状態になるまで保持し、その後、外周部分２０ａの液相温度になるまでさらに加熱し、その温度になったのと略同時に、あるいはその温度に、内側部分２０ｂの液相温度で保持した時間よりも短い時間保持した後に、つまり外周部分２０ａが液相状態になったのと略同時にこの加熱を停止して徐冷し、パワーモジュール用基板１４を形成する。   When heating the laminated body 14a using such a brazing filler metal foil 20, first, after heating until the liquid phase temperature of the inner part 20b is reached, the temperature is maintained until all of the inner part 20b is in a liquid phase state. Then, after further heating until the liquid phase temperature of the outer peripheral part 20a is reached, after being held for a time shorter than the time held at the liquid phase temperature of the inner part 20b at the same temperature or at that temperature. That is, the heating is stopped and gradually cooled to form the power module substrate 14 substantially simultaneously with the outer peripheral portion 20a being in the liquid phase state.

ここで、この製造方法についての具体的な実施例について説明する。
まず、材質については、回路層１２および金属層１８を純度９９．９８ｗｔ％の純Ａｌ、セラミックス板１１をＡｌＮによりそれぞれ形成した。そして、ろう材箔２０の外周部分２０ａとしてＡｌ−Ｓｉ系のろう材箔（Ａｌが９２．５ｗｔ％、Ｓｉが７．５ｗｔ％、固相温度が５７７℃、液相温度が６１５℃）を採用し、ろう材箔２０の内側部分２０ｂとしてＡｌ−Ｓｉ−Ｍｇ系のろう材箔（固相温度が５６０℃、液相温度が５９５℃）を採用した。厚さについては、回路層１２および金属層１８を約０．４ｍｍ、ろう材箔２０を約１３μｍ、セラミックス板１１を約０．６３５ｍｍとした。なお、外周部分２０ａの外周縁の縦および横の寸法をそれぞれ約２８ｍｍおよび約７０ｍｍとし、この外周縁と内周縁との距離は約５ｍｍとした。そして、平面視四角形とされたろう材箔２０の内側部分２０ｂは、縦および横の寸法をそれぞれ約１８ｍｍおよび約６０ｍｍとした。
そして、積層体１４ａを真空状態の加熱炉内に置いて、この加熱炉内を約５５０℃になるまで１０℃／ｍｉｎで加熱する。その後、約５５０℃の温度を約９０分間保持した後に、さらに約６４５℃になるまで１０℃／ｍｉｎで加熱し、そして、約６４５℃の温度を約４０分間保持した後に徐冷して、パワーモジュール用基板１４を形成した。 Here, specific examples of the manufacturing method will be described.
First, regarding the materials, the circuit layer 12 and the metal layer 18 were formed of pure Al having a purity of 99.98 wt%, and the ceramic plate 11 was formed of AlN. Then, an Al—Si based brazing material foil (Al: 92.5 wt%, Si: 7.5 wt%, solid phase temperature: 577 ° C., liquid phase temperature: 615 ° C.) is adopted as the outer peripheral portion 20 a of the brazing material foil 20. Then, an Al—Si—Mg-based brazing material foil (solid phase temperature of 560 ° C., liquid phase temperature of 595 ° C.) was adopted as the inner portion 20 b of the brazing material foil 20. Regarding the thickness, the circuit layer 12 and the metal layer 18 were about 0.4 mm, the brazing material foil 20 was about 13 μm, and the ceramic plate 11 was about 0.635 mm. The vertical and horizontal dimensions of the outer peripheral edge of the outer peripheral portion 20a were about 28 mm and about 70 mm, respectively, and the distance between the outer peripheral edge and the inner peripheral edge was about 5 mm. The inner portion 20b of the brazing filler metal foil 20 having a square shape in plan view has a vertical and horizontal dimension of about 18 mm and about 60 mm, respectively.
And the laminated body 14a is set | placed in the heating furnace of a vacuum state, and the inside of this heating furnace is heated at 10 degrees C / min until it reaches about 550 degreeC. After that, after holding the temperature of about 550 ° C. for about 90 minutes, further heating at 10 ° C./min until reaching about 645 ° C., holding the temperature of about 645 ° C. for about 40 minutes, and then gradually cooling to power A module substrate 14 was formed.

以上説明したように、本実施形態によるパワーモジュール用基板によれば、ろう材箔２０の外周部分２０ａが、内側部分２０ｂを形成する材質よりも液相温度の高い材質で形成されているので、積層体１４ａを加熱したときに、まず、内側部分２０ｂを溶融させて、その後、外周部分２０ａを溶融させることが可能になる。したがって、ろう材箔２０の内側部分２０ｂが溶融し、この溶融したろう材がろう材箔２０の外周縁に向けて拡がるように流れようとしても、その流れを、ろう材箔２０の外周部分２０ａでせき止めることができる。また、前記加熱してセラミックス板１１と回路層１２とをろう付けする過程において、ろう材箔２０の外周部分２０ａが溶融する時点を、全体が同一の材質からなるろう材箔を用いるのと比べて遅らせることが可能になり、この外周部分２０ａが溶融状態となっている時間を短縮することができる。
以上より、セラミックス板１１の表面に回路層１２をろう付けする際に、溶融したろう材が回路層１２の側面を伝って、半導体チップ１５が接合される表面に乗り上がるのを抑制することができる。 As described above, according to the power module substrate according to the present embodiment, the outer peripheral portion 20a of the brazing foil 20 is formed of a material having a higher liquidus temperature than the material forming the inner portion 20b. When the laminated body 14a is heated, the inner portion 20b can be melted first, and then the outer peripheral portion 20a can be melted. Therefore, even if the inner part 20b of the brazing filler metal foil 20 is melted and the molten brazing material tries to flow so as to spread toward the outer peripheral edge of the brazing filler metal foil 20, the flow is changed to the outer peripheral part 20a of the brazing filler metal foil 20. You can stop it. Further, in the process of brazing the ceramic plate 11 and the circuit layer 12 by heating, the time when the outer peripheral portion 20a of the brazing filler metal foil 20 is melted is compared with the case of using the brazing filler foil made entirely of the same material. The time during which the outer peripheral portion 20a is in a molten state can be shortened.
As described above, when the circuit layer 12 is brazed to the surface of the ceramic plate 11, it is possible to suppress the molten brazing material from traveling on the side surface of the circuit layer 12 and climbing onto the surface to which the semiconductor chip 15 is bonded. it can.

また、本実施形態では、外周部分２０ａは内側部分２０ｂを形成する材質よりも液相温度が１０℃以上３０℃以下高い材質で形成されているので、前記の作用効果が確実に奏効されることになる。すなわち、両液相温度の差が１０℃より小さいと、ろう付け時の加熱温度を加熱炉内の全域にわたってばらつき少なく均一にしなければ、外周部分２０ａが内側部分２０ｂと略同時に溶融し始めたり、あるいは外周部分２０ａが溶融した後に、内側部分２０ｂが溶融したりするおそれがある。また、両液相温度の差が３０℃より大きいと、ろう材箔２０において、内側部分２０ｂを溶融させた後、外周部分２０ａを溶融させるまでに、この内側部分２０ｂのろう材を熱により変質させたり、あるいは外周部分２０ａおよび内側部分２０ｂの各組成が互いに大きく異なったことに起因して、ろう付け時に互いが反応し合い例えばろう付けの接合強度を低下させる等し、さらには、加熱炉の温度制御が困難になる等のおそれがある。   In the present embodiment, the outer peripheral portion 20a is formed of a material having a liquidus temperature higher by 10 ° C. or higher and 30 ° C. or lower than that of the material forming the inner portion 20b. become. That is, if the difference between the liquid phase temperatures is less than 10 ° C., the outer peripheral portion 20a starts to melt almost simultaneously with the inner portion 20b unless the heating temperature during brazing is made uniform with little variation over the entire area in the heating furnace, Alternatively, after the outer peripheral portion 20a is melted, the inner portion 20b may be melted. Further, if the difference between the two liquid phase temperatures is larger than 30 ° C., after the inner portion 20b is melted in the brazing material foil 20, the brazing material of the inner portion 20b is altered by heat before the outer peripheral portion 20a is melted. Or because the respective compositions of the outer peripheral portion 20a and the inner portion 20b are greatly different from each other, they react with each other during brazing, for example, the bonding strength of the brazing is lowered, and the heating furnace It may be difficult to control the temperature.

なお、本発明の技術的範囲は前記実施の形態に限定されるものではなく、本発明の趣旨を逸脱しない範囲において種々の変更を加えることが可能である。
例えば、前記実施形態では、パワーモジュール用基板１４として金属層１８を備えた構成を示したが、この金属層１８を設けなくてもよい。さらに、パワーモジュール１０として冷却器１６を備えた構成を示したが、この冷却器１６を設けなくてもよい。
また、ろう材箔２０の外周部分２０ａおよび内側部分２０ｂを形成する各材質は、前記実施形態で示したものに限られるものではない。さらに、外周部分２０ａは、内側部分２０ｂを形成する材質よりも液相温度が高い材質で形成されていればよく、その温度差は１０℃以上３０℃以下の範囲外であってもよい。 The technical scope of the present invention is not limited to the above embodiment, and various modifications can be made without departing from the spirit of the present invention.
For example, in the above-described embodiment, the configuration in which the metal layer 18 is provided as the power module substrate 14 is shown, but the metal layer 18 may not be provided. Furthermore, although the structure provided with the cooler 16 as the power module 10 was shown, this cooler 16 does not need to be provided.
Moreover, each material which forms the outer peripheral part 20a and the inner side part 20b of the brazing material foil 20 is not restricted to what was shown by the said embodiment. Furthermore, the outer peripheral part 20a should just be formed with the material whose liquidus temperature is higher than the material which forms the inner part 20b, and the temperature difference may be outside the range of 10 degreeC or more and 30 degrees C or less.

さらに、前記実施形態では、ろう材箔２０の外周部分２０ａとして、回路層１２の裏面の外周縁に沿ってその全周にわたって延在した構成を示したが、これに代えて、例えば図３に示されるように、周方向に分割された外周部分２０ａを採用してもよい。
また、前記実施形態では、ろう材箔２０として、内側部分２０ｂの外周縁と、外周部分２０ａの内周縁との間に略隙間のない構成を示したが、これに代えて、例えば約５０μｍ程度であれば隙間を設けてもよい。さらに、図３に示したように、周方向に分割された外周部分２０ａでは、その周方向に隙間のない状態でセラミックス板１１に配置してもよいし、あるいは約５０μｍ程度であればこの周方向に隙間を設けてもよい。また、外周部分２０ａおよび内側部分２０ｂの平面視形状は前記実施形態のものに限られるものではない。 Furthermore, in the said embodiment, although the structure extended over the perimeter along the outer periphery of the back surface of the circuit layer 12 was shown as the outer peripheral part 20a of the brazing material foil 20, it replaces with this, for example in FIG. As shown, an outer peripheral portion 20a divided in the circumferential direction may be employed.
Moreover, in the said embodiment, although the structure without a substantially clearance gap was shown as the brazing material foil 20 between the outer periphery of the inner part 20b, and the inner periphery of the outer peripheral part 20a, it replaces with this, for example, about about 50 micrometers If so, a gap may be provided. Further, as shown in FIG. 3, the outer peripheral portion 20a divided in the circumferential direction may be arranged on the ceramic plate 11 without a gap in the circumferential direction, or if this is about 50 μm, A gap may be provided in the direction. Moreover, the planar view shape of the outer peripheral part 20a and the inner part 20b is not restricted to the thing of the said embodiment.

セラミックス板の表面に回路層をろう付けする際に、溶融したろう材が回路層の側面を伝って、半導体チップが接合される表面に乗り上がるのを抑制することができる。   When the circuit layer is brazed to the surface of the ceramic plate, it is possible to suppress the molten brazing material from traveling onto the surface to which the semiconductor chip is bonded along the side surface of the circuit layer.

この発明の一実施形態に係るパワーモジュール用基板を適用したパワーモジュールを示す全体図である。1 is an overall view showing a power module to which a power module substrate according to an embodiment of the present invention is applied. この発明の一実施形態に係るパワーモジュール用基板の製造方法において、積層体の断面側面図である。In the manufacturing method of the board for power modules concerning one embodiment of this invention, it is a section side view of a layered product. この発明の一実施形態に係るパワーモジュール用基板の製造方法において、図２に示す積層体の一部を示す平面図である。FIG. 3 is a plan view showing a part of the laminate shown in FIG. 2 in the method for manufacturing a power module substrate according to the embodiment of the present invention. この発明の他の実施形態に係るパワーモジュール用基板の製造方法において、図２に示す積層体の一部を示す平面図である。In the manufacturing method of the board | substrate for power modules which concerns on other embodiment of this invention, it is a top view which shows a part of laminated body shown in FIG.

符号の説明Explanation of symbols

１０ パワーモジュール
１１ セラミックス板
１２ 回路層
１４ パワーモジュール用基板
１４ａ 積層体
１５ 半導体チップ
２０ ろう材箔
２０ａ 外周部分
２０ｂ 内側部分
DESCRIPTION OF SYMBOLS 10 Power module 11 Ceramic board 12 Circuit layer 14 Power module board | substrate 14a Laminated body 15 Semiconductor chip 20 Brazing material foil 20a Outer peripheral part 20b Inner part

Claims (4)

セラミックス板の表面にろう材箔と回路層とをこの順に配置して積層体とした後に、この積層体を積層方向に加圧した状態で加熱してろう材箔を溶融させることにより、セラミックス板の表面に回路層がろう付けされてなり、この回路層の表面に半導体チップがはんだ接合されるパワーモジュール用基板を形成するパワーモジュール用基板の製造方法であって、
前記ろう材箔は、前記積層体において、表面に前記回路層の外周縁部が配置される外周部分と、この外周部分に囲まれた内側部分とを備え、前記外周部分は前記内側部分を形成する材質と比べて液相温度が高い材質で形成されていることを特徴とするパワーモジュール用基板の製造方法。 A ceramic plate is obtained by arranging a brazing material foil and a circuit layer in this order on the surface of the ceramic plate to form a laminated body, and then heating the laminated body while being pressed in the laminating direction to melt the brazing material foil. A power module substrate is formed by brazing a circuit layer on the surface of the power module, and forming a power module substrate on which the semiconductor chip is soldered to the surface of the circuit layer,
The brazing material foil includes an outer peripheral portion where an outer peripheral edge portion of the circuit layer is disposed on a surface of the laminated body, and an inner portion surrounded by the outer peripheral portion, and the outer peripheral portion forms the inner portion. A method for manufacturing a power module substrate, characterized in that the substrate is formed of a material having a liquidus temperature higher than that of the material. 請求項１記載のパワーモジュール用基板の製造方法であって、
前記外周部分は前記内側部分を形成する材質よりも液相温度が１０℃以上３０℃以下高い材質で形成されていることを特徴とするパワーモジュール用基板の製造方法。 A method for manufacturing a power module substrate according to claim 1,
The method of manufacturing a power module substrate, wherein the outer peripheral portion is formed of a material having a liquidus temperature higher by 10 ° C. or more and 30 ° C. or less than a material forming the inner portion. セラミックス板の表面に回路層がろう付けされてなり、この回路層の表面に半導体チップがはんだ接合されるパワーモジュール用基板であって、
請求項１または２に記載のパワーモジュール用基板の製造方法により形成されたことを特徴とするパワーモジュール用基板。 A power module substrate in which a circuit layer is brazed to the surface of a ceramic plate, and a semiconductor chip is soldered to the surface of the circuit layer,
A power module substrate formed by the method for manufacturing a power module substrate according to claim 1. セラミックス板の表面に回路層がろう付けされたパワーモジュール用基板と、回路層の表面にはんだ接合された半導体チップとを備えたパワーモジュールであって、
前記パワーモジュール用基板は、請求項１または２に記載のパワーモジュール用基板の製造方法により形成されたことを特徴とするパワーモジュール。

A power module including a power module substrate having a circuit layer brazed to the surface of a ceramic plate, and a semiconductor chip soldered to the surface of the circuit layer,
The power module substrate is formed by the method for manufacturing a power module substrate according to claim 1 or 2.

JP2006190266A 2006-07-11 2006-07-11 Power module substrate and method of manufacturing the same, and power module Pending JP2008021716A (en)

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JP2013038123A (en) * 2011-08-04 2013-02-21 Showa Denko Kk Method for manufacturing insulation circuit board
JP2015135850A (en) * 2014-01-16 2015-07-27 三菱マテリアル株式会社 Manufacturing method of circuit board for power module with heat sink
JP2020092154A (en) * 2018-12-05 2020-06-11 三菱電機株式会社 Semiconductor device

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JP2005101353A (en) * 2003-09-25 2005-04-14 Toshiba Corp Ceramics circuit substrate
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JP2005101353A (en) * 2003-09-25 2005-04-14 Toshiba Corp Ceramics circuit substrate
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JP2013038123A (en) * 2011-08-04 2013-02-21 Showa Denko Kk Method for manufacturing insulation circuit board
JP2015135850A (en) * 2014-01-16 2015-07-27 三菱マテリアル株式会社 Manufacturing method of circuit board for power module with heat sink
JP2020092154A (en) * 2018-12-05 2020-06-11 三菱電機株式会社 Semiconductor device
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