WO2016147252A1 - Appareil à semi-conducteur et son procédé de fabrication - Google Patents

Appareil à semi-conducteur et son procédé de fabrication Download PDF

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Publication number
WO2016147252A1
WO2016147252A1 PCT/JP2015/057477 JP2015057477W WO2016147252A1 WO 2016147252 A1 WO2016147252 A1 WO 2016147252A1 JP 2015057477 W JP2015057477 W JP 2015057477W WO 2016147252 A1 WO2016147252 A1 WO 2016147252A1
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WO
WIPO (PCT)
Prior art keywords
bonding material
semiconductor device
melting point
semiconductor chip
wiring board
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PCT/JP2015/057477
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English (en)
Japanese (ja)
Inventor
高彰 宮崎
靖 池田
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株式会社日立製作所
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Priority to PCT/JP2015/057477 priority Critical patent/WO2016147252A1/fr
Publication of WO2016147252A1 publication Critical patent/WO2016147252A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/52—Mounting semiconductor bodies in containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/40—Mountings or securing means for detachable cooling or heating arrangements ; fixed by friction, plugs or springs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

Definitions

  • the present invention relates to a semiconductor device and a manufacturing technique thereof, and more particularly to a power semiconductor device used for an inverter.
  • power semiconductor devices have a structure in which a semiconductor element (hereinafter also referred to as a semiconductor chip or simply a chip) and an insulating substrate, or an insulating substrate and a metal plate for heat dissipation are joined together by solder or the like. .
  • Solder which is a connecting member used for electrical connection of electrical and electronic equipment components, generally contained lead.
  • ELV Directive End-of Life Life Vehicles Directive
  • RoHS Restriction of the use of certain Hazardous Substances in electrical
  • lead (Pb) -containing solder has been used as a connecting member for semiconductor devices that require high heat resistance, particularly semiconductor devices used in the fields of automobiles, construction machinery, railways, and information equipment. There is a strong demand to use lead-free connecting members for reduction.
  • Si (silicon) semiconductor elements In recent years, development of wide gap semiconductors such as SiC and GaN capable of operating at high temperatures and reducing the size and weight of devices has been promoted.
  • the upper limit of the operating temperature of Si (silicon) semiconductor elements is 150 to 175 ° C., whereas SiC semiconductor elements can be used at 175 ° C. or higher.
  • Patent Document 1 Japanese Patent Application Laid-Open No. 2008-300792 discloses that “a base layer formed by curing a metal particle paste at a high temperature and a metal particle in a surface film formed by curing the metal particle paste at a low temperature include a low-temperature metal solder. A bonding layer composed of a high-temperature metal brazing material layer that is dispersed and absorbed in the material. By joining the back side of the semiconductor chip and the copper wiring pattern, it is possible to ensure strong heat resistance and power cycle performance. In addition, a technique capable of improving the reliability of a semiconductor device (see summary) is disclosed.
  • a semiconductor device in which a high-temperature metal brazing material is formed at the center of the joint and a low-temperature metal brazing material is formed outside the semiconductor chip and the insulating substrate. A part of the low-temperature metal brazing material is formed. Therefore, there is a concern that a crack in the substrate thickness direction (vertical direction) is formed in the power cycle test.
  • An object of the present invention is to provide a technique capable of improving the reliability of a semiconductor device.
  • a semiconductor device supports a semiconductor chip and is electrically connected to the semiconductor chip, a metal plate supporting the wiring board, and disposed between the wiring board and the metal plate. And a bonding material for bonding the wiring board and the metal plate. Furthermore, the bonding material is disposed around the first bonding material in a plan view and a first bonding material formed directly below the semiconductor chip and having a plane size equal to or larger than the plane size of the semiconductor chip. The first bonding material has a melting point higher than that of the second bonding material.
  • the method for manufacturing a semiconductor device includes: (a) a step of mounting a semiconductor chip on a wiring board; (b) mounting the wiring board on which the semiconductor chip is mounted on a metal plate via a bonding material. And in the step (b), the bonding material is heated and melted to bond the wiring board and the metal plate. Further, the bonding material is provided immediately below the semiconductor chip, around a first bonding material formed in a plane size equal to or larger than the plane size of the semiconductor chip, and around the first bonding material in plan view. The first bonding material has a melting point higher than that of the second bonding material.
  • FIG. 2 is a cross-sectional view showing an example of main processes in assembling the semiconductor device shown in FIG. 1.
  • FIG. 2 is a cross-sectional view showing an example of main processes in assembling the semiconductor device shown in FIG. 1.
  • FIG. shows the main processes in the assembly of the 1st modification of the semiconductor device shown in FIG.
  • FIG. 2nd modification of this invention shows the structure of the semiconductor device of the 2nd modification of this invention.
  • FIG. 8 is a plan view illustrating an example of an internal structure of the semiconductor device illustrated in FIG. 7.
  • FIG. 8 is a plan view illustrating an example of an internal structure of the semiconductor device illustrated in FIG. 7.
  • FIG. 2 is a partial side view showing an example of a railway vehicle on which the semiconductor device shown in FIG. 1 is mounted. It is a top view which shows an example of the internal structure of the inverter installed in the rail vehicle shown in FIG. It is a perspective view which shows an example of the motor vehicle carrying the semiconductor device shown in FIG. It is sectional drawing which shows the structure of the semiconductor device of a comparative example.
  • the constituent elements are not necessarily indispensable unless otherwise specified and clearly considered essential in principle. Needless to say.
  • FIG. 1 is a cross-sectional view showing an example of the structure of a semiconductor device (power module) according to an embodiment of the present invention.
  • the semiconductor device of the present embodiment is, for example, a semiconductor module (power module) mounted on a railway vehicle, an automobile body, or the like. Therefore, the semiconductor device includes a plurality of power semiconductor chips (semiconductor elements) 1 and requires heat dissipation measures.
  • the semiconductor chip 1 is, for example, an IGBT (Insulated Gate Bipolar Transistor) or the like, but is not limited thereto.
  • the configuration of the power module 20 shown in FIG. 1 will be described.
  • the power module 20 electrically connects a ceramic substrate (wiring substrate) 3 that supports the semiconductor chip 1, an electrode 1 c on the upper surface (main surface) 1 a of the semiconductor chip 1, and an electrode 3 cb (3 c) on the upper surface 3 a of the ceramic substrate 3. And a terminal (lead) 7 that is electrically connected to the electrode 3cb of the ceramic substrate 3 and drawn to the outside.
  • the ceramic substrate 3 on which the plurality of semiconductor chips 1 and the plurality of terminals 7 are mounted is mounted on a base plate (metal plate) 4 via solder (joining material, solder alloy) 5. That is, the base plate 4 supports the ceramic substrate 3 via the solder 5.
  • the ceramic substrate 3 has a plurality of electrodes 3ca (3c) and electrodes 3cb (3c) formed on the upper surface 3a, while an electrode 3cc (3c) is also formed on the lower surface 3b.
  • These electrodes 3ca, 3cb, 3cc are made of, for example, copper (Cu) or aluminum (Al). Alternatively, copper or aluminum may be subjected to desired metallization such as nickel (Ni) or gold (Au).
  • the electrode 3 cc formed on the lower surface 3 b of the ceramic substrate 3 is electrically connected to the base plate 4 by the solder 5.
  • the semiconductor chip 1 is connected to the ceramic substrate (wiring substrate, insulating substrate, connected member) 3 via the solder 2, and further, the semiconductor chip 1 A base plate (metal plate) 4 for heat release that plays a role of releasing heat during the operation of the ceramic substrate 3 and the ceramic substrate 3 are connected via a solder 5. That is, the ceramic substrate 3 and the base plate 4 are joined by the solder 5 disposed between the ceramic substrate 3 and the base plate 4.
  • the specific structure of the power module 20 will be described.
  • the semiconductor chip 1, the ceramic substrate 3 that is a chip support member connected to the semiconductor chip 1 via the solder (joining material) 5, and the semiconductor chip 1 are electrically connected.
  • the base plate 4 that is also a heat radiating plate is provided with a case 8 that covers the plurality of semiconductor chips 1, the plurality of wires 6, and the ceramic substrate 3, and a sealing resin (not shown) is contained in the case 8. Filled. That is, the plurality of semiconductor chips 1, the plurality of wires 6, and the ceramic substrate 3 are sealed with the sealing resin.
  • a gel-like resin material is preferably used as the resin.
  • the semiconductor chip 1 is joined to the electrode 3ca on the upper surface 3a of the ceramic substrate 3 via the solder 2. That is, the lower surface 1 b of the semiconductor chip 1 and the upper surface 3 a of the ceramic substrate 3 are opposed to each other, and the back electrode of the semiconductor chip 1 and the electrode 3 ca of the ceramic substrate 3 are electrically connected by the solder 2.
  • a gate electrode 1 c is formed on the upper surface 1 a of the semiconductor chip 1, and is electrically connected to the electrode 3 cb of the ceramic substrate 3 via a wire 6.
  • the base plate 4 is a metal plate for heat dissipation.
  • each of the plurality of wires 6 is, for example, an aluminum or copper wire or a ribbon.
  • an electrode 3cc as a wiring portion is formed on the lower surface 3b of the ceramic substrate 3, and a base plate for heat dissipation (metal) is connected to the electrode 3cc via a solder 5 as a bonding material. Plate, heat radiating member) 4 are joined.
  • This solder 5 is the same as a high melting point bonding material (first bonding material) 5a formed directly below the semiconductor chip 1 and having a planar size that is the same as the planar size of the semiconductor chip 1 as viewed from above. It consists of a low melting point bonding material (second bonding material) 5b disposed around the high melting point bonding material 5a in plan view. That is, the high melting point bonding material (first bonding material) 5a has a planar size that is the same as or larger than the planar size of the semiconductor chip 1 immediately below the semiconductor chip 1 corresponding to the position of the semiconductor chip 1. It is formed with.
  • the size of the high melting point bonding material (first bonding material) 5a in plan view may be larger than the size of the semiconductor chip 1 in plan view.
  • the melting point of the high melting point bonding material 5a is higher than the melting point of the low melting point bonding material 5b.
  • the solder 5 as a bonding material includes a high melting point bonding material 5a disposed immediately below the semiconductor chip 1 where the temperature rises, and a periphery of the high melting point bonding material 5a (around the high melting point bonding material 5a in plan view or And a low melting point bonding material 5b disposed on the outer side.
  • the high melting point bonding material 5a is disposed directly below the semiconductor chip 1 with the ceramic substrate 3 interposed therebetween.
  • the thickness of the solder 5 may be thicker than the thickness of the solder 2. Further, the solder 5 is larger than the solder 2 in the area in plan view.
  • the high melting point bonding material 5a is a bonding material having high heat resistance, and preferably a sintered material made of metal particles. Further, a bonding material such as Zn—Al, Au—Ge, or Au—Si may be used.
  • the low melting point bonding material 5b is preferably an Sn-based solder alloy, for example, an Sn-based solder alloy such as Sn—Cu, Sn—Cu—Sn, Sn—Sb, Sn—Ag—Cu.
  • high heat-resistant bonding (bonding with the high melting point bonding material 5a) having high reliability is applied only to a portion immediately below the semiconductor chip 1 that generates large heat, and the high melting point bonding material 5a.
  • a sintered material of metal particles as the high melting point bonding material 5a and to use an Sn-based solder alloy as the low melting point bonding material 5b. This is because there is a concern that sintered metal joints have fine voids in the joining layer even after joining, and have a large surface area compared to the bulk material and oxidize in a high temperature environment to reduce strength.
  • the joining portion (high melting point joining material 5a) of sintered metal is sealed by low melting point metal joining such as Sn-based solder alloy, the joining is performed. Even when the temperature of the portion becomes high, the sintered metal joint can be protected from oxidation.
  • FIG. 13 is a cross-sectional view showing the structure of a semiconductor device of a comparative example that the present inventors have conducted a comparative study.
  • the breakdown progresses only at the junction between the semiconductor chip 1 and the insulating substrate (ceramic substrate 3) close to the heat generating portion.
  • the operating temperature of the chip also rises at the junction of the base plate 4), and the heat generation of the chip causes temperature nonuniformity in the junction between the insulating substrate and the heat dissipation base.
  • the breakage progresses from the joint, particularly when the Sn-based solder 40 is used.
  • the joint portion between the insulating substrate and the heat dissipation base has a larger area than the joint portion between the semiconductor chip 1 and the insulating substrate, and the crack 42 from the end portion develops due to the increased strain at the end portion of the joint portion. Reliability is also required.
  • the chip generates heat when a large current is applied as compared with other electronic components. Therefore, the junction between the insulating substrate and the heat dissipation base is different from other electronic devices. Destruction is a problem.
  • the Sn-based solder 40 when used, the generation of voids at the Sn grain boundaries and the progress of breakage in the vertical direction (substrate thickness direction, vertical direction) are problematic.
  • the crack 41 in the vertical direction is generated because tensile stress acts in the joint due to a temperature change of the joint.
  • the chip (semiconductor chip 1) generates heat during its operation. At that time, it became clear that the temperature rose to almost the same level as that of the chip at the junction between the insulating substrate and the heat dissipation base, particularly in the portion directly under the chip. This is presumably because Al, Cu, AlN, Si 3 N 4 or the like having good thermal conductivity is used for the insulating substrate (ceramic substrate 3). Since the portion immediately below the chip is at a high temperature, destruction of the joint progresses due to ON / OFF of energization. When the breakage progresses in this portion which is a heat radiation path, the heat radiation performance is lowered, the temperature of the chip rises, and finally the power module 50 is broken.
  • Possible joining materials with high power cycle tolerance include sintered metal joining with high melting point after joining, joining with Zn-Al alloy, joining with Au-based solder, etc. Fine metal particles of several hundred ⁇ m are made into a paste with a solvent such as alcohol, and it is necessary to remove the solvent by heating or pressurize when joining. However, in the case of bonding with a large area such as an insulating substrate and a heat dissipation base, the area is large and it is difficult to remove the solvent to the center.
  • the power module 20 of the present embodiment in a large-area joint such as the ceramic substrate (insulating substrate) 3 and the base plate (heat radiating metal plate) 4, high heat-resistant bonding is performed only at a portion directly below the chip (necessary portion).
  • the portion (high melting point bonding material 5a) is the other portion (periphery) is a bonding portion (low melting point bonding material 5b) made of a low melting point metal such as Sn-based solder.
  • the bonded portion (high melting point bonding material 5a) made of sintered metal is sealed by a low melting point metal bonding (low melting point bonding material 5b) such as an Sn-based solder alloy. Even if the temperature becomes high, the sintered metal joint can be protected from oxidation.
  • the reliability of the power module 20 can be improved.
  • FIG. 2 is a cross-sectional view showing an example of main processes in the assembly of the semiconductor device shown in FIG. 1
  • FIG. 3 is a cross-sectional view showing an example of main processes in the assembly of the semiconductor device shown in FIG.
  • a sintered metal (sintered material by metal particles) and other parts (high melting point bonding material 5 a of high melting point bonding material 5 a) are placed on a high heat resistant bonding portion (high melting point bonding material 5 a) immediately below the chip.
  • high melting point bonding material 5 a high melting point bonding material 5 a
  • the semiconductor chip 1 is mounted on the ceramic substrate (wiring substrate, insulating substrate) 3 via the solder 2.
  • the solder 2 has a melting point of 400 ° C., for example. Accordingly, the semiconductor chip 1 is joined to the ceramic substrate 3 via the solder 2 by heating and melting the solder 2 to 400 ° C. or higher.
  • a sintered metal paste which is a high melting point bonding material 5a is applied to the back side (lower surface 3b) side of the ceramic substrate 3. Further, Sn-based solder, which is the low melting point bonding material 5b, is supplied as a foil or a paste to portions other than the high melting point bonding material 5a (around the high melting point bonding material 5a and outside the high melting point bonding material 5a).
  • the size is equal to or larger than that of the semiconductor chip 1 in a plan view immediately below the semiconductor chip 1.
  • the high melting point bonding material 5a is applied, and further, the low melting point bonding material 5b is applied around the high melting point bonding material 5a in plan view.
  • the high melting point bonding material 5a has a higher melting point than the low melting point bonding material 5b.
  • the high melting point bonding material 5a has a melting point of about 320 ° C.
  • the low melting point bonding material 5b has a melting point of less than 320 ° C.
  • the ceramic substrate 3 is disposed on the base plate 4 via the solder 5, and after the placement, the solder (joining material) 5 composed of the high melting point bonding material 5a and the low melting point bonding material 5b. Are heated and melted to join the ceramic substrate 3 and the base plate (metal plate for heat dissipation) 4 together.
  • solder 5 is melted and the ceramic substrate 3 and the base plate 4 are joined. Thereby, the solder joint between the ceramic substrate 3 and the base plate 4 in the module structure shown in FIG. 3 (FIG. 1) is completed.
  • the size of the high melting point bonding material (first bonding material) 5a immediately below the chip may be larger than the size of the semiconductor chip 1 in plan view.
  • the structure is such that the joint portion (high melting point bonding material 5a) made of sintered metal is sealed by low melting point metal bonding such as Sn-based solder alloy. Therefore, the sintered metal joint can be protected from oxidation even if the joint becomes high temperature.
  • bonding can be performed even if the area of the bonded portion of the sintered metal bonding is 400 mm 2 or more.
  • the high melting point bonding material 5 a and the low melting point bonding material 5 b are not applied to the lower surface 3 b side of the ceramic substrate 3, but the high melting point bonding material 5 a and the low melting point bonding material 5 b are applied to the base plate 4.
  • the solder 5 may be heated and melted after the bonding material 5a and the low-melting-point bonding material 5b are applied and the ceramic substrate 3 is disposed thereon.
  • a semiconductor chip 1 is mounted on a ceramic substrate (wiring substrate, insulating substrate) 3 via a solder 2.
  • the mounting of the semiconductor chip 1 on the ceramic substrate 3 via the solder 2 is the same as the above method.
  • a Zn-based sintered metal paste which is a high melting point bonding material 5a
  • Sn-based solder which is the low melting point bonding material 5b
  • Sn-based solder is supplied as a foil or a paste to portions other than the high melting point bonding material 5a (around the high melting point bonding material 5a and outside the high melting point bonding material 5a).
  • the size is equal to or larger than that of the semiconductor chip 1 in a plan view immediately below the semiconductor chip 1.
  • the high melting point bonding material 5a is applied, and further, the low melting point bonding material 5b is applied around the high melting point bonding material 5a in plan view.
  • the high melting point bonding material 5a has a higher melting point than the low melting point bonding material 5b.
  • the high melting point bonding material 5a has a melting point of about 320 ° C.
  • the low melting point bonding material 5b has a melting point of less than 320 ° C.
  • the ceramic substrate 3 is disposed on the base plate 4 via the solder 5, and after the placement, the solder (joining material) 5 composed of the high melting point bonding material 5a and the low melting point bonding material 5b. Are heated and melted to join the ceramic substrate 3 and the base plate (metal plate for heat dissipation) 4 together.
  • solder 5 is melted and the ceramic substrate 3 and the base plate 4 are joined. Thereby, the solder joint between the ceramic substrate 3 and the base plate 4 in the module structure shown in FIG. 3 (FIG. 1) is completed.
  • the size (planar size) of the high melting point bonding material (first bonding material) 5a immediately below the chip in plan view is the size of the semiconductor chip 1 in plan view ( (Plane size) or more.
  • the Zn-based solder alloy when the Zn-based solder alloy is melted, there is a concern that the vapor pressure of Zn is low and Zn evaporates and adheres to the surface of other members, thereby contaminating the other members.
  • the melting point is around 220 ° C., and the molten Sn-based solder alloy surrounds the Zn-based solder alloy. Therefore, it is possible to prevent Zn from adhering to other members.
  • the joint portion by the solder 5 has a large joint area, an Sn-based solder alloy that is softer (easily deformed) than the high heat-resistant joint by a Zn-based solder alloy or the like is applied to the end portion of the joint portion where a large strain occurs. By applying, it is possible to obtain resistance to crack propagation from the end of the joint.
  • ⁇ First Modification> 4, 5, and 6 are cross-sectional views showing main processes in assembling the first modification of the semiconductor device shown in FIG. 1.
  • a sintered material (sintered metal) made of metal particles is applied as the high heat resistant joint (high melting point bonding material 5a), and an Sn-based solder alloy is applied to the other part (low melting point bonding material 5b).
  • high melting point bonding material 5a high melting point bonding material
  • Sn-based solder alloy low melting point bonding material 5b
  • the semiconductor chip 1 is mounted on the ceramic substrate (wiring substrate, insulating substrate) 3 via the solder 2.
  • the mounting of the semiconductor chip 1 on the ceramic substrate 3 via the solder 2 is the same as the above method.
  • a porous metal joint (porous joint material) 9 shown in FIG. 5 is formed by applying a sintered metal paste (high melting point joint material 5a) on the base plate 4 and heating to 300 ° C. or higher. . Thereafter, a low melting point bonding material 5b (for example, a low melting point metal foil, a second bonding material) made of an Sn-based solder alloy is supplied between the ceramic substrate 3 and the base plate 4 so as to cover the porous bonding portion 9. And heating at 300 ° C. or higher for 15 minutes or longer.
  • a sintered metal paste high melting point joint material 5a
  • a low melting point bonding material 5b for example, a low melting point metal foil, a second bonding material
  • the structure of the molten Sn-based solder alloy (low melting point bonding material 5b) and the porous bonding portion (high melting point bonding material 5a) 9 reacts, and Sn—Cu, Sn— as shown in FIG.
  • An intermetallic compound (layer) 10 such as Ag or Ni—Sn is formed. Thereby, the high melting point is achieved.
  • An Sn-based solder alloy (low melting point bonding material 5b) is disposed around the intermetallic compound 10.
  • the intermetallic compound 10 generally has a high melting point, but has a drawback of being hard and brittle. Therefore, an Sn-based solder alloy (low melting point bonding material 5b) is disposed at the end of the joint where large distortion occurs. . Thereby, it becomes possible to satisfy the power cycle reliability required as a joint portion between the ceramic substrate 3 and the base plate 4 for heat dissipation, and the resistance to crack propagation from the end portion of the joint portion.
  • Sn-based solder alloy low melting point bonding material 5b
  • the high melting point joining material (intermetallic compound 10, first joining material) 5a immediately below the chip in plan view.
  • the size (planar size) is not less than the size (planar size) of the semiconductor chip 1 in plan view.
  • the sintered metal paste (the high melting point bonding material 5a, the first bonding material) is not applied on the base plate 4, but is applied to the lower surface 3b side of the ceramic substrate 3. May be.
  • the power module 20 and the assembly thereof according to the present embodiment can be applied to the semiconductor chip 1 made of any material such as Si, SiC, GaAs, CdTe, and GaN.
  • the base plate (metal plate) 4 for heat dissipation may be made of any member such as Cu, Al, Cu—Mo, Al—SiC, Mg—SiC, etc. Can achieve highly reliable bonding.
  • FIG. 7 is a cross-sectional view showing the structure of a semiconductor device according to a second modification of the present invention
  • FIGS. 8 and 9 are plan views showing examples of the internal structure of the semiconductor device shown in FIG.
  • FIG. 1 a plan view at a joint portion between a ceramic substrate (insulating substrate) 3 and a heat radiating base plate (metal plate) 4
  • a high heat-resistant bonding part (first bonding material, high melting point bonding material 5a) is disposed near the center.
  • the installation location of the high heat-resistant bonding part may be changed depending on the position of the semiconductor chip 1 as shown in FIGS.
  • the planar size of the semiconductor chip 1 is directly below each semiconductor chip 1 as shown in FIGS.
  • a high melting point bonding material (first bonding material, high heat resistant bonding portion) 5a having the same plane size (or a plane size larger than the plane size of the semiconductor chip 1) may be disposed.
  • a low melting point bonding material (for example, Sn-based solder alloy) 5b is disposed around each of the four high melting point bonding materials 5a.
  • each of the four high melting point bonding materials 5a is surrounded by the low melting point bonding material 5b.
  • ⁇ Application example> 10 is a partial side view showing an example of a railway vehicle on which the semiconductor device shown in FIG. 1 is mounted
  • FIG. 11 is a plan view showing an example of an internal structure of an inverter installed in the railway vehicle shown in FIG.
  • a railway vehicle 21 shown in FIG. 10 is mounted with the power module 20 shown in FIG. 1, for example, and includes a vehicle main body 26, a power module 20, a mounting member that supports the power module 20, and a current collector.
  • a pantograph 22 and an inverter 23 are provided.
  • the power module 20 is mounted on an inverter 23 installed at the lower part of the vehicle body 26.
  • a plurality of power modules 20 are mounted on a printed circuit board (mounting member) 25 inside the inverter 23, and a cooling device 24 for cooling these power modules 20 is mounted.
  • the cooling device 24 is attached so that the plurality of power modules 20 can be cooled to cool the inside of the inverter 23.
  • FIG. 12 is a perspective view showing an example of an automobile on which the semiconductor device shown in FIG. 1 is mounted.
  • An automobile 27 shown in FIG. 12 is mounted with the power module 20 shown in FIG. 1, for example, and includes a vehicle body 28, a tire 29, the power module 20, and a mounting unit that is a mounting member that supports the power module 20. 30.
  • the power module 20 is mounted on an inverter included in the mounting unit 30.
  • the mounting unit 30 is, for example, an engine control unit, and in this case, the mounting unit 30 is disposed in the vicinity of the engine. ing. In this case, the mounting unit 30 is used in a high temperature environment, and the power module 20 is also in a high temperature state.
  • the mounting unit 30 is in a high temperature environment by providing an inverter in which a plurality of power modules 20 using the module joining structure shown in FIG.
  • the reliability of the automobile 27 can be improved. That is, in the automobile 27 as well, it is possible to realize the power module 20 that can withstand operation stability under a high temperature environment and a high current load, and an inverter system using the same.

Abstract

La présente invention concerne un module de puissance 20 qui comprend un substrat en céramique 3 qui porte une puce à semi-conducteur 1 et qui est connecté électriquement à la puce à semi-conducteur 1, une plaque de base 4 de rayonnement thermique qui porte le substrat en céramique 3, et une brasure 5 qui est disposée entre le substrat en céramique et la plaque de base 4 et qui lie le substrat en céramique 3 et la plaque de base 4. Directement au-dessous de la puce à semi-conducteur 1, la brasure 5 comprend un matériau de liaison à point de fusion élevé 5a formé dans une taille plane qui est la même que la taille plane de la puce à semi-conducteur 1 ou qui est plus grande que la taille plane de la puce à semi-conducteur 1 et un matériau de liaison à point de fusion bas 5b qui est disposé autour du matériau de liaison à point de fusion élevé 5a dans une vue en plan, le matériau de liaison à point de fusion élevé 5a présentant un point de fusion supérieur à celle du matériau de liaison à point de fusion bas 5b.
PCT/JP2015/057477 2015-03-13 2015-03-13 Appareil à semi-conducteur et son procédé de fabrication WO2016147252A1 (fr)

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PCT/JP2015/057477 WO2016147252A1 (fr) 2015-03-13 2015-03-13 Appareil à semi-conducteur et son procédé de fabrication

Applications Claiming Priority (1)

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PCT/JP2015/057477 WO2016147252A1 (fr) 2015-03-13 2015-03-13 Appareil à semi-conducteur et son procédé de fabrication

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WO2016147252A1 true WO2016147252A1 (fr) 2016-09-22

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019067976A (ja) * 2017-10-03 2019-04-25 トヨタ自動車株式会社 半導体装置
WO2019097790A1 (fr) * 2017-11-15 2019-05-23 パナソニックＩｐマネジメント株式会社 Module à semi-conducteur et son procédé de production

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Publication number Priority date Publication date Assignee Title
JPH10242356A (ja) * 1997-02-27 1998-09-11 Kyocera Corp 半導体素子収納用パッケージの製造方法
JP2007243118A (ja) * 2006-03-13 2007-09-20 Fuji Electric Holdings Co Ltd 半導体装置
JP2009088215A (ja) * 2007-09-28 2009-04-23 Dowa Metaltech Kk 半導体装置
JP2015005571A (ja) * 2013-06-19 2015-01-08 株式会社デンソー 半導体装置

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Publication number Priority date Publication date Assignee Title
JPH10242356A (ja) * 1997-02-27 1998-09-11 Kyocera Corp 半導体素子収納用パッケージの製造方法
JP2007243118A (ja) * 2006-03-13 2007-09-20 Fuji Electric Holdings Co Ltd 半導体装置
JP2009088215A (ja) * 2007-09-28 2009-04-23 Dowa Metaltech Kk 半導体装置
JP2015005571A (ja) * 2013-06-19 2015-01-08 株式会社デンソー 半導体装置

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019067976A (ja) * 2017-10-03 2019-04-25 トヨタ自動車株式会社 半導体装置
WO2019097790A1 (fr) * 2017-11-15 2019-05-23 パナソニックＩｐマネジメント株式会社 Module à semi-conducteur et son procédé de production
JPWO2019097790A1 (ja) * 2017-11-15 2020-10-08 パナソニックセミコンダクターソリューションズ株式会社 半導体モジュールおよびその製造方法
US10847702B2 (en) 2017-11-15 2020-11-24 Panasonic Semiconductor Solutions Co., Ltd. Semiconductor module
JP7201439B2 (ja) 2017-11-15 2023-01-10 ヌヴォトンテクノロジージャパン株式会社 半導体モジュールおよびその製造方法

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