JP2019079958A - Power module - Google Patents

Power module Download PDF

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Publication number
JP2019079958A
JP2019079958A JP2017206343A JP2017206343A JP2019079958A JP 2019079958 A JP2019079958 A JP 2019079958A JP 2017206343 A JP2017206343 A JP 2017206343A JP 2017206343 A JP2017206343 A JP 2017206343A JP 2019079958 A JP2019079958 A JP 2019079958A
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Prior art keywords
layer
transistor
power module
electrode
bonding
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JP2017206343A
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Japanese (ja)
Inventor
宏文 伊藤
Hirofumi Ito
宏文 伊藤
臼井 正則
Masanori Usui
正則 臼井
佐藤 敏一
Toshiichi Sato
敏一 佐藤
智幸 庄司
Tomoyuki Shoji
智幸 庄司
林太郎 淺井
Rintaro Asai
林太郎 淺井
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Toyota Motor Corp
Toyota Central R&D Labs Inc
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Toyota Motor Corp
Toyota Central R&D Labs Inc
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Priority to JP2017206343A priority Critical patent/JP2019079958A/en
Publication of JP2019079958A publication Critical patent/JP2019079958A/en
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612Auxiliary members for layer connectors, e.g. spacers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H01L2224/331Disposition
    • H01L2224/3318Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/33181On opposite sides of the body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

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  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

To provide a power module capable of achieving improvement in reliability.SOLUTION: A power module of the present invention comprises: a transistor (1) as a heat generation source; a first spreader (31) joined to a first electrode (collector electrode) of a transistor via a first joining layer (41); a spacer (2) for ensuring a space for a bonding wire which is joined to a second electrode (emitter electrode) of the transistor via a second joining layer (42) and joined to a third electrode (gate electrode) of the transistor; and a second spreader (32) joined to another surface side of the spacer via a third joining layer (43). In this case, the spacer is composed of a conductive material having a thermal expansion coefficient difference within a range of 0.5-7 ppm/K with a semiconductor material which composes the transistor. According to the present invention, by utilizing the spacer required in wire bonding, reliability of a double-sided cooling structure power module can be further improved.SELECTED DRAWING: Figure 1

Description

本発明は、信頼性の向上を図れるパワーモジュールに関する。   The present invention relates to a power module capable of improving reliability.

モータ駆動用インバータ等には、IGBT(Insulated Gate Bipolar Transistor)等のパワーデバイス(半導体素子)を実装したパワーモジュールが用いられる。   As a motor driving inverter or the like, a power module mounted with a power device (semiconductor element) such as an IGBT (Insulated Gate Bipolar Transistor) is used.

パワーモジュールの信頼性を確保するため、デバイスの作動中に生じる発熱を効率的に放熱させることが重要となる。このような事情の下、パワーデバイスを両面側から冷却する両面冷却型構造のパワーモジュールが提案されており、関連する記載が下記の特許文献にある。   In order to ensure the reliability of the power module, it is important to efficiently dissipate the heat generated during operation of the device. Under such circumstances, a double-sided cooling type power module for cooling a power device from both sides has been proposed, and the related description is given in the following patent documents.

特開2008−103623号公報JP 2008-103623 A

特許文献1では、先ず、トランジスタ(IGBT)のコレクタ電極(第1電極)を第1リードフレーム(スプレッダ)の一面に接合すると共に第1リードフレームの他面に第1セラミックチューブ(冷却器)を接合している。次に、トランジスタ(IGBT)のエミッタ電極(第2電極)を銅ブロック(スペーサ)の一面に接合すると共に、銅ブロックの他面を第2リードフレーム(スプレッダ)の一面に接合し、第2リードフレームの他面に第2セラミックチューブを接合している。ちなみに、銅ブロックは、トランジスタのゲート電極(第3電極)に接合されるボンディングワイヤーと第2リードフレーム等との干渉を回避するためのスペースを確保するために設けられている。なお、各部材間の接合はAg焼結体によりなされている。   In Patent Document 1, first, a collector electrode (first electrode) of a transistor (IGBT) is joined to one surface of a first lead frame (spreader) and a first ceramic tube (cooler) is attached to the other surface of the first lead frame. It is joined. Next, the emitter electrode (second electrode) of the transistor (IGBT) is joined to one surface of the copper block (spacer), and the other surface of the copper block is joined to one surface of the second lead frame (spreader). A second ceramic tube is bonded to the other side of the frame. Incidentally, the copper block is provided to secure a space for avoiding the interference between the bonding wire bonded to the gate electrode (third electrode) of the transistor and the second lead frame or the like. In addition, joining between each member is made of Ag sintered body.

特許文献1の場合、熱膨張係数(CTE:coefficient of thermal expansion)の小さいトランジスタが、CTEの大きい銅製のブロックやリードフレームに、低靱性なAg焼結体を介して接合されている。このため、接合部材間のCTE不整合に起因して、トランジスタや接合部に大きな熱応力が集中し得る。   In the case of Patent Document 1, a transistor having a small coefficient of thermal expansion (CTE) is joined to a copper block or lead frame having a large CTE via a low toughness Ag sintered body. For this reason, large thermal stress may be concentrated on the transistor and the junction due to CTE mismatch between the junction members.

このため、そのようなパワーモジュールを模した積層構造体に温度サイクル試験(低温状態と高温状態を一定間隔で繰り返す試験)を施すと、図2に示すように、デバイス(SiC)、ブロック(Cu)、接合層(IMC:intermetallic compound/金属間化合物)等にクラックを生じ得る。従って、特許文献1のような半導体装置(パワーモジュール)では、熱応力に対する耐久性(耐熱疲労性)が十分とはいえない。   Therefore, when a temperature cycle test (a test in which a low temperature state and a high temperature state are repeated at a constant interval) is applied to a laminated structure imitating such a power module, as shown in FIG. ), Bonding layers (IMC: intermetallic compound / intermetallic compound), etc. may be cracked. Therefore, in the semiconductor device (power module) as disclosed in Patent Document 1, the durability against heat stress (heat fatigue resistance) is not sufficient.

特に、SiC、GaN、Ga等からなる次世代のデバイスを用いる場合、従来よりも高温域(例えば150℃以上)で使用されることが予想される。また、パワーモジュールは、搭載自由度の向上や軽量化を図るため、さらなる小型化が進められており、デバイスの動作温度は一層上昇傾向にある。従って、高温下で使用されても高い信頼性を確保できるパワーモジュールが求められている。 In particular, when using a next-generation device made of SiC, GaN, Ga 2 O 3 or the like, it is expected to be used in a higher temperature range (for example, 150 ° C. or more) than conventional. In addition, the power modules are being further miniaturized to improve the degree of freedom in mounting and to reduce the weight, and the operating temperature of the devices tends to further increase. Therefore, there is a need for a power module that can ensure high reliability even when used at high temperatures.

本発明はこのような事情に鑑みて為されたものであり、信頼性の向上を図れるパワーモジュールを提供することを目的とする。   The present invention has been made in view of such circumstances, and it is an object of the present invention to provide a power module which can improve the reliability.

本発明者はこの課題を解決すべく鋭意研究した結果、ワイヤーボンディングの際に必要となるスペーサを利用して、両面冷却型構造のパワーモジュールの信頼性を高めることを着想した。これを具現化すると共に、それを発展させることにより、以降に述べる本発明を完成するに至った。   As a result of earnest studies to solve this problem, the inventor of the present invention conceived to increase the reliability of a double-sided cooling type power module by using a spacer required for wire bonding. While realizing this and developing it, the present invention described below has been completed.

《パワーモジュール》
(1)本発明は、発熱源であるトランジスタと、該トランジスタの第1電極に第1接合層を介して接合される第1スプレッダと、該トランジスタの第2電極に第2接合層を介して接合されると共に該トランジスタの第3電極に接合されるボンディングワイヤーのスペースを確保するスペーサと、該スペーサの他面側に第3接合層を介して接合される第2スプレッダとを備え、前記スペーサは、前記トランジスタを構成する半導体材料との熱膨張係数差が0.5〜7ppm/Kである導電材料からなるパワーモジュールである。
Power Module
(1) In the present invention, a transistor which is a heat source, a first spreader joined to a first electrode of the transistor through a first bonding layer, and a second bonding layer to a second electrode of the transistor The spacer includes: a spacer which is joined and which secures a space of a bonding wire joined to the third electrode of the transistor; and a second spreader joined to the other surface side of the spacer via the third joining layer, Is a power module made of a conductive material having a thermal expansion coefficient difference of 0.5 to 7 ppm / K with the semiconductor material constituting the transistor.

(2)本発明に係るスペーサを構成する導電材料は、トランジスタを構成する半導体材料と熱膨張係数(CTE)が近く、それらのCTE差は小さい。このため、スペーサとトランジスタの間で生じるCTE不整合に起因した熱応力も小さい。この結果、本発明のパワーモジュールでは、スペーサとトランジスタの接合部(第2接合層)やトランジスタに、熱応力に起因したクラック等が発生することが抑止される。 (2) The conductive material constituting the spacer according to the present invention has a thermal expansion coefficient (CTE) close to that of the semiconductor material constituting the transistor, and their CTE difference is small. Therefore, the thermal stress caused by the CTE mismatch generated between the spacer and the transistor is also small. As a result, in the power module of the present invention, generation of cracks and the like due to thermal stress is suppressed in the junction between the spacer and the transistor (second junction layer) and the transistor.

次に、スペーサとトランジスタの間のCTE差が小さくなる反面、スペーサと第2スプレッダの間のCTE差は従来よりも大きくなる。このため、スペーサと第2スプレッダの間でCTE不整合に起因した熱応力が生じ得る。しかし、この部分は、スペーサとトランジスタの間よりも低温側である。このため、スペーサと第2スプレッダの間で生じる熱応力は、相対的に小さくなり、クラックの発生も抑制される。   Next, while the CTE difference between the spacer and the transistor is reduced, the CTE difference between the spacer and the second spreader is larger than in the prior art. For this reason, thermal stress due to CTE mismatch may occur between the spacer and the second spreader. However, this portion is at a lower temperature than between the spacer and the transistor. For this reason, the thermal stress generated between the spacer and the second spreader becomes relatively small, and the occurrence of cracks is also suppressed.

仮にクラックが発生するとしても、スペーサや第3接合層で優先的にクラックが生じ、トランジスタや第2接合層におけるクラックの発生は抑制される。換言すると、本発明のパワーモジュールでは、クラックの起点が、トランジスタがある第2接合層の近傍から、第2スプレッダがある第3接合層の近傍へ移動(シフト)している。   Even if a crack is generated, the crack is preferentially generated in the spacer and the third bonding layer, and the generation of the crack in the transistor and the second bonding layer is suppressed. In other words, in the power module of the present invention, the origin of the crack is shifted (shifted) from the vicinity of the second junction layer where the transistor is located to the vicinity of the third junction layer where the second spreader is located.

これらのことが相乗的に作用して、トランジスタの破損防止やパワーモジュールの機能維持が図られる。こうして本発明のパワーモジュールは、長寿命化し、高い信頼性を発揮する。   These actions act synergistically to prevent transistor damage and maintain the function of the power module. Thus, the power module of the present invention has a long life and exhibits high reliability.

《その他》
特に断らない限り本明細書でいう「x〜y」は下限値xおよび上限値yを含む。本明細書に記載した種々の数値または数値範囲に含まれる任意の数値を新たな下限値または上限値として「a〜b」のような範囲を新設し得る。
<< Others >>
Unless otherwise stated, “x to y” as used herein includes the lower limit x and the upper limit y. Ranges such as “a to b” may be newly established as new lower limit values or upper limit values for arbitrary numerical values included in various numerical values or numerical ranges described in the present specification.

実施例であるパワーモジュールの要部を示す模式断面図である。It is a schematic cross section which shows the principal part of the power module which is an Example. 従来のパワーモジュールを模した積層構造体に生じたクラックの顕微鏡写真である。It is a microscope picture of the crack which arose in the laminated structure which imitated the conventional power module.

本発明の構成要素に、本明細書中から任意に選択した一以上の構成要素を付加し得る。本明細書で説明する内容は、本発明のパワーモジュールのみならず、その製造方法にも該当し得る。「方法」に関する構成要素は「物」に関する構成要素ともなり得る。   One or more components arbitrarily selected from the present specification may be added to the components of the present invention. The contents described herein may apply not only to the power module of the present invention, but also to a method of manufacturing the same. The component relating to the “method” can also be a component relating to the “article”.

《トランジスタ》
本発明のパワーモジュールが備えるデバイスの少なくとも一つは、ワイヤーボンディングされる第3電極を備えたトランジスタである。このようなトランジスタとして、サイリスタ、バイポーラ・トランジスタ、MOSFET、IGBT等のパワーデバイスがある。代表格であるIGBTでいえば、本発明でいう第3電極はゲート電極(G)、第1電極はコレクタ電極(C)、第2電極はエミッタ電極にそれぞれ対応する。なお、本発明のパワーモジュールは、上述したトランジスタ以外に、各種のデバイス(ダイオード等)や制御回路を含み得る。
<< transistor >>
At least one of the devices included in the power module of the present invention is a transistor provided with a third electrode to be wire-bonded. Such transistors include power devices such as thyristors, bipolar transistors, MOSFETs and IGBTs. In the representative IGBT, the third electrode in the present invention corresponds to the gate electrode (G), the first electrode to the collector electrode (C), and the second electrode to the emitter electrode. The power module of the present invention may include various devices (such as diodes) and control circuits in addition to the above-described transistors.

ちなみに、トランジスタに用いられる半導体材料は、CTEが2〜5さらには3〜6ppm/K程度である。例えば、Si(CTE:3ppm/K)、SiC(CTE:3.7ppm/K)、GaN(CTE:5.5ppm/K)等が半導体材料として用いられる。   Incidentally, the semiconductor material used for the transistor has a CTE of about 2 to 5 and further about 3 to 6 ppm / K. For example, Si (CTE: 3 ppm / K), SiC (CTE: 3.7 ppm / K), GaN (CTE: 5.5 ppm / K) or the like is used as the semiconductor material.

《スペーサ》
本発明に係るスペーサは、上述したトランジスタを構成する半導体材料とのCTE差が0.5〜7ppm/K、1〜6ppm/Kさらには2〜5ppm/Kの導電材料からなると好ましい。CTE差が過大では、第2接合層の近傍における熱応力の抑制が不十分となる。スペーサのCTEは、トランジスタのCTEと第2スプレッダのCTEとの中間値であると、第2接合層の近傍における熱応力を抑制できて好ましい。そこで導電材料のCTEは、例えば、4.4〜10ppm/Kさらには5〜8ppm/Kであると好ましい。
"Spacer"
The spacer according to the present invention is preferably made of a conductive material having a CTE difference of 0.5 to 7 ppm / K, 1 to 6 ppm / K, and more preferably 2 to 5 ppm / K with the semiconductor material constituting the transistor described above. If the CTE difference is too large, suppression of thermal stress in the vicinity of the second bonding layer will be insufficient. The CTE of the spacer is preferably an intermediate value between the CTE of the transistor and the CTE of the second spreader because thermal stress in the vicinity of the second bonding layer can be suppressed. Therefore, the CTE of the conductive material is preferably, for example, 4.4 to 10 ppm / K, and more preferably 5 to 8 ppm / K.

導電材料の電気伝導率(導電率)は、少なくとも半導体材料よりも大きく、Cu系材料(純Cu、Cu合金、Cu化合物等)やAl系材料(純Al、Al合金、Al化合物等)等の電極材に近いほど好ましい。   The electrical conductivity (conductivity) of the conductive material is at least higher than that of the semiconductor material, and Cu-based materials (pure Cu, Cu alloys, Cu compounds, etc.), Al-based materials (pure Al, Al alloys, Al compounds, etc.) The closer to the electrode material, the better.

CTEが比較的小さい導電材料は種々あるが、例えば、Cu合金、CuまたはCu合金(単に「Cu系金属」という。)をマトリックスとする複合材料を用いると好ましい。Cu合金として、Cu―W合金、Cu―Mo合金等がある。また、複合材料として、Cu―ダイヤ、Cu―Si、Cu―C等がある。   There are various conductive materials having a relatively small CTE, but it is preferable to use, for example, a composite material having a Cu alloy, Cu or a Cu alloy (simply referred to as "Cu-based metal") as a matrix. Examples of Cu alloys include Cu-W alloys and Cu-Mo alloys. Further, as a composite material, there are Cu-diamond, Cu-Si, Cu-C and the like.

スペーサの厚みは、トランジスタ、スプレッダ、各接合層の諸元(材質、厚さ等)に応じて設定されるが、例えば、0.1mm〜2mmさらには0.5mm〜1.5mm程度であると好ましい。その厚みが過大ではパワーモジュールの薄型化を図れず、その厚みが過小では第2接合層近傍に作用する熱応力の低減が不十分となる。   The thickness of the spacer is set according to the transistor (spreader) and the specifications (material, thickness, etc.) of each bonding layer, and for example, 0.1 mm to 2 mm, and further 0.5 mm to 1.5 mm or so preferable. If the thickness is too large, thinning of the power module can not be achieved, and if the thickness is too small, reduction of thermal stress acting in the vicinity of the second bonding layer becomes insufficient.

《第1接合層/第2接合層》
発熱源であるトランジスタ(単に「デバイス」ともいう。)に接する第1接合層や第2接合層は、稼働中にデバイスが到達し得る最高温度でも溶融等しない高融点材からなることが求められる。一方、そのような接合層が形成されるときの温度(接合温度)は、少なくともデバイスの耐熱温度よりも小さいことが求められる。このような接合層として、例えば、金属間化合物層または金属焼結層がある。
<< First bonding layer / Second bonding layer >>
The first bonding layer and the second bonding layer in contact with the heat generating source transistor (also referred to simply as “device”) are required to be made of a high melting point material which does not melt even at the highest temperature that the device can reach during operation. . On the other hand, the temperature at which such a bonding layer is formed (bonding temperature) is required to be at least smaller than the heat resistance temperature of the device. As such a bonding layer, there is, for example, an intermetallic compound layer or a metal sintered layer.

(1)金属間化合物層は、例えば、少なくとも一方の被接合面上にメタライズ処理等した低融点金属と高融点金属を反応させて、その低融点金属よりも高融点な金属間化合物(IMC)が生成されることにより得られる。このようなIMCによる接合を、固液相互拡散接合または単に「SLID(Solid Liquid Interdiffusion )接合」という。 (1) The intermetallic compound layer is prepared, for example, by reacting a low melting point metal and a high melting point metal metallized on at least one of the surfaces to be joined, and an intermetallic compound (IMC) having a high melting point than the low melting point metal. Is obtained by generating. Such IMC bonding is referred to as solid-liquid interdiffusion bonding or simply "SLID (Solid Liquid Interdiffusion) bonding".

SLID接合に係る低融点金属と高融点金属の組合わせ(ひいては金属間化合物の組成)は、パワーモジュールの耐熱温度、接合工程中の加熱温度、熱膨張係数等を考慮して選択される。低融点金属として、例えば、Sn、In、Ga、Pb、Bi、Zn等やそれらの合金がある。高融点金属として、Ni、Cu,Ti、Mo、W、Si、Cr、Mn、Co、Zr、Nb、Ta、Ag、Au、Pt、等やそれらの合金がある。   The combination of the low melting point metal and the high melting point metal (and the composition of the intermetallic compound) involved in the SLID bonding is selected in consideration of the heat resistance temperature of the power module, the heating temperature during the bonding process, the thermal expansion coefficient and the like. The low melting point metal includes, for example, Sn, In, Ga, Pb, Bi, Zn, etc., and their alloys. As the high melting point metal, there are Ni, Cu, Ti, Mo, W, Si, Cr, Mn, Co, Zr, Nb, Ta, Ag, Au, Pt, etc., and their alloys.

一例として、Sn(融点:約230℃)と、Ni(融点:約1450℃)またはCu(融点:約1085℃)とを組み合わせるとよい。例えば、Sn層とNi層を接触させて約350℃で5分間程度加熱すると、ニッケルスズ(NiSn/融点:約795℃)からなる金属間化合物層が得られる。これにより接合温度を抑制しつつも、高融点な接合層が得られる。勿論、高融点金属/低融点金属の組合わせは、Cu/Sn、Ag/Sn、Pt/Sn/、Au/Sn等でもよい。   As an example, Sn (melting point: about 230 ° C.) and Ni (melting point: about 1450 ° C.) or Cu (melting point: about 1085 ° C.) may be combined. For example, when the Sn layer and the Ni layer are brought into contact and heated at about 350 ° C. for about 5 minutes, an intermetallic compound layer made of nickel tin (NiSn / melting point: about 795 ° C.) is obtained. Thus, a high melting point bonding layer can be obtained while suppressing the bonding temperature. Of course, the combination of high melting point metal / low melting point metal may be Cu / Sn, Ag / Sn, Pt / Sn /, Au / Sn or the like.

(2)金属焼結層は、例えば、被接合面間に介在させた金属ナノ粒子を焼結させることにより得られる。金属ナノ粒子は表面活性が非常に高いため低温で焼結されるが、焼結体自体はその金属本来の高融点を発揮する。従って、金属ナノ粒子を用いた場合も、接合温度を抑制しつつも、高融点な接合層を形成し得る。金属ナノ粒子は、例えば、Ag、Cuからなる。なお、金属ナノ粒子は、通常、その凝集を防止するため、接合時の加熱温度で分解、消失する有機物、酸化物等からなる保護層で被覆されている。 (2) The sintered metal layer can be obtained, for example, by sintering metal nanoparticles interposed between bonding surfaces. The metal nanoparticles are sintered at low temperature due to their very high surface activity, but the sintered body itself exhibits the high melting point inherent to the metal. Therefore, also when metal nanoparticles are used, a high melting point bonding layer can be formed while suppressing the bonding temperature. The metal nanoparticles are made of, for example, Ag and Cu. The metal nanoparticles are usually coated with a protective layer made of an organic substance, an oxide or the like that decomposes and disappears at the heating temperature at the time of bonding in order to prevent its aggregation.

(3)ところで、金属間化合物や金属焼結体は、耐高温性に優れるものの、必ずしも延性や靱性が十分ではない。そこでパワーモジュールの信頼性を確保するために、金属間化合物や金属焼結体からなる接合層は、応力緩和性や耐熱疲労性に優れた層または部材と接していると好ましい。 (3) By the way, although intermetallic compounds and metal sintered bodies are excellent in high temperature resistance, ductility and toughness are not necessarily sufficient. Therefore, in order to ensure the reliability of the power module, it is preferable that the bonding layer made of an intermetallic compound or a metal sintered body be in contact with a layer or member excellent in stress relaxation property and thermal fatigue resistance.

そこで第1接合層は、例えば、金属間化合物または金属焼結体からなり第1電極面に接合される耐高温層と、この耐高温層の他面に接合されるAl系金属(純AlまたはAl合金)からなる緩和層と、を有する複合接合層からなると好ましい。なお、緩和層の他面側(第1スプレッダ側)は、緩和層の厚さ、第1スプレッダからの放熱性等を考慮して、ハンダ層等とすることも可能であるが、緩和層の一面側(トランジスタ側)と同様に、金属間化合物または金属焼結体からなる耐高温層であると好ましい。   Therefore, the first bonding layer is made of, for example, an intermetallic compound or a sintered metal, and a high temperature resistant layer bonded to the first electrode surface, and an Al-based metal (pure Al or And a relaxation layer made of an Al alloy). The other surface side (first spreader side) of the relaxation layer may be a solder layer or the like in consideration of the thickness of the relaxation layer, the heat dissipation from the first spreader, etc. It is preferable that it is a high temperature resistant layer formed of an intermetallic compound or a sintered metal, as in the one side (transistor side).

純Alは、Al以外の不純物元素の合計量が1質量%未満(純度99%(2N)のAl)、0.1質量%未満(純度99.9%(3N)のAl)さらに0.01質量%未満(純度99.99%(4N)のAl)等である。   Pure Al has a total content of impurity elements other than Al of less than 1% by mass (purity 99% (2N) Al), less than 0.1% by mass (purity 99.9% (3N) Al) and further 0.01 Less than% by mass (purity 99.99% (4N) Al) or the like.

本明細書では、Al以外の元素(不純物元素も含めて「合金元素」という。)の合計量が1質量%以上のものを「Al合金」という。緩和層は、十分な延性や靱性が確保される限り、高強度である必要はない。このため合金元素の合計量は5質量%以下さらには3質量%以下であると好ましい。このため純Al以外であれば、例えば、合金元素量が比較的少ない3000番系Al合金等を緩和層に用いることも可能である。   In the present specification, a material in which the total amount of elements other than Al (including the impurity element and “alloy element”) is 1 mass% or more is referred to as “Al alloy”. The relaxation layer need not have high strength as long as sufficient ductility and toughness are ensured. Therefore, the total amount of the alloying elements is preferably 5% by mass or less, and more preferably 3% by mass or less. For this reason, it is also possible to use, for example, a 3000-series Al alloy or the like having a relatively small amount of alloy elements for the relaxation layer, as long as it is other than pure Al.

緩和層の厚みは、トランジスタ、スプレッダ等の諸元(材質、厚さ等)に応じて設定されるが、例えば、5〜200μmさらには10〜500μm程度であると好ましい。その厚みが過大ではパワーモジュールの薄型化を図れず、その厚みが過小では緩和層による応力緩和性や耐熱疲労性の確保が不十分となる。   The thickness of the relaxation layer is set in accordance with the specifications (material, thickness, etc.) of the transistor, the spreader, etc., but is preferably about 5 to 200 μm, more preferably about 10 to 500 μm. If the thickness is too large, thinning of the power module can not be achieved, and if the thickness is too small, securing of the stress relaxation property and thermal fatigue resistance by the relaxation layer becomes insufficient.

第2接合層は、第1接合層の耐高温層と同様に、金属間化合物層または金属焼結層からなると好ましい。第2接合層は、CTE差が小さいトランジスタとスペーサを接合しているため、緩和層のない耐高温層(単層)のみでもよい。   The second bonding layer is preferably made of an intermetallic compound layer or a metal sintered layer, as in the high temperature resistant layer of the first bonding layer. The second bonding layer may be only a high-temperature resistant layer (single layer) without a relaxation layer because the second bonding layer bonds a transistor and a spacer with a small CTE difference.

《第3接合層》
第3接合層は、比較的厚いスペーサと、放熱側にある第2スプレッダとの間にあり、通常、第1接合層(さらには第2接合層)よりも低温側となる。このため第3接合層は、第2接合層と同様な耐高温層(例えば、金属間化合物層、金属焼結層)、第1接合層と同様な複合接合層の他、ハンダ層等でもよい。
<< Third bonding layer >>
The third bonding layer is located between the relatively thick spacer and the second spreader on the heat dissipation side, and is usually on the lower temperature side than the first bonding layer (and the second bonding layer). For this reason, the third bonding layer may be a solder layer or the like in addition to a high temperature resistant layer (for example, an intermetallic compound layer, a metal sintered layer) similar to the second bonding layer, a composite bonding layer similar to the first bonding layer. .

但し、本発明のパワーモジュールでは、クラックの起点が、第2接合層近傍から第3接合層近傍へ移動している。そこで第3接合層は、応力緩和性や耐熱疲労性に優れた複合接合層、または金属間化合物層等よりも軟質なハンダ層からなると好ましい。   However, in the power module of the present invention, the starting point of the crack is moved from the vicinity of the second bonding layer to the vicinity of the third bonding layer. Therefore, it is preferable that the third bonding layer be composed of a composite bonding layer excellent in stress relaxation property and thermal fatigue resistance, or a solder layer softer than an intermetallic compound layer or the like.

《スプレッダ》
スプレッダは、トランジスタの発熱を受熱し、外部へ熱伝導する部材である。本発明でいうスプレッダは、熱を拡散させるための専用部材(放熱器)である必要はない。換言すれば、他機能を有するリードフレーム、電極、冷却器等も、本発明でいうスプレッダに含まれる。
Spreader
The spreader is a member that receives heat from the transistor and conducts heat to the outside. The spreader in the present invention does not have to be a dedicated member (heat sink) for diffusing heat. In other words, a lead frame having another function, an electrode, a cooler, and the like are also included in the spreader in the present invention.

このようなスプレッダ(第1スプレッダと第2スプレッダの少なくとも一方)は、純Cu(無酸素銅)またはCu合金(単に「Cu系金属」ともいう。)からなることが多い。Cu系金属からなるスプレッダは半導体からなるデバイスよりもCTEがかなり大きいため、両者間にはCTE差に応じた大きな熱応力が作用し得る。しかし、本発明のパワーモジュールでは、Al系金属からなるスペーサや第1接合層中の緩和層等により、その熱応力は大きく緩和され、またその熱応力による疲労も大幅に抑制される。   Such a spreader (at least one of the first spreader and the second spreader) is often made of pure Cu (oxygen-free copper) or a Cu alloy (also simply referred to as "Cu-based metal"). Since the spreader made of a Cu-based metal has a CTE considerably larger than that of a device made of a semiconductor, a large thermal stress can be exerted between the two depending on the CTE difference. However, in the power module of the present invention, the thermal stress is greatly relieved by the spacer made of Al-based metal, the relaxation layer in the first bonding layer, etc., and the fatigue due to the thermal stress is also greatly suppressed.

《構成》
本発明の一実施例である両面冷却構造型のパワーモジュールMを模式的に示した断面図を図1に示した。パワーモジュールMは、IGBTであるトランジスタ1と、スペーサ2と、リードフレームであるスプレッダ31(第1スプレッダ)およびスプレッダ32(第1スプレッダ)と、トランジスタ1のコレクタ電極(第1電極)とスプレッダ31を接合する接合層41(第1接合層)と、トランジスタ1のエミッタ電極(第2電極)とスペーサ2を接合する接合層42(第2接合層)と、スペーサ2とスプレッダ32を接合する接合層43(第3接合層)と、を有する。なお、トランジスタ1のゲート電極は、ボンディングワイヤー51により信号端子52と接合される。
"Constitution"
A cross-sectional view schematically showing a double-sided cooling structure type power module M according to an embodiment of the present invention is shown in FIG. The power module M includes an IGBT transistor 1, a spacer 2, a spreader 31 (first spreader) and a spreader 32 (first spreader) as a lead frame, a collector electrode (first electrode) of the transistor 1, and a spreader 31. Bonding layer 41 (first bonding layer) for bonding, a bonding layer 42 (second bonding layer) for bonding the emitter electrode (second electrode) of the transistor 1 and the spacer 2, and bonding for bonding the spacer 2 and the spreader 32. And a layer 43 (third bonding layer). The gate electrode of the transistor 1 is bonded to the signal terminal 52 by the bonding wire 51.

トランジスタ1はSiC(CTE:3.7ppm/K)からなり、スペーサ2はCu−W合金(CTE:6〜7.1ppm/K)からなり、スプレッダ31、32は無酸素銅(純度3Nの高純度銅)からなる。   The transistor 1 is made of SiC (CTE: 3.7 ppm / K), the spacer 2 is made of a Cu-W alloy (CTE: 6 to 7.1 ppm / K), the spreaders 31 and 32 are oxygen free copper (high in purity 3N) Made of pure copper).

接合層41は、純Al(純度:2N)からなる緩和層413と、その各面側に接合されているNiSnからなる金属間化合物層411、412(耐高温層)とを有する3層(複合接合層)からなる。接合層42、43は金属間化合物(NiSn)からなる。なお、接合層43はSn―Ag―Cu系等からなるハンダ層とすることもできる。   The bonding layer 41 is a three-layer (composite) having a relaxation layer 413 made of pure Al (purity: 2 N) and intermetallic compound layers 411 and 412 (high temperature resistant layers) made of NiSn bonded to each surface side thereof. Bonding layer). The bonding layers 42 and 43 are made of an intermetallic compound (NiSn). The bonding layer 43 can also be a solder layer made of Sn-Ag-Cu system or the like.

ちなみに、本実施例では、トランジスタ1の厚さ:100μm、スペーサ2の厚さ:1.15μm、スプレッダ31、32の厚さ:2mm、接合層41の厚さ:110μm(そのうち緩和層413の厚さ:100μm)、接合層42の厚さ:5μm、接合層43の厚さ:100μmとした。   Incidentally, in this embodiment, the thickness of the transistor 1 is 100 μm, the thickness of the spacer 2 is 1.15 μm, the thickness of the spreaders 31 and 32 is 2 mm, the thickness of the bonding layer 41 is 110 μm (of which the thickness of the relaxation layer 413 is The thickness of the bonding layer 42 is 5 μm, and the thickness of the bonding layer 43 is 100 μm.

《接合》
接合層41は次のようにして形成される。先ず、緩和層413となる純Al薄板(箔)の両面に、NiおよびSnが順にメタライズされた接合シートを用意する。この接合シートを、Niが各表面にメタライズされたトランジスタ1のコレクタ電極面とスプレッダ31の被接合面との間に介装する。この状態で加熱保持することにより、各被接合面間のNiとSnがSLID反応を生じて、金属間化合物層411、412が形成される。こうして純Alからなる緩和層413の両面側に金属間化合物層411、412を備えた複合接合層からなる接合層41が形成される。
Bonding
The bonding layer 41 is formed as follows. First, a bonding sheet in which Ni and Sn are sequentially metallized is prepared on both sides of a pure Al thin plate (foil) to be the relaxation layer 413. This bonding sheet is interposed between the collector electrode surface of the transistor 1 in which Ni is metallized on each surface and the bonding surface of the spreader 31. By heating and holding in this state, the Ni and Sn between the surfaces to be joined cause a SLID reaction, and the intermetallic compound layers 411 and 412 are formed. Thus, the bonding layer 41 formed of the composite bonding layer including the intermetallic compound layers 411 and 412 is formed on both surface sides of the relaxation layer 413 made of pure Al.

接合層42は次のようにして形成される。先ず、スペーサ2の片面(図1中の下面)に、NiおよびSnを順にメタライズしておく。トランジスタ1のエミッタ電極面にも、Niをメタライズしておく。次に、そのスペーサ2の片面をトランジスタ1のエミッタ電極面上に積層する。この状態で加熱保持することにより、被接合面間にあるNiとSnがSLID反応を生じて、金属間化合物からなる接合層42が形成される。なお、接合層41、42は、各部材を積層した積層体を、一度に加熱して同時に形成されると好ましい。   The bonding layer 42 is formed as follows. First, Ni and Sn are sequentially metallized on one side of the spacer 2 (the lower surface in FIG. 1). Also on the emitter electrode surface of the transistor 1, Ni is metallized. Next, one surface of the spacer 2 is laminated on the emitter electrode surface of the transistor 1. By heating and holding in this state, the Ni and Sn between the surfaces to be joined cause a SLID reaction, and the joining layer 42 made of an intermetallic compound is formed. In addition, it is preferable that the bonding layers 41 and 42 heat the laminated body which laminated | stacked each member at once, and are simultaneously formed.

接合層43は、SLID接合により接合層41、42を形成した後、スペーサ2の他面(図1中の上面)とスプレッダ32の被接合面との間に、Sn―Ag―Cuハンダペーストを介在させた状態で、リフロー炉等で加熱することにより形成される。なお、接合層43は、接合層41と同様な複合接合層としてもよい。   The bonding layer 43 forms the bonding layers 41 and 42 by SLID bonding, and then uses Sn—Ag—Cu solder paste between the other surface (upper surface in FIG. 1) of the spacer 2 and the bonding surface of the spreader 32. It forms by heating with a reflow furnace etc. in the state which made it intervene. The bonding layer 43 may be a composite bonding layer similar to the bonding layer 41.

M パワーモジュール
1 トランジスタ
2 スペーサ
31 (第1)スプレッダ
32 (第2)スプレッダ
41 (第1)接合層
42 (第2)接合層
43 (第3)接合層
M power module 1 transistor 2 spacer 31 (first) spreader 32 (second) spreader 41 (first) bonding layer 42 (second) bonding layer 43 (third) bonding layer

Claims (6)

発熱源であるトランジスタと、
該トランジスタの第1電極に第1接合層を介して接合される第1スプレッダと、
該トランジスタの第2電極に第2接合層を介して接合されると共に該トランジスタの第3電極に接合されるボンディングワイヤーのスペースを確保するスペーサと、
該スペーサの他面側に第3接合層を介して接合される第2スプレッダとを備え、
前記スペーサは、前記トランジスタを構成する半導体材料との熱膨張係数差が0.5〜7ppm/Kである導電材料からなるパワーモジュール。
A transistor that is a heat source,
A first spreader joined to a first electrode of the transistor via a first bonding layer;
A spacer which is joined to the second electrode of the transistor through the second joining layer and which secures a space of a bonding wire joined to the third electrode of the transistor;
A second spreader joined to the other surface of the spacer via a third bonding layer,
The said spacer is a power module which consists of an electrically-conductive material whose thermal expansion coefficient difference with the semiconductor material which comprises the said transistor is 0.5-7 ppm / K.
前記導電材料は、Cu合金、Cu化合物、CuまたはCu合金をマトリックスとする複合材料のいずれかである請求項1に記載のパワーモジュール。   The power module according to claim 1, wherein the conductive material is any one of a Cu alloy, a Cu compound, a Cu or a composite material having a Cu alloy as a matrix. 前記第2接合層は、金属間化合物層または金属焼結層からなる請求項1または2に記載のパワーモジュール。   The power module according to claim 1, wherein the second bonding layer comprises an intermetallic compound layer or a metal sintered layer. 前記第1接合層または前記第3接合層は、
金属間化合物または金属焼結体からなり前記第1電極面に接合される耐高温層と、
純AlまたはAl合金からなり該耐高温層の他面に接合される緩和層と、
を有する複合接合層からなる請求項1〜3のいずれかに記載のパワーモジュール。
The first bonding layer or the third bonding layer is
A high temperature resistant layer formed of an intermetallic compound or a sintered metal and joined to the first electrode surface;
A relaxation layer made of pure Al or an Al alloy and joined to the other surface of the high temperature resistant layer;
The power module according to any one of claims 1 to 3, comprising a composite bonding layer having:
前記第3接合層は、ハンダ層からなる請求項1〜3のいずれかに記載のパワーモジュール。   The power module according to any one of claims 1 to 3, wherein the third bonding layer comprises a solder layer. 前記第1スプレッダと前記第2スプレッダの少なくとも一方は、純CuまたはCu合金からなる請求項1〜5のいずれかに記載のパワーモジュール。   The power module according to any one of claims 1 to 5, wherein at least one of the first spreader and the second spreader is made of pure Cu or a Cu alloy.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2022103620A (en) * 2020-12-28 2022-07-08 財團法人工業技術研究院 Laminated body and method of manufacturing the same

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001156225A (en) * 1999-11-24 2001-06-08 Denso Corp Semiconductor device
JP2009158502A (en) * 2007-12-25 2009-07-16 Toyota Motor Corp Semiconductor module
WO2017006916A1 (en) * 2015-07-08 2017-01-12 国立研究開発法人産業技術総合研究所 Semiconductor device and method for manufacturing semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001156225A (en) * 1999-11-24 2001-06-08 Denso Corp Semiconductor device
JP2009158502A (en) * 2007-12-25 2009-07-16 Toyota Motor Corp Semiconductor module
WO2017006916A1 (en) * 2015-07-08 2017-01-12 国立研究開発法人産業技術総合研究所 Semiconductor device and method for manufacturing semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2022103620A (en) * 2020-12-28 2022-07-08 財團法人工業技術研究院 Laminated body and method of manufacturing the same
JP7189926B2 (en) 2020-12-28 2022-12-14 財團法人工業技術研究院 LAMINATED PRODUCT AND METHOD FOR MANUFACTURING LAMINATED BODY

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