JP2010267671A - Method of manufacturing electronic component built-in substrate - Google Patents

Method of manufacturing electronic component built-in substrate Download PDF

Info

Publication number
JP2010267671A
JP2010267671A JP2009115732A JP2009115732A JP2010267671A JP 2010267671 A JP2010267671 A JP 2010267671A JP 2009115732 A JP2009115732 A JP 2009115732A JP 2009115732 A JP2009115732 A JP 2009115732A JP 2010267671 A JP2010267671 A JP 2010267671A
Authority
JP
Japan
Prior art keywords
substrate
electronic component
component built
connection
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2009115732A
Other languages
Japanese (ja)
Other versions
JP5399130B2 (en
Inventor
Yoshikatsu Ishizuki
義克 石月
Kazuyuki Aiba
和之 合葉
Motoaki Tani
元昭 谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Fujitsu Semiconductor Ltd
Original Assignee
Fujitsu Ltd
Fujitsu Semiconductor Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd, Fujitsu Semiconductor Ltd filed Critical Fujitsu Ltd
Priority to JP2009115732A priority Critical patent/JP5399130B2/en
Publication of JP2010267671A publication Critical patent/JP2010267671A/en
Application granted granted Critical
Publication of JP5399130B2 publication Critical patent/JP5399130B2/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing an electronic component built-in substrate by which the electronic component built-in substrate which is thin and compact can be manufactured. <P>SOLUTION: An inter-layer connection via 11 is formed on a substrate 10, and an electronic component 13 is mounted on the substrate 10 with a terminal surface where connection terminals 13a are arrayed up. On a substrate 20 where electrodes 20b-1, 20b-2, 20c-1, and 20c-2 for connection are formed, an insulating layer 21 showing fluidity with heat is formed, the substrate 10 and substrate 20 are heated and pressed to be stuck together with the terminal surface and insulating layer 21 opposed to each other, and the connection terminal 13a and inter-layer connection via 11 are electrically connected to the electrodes 20b-2 and 20c-2 for connection. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

本発明は、電子部品内蔵基板の製造方法に関する。   The present invention relates to a method of manufacturing an electronic component built-in substrate.

近年、デジタルカメラや携帯電話などの半導体応用製品では、小型化、薄型化、軽量化などの要求が顕著であり、それに伴い、それらの製品に搭載される電子部品についても小型化や高密度化が急激に進んでいる。この電子部品の高密度化を実現するために、従来、基板上に実装していた電子部品を基板の内部に埋め込む技術、すなわち、電子部品内蔵基板の開発が急速に進められている。   In recent years, semiconductor application products such as digital cameras and mobile phones have become increasingly demanding for miniaturization, thinning, and weight reduction. Along with this, electronic components mounted on these products are also becoming smaller and higher in density. Is progressing rapidly. In order to realize a higher density of electronic components, a technology for embedding electronic components mounted on a substrate in the substrate, that is, a substrate with built-in electronic components has been developed rapidly.

電子部品内蔵基板は、通常、硬い材質のコア基板上に複数の配線層が積層された構造を有している。そして、埋め込まれる電子部品は、その配線層とコア基板の間に配置される場合が一般的である。   The electronic component built-in substrate usually has a structure in which a plurality of wiring layers are laminated on a hard core substrate. The embedded electronic component is generally arranged between the wiring layer and the core substrate.

このような電子部品内蔵基板においては、上述のような高密度化の要求により、基板全体の厚さを薄くしなければならない。したがって、薄い電子部品内蔵基板内に、電子部品がコンパクトに収まるような形で埋め込まれる必要がある。   In such an electronic component built-in substrate, the thickness of the entire substrate must be reduced due to the demand for higher density as described above. Therefore, it is necessary to embed the electronic component in a thin electronic component-embedded substrate so as to fit in a compact manner.

このような条件を満たすために、従来、コア基板や配線基板をそれぞれ個別に製造した後、樹脂により封止し、最後にそれらの基板を重ねた形に実装する技術が提案されている。   In order to satisfy such conditions, conventionally, a technique has been proposed in which a core substrate and a wiring substrate are individually manufactured, sealed with resin, and finally mounted in a form in which the substrates are stacked.

特開２００６−２１０８７０号公報JP 2006-210870 A 特開２００３−７９７０号公報JP 2003-7970 A

しかしながら、従来の電子部品内蔵基板では、貼り合わせた基板間に電子部品を封止するための中間層を設ける必要があるが、この中間層が厚く、電子部品内蔵基板全体の厚さも厚くなるという問題がある。   However, in the conventional electronic component built-in substrate, it is necessary to provide an intermediate layer for sealing the electronic component between the bonded substrates, but this intermediate layer is thick and the entire electronic component built-in substrate is also thick. There's a problem.

上記の点を鑑みて、本発明は、薄型で小型の電子部品内蔵基板を製造可能な電子部品内蔵基板の製造方法を提供することを目的とする。   In view of the above points, an object of the present invention is to provide a method for manufacturing an electronic component built-in substrate capable of manufacturing a thin and small electronic component built-in substrate.

上記目的を達成するために、以下のような工程を有する電子部品内蔵基板の製造方法が提供される。
この電子部品内蔵基板の製造方法は、第１の基板上に層間接続ビアを形成するとともに、電子部品を、接続端子が配列された端子面を上側にして前記第１の基板上に搭載する工程と、接続用電極が形成された第２の基板上に、熱により流動性を示す絶縁層を形成する工程と、前記第１の基板と前記第２の基板を、前記端子面と前記絶縁層とを対向させて、加熱及び加圧して貼り合わせ、前記接続端子及び前記層間接続ビアを、前記接続用電極に電気的に接続する工程と、を有する。 In order to achieve the above object, a method of manufacturing an electronic component built-in substrate having the following steps is provided.
In this method of manufacturing an electronic component built-in substrate, an interlayer connection via is formed on a first substrate, and the electronic component is mounted on the first substrate with a terminal surface on which connection terminals are arranged facing upward. And a step of forming an insulating layer exhibiting fluidity by heat on the second substrate on which the connection electrode is formed, the first substrate and the second substrate, the terminal surface and the insulating layer. And electrically bonding the connection terminal and the interlayer connection via to the connection electrode.

開示の電子部品内蔵基板の製造方法によれば、薄型で小型の電子部品内蔵基板を製造できる。   According to the disclosed method for manufacturing an electronic component built-in substrate, a thin and small electronic component built-in substrate can be manufactured.

第１の実施の形態の電子部品内蔵基板の製造方法の各工程での断面図である。It is sectional drawing in each process of the manufacturing method of the electronic component built-in board | substrate of 1st Embodiment. 図１の工程にて形成される電子部品内蔵基板の断面図である。It is sectional drawing of the electronic component built-in board | substrate formed in the process of FIG. 第２の実施の形態の電子部品内蔵基板の製造方法の各工程での断面図である。It is sectional drawing in each process of the manufacturing method of the electronic component built-in board | substrate of 2nd Embodiment. 図３の工程にて形成される電子部品内蔵基板の断面図である。It is sectional drawing of the electronic component built-in board | substrate formed in the process of FIG. 第２の実施の形態の電子部品内蔵基板の製造方法の変形例を示す図である。It is a figure which shows the modification of the manufacturing method of the electronic component built-in board | substrate of 2nd Embodiment.

以下、本発明の電子部品内蔵基板の製造方法の実施の形態を、図面を参照しつつ説明する。
（第１の実施の形態）
図１は、第１の実施の形態の電子部品内蔵基板の製造方法の各工程での断面図である。 Embodiments of a method for manufacturing an electronic component built-in substrate according to the present invention will be described below with reference to the drawings.
(First embodiment)
FIG. 1 is a cross-sectional view in each step of the manufacturing method of the electronic component built-in substrate according to the first embodiment.

また、図２は、図１の工程にて形成される電子部品内蔵基板の断面図である。
基板１０は、たとえば、図１（Ａ）のように多層配線回路基板であり、複数層の層間絶縁層１０ａ−１，１０ａ−２と、複数層の配線層１０ｂ−１，１０ｂ−２，１０ｂ−３を有している。 FIG. 2 is a cross-sectional view of the electronic component built-in substrate formed in the step of FIG.
The substrate 10 is, for example, a multilayer wiring circuit board as shown in FIG. 1A, and includes a plurality of interlayer insulating layers 10a-1, 10a-2 and a plurality of wiring layers 10b-1, 10b-2, 10b. -3.

層間絶縁層１０ａ−１，１０ａ−２は、たとえば、プリプレグである。層間絶縁層１０ａ−１，１０ａ−２の厚さは、たとえば、２０μｍ〜２００μｍである。配線層１０ｂ−１〜１０ｂ−３（厚さは、たとえば、５μｍ〜２０μｍ）は、たとえば、プリプレグの両面に貼り付けられた銅箔をエッチングすることによって形成される。   Interlayer insulating layers 10a-1 and 10a-2 are, for example, prepregs. The thicknesses of the interlayer insulating layers 10a-1 and 10a-2 are, for example, 20 μm to 200 μm. Wiring layers 10b-1 to 10b-3 (thickness is, for example, 5 μm to 20 μm) are formed, for example, by etching a copper foil attached to both surfaces of a prepreg.

各配線層１０ｂ−１〜１０ｂ−３間は、図示しない層間接続ビアにより接続されている。
このような基板１０上に、層間接続ビア１１を形成する。層間接続ビア１１は、たとえば、金（Ａｕ）、銀（Ａｇ）、銅（Ｃｕ）または半田ペーストなどを用いて、印刷法により形成される。 The wiring layers 10b-1 to 10b-3 are connected by an interlayer connection via (not shown).
Interlayer connection vias 11 are formed on such a substrate 10. The interlayer connection via 11 is formed by a printing method using, for example, gold (Au), silver (Ag), copper (Cu), or solder paste.

次に、接着層１２を介して、電子部品１３を、接続端子１３ａが配列された端子面を上側（フェイスアップ）にして、基板１０上に搭載する。なお、図１（Ａ）では、１つの電子部品１３を搭載する場合を例にしているが、複数搭載してもよい。   Next, the electronic component 13 is mounted on the substrate 10 through the adhesive layer 12 with the terminal surface on which the connection terminals 13 a are arranged facing upward (face-up). In addition, although FIG. 1A illustrates an example in which one electronic component 13 is mounted, a plurality of electronic components 13 may be mounted.

接着層１２は、たとえば、ＤＡＦ（ダイアタッチフィルム）などである。接続端子１３ａとしては、たとえば、Ａｕ、Ａｇ、Ｃｕまたは半田バンプなどが用いられ、たとえば、ワイヤバンプ法を用いて形成される。   The adhesive layer 12 is, for example, DAF (die attach film). As the connection terminal 13a, for example, Au, Ag, Cu, a solder bump, or the like is used, and for example, it is formed by using a wire bump method.

層間接続ビア１１を形成する工程と、電子部品１３を搭載する工程は、どちらが先でもよい。
一方、図１（Ｂ）に示すように、基板２０は、絶縁層２０ａと、絶縁層２０ａの両面に形成された接続用電極２０ｂ−１，２０ｂ−２，２０ｃ−１，２０ｃ−２を有している。 Either the step of forming the interlayer connection via 11 or the step of mounting the electronic component 13 may be performed first.
On the other hand, as shown in FIG. 1B, the substrate 20 has an insulating layer 20a and connection electrodes 20b-1, 20b-2, 20c-1, and 20c-2 formed on both surfaces of the insulating layer 20a. is doing.

絶縁層２０ａは、たとえば、プリプレグである。
接続用電極２０ｂ−２は、基板１０に形成された層間接続ビア１１との接続のための電極であり、接続用電極２０ｃ−２は、電子部品１３の接続端子１３ａとの接続のための電極である。接続用電極２０ｂ−１，２０ｂ−２間は、図示しない層間接続ビアにより接続されている。また、接続用電極２０ｃ−１，２０ｃ−２間も、図示しない層間接続ビアにより接続されている。 The insulating layer 20a is, for example, a prepreg.
The connection electrode 20b-2 is an electrode for connection with the interlayer connection via 11 formed on the substrate 10, and the connection electrode 20c-2 is an electrode for connection with the connection terminal 13a of the electronic component 13. It is. The connection electrodes 20b-1 and 20b-2 are connected by an interlayer connection via (not shown). The connection electrodes 20c-1 and 20c-2 are also connected by an interlayer connection via (not shown).

接続用電極２０ｂ−１，２０ｂ−２，２０ｃ−１，２０ｃ−２は、たとえば、プリプレグの両面に貼り付けられた銅箔をエッチングすることによって形成される。
なお、基板２０も、基板１０のように多層構造としてもよい。 Connection electrodes 20b-1, 20b-2, 20c-1, and 20c-2 are formed, for example, by etching a copper foil that is attached to both surfaces of a prepreg.
The substrate 20 may also have a multilayer structure like the substrate 10.

このような基板２０上に、熱により流動性を示す絶縁層２１を形成する。
絶縁層２１として、たとえば、ポリイミド系樹脂、アクリル系樹脂、フェノール系樹脂、エポキシ樹脂などが用いられる。絶縁層２１の厚さは、たとえば、５０μｍ〜３００μｍである。 An insulating layer 21 that exhibits fluidity is formed on the substrate 20 by heat.
As the insulating layer 21, for example, a polyimide resin, an acrylic resin, a phenol resin, an epoxy resin, or the like is used. The thickness of the insulating layer 21 is, for example, 50 μm to 300 μm.

ところで、基板１０において、層間接続ビア１１と、接続端子１３ａの基板１０からの高さが等しくなるように設計したとしても、製造ばらつきや基板１０の反りなどにより、両者の高さはばらつく可能性がある。その場合、弾性率が大きいほう（固いほう）の高さが高いと、基板２０との貼り合わせ時に、高さの低いほうが基板２０の接続用電極２０ｂ−２，２０ｃ−２に届かない可能性がある。   By the way, even if the substrate 10 is designed so that the height of the interlayer connection via 11 and the connection terminal 13a from the substrate 10 is equal, the heights of both may vary due to manufacturing variations, warpage of the substrate 10, and the like. There is. In this case, if the height of the one having a higher elastic modulus (harder one) is higher, the lower one may not reach the connection electrodes 20b-2 and 20c-2 of the substrate 20 when bonded to the substrate 20. There is.

そのため、層間接続ビア１１と電子部品１３の接続端子１３ａのうち、後述の基板２０との貼り合わせ時の温度での弾性率が小さいほうの基板１０からの高さを、他方よりも高くする。つまり、柔らかい材料を用いているほうの高さを高くする。たとえば、層間接続ビア１１を、Ａｇペーストを用いて形成し、電子部品１３の接続端子１３ａをＡｕバンプで形成した場合、層間接続ビア１１の基板１０からの高さを接続端子１３ａの基板１０からの高さよりも高く形成する。これにより、基板２０との貼り合わせ時に、基板１０の層間接続ビア１１と接続端子１３ａを両方とも、基板２０の接続用電極２０ｂ−２，２０ｃ−２に確実に接続することができる。   Therefore, the height from the board | substrate 10 with the smaller elastic modulus in the temperature at the time of bonding with the below-mentioned board | substrate 20 among the connection terminals 13a of the interlayer connection via 11 and the electronic component 13 is made higher than the other. In other words, the height of the soft material is increased. For example, when the interlayer connection via 11 is formed using Ag paste and the connection terminal 13a of the electronic component 13 is formed of Au bumps, the height of the interlayer connection via 11 from the substrate 10 is determined from the substrate 10 of the connection terminal 13a. It is formed higher than the height. Accordingly, both the interlayer connection via 11 and the connection terminal 13a of the substrate 10 can be reliably connected to the connection electrodes 20b-2 and 20c-2 of the substrate 20 when the substrate 20 is bonded.

より具体的には、電子部品１３の厚さが５０μｍ〜１００μｍの場合、Ａｇペーストを用いた層間接続ビア１１を高さ１５０μｍ程度形成し、Ａｕバンプを用いた接続端子１３ａを高さ３０μｍ程度形成する。なお、接着層１２としてＤＡＦを用いる場合、電子部品１３を、たとえば、温度１５０℃、圧力０．０４ＭＰａで１分という条件で搭載する。   More specifically, when the thickness of the electronic component 13 is 50 μm to 100 μm, the interlayer connection via 11 using Ag paste is formed with a height of about 150 μm, and the connection terminal 13 a using Au bumps is formed with a height of about 30 μm. To do. In addition, when using DAF as the contact bonding layer 12, the electronic component 13 is mounted on the conditions of 1 minute at the temperature of 150 degreeC and the pressure of 0.04 MPa, for example.

次に、図１（Ｃ）の工程では、層間接続ビア１１を形成し電子部品１３を搭載した基板１０と、絶縁層２１を形成した基板２０とを位置合わせして、真空ラミネータを用いて加熱及び加圧して貼り合わせる。   Next, in the step of FIG. 1C, the substrate 10 on which the interlayer connection via 11 is formed and the electronic component 13 is mounted and the substrate 20 on which the insulating layer 21 is formed are aligned and heated using a vacuum laminator. And pressurizing and bonding.

このとき、電子部品１３の端子面と、基板２０の絶縁層２１とを対向させて貼り合わせる。加熱により、絶縁層２１は流動性が増し、電子部品１３や層間接続ビア１１を覆っていき、層間接続ビア１１は、基板２０の接続用電極２０ｂ−２に接合され、電子部品１３の接続端子１３ａは、基板２０の接続用電極２０ｃ−２に接合される。   At this time, the terminal surface of the electronic component 13 and the insulating layer 21 of the substrate 20 are attached to face each other. By heating, the fluidity of the insulating layer 21 increases, and the electronic component 13 and the interlayer connection via 11 are covered. The interlayer connection via 11 is joined to the connection electrode 20b-2 of the substrate 20, and the connection terminal of the electronic component 13 is connected. 13 a is joined to the connection electrode 20 c-2 of the substrate 20.

たとえば、絶縁層２１として、１３０℃の加熱で流動性が増す、味の素ファインテクノ社製のＡＢＦ（Ajinomoto Build-Up Film）を用いた場合、貼り合わせは、たとえば、温度１８０℃、圧力１ＭＰａで約１時間程度行う。   For example, when ABF (Ajinomoto Build-Up Film) manufactured by Ajinomoto Fine-Techno Co., Ltd., whose fluidity is increased by heating at 130 ° C. as the insulating layer 21, the bonding is performed at a temperature of 180 ° C. and a pressure of 1 MPa, for example. Perform for about 1 hour.

これにより、図２で示されるような電子部品内蔵基板が形成される。
上記のような電子部品内蔵基板の製造方法では、加熱により絶縁層２１を流動化させた状態で、基板１０，２０を貼り合わせ、層間接続ビア１１と電子部品１３の上面の接続端子１３ａを、基板２０の接続用電極２０ｂ−２，２０ｃ−２と接合させている。これにより、貼り合わせ後の基板１０，２０間の厚さを薄くすることができ、簡単な工程で、薄型で小型の電子部品内蔵基板が製造可能となる。 Thereby, an electronic component built-in substrate as shown in FIG. 2 is formed.
In the manufacturing method of the electronic component built-in substrate as described above, the substrates 10 and 20 are bonded together with the insulating layer 21 fluidized by heating, and the interlayer connection via 11 and the connection terminal 13a on the upper surface of the electronic component 13 are The substrate 20 is joined to the connection electrodes 20b-2 and 20c-2. Thereby, the thickness between the substrates 10 and 20 after bonding can be reduced, and a thin and small electronic component built-in substrate can be manufactured by a simple process.

なお、貼り合わせ時の温度での、接着層１２の弾性率が、絶縁層２１の弾性率よりも小さくなるような材料を選択することで、より均一な接合が可能となり、接続不良を防止できる。たとえば、接着層１２として弾性率１．８ＧＰａ程度のＤＡＦを用いた場合、絶縁層２１として弾性率４．８ＧＰａ程度の絶縁樹脂材料を用いる。   Note that by selecting a material whose elastic modulus of the adhesive layer 12 is smaller than that of the insulating layer 21 at the temperature at the time of bonding, more uniform bonding is possible and connection failure can be prevented. . For example, when DAF having an elastic modulus of about 1.8 GPa is used as the adhesive layer 12, an insulating resin material having an elastic modulus of about 4.8 GPa is used as the insulating layer 21.

次に第２の実施の形態の電子部品内蔵基板の製造方法を説明する。
（第２の実施の形態）
図３は、第２の実施の形態の電子部品内蔵基板の製造方法の各工程での断面図である。 Next, a method for manufacturing the electronic component built-in substrate according to the second embodiment will be described.
(Second Embodiment)
FIG. 3 is a cross-sectional view at each step of the manufacturing method of the electronic component built-in substrate according to the second embodiment.

また、図４は、図３の工程にて形成される電子部品内蔵基板の断面図である。
図１で示した構成要素と同じものについては同一符号を付し、説明を省略する。
第２の実施の形態の電子部品内蔵基板の製造方法では、第２の実施の形態と異なり、電子部品１３を、接着層１２の代わりに、クッション層３１を介して基板１０に搭載する（図３（Ａ））。 FIG. 4 is a cross-sectional view of the electronic component built-in substrate formed in the step of FIG.
The same components as those shown in FIG. 1 are denoted by the same reference numerals, and description thereof is omitted.
In the manufacturing method of the electronic component built-in substrate according to the second embodiment, unlike the second embodiment, the electronic component 13 is mounted on the substrate 10 via the cushion layer 31 instead of the adhesive layer 12 (see FIG. 3 (A)).

クッション層３１は、たとえば、ゴム系樹脂、アクリル系樹脂、熱可塑性樹脂、ゴム系フィラー含有樹脂など、基板１０と基板２０との貼り合わせ時の熱と圧力により、弾性率が小さくなり、弾性変形する部材である。クッション層３１は、貼り合わせ時の圧力に対して反発性を有している。   The cushion layer 31 has a low elastic modulus due to heat and pressure when the substrate 10 and the substrate 20 are bonded to each other, such as a rubber resin, an acrylic resin, a thermoplastic resin, or a rubber filler-containing resin. It is a member to do. The cushion layer 31 has resilience to the pressure at the time of bonding.

基板２０に対しては、図３（Ｂ）のように絶縁層２１を形成し、電子部品１３の端子面と絶縁層２１とを対向させて、基板１０と貼り合わせる（図３（Ｃ））。貼り合わせる際の製造条件は、第１の実施の形態の電子部品内蔵基板の製造方法と同じでよい。   3B, an insulating layer 21 is formed, and the terminal surface of the electronic component 13 and the insulating layer 21 are opposed to each other and bonded to the substrate 10 (FIG. 3C). . The manufacturing conditions at the time of bonding may be the same as the manufacturing method of the electronic component built-in substrate of the first embodiment.

これにより、図４で示されるような電子部品内蔵基板が形成される。
以上のような構造とすることで、第１の実施の形態と同様の効果が得られるとともに、以下のような効果をさらに有する。たとえば、電子部品１３が傾くなどして、接続端子１３ａの高さにばらつきがあっても、基板１０，２０の貼り合わせ時にクッション層３１が変形し、そのばらつきを吸収し、確実に接続用電極２０ｃ−２に接続可能になる。また、クッション層３１により貼り合わせ時の圧力を緩和できるので、薄い電子部品１３に対して、基板２０を押し付けることによる破損を防止することができる。 Thereby, an electronic component built-in substrate as shown in FIG. 4 is formed.
With the above structure, the same effects as those of the first embodiment can be obtained, and the following effects can be further obtained. For example, even if the height of the connection terminal 13a varies due to the inclination of the electronic component 13 or the like, the cushion layer 31 is deformed when the substrates 10 and 20 are bonded to each other, and the variation is absorbed to ensure connection electrodes. 20c-2 can be connected. Moreover, since the pressure at the time of bonding can be relieved by the cushion layer 31, the damage by pressing the board | substrate 20 with respect to the thin electronic component 13 can be prevented.

なお、基板１０とクッション層３１との間に剛直な材料を用いた層を形成してもよい。
図５は、第２の実施の形態の電子部品内蔵基板の製造方法の変形例を示す図である。
図３で示した構成要素と同じものについては同一符号を付している。 A layer using a rigid material may be formed between the substrate 10 and the cushion layer 31.
FIG. 5 is a diagram showing a modification of the method for manufacturing the electronic component built-in substrate according to the second embodiment.
The same components as those shown in FIG. 3 are denoted by the same reference numerals.

ここでは、基板１０とクッション層３１との間に、基板１０との密着性を上げるために、剛直な材料（たとえば、ポリイミド樹脂、無機フィラー５０重量％以上含有のエポキシ樹脂など）を用いた層３２を形成している。このような構成によれば、電子部品１３の基板１０への沈みこみを防止することができる。   Here, a layer using a rigid material (for example, a polyimide resin, an epoxy resin containing 50% by weight or more of an inorganic filler, etc.) is used between the substrate 10 and the cushion layer 31 in order to improve adhesion to the substrate 10. 32 is formed. According to such a configuration, the electronic component 13 can be prevented from sinking into the substrate 10.

以上、複数の実施の形態に基づき、本発明の電子部品内蔵基板の製造方法の一観点について説明してきたが、これらは一例にすぎず、上記の記載に限定されるものではない。   As mentioned above, although one viewpoint of the manufacturing method of the electronic component built-in board | substrate of this invention was demonstrated based on several embodiment, these are only examples and are not limited to said description.

１０，２０ 基板
１０ａ−１，１０ａ−２ 層間絶縁層
１０ｂ−１，１０ｂ−２，１０ｂ−３ 配線層
１１ 層間接続ビア
１２ 接着層
１３ 電子部品
１３ａ 接続端子
２０ａ，２１ 絶縁層
２０ｂ−１，２０ｂ−２，２０ｃ−１，２０ｃ−２ 接続用電極 DESCRIPTION OF SYMBOLS 10, 20 Board | substrate 10a-1, 10a-2 Interlayer insulation layer 10b-1, 10b-2, 10b-3 Wiring layer 11 Interlayer connection via 12 Adhesion layer 13 Electronic component 13a Connection terminal 20a, 21 Insulation layer 20b-1, 20b -2, 20c-1, 20c-2 Connection electrodes

Claims (5)

第１の基板上に層間接続ビアを形成するとともに、電子部品を、接続端子が配列された端子面を上側にして前記第１の基板上に搭載する工程と、
接続用電極が形成された第２の基板上に、熱により流動性を示す絶縁層を形成する工程と、
前記第１の基板と前記第２の基板を、前記端子面と前記絶縁層とを対向させて、加熱及び加圧して貼り合わせ、前記接続端子及び前記層間接続ビアを、前記接続用電極に電気的に接続する工程と、
を有することを特徴とする電子部品内蔵基板の製造方法。 Forming an interlayer connection via on the first substrate and mounting the electronic component on the first substrate with the terminal surface on which the connection terminals are arranged facing upward;
Forming an insulating layer exhibiting fluidity by heat on the second substrate on which the connection electrode is formed;
The first substrate and the second substrate are bonded to each other by heating and pressing the terminal surface and the insulating layer facing each other, and the connection terminal and the interlayer connection via are electrically connected to the connection electrode. Connecting to each other,
A method of manufacturing an electronic component built-in substrate, comprising: 前記層間接続ビアと前記接続端子のうち、前記貼り合わせの際に、弾性率が低くなるほうの、前記第１の基板からの高さを、他方よりも高く形成することを特徴とする請求項１記載の電子部品内蔵基板の製造方法。   The height from the first substrate, which has a lower elastic modulus during the bonding, of the interlayer connection via and the connection terminal is formed higher than the other. A manufacturing method of the electronic component built-in substrate according to 1. 前記電子部品を、加熱及び加圧により弾性変形する部材を介して、前記第１の基板上に搭載することを特徴とする請求項１または２に記載の電子部品内蔵基板の製造方法。   3. The method of manufacturing an electronic component built-in substrate according to claim 1, wherein the electronic component is mounted on the first substrate via a member that is elastically deformed by heating and pressing. 前記第１の基板と、前記部材との間に剛直な材料を用いた層を形成することを特徴とする請求項３記載の電子部品内蔵基板の製造方法。   4. The method of manufacturing an electronic component built-in substrate according to claim 3, wherein a layer using a rigid material is formed between the first substrate and the member. 加熱及び加圧により弾性変形する前記部材は、ゴム系樹脂、アクリル系樹脂、熱可塑性樹脂またはゴム系フィラー含有樹脂であることを特徴とする請求項３または４に記載の電子部品内蔵基板の製造方法。   5. The electronic component built-in substrate according to claim 3, wherein the member that is elastically deformed by heating and pressurization is a rubber-based resin, an acrylic resin, a thermoplastic resin, or a rubber-based filler-containing resin. Method.
JP2009115732A 2009-05-12 2009-05-12 Manufacturing method of electronic component built-in substrate Expired - Fee Related JP5399130B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2009115732A JP5399130B2 (en) 2009-05-12 2009-05-12 Manufacturing method of electronic component built-in substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2009115732A JP5399130B2 (en) 2009-05-12 2009-05-12 Manufacturing method of electronic component built-in substrate

Publications (2)

Publication Number Publication Date
JP2010267671A true JP2010267671A (en) 2010-11-25
JP5399130B2 JP5399130B2 (en) 2014-01-29

Family

ID=43364428

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009115732A Expired - Fee Related JP5399130B2 (en) 2009-05-12 2009-05-12 Manufacturing method of electronic component built-in substrate

Country Status (1)

Country Link
JP (1) JP5399130B2 (en)

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01264230A (en) * 1988-04-15 1989-10-20 Hitachi Ltd Semiconductor device
JPH0918151A (en) * 1995-06-28 1997-01-17 Toshiba Corp Mounted circuit device and production thereof
JPH11224912A (en) * 1998-02-05 1999-08-17 Hitachi Chem Co Ltd Chip carrier substrate for semiconductor package and semiconductor package
JP2005302991A (en) * 2004-04-12 2005-10-27 Yamaichi Electronics Co Ltd Manufacturing method of multi-layered wiring substrate
JP2006196785A (en) * 2005-01-14 2006-07-27 Dainippon Printing Co Ltd Printed-wiring board having built-in electronic component and manufacturing method thereof
JP2008124260A (en) * 2006-11-13 2008-05-29 Toppan Printing Co Ltd Multilayer wiring substrate and manufacturing method thereof
JP2008159819A (en) * 2006-12-22 2008-07-10 Tdk Corp Method for packaging electronic component, method for producing substrate incorporating electronic component, and substrate with built-in electronic component

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01264230A (en) * 1988-04-15 1989-10-20 Hitachi Ltd Semiconductor device
JPH0918151A (en) * 1995-06-28 1997-01-17 Toshiba Corp Mounted circuit device and production thereof
JPH11224912A (en) * 1998-02-05 1999-08-17 Hitachi Chem Co Ltd Chip carrier substrate for semiconductor package and semiconductor package
JP2005302991A (en) * 2004-04-12 2005-10-27 Yamaichi Electronics Co Ltd Manufacturing method of multi-layered wiring substrate
JP2006196785A (en) * 2005-01-14 2006-07-27 Dainippon Printing Co Ltd Printed-wiring board having built-in electronic component and manufacturing method thereof
JP2008124260A (en) * 2006-11-13 2008-05-29 Toppan Printing Co Ltd Multilayer wiring substrate and manufacturing method thereof
JP2008159819A (en) * 2006-12-22 2008-07-10 Tdk Corp Method for packaging electronic component, method for producing substrate incorporating electronic component, and substrate with built-in electronic component

Also Published As

Publication number Publication date
JP5399130B2 (en) 2014-01-29

Similar Documents

Publication Publication Date Title
JP5326281B2 (en) Semiconductor mounting wiring board, manufacturing method thereof, and semiconductor package
JP5077448B2 (en) Semiconductor chip built-in wiring board and manufacturing method thereof
US7888174B2 (en) Embedded chip package process
JP2009170753A (en) Multilayer printed wiring board and mounting body using the same
JP2006173388A (en) Multi-stage configuration semiconductor module and manufacturing method therefor
JPWO2006100909A1 (en) Semiconductor device and manufacturing method thereof
JP2011222553A (en) Wiring board with built-in semiconductor chip and manufacturing method of the same
JP2005191156A (en) Wiring plate containing electric component, and its manufacturing method
JP2009152253A (en) Semiconductor device and method of manufacturing the same
JP2009289802A (en) Module having electronic part built-in and production method thereof
JP2012074497A (en) Circuit board
JP5459108B2 (en) Component built-in wiring board
JP2008159682A (en) Multilayer printed wiring board and its manufacturing method
KR20060044369A (en) Semiconductor device and mu1ti1ayer substrate therefor
JP2005302922A (en) Wiring board and its manufacturing method
JP5176676B2 (en) Manufacturing method of component-embedded substrate
JP5427476B2 (en) Semiconductor sensor device
JP2007103614A (en) Semiconductor device and manufacturing method thereof
JP2002151853A (en) Multilayer printed wiring board and manufacturing method thereof
JP2007067053A (en) Module with built-in component, and manufacturing method thereof
JP5399130B2 (en) Manufacturing method of electronic component built-in substrate
JP2010040721A (en) Semiconductor module, semiconductor device, portable apparatus, and manufacturing method of semiconductor module, and manufacturing method of semiconductor device
JP2009004813A (en) Wiring substrate for mounting semiconductor
JP4349270B2 (en) Wiring board and manufacturing method thereof
JP2008098202A (en) Multilayer wiring circuit board, multilayer wiring circuit board structure

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20120118

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20130226

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20130312

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20130513

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20131022

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20131023

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313115

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

LAPS Cancellation because of no payment of annual fees