JP2005191156A - Wiring plate containing electric component, and its manufacturing method - Google Patents

Wiring plate containing electric component, and its manufacturing method Download PDF

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Publication number
JP2005191156A
JP2005191156A JP2003428517A JP2003428517A JP2005191156A JP 2005191156 A JP2005191156 A JP 2005191156A JP 2003428517 A JP2003428517 A JP 2003428517A JP 2003428517 A JP2003428517 A JP 2003428517A JP 2005191156 A JP2005191156 A JP 2005191156A
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wiring board
electronic component
resin
wiring
electrode
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Tsuneo Hamaguchi
恒夫 濱口
Toshiyuki Toyoshima
利之 豊島
Junichi Murai
淳一 村井
Shigeru Uchiumi
茂 内海
Kenji Muraki
健志 村木
Mitsunori Ishizaki
光範 石崎
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73257—Bump and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To improve the bond reliability of a solder bonded part between laminated wiring boards or between electronic component and the wiring board, and to reduce the distortion of the solder bonded part. <P>SOLUTION: The electronic component containing wiring board 10 having a plurality of laminated wiring boards 11, 12, 13 with an electronic component 70 housed between the wiring boards comprises a first and third wiring boards 11, 13 laid on both surfaces of the electronic component containing wiring board 10, a second wiring board 12 on an inner layer between the first and third wiring boards, and an electronic component 70 disposed in an opening 22 formed in the second wiring board 12. An insulation layer 20 of each wiring board 11, 12, 13 is made of a material having a low thermal expandability having a linear expansion coefficient of 10 to 18×10<SP>-6</SP>1/°C and a high rigidity of 7 to 30 GPa in Young's modulus. The electric connection between electrodes of each wiring board 11, 12, 13 is executed by soldering with resin adhesives 50 filled between the wiring boards. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

この発明は、高密度に電子部品を内蔵した信頼性の高い電子部品内蔵配線板およびその製造方法に関するものである。   The present invention relates to a highly reliable wiring board with built-in electronic components at a high density and a method for manufacturing the same.

近年、電子機器の小型化の要求に伴い、電子部品を高密度に実装することが必要になってきている。そのため、電子部品を内蔵した回路基板の開発が進められている。   In recent years, with the demand for downsizing of electronic devices, it has become necessary to mount electronic components at high density. Therefore, development of circuit boards with built-in electronic components is in progress.

従来、部品内蔵基板とその製造方法として、例えば特開２００２−２９００５１に示す技術があった（特許文献１参照）。   Conventionally, as a component-embedded substrate and a manufacturing method thereof, for example, there is a technique disclosed in JP-A-2002-290051 (see Patent Document 1).

特許文献１の図５に示す部品内蔵基板は、電気絶縁層と、配線パターンと、電子部品としての半導体と、ビアペーストからなるインナービアと、電子部品としての回路部品と、配線板を有している。半導体はバンプにより、回路部品は半田によりそれぞれ配線パターンと接続されている。   The component-embedded substrate shown in FIG. 5 of Patent Document 1 has an electrical insulating layer, a wiring pattern, a semiconductor as an electronic component, an inner via made of via paste, a circuit component as an electronic component, and a wiring board. ing. The semiconductor is connected to the wiring pattern by bumps, and the circuit component is connected to the wiring pattern by solder.

電気絶縁層はアルミナ等のフィラーと絶縁性樹脂との混合物を用いる。配線パターンは金属箔や導電性樹脂組成物、金属板を加工したリードフレームで構成される。配線パターンは転写、スクリーン印刷、エッチング等により形成される。半導体はトランジスタ、ＩＣ、ＬＳＩなどの半導体素子を用いる。半導体素子は半導体ベアチップも含む。半導体素子と配線パターンとの接続は、例えば導電性接着剤と異方性導電接着フィルム（ＡＣＦ）を用いる。インナービアは異なる層の配線パターンを接続するためのもので、そのビアペーストは導電性粉末と樹脂の混合物で構成される。   The electrical insulating layer uses a mixture of a filler such as alumina and an insulating resin. The wiring pattern is composed of a metal foil, a conductive resin composition, or a lead frame processed from a metal plate. The wiring pattern is formed by transfer, screen printing, etching, or the like. As the semiconductor, a semiconductor element such as a transistor, IC, or LSI is used. The semiconductor element also includes a semiconductor bare chip. For example, a conductive adhesive and an anisotropic conductive adhesive film (ACF) are used for connection between the semiconductor element and the wiring pattern. The inner via is for connecting wiring patterns of different layers, and the via paste is composed of a mixture of conductive powder and resin.

上記部品内蔵基板の製造方法は、まず、フィラーと絶縁性樹脂を混合した絶縁性樹脂混合物をシート状に成形することにより電気絶縁層を形成する。次に、電気絶縁層を硬化温度以下の温度に加熱して乾燥させることにより、粘着性を低下させる。そして、半硬化状態の電気絶縁層にビア用の穴をレーザなどで形成する（特許文献１の図６Ａ）。次に、ビアに導電性接着剤を印刷や注入によって充填する（同じく図６Ｂ）。樹脂フィルムなどのキャリア上に形成した配線パターンに、バンプを用いて半導体を実装する（同じく図６Ｃ）。回路部品を実装した配線パターンを備えるキャリアと、電気絶縁層と、電気絶縁材料と、配線板と、電気絶縁層と、半導体を実装した配線パターンを備えるキャリアとを位置合わせする（同じく図６Ｄ）。そして、加熱・加圧することにより、それらの部材が一体化され、表裏のキャリアを剥がすことにより部品内蔵モジュールを得る（同じく図６Ｅ）。   In the manufacturing method of the component-embedded substrate, first, an electrically insulating layer is formed by forming an insulating resin mixture obtained by mixing a filler and an insulating resin into a sheet shape. Next, the electrical insulating layer is heated to a temperature equal to or lower than the curing temperature and dried to reduce the adhesiveness. Then, a via hole is formed in the semi-cured electrical insulating layer with a laser or the like (FIG. 6A of Patent Document 1). Next, the via is filled with a conductive adhesive by printing or injection (also in FIG. 6B). A semiconductor is mounted on a wiring pattern formed on a carrier such as a resin film using bumps (also in FIG. 6C). A carrier having a wiring pattern on which circuit components are mounted, an electrical insulating layer, an electrical insulating material, a wiring board, an electrical insulating layer, and a carrier having a wiring pattern on which a semiconductor is mounted are aligned (same FIG. 6D). . Then, by heating and pressurizing, these members are integrated, and by removing the front and back carriers, a component built-in module is obtained (same FIG. 6E).

また、従来の部品内蔵基板として、例えば特開２００１−２１０９５５に示すものがあった（特許文献２参照）。   Further, as a conventional component-embedded substrate, for example, there is one disclosed in JP-A-2001-210955 (see Patent Document 2).

特許文献２の部品内蔵基板は、ガラスエポキシ樹脂、アラミドエポキシ樹脂等の合成樹脂よりなる複数の絶縁基板およびその内層配線と両面に形成された配線およびその配線群を電気的に接続するビアホール導体を主たる構成要素とする多層配線基板において、銀または銅ペースト等の導電体が充填されるビアホール以外に複数の貫通穴を設け、その内部にチップ抵抗、チップコンデンサ、チップコイルなどの電子部品が内蔵されている。また、ビアホール及び貫通孔内に導電性ペーストを充填し、その上に銅箔を配置したのち、両面から加熱、加圧してシート基材を圧縮する。   The component-embedded substrate of Patent Document 2 includes a plurality of insulating substrates made of a synthetic resin such as glass epoxy resin and aramid epoxy resin, inner layer wiring, wiring formed on both surfaces, and via-hole conductors that electrically connect the wiring group. In the multilayer wiring board as the main component, a plurality of through holes are provided in addition to via holes filled with a conductor such as silver or copper paste, and electronic components such as chip resistors, chip capacitors, and chip coils are incorporated in the through holes. ing. In addition, after filling the via hole and the through hole with the conductive paste and disposing the copper foil thereon, the sheet base material is compressed by heating and pressing from both sides.

特開平２００２−２９００５１号公報JP-A-2002-290051 特開平２００１−２１０９５５号公報Japanese Patent Laid-Open No. 2001-210955

従来の特許文献１の部品内蔵基板においては、絶縁樹脂層として絶縁樹脂中にアルミナまたはシリカなどの無機フィラー（粒子）を含有させたものを使用している。絶縁樹脂にフィラーを高濃度に含有させると、絶縁層が脆くなる。そのため、部品内蔵基板に曲げが加わった時に、絶縁樹脂層にクラックが発生し易く信頼性が低下する。また、線膨張係数が３０から５０×１０−６１／℃と大きいため、表面に搭載した電子部品とのはんだ接合部にかかるひずみが大きくなり、はんだ接合部の接合信頼性が低くなる問題がある。 In the conventional component-embedded substrate of Patent Document 1, an insulating resin layer containing an inorganic filler (particle) such as alumina or silica in an insulating resin is used. If the insulating resin contains a high concentration of filler, the insulating layer becomes brittle. For this reason, when the component-embedded substrate is bent, the insulating resin layer is easily cracked and the reliability is lowered. In addition, since the linear expansion coefficient is as large as 30 to 50 × 10 −6 1 / ° C., the strain applied to the solder joint with the electronic component mounted on the surface increases, and the joint reliability of the solder joint decreases. is there.

また、絶縁樹脂層は、絶縁樹脂に無機フィラーを含有させたものからなるため、剛性が低い。配線板の表面に、電子部品（半導体素子など）をはんだで接合する際には、温度が約２４０℃に達する。当該温度では、絶縁樹脂層を形成する樹脂のガラス転移温度を越え、樹脂のヤング率が室温状態の約１／１００に大幅に低下するため、基板が大きくたわみ、電子部品の電極と基板電極とのはんだ接合部がはずれて、接合が困難になる問題が発生する。   Moreover, since the insulating resin layer is made of an insulating resin containing an inorganic filler, the rigidity is low. When an electronic component (semiconductor element or the like) is joined to the surface of the wiring board with solder, the temperature reaches about 240 ° C. At that temperature, the glass transition temperature of the resin forming the insulating resin layer is exceeded, and the Young's modulus of the resin is greatly reduced to about 1/100 of the room temperature state. This causes a problem that the solder joint part is detached and the joining becomes difficult.

従来の特許文献２の部品内蔵基板では、電子部品と配線パターンとの接続に導電性接着剤を使用するので、当該電気的接続が接触となり、接続信頼性がはんだなどの金属接合を伴ったものに比べて低くなる問題がある。また、電子部品をビアホールと同様に形成される貫通孔に内蔵するので、小型の電子部品しか配置できなかったり、また、貫通孔に電子部品を立てて配置すると基板自体が厚くなる問題が発生する。さらに、部品内蔵基板を製造した後でないとテストを行なうことができない。   In the conventional component-embedded substrate of Patent Document 2, a conductive adhesive is used to connect the electronic component and the wiring pattern, so that the electrical connection becomes a contact, and the connection reliability is accompanied by metal bonding such as solder. There is a problem that becomes lower than. In addition, since the electronic component is built in the through-hole formed in the same manner as the via hole, only a small electronic component can be arranged, or if the electronic component is placed upright in the through-hole, the substrate itself becomes thick. . Further, the test can be performed only after the component built-in board is manufactured.

この発明は上記のような課題を解決するためになされたものであり、積層された配線板間の剛性を高め、電子部品と配線板間のはんだ接合部のひずみを小さくすることで接合信頼性を向上することができる電子部品内蔵配線板およびその製造方法を提供する。   The present invention has been made to solve the above-described problems, and increases the rigidity between the laminated wiring boards, and reduces the distortion of the solder joint between the electronic component and the wiring board, thereby reducing the bonding reliability. An electronic component built-in wiring board and a method for manufacturing the same are provided.

この発明に係る電子部品内蔵配線板は、複数の配線板を積層するとともに当該配線板間に電子部品を収容させた電子部品内蔵配線板において、電子部品内蔵配線板の両面に配置された第１及び第３の配線板と、第１及び第３の配線板間の内層に配置された第２の配線板と、第２の配線板に形成された開口部に配置された電子部品を備え、各配線板の絶縁層はアラミド繊維またはガラス繊維に樹脂が含浸された材料で構成され、各配線板間の電極間の電気的接続をはんだ接合により実施し、積層された配線板間には樹脂接着剤が充填されていることを特徴とする。   The wiring board with a built-in electronic component according to the present invention is a wiring board with a built-in electronic component in which a plurality of wiring boards are stacked and the electronic component is accommodated between the wiring boards. And a third wiring board, a second wiring board arranged in an inner layer between the first and third wiring boards, and an electronic component arranged in an opening formed in the second wiring board, The insulating layer of each wiring board is made of a material in which aramid fiber or glass fiber is impregnated with resin, and electrical connection between electrodes between each wiring board is performed by solder bonding, and resin between the laminated wiring boards It is characterized by being filled with an adhesive.

この発明の電子部品内蔵配線板によれば、複数の配線板を積層し、内層の配線板に形成した開口部に電子部品を収容し、各配線板間の電気的接合をはんだで実施するとともに、積層された配線板間に樹脂接着剤を充填する。そして、各配線板の絶縁層を、ガラス繊維またはアラミド繊維にエポキシ樹脂等を含浸させた材料（線膨張係数は１０〜１８×１０−６１／℃、ヤング率は７〜３０ＧＰａ）で構成しているため、絶縁層を樹脂で構成したものよりも低熱膨張で剛性を高めることができ、電子部品の接合信頼性が向上し、はんだ接合時の加熱で配線基板がたわんで電子部品の接合不良が生じることはなくなる効果がある。 According to the wiring board with a built-in electronic component of the present invention, a plurality of wiring boards are stacked, the electronic parts are accommodated in openings formed in the inner wiring board, and electrical connection between the wiring boards is performed with solder. The resin adhesive is filled between the laminated wiring boards. The insulating layer of each wiring board is made of a material in which glass fiber or aramid fiber is impregnated with epoxy resin or the like (linear expansion coefficient is 10 to 18 × 10 −6 1 / ° C., Young's modulus is 7 to 30 GPa). Therefore, it is possible to increase rigidity with lower thermal expansion than that made of an insulating layer made of resin, improving the bonding reliability of electronic components, and the wiring board bends due to heating during solder bonding, resulting in poor bonding of electronic components This has the effect of preventing the occurrence of.

実施の形態１．
図１はこの発明の実施の形態１による電子部品内蔵配線板を示す断面図である。図において、電子部品内蔵配線板１０は、電子部品内蔵配線板１０の裏面に配置される第１の配線板１１と、電子部品内蔵配線板１０の表面に配置される第３の配線板１３と、電子部品内蔵配線板１０の内層にあって開口部２２を有する第２の配線板１２と、第２の配線板１２に設けた開口部２２に配置される電子部品７０と、上記各配線板１１，１２，１３の電極間を電気的に接続するはんだ接合部４２と、上記各配線板１１，１２，１３を絶縁接合する樹脂接着剤５０を主要構成要素としている。 Embodiment 1 FIG.
1 is a cross-sectional view showing an electronic component built-in wiring board according to Embodiment 1 of the present invention. In the figure, the electronic component built-in wiring board 10 includes a first wiring board 11 disposed on the back surface of the electronic component built-in wiring board 10 and a third wiring board 13 disposed on the surface of the electronic component built-in wiring board 10. A second wiring board 12 having an opening 22 in the inner layer of the electronic component built-in wiring board 10, an electronic component 70 disposed in the opening 22 provided in the second wiring board 12, and each of the above wiring boards The main components are a solder joint 42 that electrically connects the electrodes 11, 12, and 13, and a resin adhesive 50 that insulates and joins the wiring boards 11, 12, and 13.

本実施の形態では、第１、第２および第３の配線板１１，１２，１３の絶縁層２０は、ガラス繊維にエポキシ樹脂等の樹脂を含浸させた基材やアラミド繊維にエポキシ樹脂等の樹脂を含浸させた基材を用いる。すなわち、当該絶縁層２０は、線膨張係数が１０〜１８×１０−６１／℃と低熱膨張性で、ヤング率が７〜３０ＧＰａの剛性の高い材料で構成される。そのため、絶縁層が樹脂で構成されたものよりも低熱膨張であり、抵抗やコンデンサ等のチップ部品またはＬＳＩパッケージ等の電子部品７０の熱膨張に近くなる。その結果、電子部品７０と配線板１１との接合信頼性が向上し、はんだ接合時に配線板１１，１２，１３がたわんで電子部品７０の接合不良が発生することはない。 In the present embodiment, the insulating layers 20 of the first, second and third wiring boards 11, 12 and 13 are made of a base material in which a glass fiber is impregnated with a resin such as an epoxy resin or an aramid fiber such as an epoxy resin. A substrate impregnated with resin is used. That is, the insulating layer 20 is made of a highly rigid material having a linear expansion coefficient of 10 to 18 × 10 −6 1 / ° C. and low thermal expansion and a Young's modulus of 7 to 30 GPa. Therefore, the insulating layer has a lower thermal expansion than that in which the insulating layer is made of resin, and is close to the thermal expansion of a chip component such as a resistor or a capacitor or an electronic component 70 such as an LSI package. As a result, the joining reliability between the electronic component 70 and the wiring board 11 is improved, and the wiring boards 11, 12, and 13 are not bent during solder joining, and the joining failure of the electronic component 70 does not occur.

第１の配線板１１の両面には電極３０、３１が形成されており、バイア（Ｖｉａ）２１により電気的に接続されている。第３の配線板１３の両面には電極３３、３５が形成されており、バイア２１により電気的に接続されている。第１の配線板１１と第３の配線板１３は、厚さ０．１ｍｍで表面に電極３１と３３を設けた配線板を使用したが、厚さは０．１ｍｍに限定されるものでない。また、電極３１、３２、３３、３５は通常プリント配線板で形成されるのと同じ方法の写真製版とめっきで形成できる。   Electrodes 30 and 31 are formed on both surfaces of the first wiring board 11 and are electrically connected by vias (Via) 21. Electrodes 33 and 35 are formed on both surfaces of the third wiring board 13 and are electrically connected by vias 21. For the first wiring board 11 and the third wiring board 13, wiring boards having a thickness of 0.1 mm and electrodes 31 and 33 provided on the surface thereof are used, but the thickness is not limited to 0.1 mm. In addition, the electrodes 31, 32, 33, and 35 can be formed by photolithography and plating in the same method as that usually formed by a printed wiring board.

第２の配線板１２は、上述のように電子部品７０を収容するための開口部２２を設けている。開口部２２の形成はレーザ・金型による打ち抜き等で形成する。また、図１の例では、第２の配線板１２として、厚さ０．１ｍｍのプリプレグ（ガラスエポキシ基材の半硬化品）を４枚重ねたものにインナービア接続２１を備えた多層基板を使用した。しかしながら、これに限定することなく電子部品７０が収容できる厚さであればプリプレグ一枚の配線基板でも良い。   The second wiring board 12 is provided with the opening 22 for accommodating the electronic component 70 as described above. The opening 22 is formed by punching with a laser or a mold. In the example of FIG. 1, as the second wiring board 12, a multilayer board provided with an inner via connection 21 on four stacked prepregs (semi-cured glass epoxy base materials) having a thickness of 0.1 mm. used. However, the present invention is not limited to this, and a single prepreg wiring board may be used as long as the electronic component 70 can be accommodated.

また、本実施の形態では、第１、第２、第３の配線板１１，１２，１３の電極間を電気的に接続するために、配線板間接合部４２をはんだによる接合で実現している。また、電子部品７０の電極３４と配線板１１の電極３１の電子部品・配線板間接合部４４もはんだ接合により実現している。このため、上述の特許文献２と比較して、導電性接着剤を使用しないので、接続信頼性が高くなる。   Further, in the present embodiment, in order to electrically connect the electrodes of the first, second, and third wiring boards 11, 12, and 13, the inter-wiring board joint portion 42 is realized by soldering. Yes. In addition, the electronic component / wiring board junction 44 between the electrode 34 of the electronic component 70 and the electrode 31 of the wiring board 11 is also realized by solder bonding. For this reason, compared with the above-mentioned patent document 2, since a conductive adhesive is not used, connection reliability becomes high.

さらに、本実施の形態では、電子部品７０の周囲、はんだ接合部４２および配線板１１，１２，１３の周囲を樹脂接着剤５０で充填する。その結果、はんだ接合部４２のひずみを小さくすることができ、機械的な曲げおよび温度変化に伴う熱応力にも十分耐えることができる。樹脂接着剤５０として、例えばエポキシ樹脂系接着剤を用いる。さらに、エポキシ樹脂に有機酸を含有した樹脂接着剤を用いると、はんだバンプの表面酸化膜を容易に除去し、はんだ接合が歩留りよく実現できる。   Furthermore, in this embodiment, the periphery of the electronic component 70, the solder joint portion 42, and the periphery of the wiring boards 11, 12, 13 are filled with the resin adhesive 50. As a result, the distortion of the solder joint portion 42 can be reduced, and the thermal stress accompanying mechanical bending and temperature change can be sufficiently tolerated. For example, an epoxy resin adhesive is used as the resin adhesive 50. Furthermore, when a resin adhesive containing an organic acid is used as the epoxy resin, the surface oxide film of the solder bump can be easily removed, and solder bonding can be realized with a high yield.

本実施の形態においては、電子部品７０は第１の配線板１１に接合されているが、第３の配線板１３でもよいし、第１と第３の配線板１１と１３の両方に接続されていてもよい。電子部品７０は抵抗、コンデンサ、インダクタンスなどの受動部品およびＬＳＩなどの能動部品である。   In the present embodiment, the electronic component 70 is bonded to the first wiring board 11, but it may be the third wiring board 13 or connected to both the first and third wiring boards 11 and 13. It may be. The electronic component 70 is a passive component such as a resistor, a capacitor, or an inductance, and an active component such as an LSI.

さらに、図２に示すように、図１の電子部品内蔵配線板１０を複数個用意して、第１の配線板１１の表面に設けた電極３０と、第３の配線板１３の表面に設けた電極３５を接合することにより、積層された電子部品内蔵配線板を製作してもよい。   Further, as shown in FIG. 2, a plurality of the electronic component built-in wiring boards 10 of FIG. 1 are prepared and provided on the surface of the first wiring board 11 and on the surface of the third wiring board 13. A laminated electronic component built-in wiring board may be manufactured by bonding the electrodes 35.

以上のように、この発明の実施の形態１は、複数の配線板間に電子部品を収容させた電子部品内蔵配線板において、各配線板の絶縁層は、ガラス繊維またはアラミド繊維にエポキシ樹脂を含浸させた材料で構成されるため、電子部品と同等の低熱膨張と剛性が得られる。そのため、電子部品の接合信頼性が向上し、はんだ接合時の加熱で基板がたわんで電子部品の接合不良が生じることはなくなる効果がある。   As described above, according to Embodiment 1 of the present invention, in an electronic component built-in wiring board in which electronic components are accommodated between a plurality of wiring boards, the insulating layer of each wiring board is made of epoxy resin on glass fiber or aramid fiber. Since it is composed of the impregnated material, low thermal expansion and rigidity equivalent to those of electronic components can be obtained. Therefore, the bonding reliability of the electronic component is improved, and there is an effect that the substrate does not bend due to the heating at the time of soldering and the bonding failure of the electronic component does not occur.

さらに、各配線板間には樹脂接着剤が充填されているため、はんだ接合のひずみを小さくすることができ、はんだ接合部の信頼性を向上することができる。   Furthermore, since the resin adhesive is filled between the wiring boards, the distortion of the solder joint can be reduced, and the reliability of the solder joint can be improved.

実施の形態２．
この発明の実施の形態２では、実施の形態１（図１）に示す電子部品内蔵配線板の製造方法について説明する。図３は本実施の形態による電子部品内蔵配線板の製造方法を示す断面図である。 Embodiment 2. FIG.
In the second embodiment of the present invention, a method of manufacturing the electronic component built-in wiring board shown in the first embodiment (FIG. 1) will be described. FIG. 3 is a cross-sectional view showing a method of manufacturing an electronic component built-in wiring board according to the present embodiment.

図３（ａ）は、第１と第３の配線板１１、１３の電極３１、３３上に接合用のはんだバンプ４１、４３を形成すると共に電子部品７０の電極３４をはんだバンプ４３を介して第１の配線板１１に接合した状態を示す。その作製方法は第１と第３の配線板１１，１３の電極３１、３３上に、はんだペーストを印刷し、電子部品７０を搭載した後、加熱してはんだを溶融し、冷却することによって実現できる。なお、ここで、電子部品７０と第１配線板１１の隙間を樹脂で埋めてもよい。   In FIG. 3A, solder bumps 41 and 43 for bonding are formed on the electrodes 31 and 33 of the first and third wiring boards 11 and 13, and the electrodes 34 of the electronic component 70 are connected via the solder bumps 43. The state joined to the 1st wiring board 11 is shown. The manufacturing method is realized by printing solder paste on the electrodes 31 and 33 of the first and third wiring boards 11 and 13, mounting the electronic component 70, and then heating to melt and cool the solder. it can. Here, the gap between the electronic component 70 and the first wiring board 11 may be filled with resin.

図３（ｂ）は、第１と第３の配線板１１と１３上に未硬化の樹脂接着剤５０ａを配置し、開口部２２を設けた第２の配線板１２を位置合わせした状態を示す。   FIG. 3B shows a state in which the uncured resin adhesive 50a is disposed on the first and third wiring boards 11 and 13, and the second wiring board 12 provided with the opening 22 is aligned. .

図３（ｃ）は、第１、第２、第３の配線板１１，１２，１３を加圧加熱した状態を示す。第１と第３の配線板１１、１３上のはんだバンプ４１が溶融して第２の配線板１２の電極３２と接合する。その接合と同時に樹脂接着剤５０ａを硬化させて樹脂接着層５０を形成する。加圧力は１．６〜３．０ＭＰａ、加熱温度は２００〜２５０℃の範囲で実施した。第２の配線板１２上の電極３２の材料は、銅以上にはんだに濡れ易いものを使用する。例えば、金、はんだ、すず、などの金属を用いる。特に、金ははんだとの濡れがよいため、電極３２上ではんだが広がり、接合力が向上する。また、第２の配線板１２の電極３２を第１と第３の配線板上のはんだバンプ４１よりも大きくすることで、配線板１１、１２、１３間の接合が容易になる。   FIG. 3C shows a state where the first, second and third wiring boards 11, 12 and 13 are heated under pressure. The solder bumps 41 on the first and third wiring boards 11 and 13 are melted and joined to the electrodes 32 of the second wiring board 12. Simultaneously with the joining, the resin adhesive 50a is cured to form the resin adhesive layer 50. The applied pressure was 1.6 to 3.0 MPa, and the heating temperature was 200 to 250 ° C. The electrode 32 on the second wiring board 12 is made of a material that is more easily wetted by solder than copper. For example, a metal such as gold, solder, or tin is used. In particular, since gold has good wettability with solder, the solder spreads on the electrode 32 and the bonding force is improved. Further, by making the electrodes 32 of the second wiring board 12 larger than the solder bumps 41 on the first and third wiring boards, the joining between the wiring boards 11, 12, 13 is facilitated.

さらに、第１、第２、第３の配線板１１、１２、１３間に配置する樹脂接着剤５０はエポキシ樹脂系を用いる。特に、エポキシ樹脂に有機酸を含有した樹脂接着剤を用いると、はんだバンプの表面酸化膜を容易に除去し、はんだ接合が歩留りよく実現できる。   Furthermore, the resin adhesive 50 disposed between the first, second, and third wiring boards 11, 12, and 13 uses an epoxy resin system. In particular, when a resin adhesive containing an organic acid in an epoxy resin is used, the surface oxide film of the solder bump can be easily removed, and solder bonding can be realized with a high yield.

実施の形態３．
図４はこの発明の実施の形態３による電子部品内蔵配線板の構造を示す断面図である。図４において、電子部品７０の電極は、第２の配線板１２上の電極にワイヤ６０を用いて接続されている。また、電子部品７０の裏面を第１の配線板１１の放熱用電極に配設した高熱伝導部材３６に接触させる。高熱伝導部材３６は、熱伝導の大きな材料、銅、すず、アルミ、黄銅などの金属で構成される。はんだを使用する場合は、はんだペーストを放熱用電極３８に印刷後焼成することで容易に実現できる。さらに簡易的には、樹脂に金属粒子を高密度（例えば８０重量パーセント以上）に混入させた導電性接着剤を用いてもよい。 Embodiment 3 FIG.
4 is a cross-sectional view showing the structure of an electronic component built-in wiring board according to Embodiment 3 of the present invention. In FIG. 4, the electrode of the electronic component 70 is connected to the electrode on the second wiring board 12 using a wire 60. Further, the back surface of the electronic component 70 is brought into contact with the high heat conductive member 36 disposed on the heat radiation electrode of the first wiring board 11. The high thermal conductive member 36 is made of a material having a large thermal conductivity, such as copper, tin, aluminum, or brass. In the case of using solder, it can be easily realized by printing the solder paste on the heat radiation electrode 38 and baking it. More simply, a conductive adhesive in which metal particles are mixed in resin at a high density (for example, 80 weight percent or more) may be used.

また、高熱伝導部材３６は、銅、黄銅などのはんだよりも熱伝導のよい金属ブロックをはんだで固定した（図示せず）ものでもよい。   Moreover, the high heat conductive member 36 may be a member (not shown) in which a metal block having a heat conductivity higher than that of solder such as copper or brass is fixed by solder.

電子部品７０に高熱伝導部材３６を接触させることにより、電子部品７０からの熱を効率よく放散することが可能になる効果がある。   By bringing the high thermal conductivity member 36 into contact with the electronic component 70, there is an effect that heat from the electronic component 70 can be efficiently dissipated.

また、電子部品７０の底面に金属膜を形成しておいて、高熱伝導部材３６とはんだなどで接合すれば、熱の放散効率をさらに向上させることができる。電子部品７０表面に形成される金属膜としては銅、ニッケル、金、すずがあげられる。   Further, if a metal film is formed on the bottom surface of the electronic component 70 and joined to the high heat conductive member 36 with solder or the like, the heat dissipation efficiency can be further improved. Examples of the metal film formed on the surface of the electronic component 70 include copper, nickel, gold, and tin.

以上のように、実施の形態３によれば、電子部品７０の表面が、配線板に形成された高熱伝導部材３６に接触または接合しているので、電子部品の熱を効率よく放散することができる。   As described above, according to the third embodiment, since the surface of the electronic component 70 is in contact with or joined to the high thermal conductive member 36 formed on the wiring board, the heat of the electronic component can be efficiently dissipated. it can.

実施の形態４．
図５はこの発明の実施の形態４による電子部品内蔵配線板の構造を示す断面図である。図５において、電子部品７０の電極は、第２の配線板１２上の電極にワイヤ６０を用いて接続されている。そして、電子部品７０と第１の配線板１１との接合部である高熱伝導部材３６および各配線板間の接合部４２の周辺を第１の樹脂５１で充填する。また、電子部品７０と第２の配線板１２の間および電子部品７０と第２の配線板１２の電気的接合部であるワイヤ６０周辺を第２の樹脂５２で充填する。 Embodiment 4 FIG.
FIG. 5 is a sectional view showing the structure of an electronic component built-in wiring board according to Embodiment 4 of the present invention. In FIG. 5, the electrode of the electronic component 70 is connected to the electrode on the second wiring board 12 using a wire 60. Then, the first resin 51 fills the periphery of the high thermal conductive member 36 that is a joint between the electronic component 70 and the first wiring board 11 and the joint 42 between the wiring boards. Further, the second resin 52 is filled between the electronic component 70 and the second wiring board 12 and around the wire 60 which is an electrical joint portion between the electronic component 70 and the second wiring board 12.

第１の樹脂５１は例えばエポキシ樹脂にシリカなどの無機フィラーを５０〜８０重量％充填したもので、ヤング率は４〜６ＧＰａ、線膨張係数は１５〜３０×１０−６１／℃である。配線板間の接合部４２並びに電子部品７０とその搭載配線板間の接合部３６の周囲を第１の樹脂５１で覆うことにより、当該接合部４２及び３６にかかる応力を低減することができ、接合の信頼性を大幅に向上することが可能になる。 The first resin 51 is, for example, an epoxy resin filled with 50 to 80% by weight of an inorganic filler such as silica, and has a Young's modulus of 4 to 6 GPa and a linear expansion coefficient of 15 to 30 × 10 −6 1 / ° C. By covering the joint portion 42 between the wiring boards and the periphery of the joint portion 36 between the electronic component 70 and the mounted wiring board with the first resin 51, the stress applied to the joint portions 42 and 36 can be reduced. It becomes possible to greatly improve the reliability of bonding.

また、電子部品７０の周辺を第２の樹脂５２、例えば、無機フィラーを含有しないか少量（３０重量％以下が望ましい）含有したエポキシ樹脂またはシリコーン樹脂を用いる。第２の樹脂５２で電子部品７０周辺を覆うことにより、機械的な変形および熱膨張により積層した配線板１０と電子部品７０間で発生する応力を小さくすることができ、電子部品７０が破損することを防止することができる。また、第２の樹脂５２は、第１の樹脂５１よりも無機フィラーの含有量が少ないため、軟らかい。   Further, a second resin 52 such as an epoxy resin or a silicone resin containing no inorganic filler or a small amount (preferably 30 wt% or less) is used around the electronic component 70. By covering the periphery of the electronic component 70 with the second resin 52, the stress generated between the wiring board 10 and the electronic component 70 laminated by mechanical deformation and thermal expansion can be reduced, and the electronic component 70 is damaged. This can be prevented. Further, the second resin 52 is softer because it contains less inorganic filler than the first resin 51.

図５では、電子部品７０の電極と第２の配線板１２の電極とをワイヤ６０を用いて接続し、ワイヤ６０の周辺を第２の樹脂５２で充填している例を示したが、電子部品７０の電極と第２の配線板１２の電極とをポリイミドフィルム上にリード電極を形成したＴＡＢ（Ｔａｐｅ Ａｕｔｏｍａｔｅｄ Ｂｏｎｄｉｎｇ）フィルムを用いて接続し、ＴＡＢフィルムのリード電極周辺を第２の樹脂５２で充填しても良い。   FIG. 5 shows an example in which the electrode of the electronic component 70 and the electrode of the second wiring board 12 are connected using the wire 60 and the periphery of the wire 60 is filled with the second resin 52. The electrode of the component 70 and the electrode of the second wiring board 12 are connected using a TAB (Tape Automated Bonding) film in which a lead electrode is formed on a polyimide film, and the periphery of the lead electrode of the TAB film is connected with the second resin 52. It may be filled.

また、図９に示すように、電子部品７０の電極と第１の配線板１１の電極との間をワイヤ６０を用いて接続し、電子部品７０と第２の配線板１２の間および電子部品７０と第１の配線板１１の電気的接合部であるワイヤ６０の周辺を第２の樹脂５２で充填しても良い。   Further, as shown in FIG. 9, the electrodes of the electronic component 70 and the electrodes of the first wiring board 11 are connected using the wire 60, and the electronic component 70 and the second wiring board 12 are connected. The second resin 52 may be filled around the wire 60 that is an electrical joint between the first wiring board 11 and the first wiring board 11.

以上のように、実施の形態４において、配線板間に充填された樹脂は２種類で構成され、配線板間の接合部に充填された第１の樹脂は、内層の第２の配線板開口部と電子部品間に充填された第２の樹脂よりも硬くする。すなわち、配線板間のはんだ接合部には硬い樹脂が充填されることで、はんだのひずみを小さくし、一方、電子部品と配線板間の樹脂を軟らかくすることで、高温と低温を繰り返す環境において、電子部品の破損を防止することができる。   As described above, in the fourth embodiment, the resin filled between the wiring boards is composed of two types, and the first resin filled in the joint between the wiring boards is the second wiring board opening in the inner layer. Harder than the second resin filled between the part and the electronic component. In other words, the solder joint between the wiring boards is filled with a hard resin to reduce solder distortion, while the resin between the electronic component and the wiring board is softened in an environment where high and low temperatures are repeated. Damage to electronic components can be prevented.

実施の形態５．
実施の形態５では、実施の形態４（図５）に示す電子部品内蔵配線板の製造方法について説明する。図６は本実施の形態による電子部品内蔵配線板の製造方法を示す断面図である。 Embodiment 5 FIG.
In the fifth embodiment, a manufacturing method of the electronic component built-in wiring board shown in the fourth embodiment (FIG. 5) will be described. FIG. 6 is a cross-sectional view showing a method for manufacturing an electronic component built-in wiring board according to the present embodiment.

図６（ａ）は、第１と第３の配線板１１、１３の電極３１、３３上に接合用のはんだバンプ４１を形成した状態を示す。特に、電子部品７０と接合するはんだバンプは突起状に大きく形成され、高熱伝導材料３６により構成される。   FIG. 6A shows a state in which solder bumps 41 for bonding are formed on the electrodes 31 and 33 of the first and third wiring boards 11 and 13. In particular, the solder bumps to be joined to the electronic component 70 are formed in a protruding shape and are made of the high heat conductive material 36.

図６（ｂ）では、第２の配線板１２の開口部２２に電子部品７０を配置し、電子部品７０の電極３４と第２の配線板１２上の電極３２とをワイヤ６０で接合する。そして、第２の樹脂材料５２により電子部品７０と第２の配線板１２間およびワイヤ６０の周辺を埋める。第２の樹脂材料５２は、例えば無機フィラーを含有しないか少量（３０重量％以下が望ましい）含有したエポキシ樹脂またはシリコーン樹脂を用いる。   In FIG. 6B, the electronic component 70 is disposed in the opening 22 of the second wiring board 12, and the electrode 34 of the electronic component 70 and the electrode 32 on the second wiring board 12 are joined by the wire 60. Then, the space between the electronic component 70 and the second wiring board 12 and the periphery of the wire 60 are filled with the second resin material 52. As the second resin material 52, for example, an epoxy resin or a silicone resin containing no inorganic filler or a small amount (preferably 30% by weight or less) is used.

図６（ｃ）は、第１および第３の配線板１１、１３上に未硬化の第１の樹脂材料５１ａを配置し、各配線板の位置合わせを実施した状態を示す。第１の樹脂材料は、例えばエポキシ樹脂にシリカなどの無機フィラーを５０〜８０重量％充填したもので、ヤング率は４〜６ＧＰａ、線膨張係数は１５〜３０×１０−６１／℃である。ここで、第１の樹脂材料に、エポキシ樹脂に有機酸を含有した樹脂接着剤を用いると、はんだバンプの表面酸化膜を容易に除去し、はんだ接合が歩留まりよく実現できる。 FIG. 6C shows a state in which the uncured first resin material 51 a is disposed on the first and third wiring boards 11 and 13 and the respective wiring boards are aligned. The first resin material is, for example, an epoxy resin filled with 50 to 80% by weight of an inorganic filler such as silica, and has a Young's modulus of 4 to 6 GPa and a linear expansion coefficient of 15 to 30 × 10 −6 1 / ° C. . Here, when a resin adhesive containing an organic acid in an epoxy resin is used as the first resin material, the surface oxide film of the solder bump can be easily removed, and solder bonding can be realized with a high yield.

図６（ｄ）は、それぞれ配線板１１，１２，１３を加圧・加熱した状態を示す。配線板上の電極３１、３２、３３は、はんだで接合されると同時に未硬化の第１の樹脂材料５１ａを硬化させて第１の樹脂５１を形成する。加圧力は１．６〜３．０ＭＰａ、加熱温度は２００〜２５０℃の範囲で実施した。第２の配線板１２上の電極３２材料は、銅、はんだ、金、スズなどの金属を用いることができる。特に、金ははんだとの濡れがよいため、接合時にはんだバンプ４１のはんだが電極３２上にひろがり、はんだの接合力を大きくすることができる。また、第２の配線板１２の電極３２を第１と第３の配線板１１と１３上のはんだバンプ４１径よりも大きくすることにより、接合時にはんだが広がり、接合の信頼性が向上する。   FIG. 6D shows a state in which the wiring boards 11, 12, and 13 are pressurized and heated, respectively. The electrodes 31, 32, and 33 on the wiring board are bonded with solder and simultaneously cure the uncured first resin material 51 a to form the first resin 51. The applied pressure was 1.6 to 3.0 MPa, and the heating temperature was 200 to 250 ° C. The electrode 32 material on the second wiring board 12 can use metals such as copper, solder, gold, and tin. In particular, since gold has good wettability with solder, the solder of the solder bump 41 spreads on the electrode 32 at the time of joining, and the joining force of the solder can be increased. Further, by making the electrode 32 of the second wiring board 12 larger than the diameter of the solder bump 41 on the first and third wiring boards 11 and 13, the solder spreads during the joining, and the joining reliability is improved.

実施の形態６．
図７はこの発明の実施の形態６による電子部品内蔵配線板の構造を示す断面図である。本実施の形態においては、第１と第２と第３の配線板１１と１２と１３の接合側の面には絶縁樹脂層５３が形成されている。絶縁樹脂層５３の材料として、例えば、エポキシ樹脂、アクリル変性エポキシ樹脂、シリコーン樹脂などを使用する。厚さは１０〜５０μｍでヤング率は０．５ＧＰａから３．０ＧＰａ、線膨張係数は５０〜７０×１０−６ １／℃、が良い。 Embodiment 6 FIG.
7 is a sectional view showing the structure of an electronic component built-in wiring board according to Embodiment 6 of the present invention. In the present embodiment, an insulating resin layer 53 is formed on the bonding side surface of the first, second and third wiring boards 11, 12 and 13. As a material of the insulating resin layer 53, for example, an epoxy resin, an acrylic modified epoxy resin, a silicone resin, or the like is used. It is preferable that the thickness is 10 to 50 μm, the Young's modulus is 0.5 GPa to 3.0 GPa, and the linear expansion coefficient is 50 to 70 × 10 −6 1 / ° C.

絶縁樹脂層５３は第１の樹脂５１との界面および配線板１１，１２，１３との界面での応力緩和に用いる。絶縁樹脂層５３は破断までのひずみが４から５％と第１の樹脂５１よりは３倍以上と大きく、界面で剥離することを防止できるため、接着の信頼性は高くなる。   The insulating resin layer 53 is used for stress relaxation at the interface with the first resin 51 and at the interfaces with the wiring boards 11, 12, and 13. The insulating resin layer 53 has a strain up to breakage of 4 to 5%, which is three times as large as that of the first resin 51, and can prevent peeling at the interface. Therefore, the reliability of adhesion is increased.

以上のように、実施の形態６によれば、積層される各配線板の表面に絶縁樹脂層を形成し、絶縁樹脂層の材料を第１の樹脂よりも軟らかい材料としたので、配線板表面の軟らかい樹脂膜により配線板との接着強度を向上させることができる。   As described above, according to the sixth embodiment, the insulating resin layer is formed on the surface of each laminated wiring board, and the insulating resin layer is made of a material softer than the first resin. Adhesive strength with the wiring board can be improved by the soft resin film.

実施の形態７．
実施の形態７では、実施の形態６（図７）に示す電子部品内蔵配線板の製造方法について説明する。図８は本実施の形態による電子部品内蔵配線板の製造方法を示す断面図である。 Embodiment 7 FIG.
In the seventh embodiment, a manufacturing method of the electronic component built-in wiring board shown in the sixth embodiment (FIG. 7) will be described. FIG. 8 is a cross-sectional view showing a method of manufacturing an electronic component built-in wiring board according to the present embodiment.

図８（ａ）において、第１と第３の配線板１１、１３の接合側の表面であって、電極３１、３３上以外の領域に絶縁樹脂層５３を形成する。絶縁樹脂層５３は、上述したように応力緩和のためのもので、例えば、エポキシ樹脂、アクリル変性エポキシ樹脂、シリコーン樹脂などを使用する。厚さは１０〜５０μｍでヤング率は０．５ＧＰａから３．０ＧＰａ、線膨張係数は５０〜７０×１０−６ １／℃、が良い。そして、第１と第３の配線板１１、１３の電極３１、３３上に接合用のはんだバンプ４１、４３を形成し、電子部品７０の電極３４をはんだバンプ４３を介して第１の配線板１１に接合する。 In FIG. 8A, an insulating resin layer 53 is formed on the surface on the joining side of the first and third wiring boards 11 and 13 and in a region other than on the electrodes 31 and 33. The insulating resin layer 53 is for stress relaxation as described above, and for example, an epoxy resin, an acrylic-modified epoxy resin, a silicone resin, or the like is used. It is preferable that the thickness is 10 to 50 μm, the Young's modulus is 0.5 GPa to 3.0 GPa, and the linear expansion coefficient is 50 to 70 × 10 −6 1 / ° C. Then, solder bumps 41 and 43 for bonding are formed on the electrodes 31 and 33 of the first and third wiring boards 11 and 13, and the electrode 34 of the electronic component 70 is connected to the first wiring board via the solder bumps 43. 11 is joined.

次に、図８（ｂ）において、第１と第３の配線板１１、１３に形成した絶縁樹脂層５３の上に未硬化の樹脂接着剤５１ａを配置する。この樹脂接着剤は、例えばエポキシ樹脂にシリカなどの無機フィラーを５０〜８０重量％充填したもので、ヤング率は４〜６ＧＰａ、線膨張係数は１５〜３０×１０−６１／℃である。そして、上記第１と第３の配線板１１，１３と、開口部２２を有する第２の配線板１２を位置合わせする。ここで、第２の配線板１２の接合側の表面には、その電極３２上以外の領域に上記絶縁樹脂層５３が形成している。 Next, in FIG. 8B, an uncured resin adhesive 51 a is disposed on the insulating resin layer 53 formed on the first and third wiring boards 11 and 13. This resin adhesive is, for example, an epoxy resin filled with 50 to 80% by weight of an inorganic filler such as silica, and has a Young's modulus of 4 to 6 GPa and a linear expansion coefficient of 15 to 30 × 10 −6 1 / ° C. Then, the first and third wiring boards 11 and 13 and the second wiring board 12 having the opening 22 are aligned. Here, the insulating resin layer 53 is formed in a region other than on the electrode 32 on the surface on the bonding side of the second wiring board 12.

次に、図８（ｃ）において、第１、第２、第３の配線板１１，１２，１３を加圧加熱した状態を示す。第１と第３の配線板１１、１３上のはんだバンプ４１が溶融して第２の配線板１２の電極３２と接合する。その接合と同時に樹脂接着剤５１ａを硬化させて樹脂を形成する。加圧力は１．６〜３．０ＭＰａ、加熱温度は２００〜２５０℃の範囲で実施した。第２の配線板１２上の電極３２の材料は、銅以上にはんだに濡れ易いものを使用する。例えば、金、はんだ、すず、などの金属を用いる。特に、金ははんだとの濡れがよいため、電極３２上ではんだが広がり、接合力が向上する。また、第２の配線板１２の電極３２を第１と第３の配線板上のはんだバンプ４１よりも大きくすることで、配線板１１、１２、１３間の接合が容易になる。   Next, in FIG.8 (c), the state which pressurized and heated the 1st, 2nd, 3rd wiring boards 11, 12, and 13 is shown. The solder bumps 41 on the first and third wiring boards 11 and 13 are melted and joined to the electrodes 32 of the second wiring board 12. Simultaneously with the joining, the resin adhesive 51a is cured to form a resin. The applied pressure was 1.6 to 3.0 MPa, and the heating temperature was 200 to 250 ° C. The electrode 32 on the second wiring board 12 is made of a material that is more easily wetted by solder than copper. For example, a metal such as gold, solder, or tin is used. In particular, since gold has good wettability with solder, the solder spreads on the electrode 32 and the bonding force is improved. Further, by making the electrodes 32 of the second wiring board 12 larger than the solder bumps 41 on the first and third wiring boards, the joining between the wiring boards 11, 12, 13 is facilitated.

なお、樹脂接着剤５１として、エポキシ樹脂に有機酸を含有した樹脂接着剤を用いても良い。それによると、はんだバンプの表面酸化膜を容易に除去し、はんだ接合が歩留りよく実現できる。   As the resin adhesive 51, a resin adhesive containing an organic acid in an epoxy resin may be used. According to this, it is possible to easily remove the surface oxide film of the solder bump and realize the solder joint with a high yield.

この発明の実施の形態１による電子部品内蔵配線板の構造を示す断面図である。It is sectional drawing which shows the structure of the electronic component built-in wiring board by Embodiment 1 of this invention. この発明の実施の形態１による電子部品内蔵配線板の他の構造を示す断面図である。It is sectional drawing which shows the other structure of the electronic component built-in wiring board by Embodiment 1 of this invention. この発明の実施の形態２による電子部品内蔵配線板の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the electronic component built-in wiring board by Embodiment 2 of this invention. この発明の実施の形態３による電子部品内蔵配線板の構造を示す断面図である。It is sectional drawing which shows the structure of the electronic component built-in wiring board by Embodiment 3 of this invention. この発明の実施の形態４による電子部品内蔵配線板の構造を示す断面図である。It is sectional drawing which shows the structure of the electronic component built-in wiring board by Embodiment 4 of this invention. この発明の実施の形態５による電子部品内蔵配線板の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the electronic component built-in wiring board by Embodiment 5 of this invention. この発明の実施の形態６による電子部品内蔵配線板の構造を示す断面図である。It is sectional drawing which shows the structure of the electronic component built-in wiring board by Embodiment 6 of this invention. この発明の実施の形態７による電子部品内蔵配線板の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the electronic component built-in wiring board by Embodiment 7 of this invention. この発明の実施の形態４による電子部品内蔵配線板の構造を示す断面図である。It is sectional drawing which shows the structure of the electronic component built-in wiring board by Embodiment 4 of this invention.

符号の説明Explanation of symbols

１０ 電子部品内蔵配線板、１１ 第１の配線板、１２ 第２の配線板、
１３ 第３の配線板、２０ 配線板の絶縁層、２１ バイア、２２ 開口部、
３０，３１，３２，３３，３４，３５ 電極、３６ 高熱伝導部材、
４１ はんだバンプ、４２ 配線板間接合部、４３ はんだバンプ、
４４ 電子部品・配線板間接合部、５０ 樹脂接着剤、５１ 第１の樹脂、
５２ 第２の樹脂、５３ 絶縁樹脂層、７０ 電子部品。 10 electronic component built-in wiring board, 11 first wiring board, 12 second wiring board,
13 Third wiring board, 20 Insulation layer of wiring board, 21 via, 22 opening,
30, 31, 32, 33, 34, 35 electrodes, 36 high thermal conductivity members,
41 Solder bump, 42 Junction between wiring boards, 43 Solder bump,
44 Electronic component / wiring board junction, 50 resin adhesive, 51 first resin,
52 second resin, 53 insulating resin layer, 70 electronic component.

Claims (11)

複数の配線板を積層するとともに当該配線板間に電子部品を収容させた電子部品内蔵配線板において、電子部品内蔵配線板の両面に配置された第１及び第３の配線板と、第１及び第３の配線板間の内層に配置された第２の配線板と、第２の配線板に形成された開口部に配置された電子部品を備え、各配線板の絶縁層はアラミド繊維またはガラス繊維に樹脂が含浸された材料で構成され、各配線板間の電極間の電気的接続をはんだ接合により行い、積層された配線板間には樹脂接着剤が充填されていることを特徴とする電子部品内蔵配線板。 In an electronic component built-in wiring board in which a plurality of wiring boards are stacked and an electronic component is accommodated between the wiring boards, first and third wiring boards disposed on both surfaces of the electronic component built-in wiring board, A second wiring board disposed in an inner layer between the third wiring boards, and an electronic component disposed in an opening formed in the second wiring board, wherein the insulating layer of each wiring board is an aramid fiber or glass It is composed of a material in which fibers are impregnated with resin, and electrical connection between electrodes between each wiring board is performed by solder bonding, and a resin adhesive is filled between the laminated wiring boards. Electronic component built-in wiring board. 上記電子部品の表面が、第１または第３の配線板に配設された高熱伝導部材に接触または接合されており、上記高熱伝導部材は導電性接着剤以上に高い熱伝導性を有することを特徴とする請求項１項に記載の電子部品内蔵配線板。 The surface of the electronic component is in contact with or bonded to a high thermal conductive member disposed on the first or third wiring board, and the high thermal conductive member has higher thermal conductivity than the conductive adhesive. The wiring board with a built-in electronic component according to claim 1. 上記配線板間に充填される樹脂は２種類により構成され、配線板間の接合部周辺に充填された第１の樹脂は、第２の配線板の開口部と電子部品間に充填された第２の樹脂より硬いことを特徴とする請求項１または請求項２に記載の電子部品内蔵配線板。 The resin filled between the wiring boards is composed of two types, and the first resin filled around the joint between the wiring boards is filled between the opening of the second wiring board and the electronic component. The wiring board with a built-in electronic component according to claim 1 or 2, wherein the wiring board is harder than the resin (2). 上記電子部品の電極と第２の配線板間の電極をワイヤまたはリード電極により接合し、当該ワイヤ又はリード電極の周辺を上記第２の樹脂により充填したことを特徴とする請求項３に記載の電子部品内蔵配線板。 The electrode between the electrode of the electronic component and the electrode between the second wiring board is joined by a wire or a lead electrode, and the periphery of the wire or the lead electrode is filled with the second resin. Electronic component built-in wiring board. 上記電子部品の電極と第１または第３の配線板間の電極をワイヤにより接合し、当該ワイヤの周辺を上記第２の樹脂により充填したことを特徴とする請求項３に記載の電子部品内蔵配線板。 4. The electronic component built-in according to claim 3, wherein an electrode between the electrode of the electronic component and an electrode between the first or third wiring board is joined with a wire, and the periphery of the wire is filled with the second resin. Wiring board. 各配線板の接合側の表面には絶縁樹脂層が形成され、この絶縁樹脂層の材料は、上記配線板間の接合部周辺に充填された樹脂よりも軟らかいことを特徴とする請求項１から請求項５のいずれか１項に記載の電子部品内蔵配線板。 An insulating resin layer is formed on the surface of each wiring board on the bonding side, and the material of the insulating resin layer is softer than the resin filled around the bonding portion between the wiring boards. The wiring board with a built-in electronic component according to claim 5. 第１または第３の配線板に電子部品を接合する工程と、第１および第３の配線板の接合面側の電極上にはんだバンプを形成する工程と、第１および第３の配線板の接合面側上に樹脂接着剤を形成する工程と、内層となる第２の配線板の開口部に電子部品が収容されるように各配線板の電極位置を合わせる工程と、複数の配線板を重ねて加熱・圧着する工程とを備えたことを特徴とする電子部品内蔵配線板の製造方法。 A step of bonding electronic components to the first or third wiring board, a step of forming solder bumps on the electrodes on the bonding surface side of the first and third wiring boards, and the first and third wiring boards. A step of forming a resin adhesive on the bonding surface side, a step of aligning the electrode positions of each wiring board so that the electronic component is accommodated in the opening of the second wiring board serving as an inner layer, and a plurality of wiring boards A method of manufacturing a wiring board with a built-in electronic component, comprising: a step of repeatedly heating and pressure bonding. 第１または第３の配線板の電極上にはんだバンプを形成する工程と、第２の配線板の開口部に電子部品を収容し、電子部品の電極と第２配線板の電極をワイヤまたはリード電極により接続する工程と、電子部品と第２の配線板間およびワイヤまたはリード電極の周辺を第２の樹脂で充填する工程と、第１および第３の配線板表面に第１の樹脂を形成する工程と、各配線板の電極位置を合わせて加熱・圧着する工程とを備え、第１の樹脂は第２の樹脂より硬いことを特徴とする電子部品内蔵配線板の製造方法。 Forming a solder bump on the electrode of the first or third wiring board; housing an electronic component in an opening of the second wiring board; and connecting the electrode of the electronic component and the electrode of the second wiring board to a wire or lead A step of connecting by an electrode, a step of filling between the electronic component and the second wiring board and the periphery of the wire or lead electrode with the second resin, and forming the first resin on the surfaces of the first and third wiring boards A method of manufacturing a wiring board with a built-in electronic component, wherein the first resin is harder than the second resin. 第１または第３の配線板の電極上にはんだバンプを形成する工程において、はんだよりも大きな熱伝導を有する高熱伝導材料からなる突起部材を形成し、電子部品と接触または接合することを特徴とする請求項８に記載の電子部品内蔵配線板の製造方法。 In the step of forming a solder bump on the electrode of the first or third wiring board, a protruding member made of a high thermal conductive material having a thermal conductivity larger than that of the solder is formed, and contacted or joined to an electronic component. The manufacturing method of the electronic component built-in wiring board of Claim 8. 第１および第３の配線板の接合面側上に樹脂接着剤を形成する工程において、第１および第３の配線板の接合面側上に絶縁樹脂層を形成した後、樹脂接着剤を形成するようにし、上記絶縁樹脂層の材料は、上記樹脂接着剤の樹脂よりも軟らかいことを特徴とする請求項７から請求項９のいずれか１項に記載の電子部品内蔵配線板の製造方法。 In the step of forming the resin adhesive on the bonding surface side of the first and third wiring boards, after forming the insulating resin layer on the bonding surface side of the first and third wiring boards, the resin adhesive is formed The method for manufacturing an electronic component built-in wiring board according to claim 7, wherein a material of the insulating resin layer is softer than a resin of the resin adhesive. 第２の配線板の電極表面は銅以上にはんだに濡れ易い材料で構成されていることを特徴とする請求項１から請求項１０のいずれか１項に記載の電子部品内蔵回路基板の製造方法。 11. The method of manufacturing a circuit board with built-in electronic components according to claim 1, wherein the electrode surface of the second wiring board is made of a material that is more easily wetted by solder than copper. .
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