CN102215639A - Semiconductor chip built-in wiring board and manufacturing method thereof - Google Patents

Semiconductor chip built-in wiring board and manufacturing method thereof Download PDF

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Publication number
CN102215639A
CN102215639A CN2011100753642A CN201110075364A CN102215639A CN 102215639 A CN102215639 A CN 102215639A CN 2011100753642 A CN2011100753642 A CN 2011100753642A CN 201110075364 A CN201110075364 A CN 201110075364A CN 102215639 A CN102215639 A CN 102215639A
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mentioned
semiconductor chip
electrode
pad
thermoplastic resin
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近藤宏司
多田和夫
大谷祐司
铃木俊夫
原田嘉治
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Denso Corp
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Denso Corp
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/06181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73259—Bump and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92222—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92224—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Abstract

The invention provides a manufacturing method for a semiconductor chip built-in wiring board, wherein the connection reliability of the semiconductor chip built-in wiring board is improved, the processing is simplified and the manufacturing time is shortened. Specifically, in a stacked step, a semiconductor chip (50) of a column-shaped bump made of Aus arranged on an electrode (51a) and a thermo-hardening resin film (21b) for forming a pad (31) via a thermoplastic resin film (22b) are arranged on opposing directions. In addition, in a pressurized heating step, the pad (31) and a pad bump (52a), the electrode (51a) and the pad bump (52a) are bonded together by solid phase diffusion so as to form the an alloy layer by Au of the pad bump (52a) and Cu of the pad (31), that is Cu-Au alloy layer (522).

Description

Built-in wiring substrate of semiconductor chip and manufacture method thereof
Technical field
The present invention relates to the built-in wiring substrate of semiconductor chip and the manufacture method thereof that are formed with wiring part on the insulating substrate of thermoplastic resin, are built-in with semiconductor chip containing.
Background technology
In the past, as containing the manufacture method that is formed with wiring part on the insulating substrate of thermoplastic resin, is built-in with the parts built-in substrate of electronic unit, known had a method of being put down in writing in the patent documentation 1 for example.
In this manufacture method, many resin films are stacked with the built-in electronic parts, thus forming duplexer, these many resin films comprise the resin film that is formed with conductive pattern from the teeth outwards, the resin film that is filled with conductive paste in through hole.
And, by duplexer is heated from pressurizeing up and down, make the thermoplastic resin that contains in the resin film softening on one side on one side, thus, make resin film bonding and integrated together mutually, and with the electronic unit sealing.In addition, will be filled in that conduction in the through hole is stuck with paste sintering and connecting portion (conductive composition) between cambium layer, the electrode and the corresponding bonding pad (パ Star De) (conductive pattern) of electronic unit is electrically connected or conductive pattern is electrically connected to each other.
Thus, the multilager base plate that is built-in with electronic unit can be formed together by pressurization, heating, manufacturing process is oversimplified.
Yet, integrated in the semiconductor chip of element (IC chip), because the increase inhibition of highly integrated, the high speed of element, the volume of semiconductor chip (being built-in with the substrate of this semiconductor chip) etc., the interval of electrode becomes more and more narrow (so-called thin space).Therefore, adopting semiconductor chip (bare chip) as built-in electronic unit, do not carrying out again distribution ground and carry out under the situation that flip-chip installs, in said method, can expect: if want to guarantee electrical insulating property between adjacent interlayer connecting portion, then must form the through hole of diameter very little (for example diameter is about a few μ m～10 μ m), it is difficult that the formation of through hole and the filling of conductive paste become.
In addition, because the loading of conductive paste is also less, so can expect: can not guarantee q.s, carry out the electroconductive particle of diffusion bond with the metal of the pad of electrode that constitutes semiconductor chip and substrate.
To this, also can consider to adopt at the flip-chip that stud bump (studbump) is set, this stud bump is connected on the pad of substrate on the electrode of semiconductor chip and install.Particularly, as record in the patent documentation 2 like that, if, then can and improve reliability of electrical connection corresponding to thin space while pass through to pressurize and heat, the Au salient point of semiconductor chip is directly engaged with the copper pad (electrode) of substrate.
On the other hand, as the technology that the connection reliability between electrode that makes semiconductor chip and the salient point improves, have disclosed in patent documentation 3, have a semiconductor packages of the joint construction between Al electrode and Au (gold) salient point.In this semiconductor packages, Al electrode for semiconductor chip (transistor chip), form the Au salient point by the ball bonding method, in this stage, the Al that the heat treatment by for example 300 ℃-2h or 250 ℃-10h will constitute the Al electrode under the Au salient point changes into the AuAl alloy.Thus, the intensity of Al electrode/Au salient point is improved.
[patent documentation 1] TOHKEMY 2007-324550 communique
[patent documentation 2] TOHKEMY 2001-60602 communique
[patent documentation 3] TOHKEMY 2000-349125 communique
But, shown in patent documentation 2, for salient point is directly engaged with pad, need the required time as pressurization, heating time.In addition, shown in patent documentation 3,, also need the required time (for example 300 ℃-2h or 250 ℃-10h) for the Al that will constitute the Al electrode changes into the AuAl alloy.Therefore, the time that spends in order to form the built-in wiring substrate of semiconductor chip is elongated.
Summary of the invention
The present invention in view of the above problems, the 1st purpose provides and a kind ofly can improve the connection reliability of semiconductor chip and make manufacturing process oversimplify, can shorten the manufacture method of the built-in wiring substrate of semiconductor chip of manufacturing time.In addition, the 2nd purpose provides a kind of built-in wiring substrate of semiconductor chip that can improve the connection reliability of semiconductor chip.
In order to achieve the above object, according to the 1st technical scheme of the present invention,
Be the manufacture method of the built-in wiring substrate of a kind of semiconductor chip, the built-in wiring substrate of this semiconductor chip is built-in with semiconductor chip, and this semiconductor chip has the 1st electrode that contains Al class material on a face, it is characterized in that,
Possess following operation:
Stacked operation, stacked the forming of many resin films that will comprise resin film that is formed with the conductive pattern that is made of Cu from the teeth outwards and the resin film that is filled with conductive paste in through hole is duplexer, so that contain the back side that the thermoplastic resin membrane of thermoplastic resin disposed and be adjacent to electrode forming surface and this electrode forming surface of semiconductor chip every 1 ground at least; And
The pressurized, heated operation, by duplexer is pressurizeed up and down while heating from stacked direction, make thermoplastic resin softening and many resin films are integrated together and with the semiconductor chip sealing, electroconductive particle in the conductive paste as sintered body, is formed the wiring part with this sintered body and conductive pattern;
In stacked operation, to on the 1st electrode, be provided with the semiconductor chip of the stud bump that constitutes by Au and constitute and be formed with the 1st film of pad as the part of conductive pattern by resin film, across as the thermoplastic resin membrane the 2nd filmily in stud bump and the opposed direction configuration of pad;
In the pressurized, heated operation, by pad is engaged by solid-state diffusion with stud bump with stud bump and the 1st electrode, form to constitute the Cu of pad and the Au that constitutes stud bump alloy-layer, be the CuAu alloy-layer, and, the whole AuAl alloyings of the Al with the thickness direction opposed position of stud bump the 1st electrode are made the 1st electrode for not containing the AuAl alloy-layer of Al.
In above-mentioned the 1st technical scheme of the present invention, stacked the forming of many resin films that will comprise the thermoplastic resin membrane is duplexer, so that the back side that the thermoplastic resin membrane disposed and be adjacent to electrode forming surface and this electrode forming surface of semiconductor chip every 1 ground at least.Thereby, by making the thermoplastic resin that the thermoplastic resin membrane contains softening by pressurized, heated, thus many resin films are integrated together, and can be at least thermoplastic resin membrane by being adjacent to semiconductor chip with the semiconductor chip sealing.In addition, by above-mentioned pressurized, heated, the electroconductive particle in the conductive paste can be formed wiring part as sintered body with conductive pattern.Therefore, manufacturing process is oversimplified.
And then, with this duplexer in the pressurized, heated operation, by pad is engaged by solid-state diffusion with stud bump with stud bump and the 1st electrode, alloy-layer between the Cu that form to constitute pad and the Au of formation stud bump, be the CuAu alloy-layer, and the Al of the 1st electrode with the thickness direction at the opposed position of stud bump on AuAl alloyings and form the AuAl alloy-layer all.Like this, by forming alloy-layer, can improve the connection reliability of semiconductor chip in the both sides of stud bump (semiconductor chip side and its opposition side).
Particularly, in the semiconductor chip side of stud bump, if the Al of the 1st electrode of semiconductor chip residual (if promptly Al remains between semiconductor chip and the stud bump), then in the environment for use of high temperature, the Au solid-state diffusion that constitutes stud bump generates Au in residual Al 5Al 2This Au 5Al 2Growth rate significantly than Au 4Al is fast, and therefore, Au is unable to catch up with in the diffusion of Au 5Al 2Generation, at Au 4Al and Au 5Al 2The Ke Kendaer of generation at the interface emptying aperture.In addition, be that crackle takes place starting point with this Ke Kendaer emptying aperture.
So, in the 1st technical scheme of the present invention, by with the Al of in the 1st electrode and the thickness direction opposed position of stud bump all the AuAl alloying form the AuAl alloy-layer, even in the environment for use of high temperature, also can prevent to constitute the Au solid-state diffusion of stud bump, so can suppress Ke Kendaer emptying aperture and crackle generation.
Like this, heat and pressure when the present invention utilizes the pressurized, heated operation of duplexer, form the alloy-layer between Cu that constitutes pad and the Au that constitutes stud bump, it is the CuAu alloy-layer, and with the whole AuAl alloyings of Al in the 1st electrode and the thickness direction opposed position of stud bump and become the AuAl alloy-layer, so, when on the Al electrode, forming the Au salient point by the ball bonding method with the Al of Al electrode AlAu alloying all, and then in the flip-chip installation procedure, make stud bump and pad become engagement state, implement the method for pressurized, heated operation then and compare, can shorten manufacturing time.In addition, this CuAu alloy-layer and AuAl alloy-layer also can pass through this pressurized, heated operation thermoplastic resin membrane's sealing.
More than, can the manufacturing process of the built-in wiring substrate of semiconductor chip be oversimplified, can shorten manufacturing time.
In addition, as many resin films, also can except the thermoplastic resin membrane, also have the thermosetting resin film that contains thermosetting resin.In the pressurized, heated operation, integrated owing to make the thermoplastic resin that constitutes the thermoplastic resin membrane soften, thus resin film is bonded to each other, so as duplexer, as long as the thermoplastic resin membrane just can every 1 ground configuration at least.
As the thermoplastic resin membrane of containing thermoplastic resin, except the 2nd film that contains thermoplastic resin, also can adopt the film that when containing thermoplastic resin, also contains inorganic material such as glass fibre.For the film that contains thermosetting resin also is same.In addition, as the 1st film, adopt that contain the film of thermoplastic resin and to contain which kind of of film of thermosetting resin can.
In addition, according to the 2nd technical scheme of the present invention, preferably, in the pressurized, heated operation, form and mainly contain Au 4The AuAl alloy-layer of Al alloy.
In addition, according to the 3rd technical scheme of the present invention, preferably, in the pressurized, heated operation, form and contain CuAu 3The CuAu alloy-layer of alloy.
In addition, according to the 4th technical scheme of the present invention, also can be, possesses following operation as the preceding operation of stacked operation: paste operation, for the substrate that comprises the 1st film, by heating and pressurization, with the 2nd film applying on the pad formation face of substrate, so that cover pad; And flip-chip installation procedure, by with heating of the temperature more than the fusing point of the thermoplastic resin that constitutes the 2nd film and pressurization, on one side the 2nd film fusion is pressed into stud bump on one side, and stud bump is crimped on the corresponding bonding pad, and the 2nd film by fusion is with sealing between semiconductor chip and the substrate.
Like this, in the preceding operation of stacked operation, will be configured to semiconductor chip by the 2nd film that the thermoplastic resin membrane constitutes and comprise between the substrate of the 1st film, with heating of the temperature more than the fusing point of thermoplastic resin and pressurization.Thereby, in during more than the fusing point of temperature being brought up to thermoplastic resin, can make the thermoplastic resin that constitutes the 2nd film have flowability, by pressurization the thermoplastic resin between stud bump and pad is moved, stud bump is in direct contact with on the pad, thereby can makes stud bump and pad become crimped status (in other words being interim engagement state).
At this moment, by heating have mobile thermoplastic resin comprise stud bump and pad connecting portion on every side with sealing between semiconductor chip and the substrate, so can guarantee electrical insulating property between each connecting portion.In addition, can improve the connection reliability at connecting portion place.
In addition, the moment that becomes crimped status at stud bump and pad finishes flip-chip installation procedure (heating and pressurizing), by the pressurized, heated that is subjected in the pressurized, heated operation, stud bump is engaged with the pad solid-state diffusion.Like this,, stud bump is engaged with the pad solid-state diffusion,, can improve the electrode of semiconductor chip and the reliability of electrical connection between the pad so compare with crimped status by heat and the pressure that utilizes the pressurized, heated operation.
In addition, in the flip-chip installation procedure, make stud bump and pad become crimped status, by heat and the pressure that utilizes the pressurized, heated operation, stud bump is engaged with the pad solid-state diffusion, so compare with the method that in the flip-chip installation procedure, stud bump is engaged, implements then the pressurized, heated operation with the pad solid-state diffusion, can shorten manufacturing time.
In addition, if before stacked operation, do not make stud bump contact on the pad, make the stud bump contact on pad and become engagement state by the pressurized, heated operation, then because the buffering effect of softening thermoplastic resin, stud bump is difficult for being pressed in the 2nd film, and the result can expect that thermoplastic resin can remain between stud bump and the pad.With respect to this, in the 4th technical scheme of the present invention,,, can make stud bump and pad become engagement state reliably so pass through the pressurized, heated of pressurized, heated operation owing to before stacked operation, make stud bump and pad become crimped status in advance.
In addition, according to the 5th technical scheme of the present invention, also can be, as the preceding operation of stacked operation and possess the flip-chip installation procedure, for the substrate that comprises the 1st film, be provided with under the state of the 2nd film of through hole being pasted with on the pad formation face in position corresponding to pad, by with heating of the temperature more than the glass branchpoint of the thermoplastic resin that constitutes the 2nd film and pressurization, make stud bump pass through hole and be crimped on the corresponding bonding pad, and with the 2nd softening film with sealing between semiconductor chip and the substrate.
Like this, before the heating and pressurizing of flip-chip installation procedure, to be located in advance on the 2nd film corresponding to the through hole of pad, thus if heat is identical, then can form at short notice between stud bump and the pad crimped status and based on the packing structure of the 2nd film.That is, can further shorten the heating and pressurizing time in the flip-chip installation procedure and the manufacturing time of the built-in wiring substrate of semiconductor chip.
In addition, if heating and pressurizing time and pressurized conditions are identical, then can guarantee crimped status between stud bump and weld zone (land) with the heat that lacks than the method for above-mentioned the 4th technical scheme.
About this through hole, also can as the 6th technical scheme of the present invention, be provided with according to each pad.Thus, the thermoplastic resin membrane is between each connecting portion between stud bump and the pad, so in the flip-chip installation procedure, softening thermoplastic resin covers connecting portion easily.That is, when through hole is set, guarantee the electrical insulating property between each connecting portion easily, improve the connection reliability at connecting portion place easily.
In addition, be under the situation of thin space at the 1st electrode of semiconductor chip, pad also is a thin space.Therefore, be difficult to form than the little through hole of pad (for example diameter 30 μ m).But the through hole of connecting portion is different with being used between cambium layer, filled conductive paste not in through hole, and in addition, this through hole is not stipulated the volume of the connecting portion that the electrode with semiconductor chip is electrically connected with pad.Thereby, for above-mentioned through hole, also can be bigger than pad, so compare the degree of freedom of hole formation with through hole higher, can be provided with according to each pad.
On the other hand, also can as the 7th technical scheme of the present invention, be provided with 1 according to a plurality of pads.Thus, compare, no matter the interval between pad (spacing) how, all forms through hole easily with the structure that 1 through hole is set according to 1 pad.In other words, be suitable for thin space.
In addition, can be as the 8th technical scheme of the present invention, as the flip-chip installation procedure, comprise following operation:, thereby will be provided with the pad formation face of the 2nd film applying of through hole to substrate by position heating and pressurization that will be different with the formation position of through hole.
Thus, set in advance through hole, and in position heating and pressurizing that will be different on substrate the time with the 2nd film applying and paste with the formation position of through hole, so that through hole can be because of the heating and pressurizing conquassation, so when being installed to semiconductor chip on the substrate, can make stud bump and pad become crimped status at short notice.
On the other hand, also can be as the 9th technical scheme of the present invention, as the flip-chip installation procedure, comprise by heating and pressurization and with the 2nd film applying the pad of substrate form face so that its cover pad after, form the operation of through hole at the 2nd film corresponding to the position of pad.
Thus, after the 2nd film applying is on substrate, forming through hole, so can form through hole with the high position precision.
In addition, also can be as the 10th technical scheme of the present invention, in stacked operation, with semiconductor chip and the 1st film under the state that separates on the opposed direction of stud bump and pad, carry out filmily across the 2nd stacked; In the pressurized, heated operation,, pad is engaged by solid-state diffusion with stud bump with stud bump and the 1st electrode while the 2nd film fusion is pressed into stud bump.
By like this, can not carry out above-mentioned before operation and make the built-in wiring substrate of semiconductor chip, so can shorten manufacturing time.
And then, also can as the 11st technical scheme of the present invention, make semiconductor chip on the back side of the electrode forming surface that is formed with the 1st electrode, have the 2nd electrode.
In addition, also can be as the 12nd technical scheme of the present invention, in stacked operation, the top layer of the direction of in duplexer and the 2nd electrode contraposition semiconductor chip, the thermal component that configuration is made of metal material, in the pressurized, heated operation, thermal component is engaged with conductive paste in the through hole that is filled in resin film.
By like this, the worker ordinal number of the built-in wiring substrate of semiconductor chip is increased and the raising thermal diffusivity.
In addition, if less than 5 μ m, then stress uprises in the pressurized, heated operation with thermoplastic resin membrane's (for example the 2nd film) of semiconductor chip sealing, might be from the surfacial spalling of semiconductor chip.So, as the 13rd technical scheme of the present invention, preferably, be more than the 5 μ m with the thermoplastic resin membrane's of semiconductor chip sealing thickness.
By like this, can suppress surfacial spalling from semiconductor chip.
In addition, as the 14th technical scheme of the present invention, preferably, thermoplastic resin membrane's (for example the 2nd film) of semiconductor chip sealing is not contained filler.
By like this, in the pressurized, heated operation, can reduce stress to semiconductor chip.
In order to reach above-mentioned the 2nd purpose, according to the 15th technical scheme of the present invention, the built-in wiring substrate of semiconductor chip is characterised in that,
Have:
Insulating substrate contains thermoplastic resin at least;
Semiconductor chip constitutes a plurality of elements, and has the 1st electrode on a face, is embedded in the insulating substrate, by the thermoplastic resin sealing of this insulating substrate;
Wiring part, be located at insulating substrate, be electrically connected with the 1st electrode of semiconductor chip, comprise: the conductive pattern that constitutes by Cu, be located at interlayer connecting portion and the connecting portion that constitutes by Au and the 1st electrode is connected with pad as the part of conductive pattern in the through hole;
The CuAu alloy-layer at connecting portion and pad at the interface, is to constitute the Au of connecting portion and the alloy-layer of the Cu that constitutes pad;
The 1st electrode with the opposed position of connecting portion, on thickness direction, constitute by the AuAl alloy-layer that does not contain Al.
Like this, at stud bump and between as the pad of the part of conductive pattern at the interface, have alloy-layer between the Cu of the Au that constitutes stud bump and formation pad, be the CuAu alloy-layer, and by make the 1st electrode for the thickness direction at the opposed position of connecting portion on do not contain the AuAl alloy-layer of Al, can improve the connection reliability of built-in semiconductor chip.
Particularly, in the semiconductor chip side of stud bump, if the residual Al that the 1st electrode of semiconductor chip arranged (if i.e. the residual Al of having between semiconductor chip and stud bump), then in the environment for use of high temperature, the Au solid-state diffusion that constitutes stud bump generates Au in residual Al 5Al 2This Au 5Al 2Growth rate significantly than Au 4Al is fast, so Au is unable to catch up with in the diffusion of Au 5Al 2Generation, at Au 4Al and Au 5Al 2Between the Ke Kendaer of generation at the interface emptying aperture.In addition, be that crackle takes place starting point with this Ke Kendaer emptying aperture.
So, in the present invention, by on the 1st electrode and the thickness direction opposed position of connecting portion with Al all the AuAl alloying form and mainly contain Au 4The AuAl alloy-layer of Al alloy even in the environment for use of high temperature, also can prevent to constitute the Au solid-state diffusion of stud bump, so can suppress Ke Kendaer emptying aperture and crackle generation.
In addition, the 1st electrode preferably mainly contains Au as the 16th technical scheme of the present invention 4The alloy of Al.
In addition, shown in the 17th technical scheme of the present invention, preferably, between connecting portion and pad, at the interface, contain CuAu as the CuAu alloy-layer 3Alloy.
In addition, shown in the 18th technical scheme of the present invention, also can be, insulating substrate by with the stacked so that thermoplastic resin membrane of containing thermoplastic resin of many resin films at least every 1 ground configuration and be adjacent to two electrode forming surfaces of semiconductor chip and with the thermoplastic resin membrane as adhesive linkage bonding forming mutually.
In addition, as built-in semiconductor chip, shown in the 19th technical scheme of the present invention, can adopt the structure that has the 2nd electrode at the back side of the electrode forming surface that is formed with the 1st electrode.In the case, the 2nd electrode is electrically connected with the interlayer connecting portion.
In addition, also can be shown in the 20th technical scheme of the present invention like that, the top layer in the direction of insulating substrate and the 2nd electrode contraposition semiconductor chip disposes the thermal component that is made of metal material, this thermal component is connected with the 2nd electrode via wiring part.
By like this, can improve thermal diffusivity.
In addition, also can be shown in the 21st technical scheme of the present invention like that, the thermoplastic resin of semiconductor chip sealing is not contained filler.
By like this, in the pressurized, heated operation, can reduce stress to semiconductor chip.Thus, can improve the reliability of semiconductor chip.
Description of drawings
Fig. 1 is the cutaway view of expression by the schematic configuration of the built-in wiring substrate of semiconductor chip of the manufacture method formation of relevant the 1st execution mode.
Fig. 2 is illustrated in cutaway view in the manufacturing process of the built-in wiring substrate of semiconductor chip shown in Figure 1, that be layered in the preparatory process of the resin film on the substrate that semiconductor chip is installed.
Fig. 3 (a)～Fig. 3 (d) is illustrated in cutaway view in the manufacturing process of the built-in wiring substrate of semiconductor chip shown in Figure 1, that the semiconductor chip flip-chip is installed to the operation on the substrate.
Fig. 4 is illustrated in the vertical view that is pasted with the state of the 2nd film in the operation shown in Figure 3, on the pad formation face of substrate.
Fig. 5 is the cutaway view of the stacked operation in the manufacturing process of the expression built-in wiring substrate of semiconductor chip shown in Figure 1.
Fig. 6 is the cutaway view of the pressurized, heated operation in the manufacturing process of the expression built-in wiring substrate of semiconductor chip shown in Figure 1.
Fig. 7 is the enlarged drawing of the connecting portion in the built-in wiring substrate of semiconductor chip shown in Figure 1.
Fig. 8 is the cross-sectional image by the connecting portion built-in wiring substrate of semiconductor chip, when stud bump forms of the manufacture method formation of relevant the 1st execution mode.
Fig. 9 is the cross-sectional image by the connecting portion after the formation operation of semiconductor unit in the built-in wiring substrate of semiconductor chip of the manufacture method formation of relevant the 1st execution mode, the built-in wiring substrate of semiconductor chip.
Figure 10 is the cross-sectional image of connecting portion in the built-in wiring substrate of semiconductor chip that forms of the manufacture method by relevant the 1st execution mode, after the pressurized, heated operation.
Figure 11 is the enlarged image of the phantom line segments XI of Figure 10.
Figure 12 is the cross-sectional image of connecting portion in the built-in wiring substrate of semiconductor chip that forms of the manufacture method by comparative example, after the pressurized, heated operation.
Figure 13 is the cross-sectional image of connecting portion in the built-in wiring substrate of semiconductor chip that forms of the manufacture method by relevant the 1st execution mode, after the pressurized, heated operation.
Figure 14 is the enlarged image of the semiconductor chip part of Figure 13.
Figure 15 be illustrated in the relevant manufacturing process of the 2nd execution mode, the semiconductor chip flip-chip is installed in the operation on the substrate, is pasting the figure of the state of the 2nd film on the pad formation face of substrate, Figure 15 (a) is a vertical view, and Figure 15 (b) is the cutaway view along the VIIB-VIIB line of Figure 15 (a).
Figure 16 is the figure of variation that the state of the 2nd film is being pasted in expression, and Figure 16 (a) is a vertical view, and Figure 16 (b) is the cutaway view along the VIIIB-VIIIB line of Figure 16 (a).
Figure 17 is the cutaway view of the schematic configuration of the built-in wiring substrate of semiconductor chip in the expression variation.
Embodiment
The present invention is when forming the built-in wiring substrate of semiconductor chip, and the semiconductor chip (the IC chip of naked state) that will be provided with stud bump through (1) is across the 2nd film that is made of thermoplastic resin and flip-chip is installed on the substrate that is made of the 1st film that is provided with pad; (2) after the installation, by as PALAP known layered manner forms wiring substrate together the time, built-in these two steps of substrate that semiconductor chip is installed, and, mainly be characterised in that connection status in these two steps, between stud bump and the pad.
Thereby the basic structure of wiring substrate and manufacture method be not so long as specify, just can suitably adopt the structure of the relevant PALAP that up to the present the applicant file an application.In addition, PALAP is the registered trade mark of the デ of Co., Ltd. Application ソ one (Denso).
(the 1st execution mode)
Below, based on accompanying drawing embodiments of the present invention are described.In addition, the thickness direction (in other words being the stacked direction of many resin films) of insulating substrate 20 is expressed as thickness direction simply, will be expressed as vertical direction simply perpendicular to the direction of this thickness direction.In addition, unless otherwise specified, so-called thickness, expression is along the thickness of thickness direction.
The built-in wiring substrate 10 of semiconductor chip shown in Figure 1 (below, be expressed as wiring substrate 10 simply), as the basic formation unit of the wiring substrate of built-in semiconductor chip and possess insulating substrate 20, be located at insulating substrate 20 conductive pattern 30 and interlayer connecting portion 40, bury the semiconductor chip 50 of the inside that promptly is built in insulating substrate 20 underground.And then wiring substrate 10 shown in Figure 1 also possesses thermal component 60 except above-mentioned basic comprising unit.The built-in wiring substrate 10 of semiconductor chip is owing to possessing such formation unit, so can also be called semiconductor device simply.
Insulating substrate 20 is made of electrical insulating material; formation unit beyond this insulating substrate 20 plays in example shown in Figure 1 as conductive pattern 30, interlayer connecting portion 40, semiconductor chip 50 and thermal component 60 are remained on the function of the base material on the assigned position, and plays semiconductor chip 50 is remained on its inner and function that protect.
This insulating substrate 20 is for mainly containing resin and containing the material of thermoplastic resin at least as this resin, the stacked and pressurized, heated by many resin films that will comprise the thermoplastic resin membrane and bonding integrated forming.The reason that contains thermoplastic resin is because when forming insulating substrate 20 together in pressurized, heated operation described later, the thermoplastic resin after high temperature resistant, softening is utilized as adhesives and material for sealing.
Therefore, as many resin films, as long as comprise the thermoplastic resin membrane so that it is provided with just passable down to few every 1 ground at stacked state.For example also the structure that includes only the thermoplastic resin membrane can be made, also the structure that when comprising the thermoplastic resin membrane, also comprises the thermosetting resin film can be made.
As the thermoplastic resin membrane, can adopt the film of the inorganic material that when containing thermoplastic resin, also contains glass fibre, aramid fiber etc. and the film that constitutes by the thermoplastic resin that does not contain organic and/or inorganic materials at least a.Equally, as the thermosetting resin film, can adopt the film that when containing thermosetting resin, also contains above-mentioned inorganic material and the film that constitutes by the thermosetting resin that does not contain organic and/or inorganic materials at least a.
The insulating substrate 20 of relevant present embodiment as shown in Figure 1,8 resin films that amount to that stack gradually thermosetting resin film 21a, thermoplastic resin membrane 22a, thermosetting resin film 21b, thermoplastic resin membrane 22b, thermosetting resin film 21c, thermoplastic resin membrane 22c, thermosetting resin film 21d, thermoplastic resin membrane 22d from one side 20a side on thickness direction form.That is, that thermoplastic resin membrane and thermosetting resin film is alternately stacked and constitute insulating substrate 20.
In addition, as thermosetting resin film 21a～21d, the film that adopts the inorganic material do not contain glass fibre etc., constitutes by thermmohardening polyimides (PI).On the other hand, as thermoplastic resin membrane 22a～22d, adopt inorganic material such as not containing glass fibre and be used for resin film inorganic filler, that constitute by polyether-ether-ketone (PEEK) 30 weight % and Polyetherimide (PEI) 70 weight % of the linear adjustment coefficient of expansion etc.
In the above-mentioned resin film, thermosetting resin film 21b is equivalent to install the substrate (the 1st film) of semiconductor chip 50, and thermoplastic resin membrane 22b is equivalent to semiconductor chip 50 and as the 2nd film of sealing between the thermosetting resin film 21b of substrate.
Conductive pattern 30 forms the conductor foil Butut, is as the wiring part use that semiconductor chip 50 is connected with external electric.And then, not only use as electric wiring part, also can be used as the heat that the action that is used for being formed in the element in the semiconductor chip 50 brings and use to the heat radiation wiring part of outside heat radiation.
On the other hand, interlayer connecting portion 40, be in resin film, with conductive paste, be filled into the through hole (through hole) that is provided with along thickness direction thus in, the electroconductive particle heating and pressurizing sintering in this conductive paste is formed.The sintered body that this interlayer connecting portion 40 is equivalent to put down in writing in the technical scheme.Layer part connecting portion 40 also is to use as the wiring part that semiconductor chip 50 is connected with external electric with conductive pattern 30.In addition, also can be used as above-mentioned heat radiation wiring part uses.
In the present embodiment, by conductive pattern 30 and interlayer connecting portion 40, constitute the electrode 51a (AuAl alloy-layer 521) of semiconductor chip 50, the wiring part that 51b is electrically connected with external connection electrode 35.In addition, conductive pattern 30 and interlayer connecting portion 40 conductive pattern 30 and interlayer connecting portion 40 in addition by constituting above-mentioned wiring part constitute pseudo electrode 51c and thermal component 60 hot linked heat radiation wiring parts with semiconductor chip 50.In addition, the 2nd electrode that the 1st electrode that electrode 51a is equivalent to put down in writing in the technical scheme, electrode 51b, 51c are equivalent to put down in writing in the technical scheme.In addition, electrode 51a explains in the back, is provided in a side of the electrode that is made of Al class material of semiconductor chip 50 before the pressurized, heated operation.But, after the pressurized, heated operation, on electrode 51a and thickness directions connecting portion 52 opposed positions, the whole Al that constitutes electrode 51a is carried out the AuAl alloying, become and mainly contain Au 4The AuAl alloy-layer 521 (with reference to Fig. 7) of Al alloy.That is, connecting portion 52 under be AuAl alloy-layer 521.In other words, be the AuAl alloy-layer 521 that does not contain the Al that constitutes electrode 51a by semiconductor chip 50 and connecting portion 52 folded positions.In addition, if at least by the folded position of semiconductor chip 50 and connecting portion 52, be that the whole AuAl of the being alloy-layers 521 with thickness directions connecting portion 52 opposed positions electrode 51a are just passable.But as shown in Figure 7, the position that the dielectric film 53 that for example is made of SiN etc. covers is residual the Al that constitutes electrode 51a.
Wiring part particularly, conductive pattern 30 forms copper (Cu) paper tinsel Butut.And, as conductive pattern 30, comprise pad 31 corresponding to the electrode 51a of semiconductor chip 50, equally corresponding to the pad 32 of electrode 51b, equally corresponding to the pad 33 of pseudo electrode 51c, the horizontal wiring part 34 that vertically extends.And then, for the external connection electrode 35 that provides with being connected of external equipment also as the part of conductive pattern 30 and included.
And each pad 31～33 is with the spacing of the pitch match of the corresponding electrode 51 of semiconductor chip 50 and be provided with.Though diagram not, in the present embodiment, electrode 51a is configured to the rectangular rings with 10 one row in 1 limit, also corresponding to the configuration of electrode 51a a plurality of pads 31 is set to rectangular ring as shown in Figure 4 corresponding to the pad 31 of electrode 51a.And each pad 31 is drawn (distribution again) by being located at the horizontal wiring part 34 in one deck to the outside of the ring of rectangular ring or inboard (in Fig. 1 illustration the outside), and is connected with interlayer connecting portion 40 as shown in Figure 1.In addition, in Fig. 4, for convenience, omit horizontal wiring part 34 and illustrate.
In addition, in the present embodiment, interlayer connecting portion 40 is made of the Ag-Sn alloy.And,, comprise the interlayer connecting portion 41 that constitutes the vertical wiring part in the wiring part and be used for pseudo electrode 51c and thermal component 60 hot linked interlayer connecting portions 42 as interlayer connecting portion 40.
And, comprise interlayer connecting portion 41 and horizontal wiring part 34, pad 31,32 and constitute wiring part.In addition, comprise interlayer connecting portion 42 and pad 33 and constitute the heat radiation wiring part.
On the interface between conductive pattern 30 that constitutes by Cu and the interlayer connecting portion 40 that constitutes by the Ag-Sn alloy, be formed with the metal diffusion layer (Cu-Sn alloy-layer) that forms of counterdiffusion mutually by Cu and Sn, thus, improved connection reliability between conductive pattern 30 and the interlayer connecting portion 40.
In addition, the pad 31 that constitutes by Cu as conductive pattern 30, with the electrode 51a that is located at semiconductor chip 50 on, constitute by gold (Au), as the interface between the connecting portion 52 of the wiring part use that semiconductor chip 50 is connected with external electric on, be formed with by Cu and Au mutually the CuAu alloy-layer 522 that forms of counterdiffusion as metal diffusion layer (preferably contain CuAu 3Alloy-layer) (with reference to Fig. 7) thus, improved the connection reliability between pad 31 and the connecting portion 52.
In addition, in the present embodiment, the inner face at the thermosetting resin film 21a on the one side 20a side top layer that forms insulating substrate 20 is formed with external connection electrode 35 as conductive pattern 30.
Semiconductor chip 50 is element such as integrated transistor, diode, resistance, capacitor and IC chips (bare chip) of forming circuit (large scale integrated circuit) on the semiconductor substrate of silicon etc.On the surface of this semiconductor chip 50, for the outside between be connected with and be formed with electrode 51, comprise the electrode that connects above-mentioned wiring part at least as this electrode 51.In addition, semiconductor chip 50 is by above-mentioned insulating substrate 20 sealing.
In the present embodiment, as shown in Figure 1, be formed with AuAl alloy-layer 521, the electrode 51b that is electrically connected with foregoing circuit and be not connected, do not provide the pseudo electrode 51c that is electrically connected function with foregoing circuit.
In the one side side of semiconductor chip 50, the Al of the electrode 51a by semiconductor chip 50 and constitute solid-state diffusion between the Au of connecting portion 52, forming a plurality of (mainly is Au by the Au-Al alloy 4The Al alloy) constitutes, do not contain the AuAl alloy-layer 521 of aluminium (Al) with the metal monomer.That is, this AuAl alloy-layer 521 is with the electrode 51a alloying of the semiconductor chip before the pressurized, heated operation 50, is equivalent to the electrode (the 1st electrode) of the semiconductor chip 50 after the pressurized, heated operation.Thus, on this AuAl alloy-layer 521, connecting the connecting portion 52 that constitutes by Au respectively.AuAl alloy-layer 521 before the pressurized, heated operation described later be do not contain Au, by the electrode 51a that Al class material constitutes, by the solid-state diffusion of the Au in the pressurized, heated operation to Al, all Al and Au chemical combination become the structure that does not contain Al with the metal monomer.In addition, the element (being Au here) that constitutes connecting portion 52 (the stud bump 52a before the pressurized, heated operation) adopts the fusing point element higher than the fusing point of thermoplastic resin.
On the composition surface under the connecting portion 52 (interface), if in AuAl alloy-layer 521, Al (if the Al of electrode 51a is promptly arranged with monomer residue) is arranged on the interface between this semiconductor chip 50 and the stud bump 52a (connecting portion 52) with monomer residue, then in the environment for use of high temperature, the Au solid-state diffusion of connecting portion 52 generates Au in the Al of electrode 51a 5Al 2This Au 5Al 2Growth rate and Au 4Al compares fast significantly, and therefore, Au is unable to catch up with in the diffusion of Au 5Al 2Generation, (Au for example between semiconductor chip 50 and junction surface 52 5Al 2With Au 4Between the Al) generation Ke Kendaer emptying aperture (the emptying aperture B1 of Figure 12).In addition, be that starting point cracks with the Ke Kendaer emptying aperture.
With respect to this, in the present embodiment, AuAl alloy-layer 521 does not contain Al with the metal monomer, and mainly contains the Au as the end product of Au-Al alloy 4The Al alloy.Thereby, even under the environment for use of high temperature, also can suppress Ke Kendaer emptying aperture and crackle and take place.Thereby the built-in wiring substrate 10 of semiconductor chip that produces by manufacture method of the present invention is suitable for being configured in enging cabin of vehicle etc., environment for use is electronic installation of high temperature etc.
In addition, the spacing (at interval) between electrode 51a (AuAl alloy-layer 521) is narrower than the spacing of the electrode on the face of the opposition side that is formed on semiconductor chip 50 (51b, 51c).Particularly, be tens μ m spacings (for example 60 μ m spacings).
On the other hand, forming on the face of face opposition side of semiconductor chip 50, be formed with the electrode 51b and the pseudo electrode 51c that constitute by Ni class material respectively with electrode 51a.On these electrodes 51b, 51c, as with corresponding bonding pad 32,33 between connecting portion and be connected interlayer connecting portion 41,42 respectively.On the interface between the electrode 51b, the 51c that constitute by Ni and the interlayer connecting portion 41,42 that constitutes by the Ag-Sn alloy, be formed with the metal diffusion layer (Ni-Sn alloy-layer) that forms of counterdiffusion mutually by Sn and Ni, thus, improved connection reliability between conductive pattern 30 and the interlayer connecting portion 40.In addition, electrode 51b, 51c for example form with the spacing of hundred μ m units.In addition, at least a element (being Sn here) that constitutes the interlayer connecting portion 41,42 be electrically connected with electrode 51b, 51c is glass branchpoint (in other words be softening point that thermoplastic resin soften) the low element of fusing point than thermoplastic resin.That is, electrode 51b, 51c and interlayer connecting portion 41,42 form metal diffusion layer by Liquid Phase Diffusion in pressurized, heated operation described later.
Like this, semiconductor chip 50 has on the two sides provides electrode 51a, the 51b that is electrically connected function, and has the pseudo electrode 51c that the electrical connection function is not provided.On the two sides, have electrode 51a, 51b and be because comprise the MOSFET of element that electric current flows along thickness direction, for example longitudinal type and IGBT, resistance etc. as element.
Thermal component 60 is made of metal materials such as Cu, is the parts of the heat brought of the action that is used for being formed in the element in the semiconductor chip 50 to the outside heat radiation.As such thermal component 60, can adopt so-called heat sink (heat sink), radiating fin etc.
In the present embodiment, adopt by Cu and constitute, have and the roughly consistent size of the one side 20b of insulating substrate 20 and the flat thermal component 60 of shape.And, connect airtight on this thermal component 60 by thermoplastic resin membrane 22d, thermal component 60 is fixed on the one side 20b of insulating substrate 20.
In addition, on thermal component 60, connecting an end of the interlayer connecting portion 42 that is formed at thermoplastic resin membrane 22d.In the present embodiment, on the interface between thermal component 60 that constitutes by Cu and the interlayer connecting portion 42 that constitutes by the Ag-Sn alloy, be formed with the metal diffusion layer (Cu-Sn alloy-layer) that forms of counterdiffusion mutually by Cu and Sn, thus, improved connection reliability between interlayer connecting portion 42 (heat radiation wiring part) and the thermal component 60.
In the present embodiment, become the heat that will be produced by semiconductor chip 50 passes to thermal component 60 by the heat radiation wiring part that is made of interlayer connecting portion 42 and pad 33 from pseudo electrode 51c structure.Therefore, improved thermal diffusivity.
In addition, in the one side 20a of insulating substrate 20 side, conductive component such as configuration electroplating film is formed with soldered ball 70 on this conductive component in the hole that one side 20a side direction forms for the bottom surface with external connection electrode 35.
Like this, in the present embodiment, semiconductor chip 50 has on the two sides provides electrode 51a, the 51b that is electrically connected function, and is provided with thermal component 60 in the one side 20b of insulating substrate 20 side, only is provided with external connection electrode 35 in the one side 20a of insulating substrate 20 side.That is, semiconductor chip 50 is double-sided electrode structures, and wiring substrate 10 is the single-side electrode structure.
Then, the manufacture method to above-mentioned wiring substrate (semiconductor device) 10 describes.In addition, record the label of corresponding interlayer connecting portion in the bracket behind the label 40a of expression conductive paste.
At first, for the duplexer pressurized, heated is formed wiring substrate 10, prepare to constitute the material of duplexer.Prepare many resin films the substrate (following table is shown semiconductor unit 80) of semiconductor chip 50 being installed and being laminated in this semiconductor unit 80 respectively.
In the present embodiment, as mentioned above,, adopt the film inorganic material do not contain glass fibre etc., that constitute by thermmohardening polyimides (PI) as thermosetting resin film 21a～21d.In the present embodiment, as an example, make the thickness of all resin film 21a～21d identical (for example 50 μ m).
On the other hand, as thermoplastic resin membrane 22a～22d, adopt inorganic material such as not containing glass fibre and be used for resin film inorganic filler, that constitute by polyether-ether-ketone (PEEK) 30 weight % and Polyetherimide (PEI) 70 weight % of the linear adjustment coefficient of expansion etc.In the present embodiment, as an example, making resin film 22a, 22c, 22d is identical thickness (for example 80 μ m), makes as the thermoplastic resin membrane 22b of the 2nd film to than above-mentioned resin film 22a, thickness (for example 50 μ m) that 22c, 22d are thin.
In this preparatory process, by as the known layered manner together of PALAP, as known, stacked together before, the resin film that constitutes insulating substrate 20 is formed conductive pattern 30, will be filled in the through hole by the conductive paste 40a that sintering becomes interlayer connecting portion 40.The configuration of the through hole of conductive pattern 30 and filled conductive paste 40a is according to above-mentioned wiring part and heat radiation wiring part and suitably decision.
Conductive pattern 30 can be by will sticking on resin film the conductor foil Butut on surface form.As many resin films that constitute insulating substrate 20, as long as comprise that the resin film with conductive pattern 30 is just passable, structure or a part of resin film that for example can adopt all resin films all to have conductive pattern 30 do not have the structure of conductive pattern 30.In addition, as resin film, only adopt in the resin film that has conductive pattern 30 on the resin film that has conductive pattern 30 on the single face, the two sides which kind of can at stacked direction with conductive pattern 30.
On the other hand, conductive paste 40a can be by adding ethyl cellulose resin and acrylic resin etc., under the state that has added organic solvents such as terpinol its mixing obtained in order to give conformality in electroconductive particle.And (charcoal acid ガ ス レ one ザ) waits the through hole that forms the perforation resin film by carbonic acid gas laser, by silk screen printing etc. conductive paste 40a is filled in the through hole.Through hole can be that the bottom surface forms with above-mentioned conductive pattern 30 both, also can form through hole in the position that does not have conductive pattern 30.
Forming under the situation of through hole on the conductive pattern 30, because conductive pattern 30 is the end, so conductive paste 40a can be stayed in the through hole.On the other hand, though at the resin film that does not have conductive pattern 30 or have conductive pattern 30 but form in the position different under the situation of through hole with the formation position of conductive pattern 30, for conductive paste 40a being stayed in the through hole that does not have the end, use the conductive paste 40a of record in Japanese Patent Application 2008-296074 number of the applicant.In addition, as the device (method) of filling this conductive paste 40a, can adopt the device (method) of record in Japanese Patent Application 2009-75034 number of the applicant.
This conductive paste 40a to electroconductive particle added with the temperature lower than the sintering temperature of electroconductive particle decompose or volatilization and lower than this temperature and be molten condition under the high temperature than room temperature, at room temperature be the low melting point room temperature hard resin of solid state.As low melting point room temperature hard resin, paraffin is for example arranged.Thus, by when filling, heating, low melting point room temperature hard resin fusion and become pasty state, in the cooling after filling, thereby solidifying conductive paste 40a by low melting point room temperature hard resin also solidifies, and can remain in the through hole.In addition, when filling, as long as stop up just passable with smooth parts an end of through hole.
At first, the preparatory process to 6 resin film 21a, 21c being laminated to semiconductor unit 80,21d, 22a, 22c, 22d describes.
In the present embodiment, as shown in Figure 2, only, prepare to be pasted with on the single face film of Copper Foil (for example thickness 18 μ m), the Copper Foil Butut is formed conductive pattern 30 respectively for thermosetting resin film 21a, 21c, 21d among 6 resin film 21a, 21c, 21d, 22a, 22c, the 22d.In addition,, also only thermosetting resin film 21b is prepared to be pasted with the film of Copper Foil (for example thickness 18 μ m) on single face, this Copper Foil Butut is formed conductive pattern 30 about constituting all the other two resin film 21b, 22b of semiconductor unit 80.
That is, thermosetting resin film 21a～21d is for having the structure of conductive pattern 30 on single face, and thermoplastic resin membrane 22a～22d is not for having the structure of conductive pattern 30.
In addition, in 6 resin film 21a, 21c, 21d, 22a, 22c, 22d, except having external connection electrode 35 and constitute on 5 resin film 21c, 21d the thermosetting resin film 21a on one side 20a side top layer of insulating substrate 20,22a, 22c, the 22d at single face (being inner face under the stacked state) as conductive pattern 30, form through hole (label slightly) respectively, filled conductive paste 40a in this through hole.And, after filling, in drying process, make solvent evaporates.
In the present embodiment, owing to only on thermosetting resin film 21a, 21c, 21d, form conductive pattern 30, so, adopt as electroconductive particle and contain Ag particle and Sn particle and be added with the conductive paste 40a of low melting point room temperature hard resin such as paraffin as described above with the ratio of regulation for thermoplastic resin membrane 22a, the 22c, the 22d that do not form conductive pattern 30.
For thermosetting resin film 21a, 21c, 21d, both can adopt and thermoplastic resin membrane 22a, 22c, conductive paste 40a that 22d is identical, and also can adopt as electroconductive particle and contain Ag particle and Sn particle and do not contain the conductive paste 40a of low melting point room temperature hard resin with the ratio of regulation.
And then, in this preparatory process, because duplexer has the cavity of accommodating semiconductor chip 50, so on the part of many resin films, be pre-formed blank part.In the present embodiment, on thermosetting resin film 21c, form the blank part 23 that is used for accommodating semiconductor chip 50.Therefore, the rectangular frame shape of thermosetting resin film 21c that has blank part 23.
Blank part 23 can form by the irradiation of machinings such as die-cut or lead plug, laser, with respect to the volume of semiconductor chip 50 and leave the surplus of regulation and form.As the formation of blank part 23 constantly, be before the formation of conductive pattern 30 and interlayer connecting portion 40, can after forming.
In addition, with the preparatory process of above-mentioned resin film 21a, 21c, 21d, 22a, 22c, 22d concurrently, implement the formation operation (preceding operation) of semiconductor unit 80.
At first, prepare to comprise the 1st film at least, be configured to install semiconductor chip 50 substrate resin film and with the 2nd film of sealing between substrate and the semiconductor chip 50.
In the present embodiment, shown in Fig. 3 (a), prepare as the thermosetting resin film 21b of the 1st film that forms substrate with as the thermoplastic resin membrane 22b of the 2nd film.For thermosetting resin film 21b, prepare on single face, to be pasted with the structure of Copper Foil, this Copper Foil Butut is formed conductive pattern 30.At this moment, as conductive pattern 30, also form pad 31.
Then,, thermoplastic resin membrane 22b is sticked on the pad formation face of substrate, so that it covers pad 31 by heating and pressurizing.
In the present embodiment, as Fig. 3 (b) and shown in Figure 4, with thermoplastic resin membrane 22b thermo-compressed on pad formation face, so that it covers pad 31 as the thermosetting resin film 21b of substrate.The lift-launch zone 24 of the region representation semiconductor chip of in Fig. 4, representing in addition, 50 with double dot dash line.
Particularly, by heating so that the temperature of thermoplastic resin membrane 22b become more than the glass branchpoint of the thermoplastic resin that constitutes this film 22b, below the fusing point and to the pressurization of thermosetting resin film 21b side, thereby softening thermoplastic resin is connected airtight on the surface of the weld zone of thermosetting resin film 21b (land) formation face and conductive pattern 30.
With after thermoplastic resin membrane 22b thermo-compressed is on thermosetting resin film 21b, in resin film 21b, 22b, be that the bottom surface forms through hole, and for through hole with conductive pattern 30, filled conductive paste 40a like that shown in Fig. 3 (b).Here and since all with conductive pattern 30 as the bottom surface, so, both can adopt the conductive paste that does not contain low melting point room temperature hard resin, also can adopt the conductive paste that contains low melting point room temperature hard resin as conductive paste 40a.
Then, semiconductor chip 50 flip-chips of preparing in addition are installed on the substrate.
On semiconductor chip 50, on the electrode 51a of the lift-launch face of facing substrate, be formed with stud bump 52a.In the present embodiment, on the electrode 51a that constitutes by Al class material, be formed with the stud bump 52a (salient point of rivet-like) that constitutes by Au by for example using the known method of lead-in wire (wire).In addition, in this stage, as shown in Figure 8, the residual Al that electrode 51a is arranged between semiconductor chip 50 and stud bump 52a.
And shown in Fig. 3 (c), for example the thermo-compression bonding tool 100 by the PULSE HEATING mode pressurizes this semiconductor chip 50 from the rear side heating of substrate lift-launch face on one side on one side towards substrate.At this moment, with the above temperature heating of fusing point (PEEK: PEI=30: 70,330 ℃) of the thermoplastic resin that constitutes thermoplastic resin membrane 22b, and pressurize to thermosetting resin film 21b side.
Heat from thermo-compression bonding tool 100 passes to semiconductor chip 50, if the front end temperature of stud bump 52a becomes more than the fusing point of the thermoplastic resin that constitutes thermoplastic resin membrane 22b, the partial melting of the thermoplastic resin membrane 22b of stud bump 52a contact then.Thereby, while, can make its contact on corresponding bonding pad 31 by thermoplastic resin membrane 22b fusion is pressed into stud bump 52a among the thermoplastic resin membrane 22b.Thus, shown in Fig. 3 (d), can make stud bump 52a and pad 31 become crimped status.In addition, in this stage, as shown in Figure 9, the residual Al that electrode 51a is arranged between semiconductor chip 50 and stud bump 52a.
In addition, fusion, softening thermoplastic resin are under pressure and flow, and connect airtight with the substrate lift-launch face of semiconductor chip 50, pad formation face, conductive pattern 30, electrode 51a and the stud bump 52a of thermosetting resin film 21b.Thereby, shown in Fig. 3 (d), by thermoplastic resin membrane 22b, can be with sealing between semiconductor chip 50 and the thermosetting resin film 21b (substrate).Like this, form semiconductor unit 80.
In the present embodiment, the heating-up temperature when flip-chip is installed becomes than high slightly about 350 ℃ of fusing point, applies load to 1 stud bump 52a effect and be the pressure about 20～50gf.Thus, can make stud bump 52a and pad 31 become crimped status at short notice.
In addition,, then constitute the Au and the Cu counterdiffusion mutually (solid-state diffusion) that constitutes pad 31 of stud bump 52a, form metal diffusion layer (Cu-Au alloy-layer) if after becoming crimped status, also continue heating and pressurizing.In addition, the Au that constitutes stud bump 52a forms metal diffusion layer (Au-Al alloy-layer) with respect to the Al solid-state diffusion that contains among the electrode 51a.But, form such metal diffusion layer, compare with forming above-mentioned crimped status, need long-time as the heating and pressurizing time.If need on the substrate for a long time for 1 semiconductor chip 50 is installed to, then the result is, the formation time of the wiring substrate 10 of built-in semiconductor chip 50 is elongated, and manufacturing cost also increases.In addition, during this period in, the position for beyond the electrical connection section of electrode 51a, stud bump 52a, pad 31 also applies unwanted heat.Therefore, in this installation procedure, the connection status between stud bump 52a and the pad 31 is defined as crimped status.
In addition, in the present embodiment, represented after thermoplastic resin membrane 22b being sticked on the thermosetting resin film 21b, formed the example of through hole, filled conductive paste 40a.But, also can on each resin film 21b, 22b, form through hole under the state before stickup, filled conductive paste 40a.
About conductive paste 40a, both can by the heating and pressurizing when being installed to semiconductor chip 50 flip-chips on the substrate, and situation about before pasting thermoplastic resin membrane 22b, forming under stickup the time pressurized, heated, connecting portion 40 (41) with the electroconductive particle sintering and between cambium layer, also sintering and keep the original state of conductive paste 40a in the moment that forms semiconductor unit 80 not.In addition, the state that also can be sintered for a part.In the present embodiment, be conductive paste 40a under the state after flip-chip is installed.
Then, implement to form the stacked operation of duplexer.In this operation, many resin films of the resin film that will comprise the resin film that is formed with conductive pattern 30 from the teeth outwards, is filled with conductive paste 40a in through hole are stacked, so that the thermoplastic resin membrane is at least every 1 ground configuration and be adjacent to the back side of electrode forming surface and this electrode forming surface of semiconductor chip 50.
In the present embodiment, as shown in Figure 5, one distolateral from stacked direction, with the order of thermosetting resin film 21a, thermoplastic resin membrane 22a, thermosetting resin film 21b, thermoplastic resin membrane 22b, thermosetting resin film 21c, thermoplastic resin membrane 22c, thermosetting resin film 21d, thermoplastic resin membrane 22d, that many resin film 21a, 21c, 21d, 22a, 22c, 22d and semiconductor unit 80 is stacked.Like this, in the present embodiment, carry out stacked so that thermoplastic resin membrane 22a～22d and thermosetting resin film 21a～21d are alternately configuration.
And then, stacked thermal component 60 on thermoplastic resin membrane 22d.In addition, in Fig. 5, for convenience, will constitute the unit separation of duplexer and illustrate.
At length say, stacked thermoplastic resin membrane 22a on the conductive pattern formation face of thermosetting resin film 21a, on thermoplastic resin membrane 22a, with thermosetting resin film 21b as lift-launch face and stacked semiconductor unit 80.On the thermoplastic resin membrane 22b of semiconductor unit 80, semiconductor chip 50 around, be lift-launch face and stacked thermosetting resin film 21c with the face that forms the face opposition side with conductive pattern.In addition, stacked thermoplastic resin membrane 22c on thermosetting resin film 21c and semiconductor chip 50 on thermoplastic resin membrane 22c, serves as to carry the folded thermosetting resin film 21d of surface layer with conductive pattern formation face.And, thermoplastic resin membrane 22d is layered on the thermosetting resin film 21d, stacked again thermal component 60 forms 1 duplexer.
In this duplexer, on stacked direction, the resin film that is adjacent to semiconductor chip 50 is thermoplastic resin membrane 22b, 22c.At least these resin films 22b, 22c play the function with sealing around the semiconductor chip 50 in the pressurized, heated operation.In the present embodiment, the resin film that surrounds semiconductor chip 50 in vertical direction is thermosetting resin film 21c, so above-mentioned two resin film 22b, 22c play the function with sealing around the semiconductor chip 50.
Like this, as thermoplastic resin membrane 22b, 22c, preferably adopt and not only in the thermoplastic resin membrane, do not contain the inorganic material of glass fibre and aramid fiber etc., also do not contain and be used for the resin film of inorganic filler (filler) of the linear adjustment coefficient of expansion and fusing point semiconductor chip 50 sealing.By like this, can being suppressed on the semiconductor chip 50 partly in the pressurized, heated operation, effect has stress.
But, if adopt not contain and be used for thermoplastic resin membrane 22b, the 22c of inorganic filler of the linear adjustment coefficient of expansion and fusing point, then and the linear expansion coefficient difference between the semiconductor chip 50 become big with do not have inorganic filler to measure accordingly, can expect following its stress to increase.Thereby, in order to reduce stress, can adopt lower (for example 10GPa the is following) resin film of spring rate as thermoplastic resin membrane 22b, 22c.
In addition, as thermoplastic resin membrane 22b, 22c, preferably adopt the above resin film of thickness 5 μ m with semiconductor chip 50 sealing.This is because if less than 5 μ m, then in the pressurized, heated operation, the stress of these resin films 22b, 22c uprises, might be from the sur-face peeling of semiconductor chip 50.
Then, use the vacuum hotpressing machine, while the pressurized, heated operation that enforcement is pressurizeed duplexer up and down and heated from stacked direction.In this operation, make thermoplastic resin softening and many resin films are integrated together, and, the electroconductive particle among the conductive paste 40a as sintered body, is formed the wiring part with this sintered body and conductive pattern 30 semiconductor chip 50 sealing.
In the pressurized, heated operation, for resin film is integrated together and become insulating substrate 20 and make the electroconductive particle among the conductive paste 40a become sintered body, with constitute the temperature below the above fusing point of glass branchpoint of thermoplastic resin of resin film, the pressure of several Mpa keeps the stipulated time.In the present embodiment, keep 280 ℃～330 ℃ pressed temperature, the pressure of 4～5MPa more than 5 minutes (for example 10 minutes).
At first, in the pressurized, heated operation, connection partly describes to resin film.
Thermoplastic resin membrane 22a～22d every 1 configuration softens by above-mentioned heating.At this moment, owing to be under pressure, softening thermoplastic resin membrane 22a～22d connects airtight on the thermosetting resin film 21a～21d of adjacency.Thus, a plurality of resin film 21a～21d, 22a～22d are integrated together, form insulating substrate 20.At this moment, on thermal component 60, also connecting airtight the thermoplastic resin membrane 22d of adjacency, so thermal component 60 is also integrated on insulating substrate 20.
In addition, the thermoplastic resin membrane 22b, the 22c that are adjacent to semiconductor chip 50 are under pressure and flow, connect airtight the electrode 51a of semiconductor chip 50 form face and as the electrode 51b at its back side, 51c formation face on.In addition, also enter into the side of semiconductor chip 50 and the gap between the thermosetting resin film 21c,, and connect airtight on the side of semiconductor chip 50 this gap landfill.Thereby, by thermoplastic resin ( thermoplastic resin membrane 22b, 22c) with semiconductor chip 50 sealing.
Then, in the pressurized, heated operation, the connection of the electrode 51 of semiconductor chip 50, conductive pattern 30, interlayer connecting portion 40 is described.
By above-mentioned heating, the Sn among the conductive paste 40a (232 ℃ of fusing points) fusion is diffused in the Ag particle among the conductive paste 40a equally, forms Ag-Sn alloy (480 ℃ of fusing points).In addition, owing on conductive paste 40a, be applied with pressure, in through hole, form the incorporate interlayer connecting portion 40 that constitutes by alloy (41,42) by sintering.
The Sn of fusion and the also counterdiffusion mutually of Cu that constitutes conductive pattern 30 (pad 31～33).Thus, at the at the interface formation metal diffusion layer (Cu-Sn alloy-layer) of interlayer connecting portion 40 with conductive pattern 30.
The Sn of fusion also with the Ni counterdiffusion mutually of the electrode 51b, the 51c that constitute semiconductor chip 50.Thus, the metal diffusion layer of formation at the interface (Ni-Sn alloy-layer) between interlayer connecting portion 40 and electrode 51b, 51c.
In addition, constitute the Au solid-state diffusion of stud bump 52a in the Al of the electrode 51a of semiconductor chip 50.Electrode 51a is the electrode of corresponding thin space, so the amount of the Al of electrode 51a is lacked than the amount of the Au that constitutes stud bump 52a, all Al that constitute electrode 51a expended in the alloying of Au, after the pressurized, heated operation, as mentioned above, become the structure that does not contain Al with the metal monomer.In addition, the electrode 51a after the pressurized, heated (being AuAl alloy-layer 521) mainly contains Au as the Au-Al alloy 4The Al alloy.This AuAl alloy-layer 521 for example as shown in figure 10, by Au 4Al and Au 5Al 2Constitute.
In addition, in the pressurized, heated operation, even at Au 4Before generating, the Al alloy generated growth rate Au faster 5Al 2, also owing to having applied pressure, so, can suppress the generation of above-mentioned Ke Kendaer emptying aperture as Figure 10, shown in Figure 11.In addition, in Figure 11, be that to make the thickness of electrode 51a be the example of the situation of 1.0 μ m.
With respect to this, as a comparative example, the cross-sectional image of AuAl alloy-layer 521 parts of the built-in wiring substrate of semiconductor chip that the pressurization of expression nothing is made in Figure 12.By Figure 12 also as can be known, made under the situation of the built-in wiring substrate of semiconductor chip, formed emptying aperture B1 in the nothing pressurization.
And then, constitute the Cu counterdiffusion mutually of Au and the formation conductive pattern 30 (pad 31) of stud bump 52a.Thus, as shown in figure 10, on the interface between connecting portion 52 that derives from stud bump and the pad 31, form CuAu alloy-layer 522 (CuAu 3Alloy-layer).As long as the Cu-Au alloy has heating above about 250 ℃ just can generate,, can form CuAu according to above-mentioned pressurized, heated condition 3Alloy-layer.
In addition, stud bump 52a by expend the residual of the Au that engages in solid-state diffusion, become the AuAl alloy-layer 521 that will constitute by the Au-Al alloy, with constitute by Cu and on the interface, have a CuAu 3 The connecting portion 52 that the pad 31 of alloy-layer is electrically connected.Like this, in the pressurized, heated operation, can make the connection status between stud bump 52a and the pad 31 become direct engagement state.
In addition, the Cu of formation pad 31 preferably adopts the low material of Au spring rate than connecting portion 52 (stud bump 52a).By like this, the based semiconductor chip 50 and the thermal stress of the difference of the coefficient of thermal expansion of insulating substrate 20 are concentrated on the pad 31 that is made of Cu.Thus, as shown in figure 13, on pad 31, crack, can relax the thermal stress that semiconductor chip 50 is applied.Thus, as shown in figure 14, can be suppressed on the semiconductor chip 50 and crack, can suppress semiconductor chip 50 and destroy.
By more than, as shown in Figure 6, can access in insulating substrate 20, be built-in with semiconductor chip 50, semiconductor chip 50 by thermoplastic resin sealing, semiconductor chip 50 and external connection electrode 35 by wiring part be electrically connected, semiconductor chip 50 and thermal component 60 be by the hot linked substrate of heat radiation wiring parts.
And for this substrate, forming with external connection electrode 35 from the one side 20a side of insulating substrate 20 is the hole of bottom surface, behind the conductive component such as configuration electroplating film, forms soldered ball 70 on conductive component, thereby can access wiring substrate shown in Figure 1 10 in the hole.
Then, the effect to the characteristic in wiring substrate 10 shown in the above-mentioned execution mode and the manufacture method thereof describes.
In the present embodiment, when forming wiring substrate 10, many resin film 21a～21d, 22a～22d are laminated are duplexer, so that thermoplastic resin membrane 22a～22d forms the back side of face and this electrode forming surface at least every 1 ground configuration and the electrode 51a that is adjacent to semiconductor chip 50.
Thereby, by pressurized, heated, can will constitute the thermoplastic resin of thermoplastic resin membrane 22a～22d as adhesives, many resin film 21a～21d, 22a～22d are integrated together.In addition, at least can be with semiconductor chip 50 sealing by the thermoplastic resin membrane 22b, the 22c that are adjacent to semiconductor chip 50.And then, by above-mentioned pressurized, heated, can form wiring part as sintered body with conductive pattern 30 with the electroconductive particle among the conductive paste 40a.Therefore, the manufacturing process of wiring substrate 10 is oversimplified.
In addition, in the present embodiment, by this pressurized, heated operation, the Au that constitutes the Cu of pad 31 and constitute stud bump 52a is formed CuAu alloy-layer 522 by solid-state diffusion, and the Al of electrode 51a and the Au that constitutes stud bump 52a formed by solid-state diffusion do not exist as AuAl alloy-layer 521 Al of metal monomer, that constitute by the Au-Al alloy.That is, electrode 51a with the thickness direction at connecting portion 52 opposed positions on become AuAl alloy-layer 521.Therefore, in the environment for use of high temperature, also can suppress the generation of the Ke Kendaer emptying aperture that the diffusion because of Au causes.And then, AuAl alloy-layer 521 and the same operation of CuAu alloy-layer 522 usefulness (pressurized, heated operation) can be formed, and can be, thereby manufacturing process be oversimplified with AuAl alloy-layer 521 and the same operation of CuAu alloy-layer 522 usefulness (pressurized, heated operation) sealing.
By more than, according to the present invention, can improve the connection reliability of semiconductor chip and the manufacturing process of the built-in wiring substrate of semiconductor chip is oversimplified, can shorten manufacturing time.
In addition, in the present embodiment, by having AuAl alloy-layer 521 having on the interface between stud bump 52a and the pad 31 in CuAu alloy-layer 522 and at least a portion between semiconductor chip 50 and stud bump 52a, can improve the connection reliability of built-in semiconductor chip.
In addition, before the stacked operation that forms duplexer, thermoplastic resin membrane 22b is configured between semiconductor chip 50 and the substrate (thermosetting resin film 21b) heating and pressurization under the temperature more than the fusing point of thermoplastic resin.Thereby, in during more than the fusing point of temperature being brought up to thermoplastic resin, can make thermoplastic resin have flowability, by pressurization the thermoplastic resin between stud bump 52a and pad 31 is moved, stud bump 52a is in direct contact with on the pad 31, can makes stud bump 52a and pad 31 become crimped status.
At this moment, the thermoplastic resin of fusion is under pressure and flows, comprise stud bump 52a and pad 31 connecting portion around, with sealing between semiconductor chip 50 and the substrate (thermosetting resin film 21b).Thereby, can guarantee the electrical insulating property between each connecting portion.In addition, can improve the connection reliability of connecting portion.
In addition, become moment of crimped status, finish flip-chip installation procedure (heating and pressurizing),, make stud bump 52a and pad 31 become engagement state by the heating and pressurizing that in the pressurized, heated operation, is subjected at stud bump 52a and pad 31.Like this,, make stud bump 52a (connecting portion 52) and pad 31 become engagement state,, can improve the electrode 51a of semiconductor chip 50 and the reliability of electrical connection between the pad 31 so compare with crimped status by heat and the pressure that utilizes the pressurized, heated operation.
In addition, in the flip-chip installation procedure, make stud bump 52a and pad 31 become crimped status,, make stud bump 52a and pad 31 become engagement state by heat and the pressure that utilizes the pressurized, heated operation.Thereby, compare with the method that in the flip-chip installation procedure, makes stud bump 52a and pad 31 become engagement state, to implement the pressurized, heated operation then, can shorten manufacturing time.
In addition, if do not make stud bump 52a contact before the stacked operation on pad 31, make stud bump 52a contact on pad 31 and become engagement state by the pressurized, heated operation, then because the buffering effect of softening thermoplastic resin, stud bump 52a is difficult for being pressed among the thermoplastic resin membrane 22b as the 2nd film.As a result, can expect that also thermoplastic resin remains between stud bump 52a and the pad 31.
With respect to this, in the present embodiment,,, can make stud bump 52a and pad 31 become engagement state reliably so pass through the pressurized, heated of pressurized, heated operation owing to before stacked operation, make stud bump 52a and pad 31 become crimped status.
In addition, in the present embodiment, only on thermosetting resin film 21a～21d, form conductive pattern 30, on thermoplastic resin membrane 22a～22d, do not form conductive pattern 30.Thereby, even thermoplastic resin softens, is under pressure and flows in pressurized, heated operation etc., also since conductive pattern 30 be fixed on thermosetting resin film 21a～21d, so can suppress the position deviation of conductive pattern 30.Therefore, the wiring substrate 10 that is suitable for built-in semiconductor chip 50 corresponding to thin space.
In addition, on the two sides, have in the semiconductor chip 50 of electrode 51, engage if electrode 51 is carried out solid-state diffusion, then during the pressurized, heated operation in, because the solid contact is on semiconductor chip 50, so semiconductor chip 50 applied pressures (moulding pressure) are uprised.Particularly, if will be located on the two sides electrode 51 all solid-state diffusion engage, then semiconductor chip 50 applied pressures (moulding pressure) are become higher.With respect to this, in the present embodiment, one side side at semiconductor chip 50, solid-state diffusion by Au, electrode 51a is electrically connected with pad 31, on the other hand, in opposing face one side of semiconductor chip 50, the Liquid Phase Diffusion of Sn by fusion is electrically connected electrode 51b, 51c with pad 32,33.Thereby, can be by the liquid side buffering to semiconductor chip 50 applied pressures.Therefore, make a side as the solid-state diffusion of utilizing stud bump 52a and corresponding to thin space, and make and in the pressurized, heated operation, semiconductor chip 50 applied pressures are reduced, can improve the reliability of semiconductor chip 50.
In addition, in the present embodiment,, adopt the resin film of inorganic material such as not containing glass fibre, inorganic filler, so also can reduce thus in the pressurized, heated operation to semiconductor chip 50 applied pressures as thermoplastic resin membrane 22b, 22c.
(the 2nd execution mode)
In the 1st execution mode, be pressed among the thermoplastic resin membrane 22b on the pad formation face that sticks on thermosetting resin film 21b when having represented on semiconductor chip 50 flip-chips being installed to, with stud bump 52a, guarantee the example with the crimped status of pad 31 as the thermosetting resin film 21b of substrate.
With respect to this, in the present embodiment, shown in Figure 15 (a), Figure 15 (b), it is characterized in that, on the pad formation face of thermosetting resin film 21b, stick on the thermoplastic resin membrane 22b that is provided with through hole 25 corresponding to the position of pad 31, so that through hole 25 covers pad 31.
In the example shown in Figure 15 (a), Figure 15 (b), be provided with through hole 25 according to each pad 31.Thus, thermoplastic resin membrane 22b is between each connecting portion between stud bump 52a and the pad 31, so in the flip-chip installation procedure, softening thermoplastic resin covers connecting portion easily.That is, through hole 25 is set, and guarantees the electrical insulating property between each connecting portion easily, improve the connection reliability of connecting portion easily.
In addition, be under the situation of thin space at the electrode 51a of semiconductor chip 50, pad 31 also is a thin space.Thereby, be difficult to form than the little through hole 25 of pad 31 (for example diameter 30 μ m).But the through hole (through hole) of connecting portion 40 is different with being used between cambium layer, does not have filled conductive paste 40a in through hole 25, in addition, does not also stipulate the volume of the connecting portion 52 that the electrode 51a with semiconductor chip 50 is electrically connected with pad 31.Thereby, about through hole 25, also can make it bigger, so the degree of freedom that through hole forms can be provided with according to each pad 31 than through hole height than pad 31.
And heating and pressurization under the temperature more than the glass branchpoint (in other words being the softening softening point of thermoplastic resin) of the thermoplastic resin that constitutes thermoplastic resin membrane 22b are installed to semiconductor chip 50 flip-chips on the thermosetting resin film 21b.Thus, the stud bump 52a of semiconductor chip 50 is crimped on the corresponding bonding pad 31 by through hole 25, and passes through softening thermoplastic resin sealing between semiconductor chip 50 and the thermosetting resin film 21b.
Use such method, also can play and the same effect of manufacture method shown in the 1st execution mode.
In addition, according to the manufacture method shown in the present embodiment, when the crimped status between formation stud bump 52a and the pad 31, also can not make thermoplastic resin membrane 22b fusion.It is as long as just passable by sealing between thereby heating under the temperature more than the glass branchpoint of the thermoplastic resin that constitutes thermoplastic resin membrane 22b and the enough softening thermoplastic resins of pressurization energy are with semiconductor chip 50 and thermosetting resin film 21b.In other words, as long as semiconductor chip 50 thermo-compressed just can on thermoplastic resin membrane 22b.Because on the thermoplastic resin membrane 22b, before flip-chip is installed, set in advance through hole 25, can easily form crimped status so compare with the method shown in the 1st execution mode.
Thereby, if heat is identical, then can forms stud bump 52a and crimped status between the pad 31 with the time shorter and reach packing structure based on thermoplastic resin membrane 22b than the method shown in the 1st execution mode.That is, can further shorten the heating and pressurizing time in the flip-chip installation procedure and the manufacturing time of wiring substrate 10.
In addition, if heating and pressurizing time and pressurized conditions are identical, then can guarantee crimped status between stud bump 52a and the pad 31 with the heat that lacks than the method shown in the 1st execution mode.
In addition, through hole 25 both can form before thermoplastic resin membrane 22b being pasted on the thermosetting resin film 21b, also can form after stickup.In the present embodiment, after stickup, on the position on the thermoplastic resin membrane 22b, by formation through holes 25 such as carbonic acid gas laser corresponding to pad 31.If adopt such method, then can form through hole 25 in precision ground, high position.
On the other hand, the irradiation by laser before stickup etc. form under the situation of through hole 25, when pasting thermoplastic resin membrane 22b, can and paste the position heating and pressurizing different with formation position through hole 25 thermoplastic resin membrane 22b.Owing to the position heating and pressurizing different with the formation position of through hole 25 pasted, so can prevent the conquassation (obstruction) of through hole 25.Thereby, when being installed to semiconductor chip 50 on the substrate, can be so that chien shih stud bump 52a and pad 31 become crimped status in short-term.
In the present embodiment, represented to be provided with the example of through hole 25, but also can 1 through hole 25 be set according to a plurality of pads 31 according to each pad 31.For example in the example shown in Figure 16 (a), Figure 16 (b), a plurality of pads 31 are configured to the rectangular rings with 10 one row in 1 limit, and 25 pairs of each limits of through hole, promptly 10 pads 31 are provided with 1 through hole 25.That is, be the long through hole 25 of a direction in vertically.
Thus, compare, no matter the interval (spacing) of 31 of pads how, can both form through hole 25 with the structure that 1 through hole 25 is set according to per 1 pad 31 shown in Figure 15 (a), Figure 15 (b).That is, the formation degree of freedom of through hole 25 is higher, is suitable for thin space.
More than, preferred embodiment be illustrated of the present invention, but the present invention is not limited by above-mentioned execution mode at all, in the scope that does not break away from purport of the present invention, can carry out various distortion and implement.
In the above-described embodiment, adopted forming the semiconductor unit example that carries out stacked operation and pressurized, heated operation after 80s, but the present invention is not limited thereto.In stacked operation, also can semiconductor chip the 50, the 1st film (thermosetting resin film 21b) is stacked under the state that separates with the 2nd film (thermoplastic resin membrane 22b).That is, also can semiconductor chip 50 and the 1st film (thermosetting resin film 21b) is stacked under stud bump 52a and state that pad 31 separates along the direction of facing via the 2nd film (thermoplastic resin membrane 22b).That is, in stacked operation shown in Figure 5, also can in the space of configuring semiconductor unit 80, dispose thermosetting resin film 21b, thermoplastic resin membrane 22b, semiconductor chip 50 (with this in proper order) from the paper downside.And, in the pressurized, heated operation, on one side thermoplastic resin membrane 22b fusion is pressed into stud bump 52a on one side, pad 31 is engaged by solid-state diffusion with stud bump 52a with stud bump 52a and electrode 51a.By like this, can omit the operation that forms semiconductor unit 80, can shorten the manufacturing time of the built-in wiring substrate of semiconductor chip.
In addition, the structure of many resin films of formation insulating substrate 20 is not limited to above-mentioned example.The number of resin film is not limited to above-mentioned example (8).So long as number that can built-in semiconductor chip 50 is just passable.
Thermoplastic resin membrane's constituent material also is not limited to above-mentioned example.For example, if the material that is made of PEEK/PEI also can adopt and the different material of above-mentioned example ratio.In addition, also can adopt constituent material beyond the PEEK/PEI, for example liquid crystal polymer (LCP) etc.And then, also can adopt FEP (tetrafluoraoethylene-hexafluoropropylene copolymer), PFA (tetrafluoroethene-perfluoro propyl vinyl ether copolymer), PPS (polyphenylene sulfide) etc.
Thereby represented to apply the example that uses the film of inorganic material of in base material, using that does not have glass fibre, aramid fiber etc. and the inorganic filler of adding in order to regulate fusing point and linear expansion coefficient as thermoplastic resin membrane 22a～22d, but also can adopt the thermoplastic resin membrane 22a～22d that contains them for the stress that suppresses in the pressurized, heated operation to the part of semiconductor chip 50.But, as mentioned above, for thermoplastic resin membrane's (being two thermoplastic resin membrane 22b, 22c in the present embodiment) for semiconductor chip 50 sealing are used, in order to suppress to apply, preferably use the film of inorganic material of in base material, using that does not have glass fibre, aramid fiber etc. and the inorganic filler of adding in order to regulate fusing point and linear expansion coefficient to the stress of the part of semiconductor chip 50.
The constituent material of thermosetting resin film also is not limited to above-mentioned example.For example, also can adopt the film that contains the inorganic material that glass fibre, aramid fiber etc. use in base material.In addition, also can adopt thermmohardening polyimides thermosetting resin in addition.
In addition, as many resin films, also can make the structure that does not contain the thermosetting resin film and only contain the thermoplastic resin membrane.In addition, also can make thermoplastic resin membrane's number more than the thermosetting resin film, in the continuous structure of stacked state next part thermoplastic resin membrane.
In the present embodiment, the substrate of semiconductor chip 50 is installed as flip-chip, illustration as the example of the thermosetting resin film 21b of the 1st film.But, also can adopt the thermoplastic resin membrane as the 1st film.In addition, also can use many resin films that comprise the 1st film and constitute substrate.
In the present embodiment, represented thermal component 60 to be fixed on example on the one side 20b of insulating substrate 20 in order to improve thermal diffusivity.In addition, represented equally in order to improve thermal diffusivity pseudo electrode 51c to be set on the semiconductor chip 50, on pseudo electrode 51c, to connect the example of heat radiation wiring part (pad 33 and interlayer connecting portion 42).But, also can be the structure that does not have a side at least.If make the structure that thermal component 60 and a certain side of heat radiation in the wiring part are only arranged, though then poor than structure shown in Figure 1, compare with the structure which does not have and can improve thermal diffusivity.
In addition, thermal component 60 is located on whole of the one side 20b of insulating substrate 20, but also can make the structure that on the part of one side 20b, is fixed with thermal component 60, also can make the structure that on the two sides of the two sides of insulating substrate 20 20a, 20b, is fixed with thermal component 60 respectively.
In the present embodiment, represented that semiconductor chip 50 has electrode 51 on the two sides and then comprised that as electrode 51 conduct provides the example of AuAl alloy-layer 521, electrode 51b and the pseudo electrode 51c of the electrode that is electrically connected function.But, also can make structure with pseudo electrode 51c and heat radiation wiring part.In addition, as semiconductor chip 50, also can make the structure that only on one side, has electrode 51 (AuAl alloy-layer 521).At least comprise that as electrode 51 the electrode 51a that is provided with stud bump 52a gets final product.
For example semiconductor chip 50 also can be made the structure that only has pseudo electrode 51c on AuAl alloy-layer 521 as electrode, the face at opposition side having on the one side.In the case, also as described above,, then can be suppressed in the pressurized, heated operation semiconductor chip 50 applied pressures (moulding pressure) if make the Liquid Phase Diffusion that electrically connects as between pseudo electrode 51c and the pad 33.
In addition, variation as shown in figure 17 is such, and the built-in wiring substrate 10a of semiconductor chip also can be for having the structure that does not have electrode 51 on electrode 51 (AuAl alloy-layer 521), the face at opposition side in the one side side.In the case, owing on the face that electrode 51 is not set, do not connect wiring part, heat radiation wiring part, so in the pressurized, heated operation, by softening thermoplastic resin membrane 22c, compare with the structure that on the two sides, has electrode 51, can suppress semiconductor chip 50 applied pressures (moulding pressure).
In addition, the thickness of resin film, and the thickness of conductive pattern 30 also be not limited to above-mentioned example.But, on stacked direction, for be adjacent to semiconductor chip 50, with thermoplastic resin membrane 22b, the 22c of semiconductor chip 50 sealing, adopting thickness as described above is that the above structure of 5 μ m is preferred.

Claims (21)

1. the manufacture method of the built-in wiring substrate of semiconductor chip, the built-in wiring substrate of this semiconductor chip is built-in with semiconductor chip, and this semiconductor chip has the 1st electrode that contains Al class material on a face, it is characterized in that,
Possess following operation:
Stacked operation, stacked the forming of many resin films that will comprise resin film that is formed with the conductive pattern that is made of Cu from the teeth outwards and the resin film that is filled with conductive paste in through hole is duplexer, so that contain the back side that the thermoplastic resin membrane of thermoplastic resin disposed and be adjacent to electrode forming surface and this electrode forming surface of semiconductor chip every 1 ground at least; And
The pressurized, heated operation, by above-mentioned duplexer is pressurizeed up and down while heating from stacked direction, make above-mentioned thermoplastic resin softening and many above-mentioned resin films is integrated together and with above-mentioned semiconductor chip sealing, electroconductive particle in the above-mentioned conductive paste as sintered body, is formed the wiring part with this sintered body and above-mentioned conductive pattern;
In above-mentioned stacked operation, to on above-mentioned the 1st electrode, be provided with the above-mentioned semiconductor chip of the stud bump that constitutes by Au and constitute and as the part of above-mentioned conductive pattern and be formed with the 1st film of pad, across on above-mentioned stud bump and the opposed direction of above-mentioned pad, disposing filmily as the 2nd of above-mentioned thermoplastic resin membrane by above-mentioned resin film;
In above-mentioned pressurized, heated operation, by above-mentioned pad is engaged by solid-state diffusion with above-mentioned stud bump with above-mentioned stud bump and above-mentioned the 1st electrode, form to constitute the Cu of above-mentioned pad and the Au that constitutes above-mentioned stud bump alloy-layer, be the CuAu alloy-layer, and, be the AuAl alloy-layer that does not contain Al with the 1st electrode that makes with the whole AuAl alloyings of Al of the thickness direction opposed position of above-mentioned stud bump above-mentioned the 1st electrode.
2. the manufacture method of the built-in wiring substrate of semiconductor chip as claimed in claim 1 is characterized in that,
In above-mentioned pressurized, heated operation, form and mainly contain Au 4The above-mentioned AuAl alloy-layer of Al alloy.
3. the manufacture method of the built-in wiring substrate of semiconductor chip as claimed in claim 1 is characterized in that,
In above-mentioned pressurized, heated operation, form and contain CuAu 3The above-mentioned CuAu alloy-layer of alloy.
4. as the manufacture method of the built-in wiring substrate of each described semiconductor chip in the claim 1～3, it is characterized in that,
Preceding operation as above-mentioned stacked operation possesses following operation:
Paste operation, for the substrate that comprises above-mentioned the 1st film, by heating and pressurization, with above-mentioned the 2nd film applying on the pad formation face of aforesaid substrate, so that cover above-mentioned pad; And
The flip-chip installation procedure, by with heating of the temperature more than the fusing point of the thermoplastic resin that constitutes above-mentioned the 2nd film and pressurization, while above-mentioned the 2nd film fusion is pressed into above-mentioned stud bump, and above-mentioned stud bump is crimped on the corresponding above-mentioned pad, and above-mentioned the 2nd film by fusion is with sealing between above-mentioned semiconductor chip and the aforesaid substrate.
5. as the manufacture method of the built-in wiring substrate of each described semiconductor chip in the claim 1～3, it is characterized in that,
As the preceding operation of above-mentioned stacked operation and possess the flip-chip installation procedure, this flip-chip installation procedure is for the substrate that comprises above-mentioned the 1st film, be provided with under the state of above-mentioned the 2nd film of through hole being pasted with on the pad formation face in position corresponding to above-mentioned pad, by with heating of the temperature more than the glass branchpoint of the thermoplastic resin that constitutes above-mentioned the 2nd film and pressurization, make above-mentioned stud bump pass above-mentioned through hole and be crimped on the corresponding above-mentioned pad, and with above-mentioned the 2nd film that softens with sealing between above-mentioned semiconductor chip and the aforesaid substrate.
6. the manufacture method of the built-in wiring substrate of semiconductor chip as claimed in claim 5 is characterized in that,
According to each above-mentioned pad above-mentioned through hole is set.
7. the manufacture method of the built-in wiring substrate of semiconductor chip as claimed in claim 5 is characterized in that,
According to a plurality of above-mentioned pads 1 above-mentioned through hole is set.
8. the manufacture method of the built-in wiring substrate of semiconductor chip as claimed in claim 6 is characterized in that,
As above-mentioned flip-chip installation procedure, comprise following operation:, thereby will be provided with the pad formation face of the 2nd film applying of above-mentioned through hole to aforesaid substrate by position heating and pressurization that will be different with the formation position of above-mentioned through hole.
9. the manufacture method of the built-in wiring substrate of semiconductor chip as claimed in claim 6 is characterized in that,
As above-mentioned flip-chip installation procedure, comprise following operation: by heating and pressurization will above-mentioned the 2nd film applying on the pad formation face of aforesaid substrate so that after covering above-mentioned pad, at the position formation through hole corresponding to above-mentioned pad of above-mentioned the 2nd film.
10. the manufacture method of the built-in wiring substrate of semiconductor chip as claimed in claim 1 is characterized in that,
In above-mentioned stacked operation, with above-mentioned semiconductor chip and above-mentioned the 1st film under the state that separates on above-mentioned stud bump and the opposed direction of above-mentioned pad, carry out filmily across the above-mentioned the 2nd stacked;
In above-mentioned pressurized, heated operation,, above-mentioned pad is engaged by solid-state diffusion with above-mentioned stud bump with above-mentioned stud bump and above-mentioned the 1st electrode while above-mentioned the 2nd film fusion is pressed into stud bump.
11. the manufacture method as the built-in wiring substrate of each described semiconductor chip in the claim 1～3 is characterized in that,
Above-mentioned semiconductor chip has the 2nd electrode at the back side of the electrode forming surface that is formed with above-mentioned the 1st electrode.
12. the manufacture method of the built-in wiring substrate of semiconductor chip as claimed in claim 11 is characterized in that,
In above-mentioned stacked operation, the top layer of the direction of in above-mentioned duplexer and the 2nd electrode contraposition above-mentioned semiconductor chip, the thermal component that configuration is made of metal material, in above-mentioned pressurized, heated operation, above-mentioned thermal component is engaged with conductive paste in the through hole that is filled in above-mentioned resin film.
13. the manufacture method as the built-in wiring substrate of each described semiconductor chip in the claim 1～3 is characterized in that,
With the above-mentioned thermoplastic resin membrane's of above-mentioned semiconductor chip sealing thickness is more than the 5 μ m.
14. the manufacture method as the built-in wiring substrate of each described semiconductor chip in the claim 1～3 is characterized in that,
The above-mentioned thermoplastic resin membrane of above-mentioned semiconductor chip sealing is not contained filler.
15. the built-in wiring substrate of semiconductor chip is characterized in that,
Have:
Insulating substrate contains thermoplastic resin at least;
Semiconductor chip constitutes a plurality of elements, and has the 1st electrode on a face, is embedded in the above-mentioned insulating substrate, by the thermoplastic resin sealing of this insulating substrate;
Wiring part, be located at above-mentioned insulating substrate, be electrically connected with the 1st electrode of above-mentioned semiconductor chip, comprise: the conductive pattern that constitutes by Cu, be located at interlayer connecting portion and the connecting portion that constitutes by Au and above-mentioned the 1st electrode is connected with pad as the part of above-mentioned conductive pattern in the through hole;
The CuAu alloy-layer at above-mentioned connecting portion and above-mentioned pad at the interface, is to constitute the Au of above-mentioned connecting portion and the alloy-layer of the Cu that constitutes above-mentioned pad;
Above-mentioned the 1st electrode with the opposed position of above-mentioned connecting portion, on thickness direction, constitute by the AuAl alloy-layer that does not contain Al.
16. the built-in wiring substrate of semiconductor chip as claimed in claim 15 is characterized in that,
Above-mentioned the 1st electrode mainly contains Au 4The Al alloy.
17. the built-in wiring substrate of semiconductor chip as claimed in claim 16 is characterized in that,
Between above-mentioned connecting portion and above-mentioned pad, at the interface, contain CuAu as above-mentioned CuAu alloy-layer 3Alloy.
18. as the built-in wiring substrate of each described semiconductor chip in the claim 15～17, it is characterized in that,
Above-mentioned insulating substrate, by with the stacked so that thermoplastic resin membrane of containing thermoplastic resin of many resin films at least every 1 ground configuration and be adjacent to two electrode forming surfaces of above-mentioned semiconductor chip and with above-mentioned thermoplastic resin membrane as adhesive linkage bonding forming mutually.
19. as the built-in wiring substrate of each described semiconductor chip in the claim 15～17, it is characterized in that,
Above-mentioned semiconductor chip has the 2nd electrode at the back side of the electrode forming surface that is formed with above-mentioned the 1st electrode, and the 2nd electrode is electrically connected with above-mentioned interlayer connecting portion.
20. the built-in wiring substrate of semiconductor chip as claimed in claim 19 is characterized in that,
Top layer in the direction of above-mentioned insulating substrate and the 2nd electrode contraposition above-mentioned semiconductor chip disposes the thermal component that is made of metal material, and this thermal component is connected with above-mentioned the 2nd electrode via above-mentioned wiring part.
21. as the built-in wiring substrate of each described semiconductor chip in the claim 15～17, it is characterized in that,
The above-mentioned thermoplastic resin of above-mentioned semiconductor chip sealing is not contained filler.
CN2011100753642A 2010-04-02 2011-03-28 Semiconductor chip built-in wiring board and manufacturing method thereof Pending CN102215639A (en)

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