JP2010062339A - Component built-in wiring board, and method of manufacturing component built-in wiring board - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a component built-in wiring board capable of being produced at a low cost while maintaining the reliability of a flip connection and the functionality as the wiring board, and to provide a method of manufacturing the same. <P>SOLUTION: The component built-in wiring board includes: a first insulation layer; a second insulation layer laminated on the first insulation layer; a semiconductor chip having a terminal pad buried in the second insulation layer; a wiring pattern containing a mounting land for the semiconductor chip disposed in-between the first insulation layer and the second insulation layer; a soldering material for electrically connecting the terminal pad of the semiconductor chip and the mounting land of the wiring pattern, disposed in-between the terminal pad and the mounting land; and a resin disposed between the semiconductor chip and the first insulation layer, and the wiring pattern. This resin is an anisotropic conductive resin in which solder particles are dispersed, and the soldering material is generated by melting of the solder particle dispersed in the resin. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a component built-in wiring board in which components are embedded and mounted in an insulating plate, and more particularly to a component built-in wiring board in which a semiconductor chip is embedded and mounted by flip connection and a method for manufacturing the same.

  An example of a component built-in wiring board in which a semiconductor chip is embedded and mounted by flip connection is disclosed in Japanese Unexamined Patent Application Publication No. 2003-197849. If a semiconductor chip (bare chip) is flip-connected, the thickness generated by the mounting is saved to a minimum. Therefore, the flip connection is an effective method for incorporating a semiconductor element in a wiring board.

  In the flip connection, for example, an Au bump is further formed on a terminal pad formed on a semiconductor chip, and this is press-contacted to a wiring pattern formed on a wiring board via an adhesive (underfill resin). Can be made. The consideration here is the low resistance connection between the Au bump and the wiring pattern and the securing of the connection reliability. Therefore, a high degree of cleaning is required on the surface of the wiring pattern, and as a common method, an Au plating layer is also formed on the surface layer of the wiring pattern.

  Generally, when flip-connecting a semiconductor chip on the main surface of a wiring board, a protective layer such as a solder resist is formed, leaving only a portion of the wiring pattern to be connected, and then a portion to be connected An Au plating layer is formed on the substrate. As a result, Au plating, which is not inexpensive, can be applied with a minimum area.

In the case of embedding a semiconductor chip in a wiring board and flip-connecting it, there are some differences from the flip-connection of the semiconductor chip on the main surface as described above. First, there is an influence of the solder resist becoming a part of the inner insulating layer. Generally, the adhesion between the solder resist and the insulating plate material used in the wiring board is not so strong between the insulating plate materials. Therefore, when a configuration in which the solder resist as the inner layer is omitted is adopted, it is necessary to perform Au plating over a wide area, which affects the manufacturing cost. It cannot be said that the adhesion between the Au plating layer and the insulating plate material is strong, and a problem remains in this respect.
JP 2003-197849 A

  The present invention has been made in consideration of the above-described circumstances. In a component-embedded wiring board in which a semiconductor chip is embedded and mounted in an insulating plate by flip connection, and a manufacturing method thereof, the reliability of flip connection and the wiring board An object of the present invention is to provide a component built-in wiring board that can be manufactured at low cost while maintaining the functionality of the above and a method for manufacturing the same.

  In order to solve the above-described problem, a component built-in wiring board according to an aspect of the present invention includes a first insulating layer, a second insulating layer positioned in a stacked manner with respect to the first insulating layer, A semiconductor chip having a terminal pad embedded in a second insulating layer; and a mounting land for the semiconductor chip provided between the first insulating layer and the second insulating layer. A wiring pattern, a solder material sandwiched between the terminal pad of the semiconductor chip and the mounting land of the wiring pattern, and electrically connecting the terminal pad and the mounting land; and the semiconductor A resin provided between a chip and the first insulating layer and the wiring pattern, wherein the resin is an anisotropic conductive resin in which solder particles are dispersed, and the solder material is Melting of the solder particles dispersed in the resin Characterized in that it is a more resulting solder material.

  That is, the component built-in wiring board has a structure in which the semiconductor chip is embedded in the wiring board by mounting the semiconductor chip on the inner wiring pattern sandwiched between the first and second insulating layers via the solder material. have. Here, the solder material is sandwiched between the terminal pad of the semiconductor chip and the mounting land of the wiring pattern, that is, the semiconductor chip is connected to the mounting land in the form of flip connection. The solder material is formed by melting solder particles dispersed in a resin provided between the semiconductor chip, the first insulating layer, and the wiring pattern.

  According to such a structure and configuration, both the connection between the solder material and the terminal pad side of the semiconductor chip, and the connection between the solder material and the mounting land side of the wiring pattern are due to the expression of the intermetallic compound. The reliability of the connection between these is high. That is, as the terminal pads of the semiconductor chip and the mounting lands for the wiring pattern, those materials that can be connected to the solder may be selected, and it is not particularly necessary to provide Au plating on the wiring pattern. Therefore, this wiring board can be manufactured at low cost while maintaining the reliability of flip connection and the functionality as a wiring board.

  According to another aspect of the present invention, there is provided a method of manufacturing a component built-in wiring board in which a semiconductor chip having a terminal pad on the wiring pattern of a first insulating plate having a wiring pattern on at least one side is flip-connected. A step of applying an anisotropic conductive resin before curing in which solder particles are dispersed, and the semiconductor chip on the wiring pattern via the applied anisotropic conductive resin before curing. And heating the solder chips dispersed in the anisotropic conductive resin by applying pressure and heating to a predetermined temperature so as to fix the semiconductor chip to the wiring pattern, and before the curing A step of curing the anisotropic conductive resin, and the first insulating plate so as to embed the semiconductor chip fixed to the wiring pattern in a second insulating plate different from the first insulating plate. Laminated to Characterized by comprising the step of integrating said second insulating plate.

  According to still another aspect of the present invention, there is provided a method of manufacturing a component built-in wiring board, wherein a semiconductor chip having a terminal pad on the wiring pattern of a first insulating plate having a wiring pattern on at least one side is flip-connected. A step of applying an anisotropic conductive resin before curing in which solder particles are dispersed, and the semiconductor on the wiring pattern via the applied anisotropic conductive resin before curing, A step of placing a chip, and melting the solder particles dispersed in the anisotropic conductive resin by heating and heating to a first predetermined temperature so as to fix the semiconductor chip to the wiring pattern; A step of curing the anisotropic conductive resin before curing by heating to a second predetermined temperature higher than the first predetermined temperature; and a second insulating plate different from the first insulating plate Inside the wiring pattern So as to fill the fixed said semiconductor chip, characterized by comprising the step of integrating said second insulating plate in layers with the first insulating plate.

  Each of these manufacturing methods is an example of a method for manufacturing the component built-in wiring board. In the former method, the melting of the solder particles dispersed in the anisotropic conductive resin and the thermosetting of the resin are performed at a predetermined temperature, so that the setting and management of the temperature profile are easier. In the latter method, with respect to the anisotropic conductive resin, the solder particles are melted at a lower first predetermined temperature, and then the resin is thermoset at a higher second predetermined temperature. Therefore, setting and management of the temperature profile are slightly complicated, but an appropriate temperature can be set by both melting of the solder particles and thermosetting of the resin.

  According to the present invention, in a component built-in wiring board in which a semiconductor chip is embedded and mounted in an insulating plate by flip connection and a manufacturing method thereof, the reliability of flip connection and functionality as a wiring board are maintained, and low Cost is realized.

  As an embodiment of the present invention, the solder particles may be solder particles containing Sn. Solder containing Sn has many advantages in terms of functions such as melting temperature and ease of appearance of intermetallic compounds, and cost. A lead-free solder having a composition such as Sn-3Ag-0.5Cu can also be used.

  As an embodiment, the wiring pattern may include Cu as a material thereof. Cu is the most common and low cost wiring pattern. Bonding with solder material is also good.

  As an embodiment, the surface of the wiring pattern on the second insulating layer side may be a roughened surface. Such roughening is preferable because it improves the adhesion between the wiring pattern and the second insulating layer and improves the bonding reliability between the wiring pattern and the solder material.

  Further, as an embodiment, the terminal pad and the mounting land provided between the terminal pad of the semiconductor chip and the mounting land of the wiring pattern and closer to the terminal pad than the solder material. And a conductive bump that is electrically connected to each other. By providing such conductive bumps, the reliability of electrical connection between the terminal pads of the semiconductor chip and the mounting lands of the wiring pattern can be improved. That is, the presence of the bump-shaped conductive material makes it easier for the pressure applied to the mounting land to appear, contributing to the reliable generation of the joining state by the solder material.

  As an embodiment, the conductive bump can be made of Au or Cu as its material. Both have good bonding compatibility with the solder material and are preferable. If it is Au, for example, it can be formed as a stud bump by connecting a gold wire onto a terminal pad of a semiconductor chip with a bonding tool and cutting it near the base. Further, with either Au or Cu, conductive bumps can be formed on the terminal pads of the semiconductor chip, for example, by plating.

  Further, as an embodiment, the conductive bump may be solder as a material thereof, and the solder may have a melting point higher than the melting point of the solder particles. Even if solder is used as the conductive bump, it is suitable for joining this to the solder material. Here, if the melting point of the solder of the conductive bump is made higher than the melting point of the solder particle, it is possible to express only the melting of the solder particle and not to melt the solder as the conductive bump. It can be treated like a bump.

  As an embodiment as a manufacturing method, the semiconductor chip may be a semiconductor chip in which conductive bumps are formed in advance on the terminal pads. By providing such conductive bumps, the reliability of electrical connection between the terminal pads of the semiconductor chip and the mounting lands of the wiring pattern can be improved. That is, the presence of the bump-shaped conductive material makes it easier for the pressure applied to the mounting land to appear, contributing to the reliable generation of the joining state by the solder material.

  As an embodiment as a manufacturing method, the conductive bump can be made of Au or Cu as its material. Both have good bonding compatibility with the solder material and are preferable. If it is Au, for example, it can be formed as a stud bump by connecting a gold wire onto a terminal pad of a semiconductor chip with a bonding tool and cutting it near the base. In addition, either Au or Cu can be formed in a bump shape on the terminal pad of the semiconductor chip by plating.

  As an embodiment as a manufacturing method, the conductive bump may be a solder as a material thereof, and the solder may have a melting point higher than the melting point of the solder particles. Even if solder is used as the conductive bump, it is suitable for joining this to the solder material. Here, if the melting point of the solder of the conductive bump is made higher than the melting point of the solder particle, it is possible to express only the melting of the solder particle and not to melt the solder as the conductive bump. It can be treated like a bump.

  Further, as an embodiment as a manufacturing method, before applying the anisotropic conductive resin before curing in which solder particles are dispersed on the wiring pattern, a step of roughening the surface of the wiring pattern It can be further provided. Such roughening is preferable because it improves the adhesion between the wiring pattern and the second insulating layer and improves the bonding reliability between the wiring pattern and the solder material.

  Further, as an embodiment as a manufacturing method, after the semiconductor chip is fixed to the wiring pattern, the surface of the wiring pattern is integrated before the second insulating plate is integrated with the first insulating plate. The method may further include a step of roughening the top. Such roughening is preferable because it improves the adhesion between the wiring pattern and the second insulating layer.

  Based on the above, embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a cross-sectional view schematically showing a configuration of a component built-in wiring board according to an embodiment of the present invention. As shown in FIG. 1, this component built-in wiring board includes an insulating layer 11 (first insulating layer), 12, 12, 13, 14, and 15 (12, 13, 14, 15 second insulating layer). ), Wiring layer (wiring pattern) 21, 22, 23, 24, 25, 26 (= 6 layers in total), interlayer connector 31, 32, 34, 35, and through-hole conductor 33. The semiconductor chip 41, the conductive bump 42, and the anisotropic conductive resin 51 are included.

  The semiconductor chip 41 is electrically and mechanically connected to the inner wiring layer 22 via conductive bumps 42 by flip connection. For this connection, conductive bumps 42 are formed in advance on terminal pads (not shown) of the semiconductor chip 41, and the built-in component mounting lands are patterned on the wiring layer 22 in alignment with the conductive bumps 42. Is formed. The conductive bump 42 is made of, for example, Au, and is previously formed in a stud shape on the terminal pad. A resin is filled between the semiconductor chip 41 and the wiring layer 22 and the insulating layer 11 for mechanical and chemical protection of the flip connection portion. In this embodiment, an anisotropic conductive resin is used as the resin. 51 is used.

  Here, a fine structure of a connection portion between the semiconductor chip 41 and the wiring layer 22 will be described with reference to FIG. FIG. 2 is a cross-sectional structure diagram showing the connection portion between the semiconductor chip 41 and the wiring layer 22 in the component built-in wiring board shown in FIG. In FIG. 2, the same components as those shown in FIG. As shown in FIG. 2, conductive bumps 42 are formed on the terminal pads 41 a of the semiconductor chip 41, and the conductive bumps 42 and the wiring layer 22 are dispersed in the anisotropic conductive resin 51. It is electrically connected by a solder material 55bb derived from the solder particles 51b.

  That is, the anisotropic conductive resin 51 has a configuration in which the solder particles 51b are dispersed in the resin portion 51a. However, the solder particles 51b are formed at the portion sandwiched between the conductive bumps 42 and the wiring layer 22. It is melted while being subjected to a crushing force and changed to a solder material 51bb. The solder material 51bb is made of a material that easily generates an intermetallic compound in both the conductive bump 42 and the wiring layer 22 depending on the composition. For example, when solder containing Sn is used for the solder material 51bb, the conductive bump 42 is Au, and the wiring layer 22 is Cu, the bonding portion between the solder material 51bb and the conductive bump 42 is made of Au-Sn. As for the intermetallic compounds, Cu—Sn intermetallic compounds are formed at the joint portions between the solder material 51bb and the wiring layer 22, respectively.

  By generating such an intermetallic compound, the electrical connection between the conductive bump 42 and the wiring layer 22 via the solder material 51bb is significantly more reliable than in the case of simple contact between metal members. . Of course, the resin portion 51a of the anisotropic conductive resin 51 functions as an underfill resin that mechanically bonds between the semiconductor chip 41 and the wiring layer 22 and the insulating layer 11. From this point, Even connection reliability has been improved.

  Returning to FIG. 1, the other structure as the component built-in wiring board will be described. The wiring layers 22, 23, 24 and 25 different from the outer wiring layers 21 and 26 are the inner wiring layers. The insulating layer 11 between the wiring layer 22 and the wiring layer 22, the insulating layer 12 between the wiring layer 22 and the wiring layer 23, the insulating layer 13 between the wiring layer 23 and the wiring layer 24, and the wiring layer 24 and the wiring layer. The insulating layer 14 is located between the wiring layers 25 and 26, and the insulating layer 15 is located between the wiring layers 25 and 26. Each of the wiring layers 21 to 26 is made of, for example, a metal (copper) foil having a thickness of 18 μm.

  Each of the insulating layers 11 to 15 is a rigid material made of, for example, a glass epoxy resin, for example, having a thickness of 100 μm, and the insulating layer 13 only having a thickness of, for example, 300 μm. In particular, the insulating layer 13 has an opening at a position corresponding to the built-in semiconductor chip 41, and provides a space for housing the semiconductor chip 41. The insulating layers 12 and 14 are deformed so as to fill the opening of the insulating layer 13 for the built-in semiconductor chip 41 and the space inside the through-hole conductor 33 of the insulating layer 13 and become voids inside. There is no space.

  The wiring layer 21 and the wiring layer 22 can be conducted by an interlayer connector 31 that is sandwiched between the surfaces of the patterns and penetrates the insulating layer 11. Similarly, the wiring layer 22 and the wiring layer 23 can be conducted by an interlayer connector 32 that is sandwiched between the surfaces of the patterns and penetrates the insulating layer 12. The wiring layer 23 and the wiring layer 24 can be conducted by a through-hole conductor 33 provided through the insulating layer 13. The wiring layer 24 and the wiring layer 25 can be conducted by an interlayer insulator 34 that is sandwiched between the surfaces of these patterns and penetrates the insulating layer 14. The wiring layer 25 and the wiring layer 26 can be conducted by an interlayer connector 35 that is sandwiched between the surfaces of these patterns and penetrates the insulating layer 15.

  The interlayer connectors 31, 32, 34, and 35 are derived from conductive bumps formed by screen printing of a conductive composition, respectively, and depend on the manufacturing process in the axial direction (shown in FIG. 1). The diameter changes in the upper and lower stacking directions). The diameter is, for example, 200 μm on the thick side.

  As described above, the component built-in wiring board according to this embodiment is connected to the solder material 51bb and the terminal pad 41a side (here, the conductive bump 42) of the semiconductor chip 41, and the solder material 51bb and the wiring pattern 22 are mounted. Since the connection with the land for use is a connection due to the expression of an intermetallic compound, the reliability of the connection between them is high. That is, as the terminal pads 41a of the semiconductor chip 41 and the mounting lands for the wiring pattern 22, it is only necessary to select those materials that can be connected to solder, and it is not particularly necessary to provide Au plating on the wiring pattern 22. . Therefore, this wiring board can be manufactured at low cost while maintaining the reliability of flip connection and the functionality as a wiring board.

  In the above description, the conductive bump 42 is formed on the terminal pad 41a of the semiconductor chip 41. However, the terminal pad 41a is directly connected to the solder material 51bb without forming the conductive bump 42. A configuration in which the wiring layer 22 is connected to the wiring layer 22 is also conceivable. In that case, a layer of a material to which the solder material 51bb can be connected is provided on at least the surface layer of the terminal pad 41a. Even if the conductive bumps 42 are not provided, the mounting lands by the wiring layer 22 protrude from the insulating layer 11, so that the solder particles 51a are sandwiched between the mounting lands and the terminal pads 41a, and the solder lands are soldered. There is little trouble in changing to the material 51bb.

  Next, FIG. 3 is a cross-sectional structure diagram schematically showing in a slightly more detailed manner another example of the connection portion between the semiconductor chip 41 and the wiring layer 22 in the component built-in wiring board shown in FIG. In FIG. 3, the same components as those shown in the already described drawings are denoted by the same reference numerals. The description of that part is omitted. In this example, conductive bumps 42A that are solder are provided instead of the conductive bumps 42 in FIG. In this case as well, the electrical connection between the conductive bump 42A and the wiring layer 22 by the solder material 51bb is remarkably higher than in the case of simple contact between the metal members.

  A preferable relationship between the melting points of the solder bumps 42A and the solder particles 51b in the anisotropic conductive resin 51 will be described below with reference to FIG. FIG. 4 is a table showing specific composition examples of the solder bumps 42A and the solder particles 51b shown in FIG.

  The material of the solder bump 42A and the material of the solder particle 51b can be variously employed as shown in FIG. 4, but those materials are selected so that the melting point of the solder bump 42A is higher than that of the solder particle 51b. More specifically, for example, when the solder bump 42A is Sn-3Ag-0.5Cu (melting point 217 ° C.) and the solder particle 51b is Sn-58Bi (melting point 139 ° C.), or the solder bump 42A is Pb-10Sn ( And a case where the solder particles 51b are Sn-3Ag-0.5Cu (melting point: 217 ° C.).

  Thus, when the material is selected and the semiconductor chip 41 is flip-connected, the solder bump 42A is not melted, and mounting is performed at a temperature that melts only the solder particles 51b (and the temperature at which the resin portion 51a is cured). Do. As a result, as in the case where the solder bumps 42A are, for example, Au conductive bumps 42 (see FIG. 1 and FIG. 2), the flip connection is obtained by the generation of the solder material 51bb.

  Next, the manufacturing process of the component built-in wiring board shown in FIG. 1 will be described with reference to FIGS. 5 to 7 are process diagrams schematically showing a part of a manufacturing process of the component built-in wiring board shown in FIG. In these figures, the same or equivalent components as those shown in FIG.

  It demonstrates from FIG. FIG. 5 shows a manufacturing process of a portion centering on the insulating layer 11 in each configuration shown in FIG. First, as shown in FIG. 5 (a), a paste-like conductive composition to be an interlayer connection 31 is formed on a metal foil (electrolytic copper foil) 22A having a thickness of 18 μm, for example, by screen printing. It is formed in a bump shape (bottom diameter, for example, 200 μm, height, for example, 160 μm). This conductive composition is obtained by dispersing fine metal particles such as silver, gold and copper or fine carbon particles in a paste-like resin. For convenience of explanation, printing is performed on the lower surface of the metal foil 22A, but it may be printed on the upper surface (the following drawings are also the same). After the interlayer connector 31 is printed, it is dried and cured.

  Next, as shown in FIG. 5B, an FR-4 prepreg 11A having a thickness of, for example, 100 μm is laminated on the metal foil 22A to penetrate the interlayer connector 31 so that the head is exposed. To do. At the time of exposure or afterwards, the tip thereof may be crushed by plastic deformation (in any case, the shape of the interlayer connection body 31 is a shape having an axis coinciding with the stacking direction and the diameter changing in the axial direction). Subsequently, as shown in FIG. 5C, a metal foil (electrolytic copper foil) 21A is laminated on the prepreg 31A, and the whole is integrated by pressing and heating. At this time, the metal foil 21A is in electrical continuity with the interlayer connector 31, and the prepreg 11A is completely cured to become the insulating layer 11.

  Next, as shown in FIG. 5D, patterning by, for example, well-known photolithography is performed on the metal foil 22A on one side, and this is processed into a wiring layer 22 including mounting lands. And as shown in FIG.5 (e), the anisotropic conductive resin of paste-form (or a sheet form) before hardening using a dispenser in the position on the insulating layer 11 in which the semiconductor chip 41 should be mounted, for example. 51A is applied. Further, as shown in FIG. 5 (f), the semiconductor chip 41 with the conductive bumps 42 is brought into pressure contact with the mounting land of the wiring layer 22 by using, for example, a flip chip bonder.

  In order to melt the solder particles 51b (see FIG. 2) in the anisotropic conductive resin 51A and to cure the resin portion 51a (see FIG. 2) in the anisotropic conductive resin 51A after the press contact, a heating step I do. As described above, the semiconductor chip 41 is connected and fixed on the mounting land of the wiring layer 22 via the solder material 51bb (see FIG. 2) derived from the solder particles 51b, and the semiconductor chip 41, the wiring layer 22 and the insulating layer are fixed. 11 is obtained. The wiring board material 1 is filled with the anisotropic conductive resin 51A. The subsequent steps using the wiring board material 1 will be described later with reference to FIG.

  It supplements about the above process. As the paste-like anisotropic conductive resin 51A before curing, for example, in the resin portion 51a (see FIG. 2) which is, for example, an epoxy-modified polyimide resin having a curing temperature of 240 ° C., for example, solder particles 51b (see FIG. 2). (Refer to FIG. 4) A particle in which particles having a composition of Sn-3Ag-0.5Cu (melting point: 217 ° C.) are dispersed can be used. Incidentally, the anisotropic conductive resin 51A before curing may contain a flux component having a property of activating the solder particles 51b when heated and dissolved. Using such an anisotropic conductive resin 51A eliminates the need for a separate step of applying a flux, which is preferable in improving productivity.

  In the heating step, the temperature for melting the solder particles 51b (see FIG. 2) in the anisotropic conductive resin 51A and curing the resin portion 51a (see FIG. 2) in the anisotropic conductive resin 51A. For example, the heating temperature is set to about 250 ° C. More specifically, the temperature profile of this heating step can be set as shown in FIG. 8, for example. FIG. 8 is a graph showing an example of a temperature profile in the mounting process shown in FIG. Such a temperature profile is essentially achieved with a single stage of heating and is relatively easy to manage.

  In this heating step, the temperature profile shown in FIG. 9 can be adopted instead of the temperature profile shown in FIG. That is, the resin portion 51a (see FIG. 2) is not cured, and heating for melting the solder particles 51b (see FIG. 2) in the anisotropic conductive resin 51A is first performed at about 225 ° C. Subsequently, the heating temperature is slightly increased (for example, 250 ° C.) to thermally cure the resin portion 51a.

  The temperature profile in such a two-stage heating process can be set as shown in FIG. 9, for example. FIG. 9 is a graph showing another example of the temperature profile in the mounting process shown in FIG. As shown in FIG. 9, in this case, this temperature is once maintained for several tens of seconds when it is gradually heated and reaches about 225 ° C. Thereafter, the temperature is raised to 250 ° C. and this temperature state is maintained for several tens of seconds. In this way, when two-stage temperature holding is performed, the management of the temperature profile is slightly complicated, but a more appropriate temperature can be set for both melting of the solder particles 51b and thermosetting of the resin portion 51a. .

  Next, with reference to FIG. 5F, a supplementary description will be given of a method in which conductive bumps 42 are formed in advance on the semiconductor chip 41. If the conductive bump 42 is made of Au and is previously formed in a stud shape on the terminal pad 41a (see FIG. 2), for example, a gold wire is placed on the terminal pad 41a of the semiconductor chip 41 with a bonding tool. It can be formed into a stud shape by connecting and cutting it near its root. Alternatively, as a completely different method, it is also possible to form Au or Cu bumps on the terminal pads 41a by plating.

  In order to form the solder bumps 42A as the conductive bumps on the semiconductor chip 41 as in the embodiment shown in FIG. 2, for example, as used in a BGA package which is one of the semiconductor element packages. The solder ball mounting technique can be used.

  Next, a description will be given with reference to FIG. FIG. 6 shows a manufacturing process of a portion centering on the insulating layer 13 and the same 12 in each configuration shown in FIG. First, as shown in FIG. 6A, for example, an FR-4 insulating layer 13 having a thickness of, for example, 300 μm in which metal foils (electrolytic copper foils) 23A and 24A having a thickness of 18 μm are laminated on both surfaces is prepared. A through-hole 72 for forming a through-hole conductor is formed at a predetermined position, and an opening 71 is formed in a portion corresponding to the built-in semiconductor chip 41.

  Next, electroless plating and electrolytic plating are performed to form a through-hole conductor 33 on the inner wall of the through hole 72 as shown in FIG. At this time, a conductor is also formed on the inner wall of the opening 71. Further, as shown in FIG. 6C, the metal foils 23A and 24A are patterned in a predetermined manner using well-known photolithography to form wiring layers 23 and 24. By patterning the wiring layers 23 and 24, the conductor formed on the inner wall of the opening 71 is also removed.

  Next, as shown in FIG. 6 (d), conductive bumps (bottom diameter: 200 μm, height: 160 μm, for example) that will become the interlayer connector 32 are formed at predetermined positions on the wiring layer 23 of the paste-like conductive composition. It is formed by screen printing. Subsequently, as shown in FIG. 5E, the FR-4 prepreg 12A (nominal thickness, for example, 100 μm) to be the insulating layer 12 is laminated on the wiring layer 23 side using a press. The prepreg 12 </ b> A is provided with an opening in advance corresponding to the built-in semiconductor chip 41, similar to the insulating layer 13.

  In this lamination process, the head of the interlayer connector 32 is passed through the prepreg 12A. In addition, the broken line of the head part of the interlayer connection body 32 in FIG. 6 (e) indicates that there are both cases where the head part is plastically deformed and crushed at this stage, and when it is not plastically deformed. By this step, the wiring layer 23 is located by sinking to the prepreg 12A side. The wiring board material obtained as described above is referred to as a wiring board material 2.

  Note that the process shown in FIG. 6 can be performed as follows. In the stage of FIG. 6A, only the through hole 72 is formed and the subsequent steps from FIG. 6B to FIG. 6D are performed without forming the opening 71 for the built-in component. Next, as a step corresponding to FIG. 6E, prepreg 12A (without opening) is stacked. And it is the process of forming simultaneously the opening part for components incorporation in the insulating layer 13 and the prepreg 12A.

  Next, a description will be given with reference to FIG. FIG. 7 is a diagram showing an arrangement relationship in which the wiring board materials 1 and 2 obtained as described above are stacked.

  In FIG. 7, the upper wiring board material 3 shown in FIG. 7 applies the same process as the lower wiring board material 1, and then the interlayer connection body 34 and the prepreg 14 </ b> A are connected to the interlayer connection body in the intermediate wiring board material 2. 32 and the prepreg 12A. However, there is no component (semiconductor chip 41) and no part (mounting land) for connecting it, and the prepreg 14A is not provided with an opening for the semiconductor chip 41. Other than that, the metal foil (electrolytic copper foil) 26A, the insulating layer 15, the interlayer connection body 35, the wiring layer 25, the prepreg 14A, and the interlayer connection body 34 are the metal foil 21A of the wiring board material 1, the insulating layer 11, and the interlayer connection, respectively. The same as the body 31, the wiring layer 22, the prepreg 12 </ b> A of the wiring board material 2, and the interlayer connection body 32.

  The respective wiring board materials 1, 2, and 3 are laminated and arranged in the arrangement as shown in FIG. Thereby, the prepregs 12A and 14A are completely cured, and the whole is laminated and integrated. At this time, due to the fluidity of the prepregs 12 </ b> A and 14 </ b> A obtained by heating, the prepregs 12 </ b> A and 14 </ b> A are deformed into the space around the semiconductor chip 41 and the space inside the through-hole conductor 33, and no gap is generated. The wiring layers 22 and 24 are electrically connected to the interlayer connectors 32 and 34, respectively.

  After the laminating step shown in FIG. 5, the upper and lower metal foils 26A and 21A are patterned in a predetermined manner using well-known photolithography, and further, layers of solder resists 61 and 62 are formed, as shown in FIG. Such a component built-in wiring board can be obtained.

  As a modification, the through-hole conductor 33 provided in the intermediate insulating layer 13 can naturally have a configuration similar to the interlayer connector 31 or 32. In addition, the outer wiring layers 21 and 26 are formed at the stage of each wiring board material 1 and 3 (for example, at the stage of FIG. 5D) other than patterning after the last lamination step. May be.

  Further, in the laminating process shown in FIG. 7, for the wiring board materials 1 and 2, the prepreg 12 </ b> A and the interlayer connector 32 are provided not on the wiring board material 2 side but on the wiring board material 1 side. May be. That is, the formation of the interlayer connector 32 and the lamination of the prepreg 12A are performed in advance on the wiring layer 22 (on the insulating layer 11) of the wiring board material 1. In this case, the mounted semiconductor chip 41 seems to be an interference factor when the interlayer connection body 32 is formed by screen printing at first glance, but in the case of a sufficiently thin component as the semiconductor chip 41, what is actually an interference factor? Don't be. In the step of laminating the prepreg 12A, the prepreg 12A can be uniformly laminated in the in-plane direction by pressing and heating with a cushioning material capable of absorbing the thickness of the semiconductor chip 41 interposed.

  Next, a modified example of the manufacturing process shown in FIG. 5 will be described. First, FIG. 10 is a partial process diagram showing a process (FIGS. 10 (d1) to 10 (f1)) that can be employed instead of the process shown in FIGS. 5 (d) to 5 (f). 10, the same components as those shown in FIGS. 5D to 5F are denoted by the same reference numerals. The description of that part is omitted. In this example, the surface on the insulating layer 12 side of the wiring layer 22 including a portion provided for connection with the conductive bump 42 is processed into a roughened surface 22a so that the surface roughness is appropriately increased. deep. By providing the roughened surface 22a, the new surface of the wiring layer 22 is exposed, and the reliability of electrical connection with the conductive bump 42 via the solder material 51bb can be further enhanced.

  In addition, in this case, the use of the wiring board material 1A is preferable in the sense that the adhesion between the insulating layer 12 and the wiring layer 22 is improved by the roughened surface 22a in the laminating process shown in FIG. That is, reliability deterioration factors such as peeling can be suppressed. Specifically, for example, a blackening reduction process or a microetching process can be employed for forming the roughened surface 22a. Examples of the micro-etching process include CZ processing (MEC product name) and bond film processing (Atotech product name).

  Next, FIG. 11 is a partial process diagram showing a process (FIG. 11 (f2)) that can be adopted instead of the process shown in FIG. 5 (f). In FIG. 11, the same components as those shown in FIG. 5 (f) are denoted by the same reference numerals. The description of that part is omitted. In this example, the surface on the insulating layer 12 side of the wiring layer 22 is processed into the roughened surface 22a so that the surface roughness becomes moderately large except for the portion used for connection with the conductive bumps 42. This processing can be performed after the semiconductor chip 41 is flip-connected. In the case of this modification, it is preferable in the sense that the adhesion between the insulating layer 12 and the wiring layer 22 is improved by the roughened surface 22a in the laminating process shown in FIG. 7 by using the wiring board 1AA. That is, reliability deterioration factors such as peeling can be suppressed.

Sectional drawing which shows typically the structure of the component built-in wiring board which concerns on one Embodiment of this invention. FIG. 2 is a cross-sectional structure diagram illustrating a connection portion between a semiconductor chip 41 and a wiring layer 22 in the component built-in wiring board illustrated in FIG. FIG. 3 is a cross-sectional structure diagram that shows another example of a connection portion between a semiconductor chip 41 and a wiring layer 22 in the component built-in wiring board shown in FIG. The table | surface which shows the specific example of a composition of the solder bump 42A and the solder particle 51b which were shown in FIG. Process drawing which shows a part of manufacturing process of the component built-in wiring board shown in FIG. Process drawing which shows another part of manufacturing process of the component built-in wiring board shown in FIG. FIG. 9 is a process diagram schematically showing still another part of the manufacturing process of the component built-in wiring board shown in FIG. 1. The graph which shows the example of the temperature profile in the mounting process shown in FIG.5 (f). The graph which shows another example of the temperature profile in the mounting process shown in FIG.5 (f). FIG. 6 is a partial process diagram showing a process that can be adopted instead of the process shown in FIGS. FIG. 6 is a partial process diagram showing a process that can be employed instead of the process shown in FIG.

Explanation of symbols

  1, 1A, 1AA ... wiring board material, 2 ... wiring board material, 3 ... wiring board material, 11 ... insulating layer, 11A ... prepreg, 12 ... insulating layer, 12A ... prepreg, 13 ... insulating layer, 14 ... insulating layer, 14A ... Prepreg, 15 ... Insulating layer, 21 ... Wiring layer (wiring pattern), 21A ... Metal foil (copper foil), 22 ... Wiring layer (wiring pattern), 22a ... Roughened surface, 22A ... Metal foil (copper foil) , 23 ... wiring layer (wiring pattern), 23A ... metal foil (copper foil), 24 ... wiring layer (wiring pattern), 24A ... metal foil (copper foil), 25 ... wiring layer (wiring pattern), 26 ... wiring layer (Wiring pattern), 26A ... metal foil (copper foil), 31, 32, 34, 35 ... interlayer connection (conductive bumps printed by conductive composition), 33 ... through-hole conductor, 41 ... semiconductor chip, 41a ... Terminal pad, 42 ... Conductive van (Au stud bump), 42A ... conductive bump (solder bump), 51 ... anisotropic conductive resin, 51a ... resin portion, 51b ... solder particle, 51bb ... solder material, 51A ... anisotropic conductive resin (cured) Front), 61, 62 ... solder resist, 71 ... opening for parts, 72 ... through hole.

Claims (14)

A first insulating layer;
A second insulating layer positioned in a stack with respect to the first insulating layer;
A semiconductor chip having a terminal pad embedded in the second insulating layer;
A wiring pattern including a mounting land for the semiconductor chip provided between the first insulating layer and the second insulating layer;
A solder material sandwiched between the terminal pads of the semiconductor chip and the mounting lands of the wiring pattern to electrically connect the terminal pads and the mounting lands;
Comprising a resin provided between the semiconductor chip and the first insulating layer and the wiring pattern;
The resin is an anisotropic conductive resin in which solder particles are dispersed;
The component built-in wiring board, wherein the solder material is a solder material generated by melting the solder particles dispersed in the resin.   The component built-in wiring board according to claim 1, wherein the solder particles are Sn-containing solder particles.   2. The component built-in wiring board according to claim 1, wherein the wiring pattern has Cu as a material thereof.   4. The component built-in wiring board according to claim 3, wherein the surface of the wiring pattern on the second insulating layer side is a roughened surface.   Electrically connecting the terminal pad and the mounting land provided between the terminal pad of the semiconductor chip and the mounting land of the wiring pattern and closer to the terminal pad than the solder material The component built-in wiring board according to claim 1, further comprising conductive bumps.   6. The component built-in wiring board according to claim 5, wherein the conductive bump is made of Au or Cu as a material thereof.   6. The component built-in wiring board according to claim 5, wherein the conductive bump is a solder as a material thereof, and the solder has a melting point higher than that of the solder particles. Anisotropic conductivity before curing in which solder particles are dispersed on the wiring pattern of the first insulating plate provided with the wiring pattern on at least one side and where a semiconductor chip having terminal pads is to be flip-connected. Applying a resin;
Placing the semiconductor chip on the wiring pattern via the applied anisotropic conductive resin before curing;
In order to fix the semiconductor chip to the wiring pattern, the solder particles dispersed in the anisotropic conductive resin are melted by pressing and heating to a predetermined temperature, and the anisotropic conductive resin before curing is Curing, and
The second insulating plate is integrated with the first insulating plate in a stacked manner so that the semiconductor chip fixed to the wiring pattern is embedded in a second insulating plate different from the first insulating plate. A process for producing a component built-in wiring board, comprising the steps of: Anisotropic conductivity before curing in which solder particles are dispersed on the wiring pattern of the first insulating plate provided with the wiring pattern on at least one side and where a semiconductor chip having terminal pads is to be flip-connected. Applying a resin;
Placing the semiconductor chip on the wiring pattern via the applied anisotropic conductive resin before curing;
In order to fix the semiconductor chip to the wiring pattern, the solder particles dispersed in the anisotropic conductive resin are melted by pressurization and heating to a first predetermined temperature, and then the first predetermined Heating to a second predetermined temperature higher than the temperature to cure the anisotropic conductive resin before curing;
The second insulating plate is integrated with the first insulating plate in a stacked manner so that the semiconductor chip fixed to the wiring pattern is embedded in a second insulating plate different from the first insulating plate. A process for producing a component built-in wiring board comprising the steps of:   10. The method of manufacturing a component built-in wiring board according to claim 8, wherein the semiconductor chip is a semiconductor chip in which conductive bumps are formed in advance on the terminal pads.   11. The method of manufacturing a component built-in wiring board according to claim 10, wherein the conductive bump is made of Au or Cu as a material thereof.   The method of manufacturing a component built-in wiring board according to claim 10, wherein the conductive bump is solder as a material thereof, and the solder has a melting point higher than a melting point of the solder particles.   The method further comprises a step of roughening a surface of the wiring pattern before applying the uncured anisotropic conductive resin in which solder particles are dispersed on the wiring pattern. A method of manufacturing a component built-in wiring board according to 8 or 9.   The method further comprises the step of roughening the surface of the wiring pattern after the semiconductor chip is fixed to the wiring pattern and before the second insulating plate is integrated with the first insulating plate in a stacked manner. 10. The method for manufacturing a component built-in wiring board according to claim 8 or 9, wherein:

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