JP2004221567A - Solder joint part and multilayer wiring board - Google Patents

Solder joint part and multilayer wiring board Download PDF

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JP2004221567A
JP2004221567A JP2003430642A JP2003430642A JP2004221567A JP 2004221567 A JP2004221567 A JP 2004221567A JP 2003430642 A JP2003430642 A JP 2003430642A JP 2003430642 A JP2003430642 A JP 2003430642A JP 2004221567 A JP2004221567 A JP 2004221567A
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solder
layer
solder joint
alloy
conductor post
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Ryoichi Okada
亮一 岡田
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Sumitomo Bakelite Co Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a multilayer wiring board in which a multilayer connection can be certainly carried out and has a solder joint part of high reliability. <P>SOLUTION: The multilayer wiring board is constructed so that a connecting layer, which has a wiring pattern, a conductive post formed on the wiring pattern, and a solder layer formed on a tip surface of the conductive post, and a layer to be connected, which has an interlayer connecting land with the conductive post, are connected by solder joining. There are formed a solder and an alloy composed of a metal element making up the conductive post and connecting land between the conductive post and the layer to be connected. The solder joint part, where a solder fillet is formed around the solder joint part of the conductive post, is attained. The solder joint part of high reliability is attained, and the multilayer wiring board having the solder joint part can be connected by the solder joint part having high reliability and strength, thereby, high density integration and high density mounting of electronic components using them can be made possible. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

本発明は、半田接合部および多層配線板に関するものである。更には、多層配線板の層間の半田接合部に関するものである。   The present invention relates to a solder joint and a multilayer wiring board. Further, the present invention relates to a solder joint between layers of a multilayer wiring board.

近年の電子機器の高機能化並びに軽薄短小化の要求に伴い、その回路基板としてビルドアップ多層配線板が採用されている。ビルドアップ多層配線板は、樹脂のみで構成される絶縁層と、導体とを積み重ねながら成形される。ビア形成方法としては、従来のドリル加工に代わって、レーザー法、プラズマ法、フォト法等多岐にわたり、小径のビアホールを自由に配置することで、高密度化を達成するものである。層間接続部としては、ブラインドビア(Blind Via)やバリードビア(Buried Via:ビアを導電体で充填した構造)等がある。バリードビアホールとしては、ビアホールをめっきで充填する方法と、導電性ペースト等で充填する場合とに分けられる。一方、更なる小型、軽量化、多ピン化および高速信号伝送を実現させるために、配線の高密度化、ビアの小径化とともに層間絶縁層の薄膜化が求められている。そのような中、従来のビルドアップ法のような逐次積層法に代わる新たな層間接続方式として、絶縁シートの少なくとも片面に配線パターンを有し、絶縁シートの表裏面を貫通して導電性のビアホールを有し、電気的な接続を行うための、導電性接着剤、Sn−Pb半田、AuやSn等で形成された接続用電極同士を熱圧着して接続する方法(例えば、特許文献1参照。)がある。また、導電体回路層の所定場所上に導電体回路層間の電気的接続用の導電体からなる突起(金属塊)の先端部に半田層を設けておき、熱および圧力で絶縁体樹脂層を突起で突き破り半田層を導電体回路層に接続させた後、この状態で温度を半田の溶融温度まで上昇し半田層を溶融させて突起を導電体回路層に接続させた後、冷却して半田層を固化させる製造方法(例えば、特許文献2参照。)なども提案されている。   2. Description of the Related Art In recent years, with the demand for higher functionality and lighter, thinner and smaller electronic devices, build-up multilayer wiring boards have been employed as circuit boards. The build-up multilayer wiring board is formed while stacking an insulating layer made of only a resin and a conductor. As a via forming method, instead of the conventional drilling, a laser method, a plasma method, a photo method, and various other methods are used, and high-density is achieved by freely arranging small-diameter via holes. Examples of the interlayer connection portion include a blind via (Blind Via) and a buried via (Buried Via: a structure in which a via is filled with a conductor). The buried via hole is classified into a method of filling the via hole with plating and a method of filling the via hole with a conductive paste or the like. On the other hand, in order to further reduce the size, weight, increase the number of pins, and achieve high-speed signal transmission, it is required to increase the density of wiring, reduce the diameter of vias, and reduce the thickness of the interlayer insulating layer. Under such circumstances, as a new interlayer connection method that replaces the sequential lamination method such as the conventional build-up method, a conductive via hole that has a wiring pattern on at least one surface of an insulating sheet and penetrates the front and back surfaces of the insulating sheet. And a method of connecting the connecting electrodes formed of a conductive adhesive, Sn-Pb solder, Au, Sn, or the like by thermocompression bonding for electrical connection (for example, see Patent Document 1) )). In addition, a solder layer is provided on a predetermined portion of the conductor circuit layer at the tip of a protrusion (metal block) made of a conductor for electrical connection between the conductor circuit layers, and the insulator resin layer is formed by heat and pressure. After the solder layer is connected to the conductor circuit layer by breaking through the protrusion, the temperature is raised to the melting temperature of the solder in this state, the solder layer is melted, the protrusion is connected to the conductor circuit layer, and then the solder is cooled. A manufacturing method for solidifying a layer (for example, see Patent Document 2) has also been proposed.

特開平11−204939号公報(第10−12頁、図1)JP-A-11-204939 (pages 10-12, FIG. 1) 特開平8−195560号公報(第6−31頁、図1)JP-A-8-195560 (page 6-31, FIG. 1)

しかしながら、導電性接着剤による接続や、物理的接触だけによる電気的接続である場合において、接続信頼性が低く、さらには、突起先端の半田層の濡れ拡がりが十分でないと高い接続信頼性を有する接合部が形成できていないのが現状である。
本発明は、半導体チップを搭載する多層配線板における、層間接続のこのような現状の問題点に鑑み、高信頼性の層間接合部、ならびに、その接合部を有する多層配線板を提供することを目的とする。
However, in the case of connection using a conductive adhesive or electrical connection only by physical contact, the connection reliability is low, and furthermore, the connection reliability is high if the solder layer at the tip of the protrusion is not sufficiently spread. At the present time, no joint has been formed.
The present invention has been made in view of such a current problem of interlayer connection in a multilayer wiring board on which a semiconductor chip is mounted, and has as its object to provide a highly reliable interlayer bonding part, and a multilayer wiring board having the bonding part. Aim.

すなわち本発明は、
(1) 絶縁層を貫通して、該絶縁層から突出している導体ポストの先端表面に形成された半田層と、該導体ポストに相対する層間接続用ランドを有する被接続層とを、接着剤層を介して半田接合させて得られる半田接合部であって、前記導体ポストと前記層間接続用ランドとの接合部に、前記半田層、前記導体ポスト、および前記層間接続用ランドを形成する金属成分から構成される合金が形成され、さらに前記半田接合部周辺に半田または半田の金属を含む合金からなるフィレットが形成されていることを特徴とする半田接合部、
(2) 導体ポストと被接続層の間に形成された合金が、半田よりも高い融点を有するものである第(1)項記載の半田接合部、
(3) 半田層が、導体ポストの断面積よりも大きく濡れ広がって、層間接続用ランドと半田接合される第(1)項または第(2)項に記載の半田接合部、
(4) 半田の濡れ広がり面積が、導体ポストの断面積よりも2倍以上7倍以下である第(3)項記載の半田接合部、
(5) 半田接合部が、少なくとも半田層を接着剤層と接触させ、半田層を形成する半田の融点以上の温度で加熱して、半田層を溶融させて、次いで、圧着して半田接合させて得られたものである第(1)項〜第(4)項いずれかに記載の半田接合部、
(6) 導体ポストと被接続層の間に形成された合金が、銅と錫の合金である第(1)項〜第(5)項のいずれかに記載の半田接合部、
(7) 導体ポストと被接続層の間に形成された合金が、金とニッケルと錫の合金である第(1)項〜第(5)項のいずれかに記載の半田接合部、
(8) フィレットを形成する合金が、金と錫の合金である第(1)項〜第(7)項のいずれかに記載の半田接合部、
(9) 第(1)項〜第(8)項のいずれかに記載の半田接合部を有することを特徴とする多層配線板、
である。
That is, the present invention
(1) An adhesive is formed by bonding an solder layer formed on a tip end surface of a conductor post projecting from the insulating layer through the insulating layer and a connected layer having an interlayer connection land facing the conductor post. A solder joining portion obtained by soldering via a layer, wherein the solder layer, the conductor post, and the interlayer connection land are formed at a joint between the conductor post and the interlayer connection land. An alloy composed of components is formed, and further a solder joint, wherein a fillet made of an alloy containing solder or solder metal is formed around the solder joint,
(2) The solder joint according to (1), wherein the alloy formed between the conductor post and the connected layer has a higher melting point than solder.
(3) The solder joint according to (1) or (2), wherein the solder layer spreads more than the cross-sectional area of the conductor post and is soldered to the land for interlayer connection.
(4) The solder joint according to (3), wherein the wet spread area of the solder is 2 times or more and 7 times or less than the cross-sectional area of the conductor post.
(5) At least the solder bonding portion contacts the solder layer with the adhesive layer, heats at a temperature equal to or higher than the melting point of the solder forming the solder layer, melts the solder layer, and then press-bonds to perform solder bonding. The solder joint according to any one of (1) to (4), which is obtained by:
(6) The solder joint according to any one of (1) to (5), wherein the alloy formed between the conductor post and the connected layer is an alloy of copper and tin.
(7) The solder joint according to any one of (1) to (5), wherein the alloy formed between the conductor post and the connected layer is an alloy of gold, nickel, and tin;
(8) The solder joint according to any one of (1) to (7), wherein the alloy forming the fillet is an alloy of gold and tin;
(9) A multilayer wiring board comprising the solder joint according to any one of (1) to (8).
It is.

本発明によれば、高信頼性の半田接合部を提供することができ、本発明の半田接合部を有する多層配線板は、高い信頼性と強度を持つ半田接合部により層間接続をすることができるので、これを用いた電子部品の高密度集積化や、高密度実装化が可能とすることができる。   According to the present invention, a highly reliable solder joint can be provided, and the multilayer wiring board having the solder joint of the present invention can perform interlayer connection by a solder joint having high reliability and strength. Therefore, it is possible to achieve high-density integration and high-density mounting of electronic components using this.

本発明の半田接合部は、絶縁層を貫通して該絶縁層から突出して形成された導体ポストの先端表面に形成された半田層と、該導体ポストに相対する層間接続用ランドを有する被接続層とを接着剤層を介して層間接続を行う際に、前記導体ポストの先端表面に形成された半田層と、前記層間接続用ランドとの、半田接合によって得られるものである。
本発明の半田接合部には、前記導体ポストと前記層間接続用ランドとの間に、前記半田層、前記導体ポストおよび前記層間接続用ランドを形成する金属成分から構成される合金層が形成されている。さらに、半田接合部の根元には、接合部を補強するように、半田または半田の金属を含む合金のフィレットが形成されている。半田または半田の金属を含む合金のフィレットが形成されていることで、熱衝撃試験による半田接合部への応力集中を防ぐことができ、また、フィレットそのものによる半田接合部の補強効果により、接合強度自体が増すことで、高い接続信頼性が確保される。
The solder joint according to the present invention is a connected part having a solder layer formed on a tip end surface of a conductor post formed so as to penetrate an insulation layer and protrude from the insulation layer, and a land for interlayer connection facing the conductor post. When the layers are connected to each other via an adhesive layer, the layers are obtained by soldering a solder layer formed on the tip surface of the conductor post and the land for interlayer connection.
In the solder joint of the present invention, an alloy layer composed of a metal component forming the solder layer, the conductor post and the land for interlayer connection is formed between the conductor post and the land for interlayer connection. ing. Further, a fillet of solder or an alloy containing solder metal is formed at the base of the solder joint so as to reinforce the joint. The formation of a fillet of solder or an alloy containing a solder metal can prevent stress concentration on the solder joint by the thermal shock test, and the reinforcing effect of the solder joint by the fillet itself can increase the bonding strength. By increasing itself, high connection reliability is ensured.

さらに、半田接合部に形成されている合金は、半田の融点よりも高くなるように設計されることが好ましい。例えば、半田が、錫を主成分とする金属からなり、導体ポストおよび層間接続用ランドが、銅を主成分とする金属からなる場合、半田接合によって得られる接合部には、銅と錫の合金が形成される。形成された合金の融点は、400℃以上である。一般に、半導体チップが実装される際のリフロー工程の温度は400℃を超えることはない。従って、本発明の半田接合部を有する多層配線板に、半導体チップが実装されるリフロー工程においては、多層配線板の半田接合部が溶融することが無いため、半田接合部が断線することが無く、安定した導通を維持することができる。これは、パッケージ実装においても同様である。   Further, it is preferable that the alloy formed in the solder joint is designed to be higher than the melting point of the solder. For example, when the solder is made of a metal containing tin as a main component, and the conductor posts and the lands for interlayer connection are made of a metal containing copper as a main component, an alloy of copper and tin is formed at a joint obtained by soldering. Is formed. The melting point of the formed alloy is 400 ° C. or higher. Generally, the temperature of the reflow step when a semiconductor chip is mounted does not exceed 400 ° C. Therefore, in the reflow step in which the semiconductor chip is mounted on the multilayer wiring board having the solder joint of the present invention, the solder joint of the multilayer wiring board does not melt, so that the solder joint does not break. , And stable conduction can be maintained. This is the same in package mounting.

さらに、本発明の半田接合部は、導体ポストに形成された半田層が、層間接続用ランドに濡れ広がって、半田接合するが、半田の濡れ広がり面積は、導体ポストの断面積よりも大きくなっていることが好ましい。導体ポストの断面積よりも大きくなることで、良好な半田または半田の金属を含む合金のフィレットが形成され、接合強度は、より高くなる。また、半田の濡れ広がり面積は、導体ポスト断面積よりも2倍以上7倍以下であることが好ましい。2倍を下回ると、良好な半田または半田の金属を含む合金のフィレットが形成されずに、十分な接合強度が得られない場合がある。また、7倍を上回ると、半田がランドに広範囲に濡れ広がり、半田または半田の金属を含む合金のフィレットを形成するに十分な半田が確保されない恐れがあり、十分な接合強度が得られない場合がある。   Furthermore, in the solder joint portion of the present invention, the solder layer formed on the conductor post wets and spreads on the interlayer connection land and performs the solder joint, but the wet spread area of the solder is larger than the cross-sectional area of the conductor post. Is preferred. When the cross-sectional area is larger than that of the conductor post, a fillet of a good solder or an alloy containing a metal of the solder is formed, and the bonding strength is further increased. Further, the wet spread area of the solder is preferably at least 2 times and not more than 7 times the cross-sectional area of the conductor post. If the ratio is less than twice, good fillet of solder or alloy containing solder metal may not be formed, and sufficient bonding strength may not be obtained. On the other hand, if it exceeds 7 times, the solder will spread widely over the lands, and sufficient solder may not be secured to form a fillet of the solder or an alloy containing the metal of the solder, and sufficient bonding strength may not be obtained. There is.

これらの良好な半田接合を得る方法としては、半田接合において、まず、少なくとも半田層を接着剤層と接触させ、半田層を形成する半田の融点以上の温度で加熱して、半田層を溶融させ、次いで、圧着して接合する方法が好ましい。   As a method of obtaining these good solder joints, in solder joining, first, at least the solder layer is brought into contact with the adhesive layer, and heated at a temperature equal to or higher than the melting point of the solder forming the solder layer to melt the solder layer. Then, a method of bonding by pressing is preferable.

次に、本発明の半田接合部の形成工程について、多層配線板の製造方法の例を用いて説明するが、本発明はこれによって、何ら限定されるものではない。
図1は、本発明の半田接合部を有する多層配線板の製造方法の例を説明するための図で、図1(h)は得られる多層配線板の構造を示す断面図である。
Next, the step of forming a solder joint according to the present invention will be described using an example of a method for manufacturing a multilayer wiring board, but the present invention is not limited thereto.
FIG. 1 is a view for explaining an example of a method for manufacturing a multilayer wiring board having a solder joint according to the present invention, and FIG. 1H is a cross-sectional view showing the structure of the obtained multilayer wiring board.

本発明の多層配線板の製造方法の例としては、まず、金属箔101と絶縁膜102からなる2層構造体を用意し、前記絶縁膜102の導体ポストを形成する位置に、ビア103を形成する(図1(a))。次に、金属箔101を電解めっき用リード(給電用電極)として、電解めっきにより、導体ポスト104をビア103に形成し、続いて、導体ポスト104の先端表面に、絶縁層102を突出して、半田層105を形成する(第1図(b))。次に、金属箔101を、選択的にエッチングすることにより、導体回路106を形成して、接続層110を得る(図1(c))。   As an example of the method for manufacturing a multilayer wiring board of the present invention, first, a two-layer structure composed of a metal foil 101 and an insulating film 102 is prepared, and a via 103 is formed in the insulating film 102 at a position where a conductor post is to be formed. (FIG. 1A). Next, using the metal foil 101 as a lead for electrolytic plating (electrode for power supply), a conductor post 104 is formed in the via 103 by electrolytic plating, and then the insulating layer 102 is protruded from the front end surface of the conductor post 104, A solder layer 105 is formed (FIG. 1B). Next, the conductive circuit 106 is formed by selectively etching the metal foil 101 to obtain the connection layer 110 (FIG. 1C).

次に、絶縁膜102の表面に接着剤層108を形成する(図1(d))。次に、接続層110の半田層105と被接続層120の層間接続用ランド107が相対するように位置合わせする(図1(e))。次に、接着剤層108を介して、接続層110と被接続層120とを、それぞれが有する半田層105および層間接続用ランド107が、接着剤層108と接触するように貼り合わせる(図1(f))。   Next, an adhesive layer 108 is formed on the surface of the insulating film 102 (FIG. 1D). Next, the solder layer 105 of the connection layer 110 and the land 107 for interlayer connection of the connected layer 120 are aligned so as to face each other (FIG. 1E). Next, the connection layer 110 and the connection-target layer 120 are bonded via the adhesive layer 108 such that the solder layer 105 and the interlayer connection land 107 of the connection layer 110 and the interlayer connection land 107 are in contact with the adhesive layer 108 (FIG. 1). (F)).

次いで、接続層110と被接続層120とを、半田層105を形成する半田の融点以上の温度に加熱し半田を溶融させた後、加圧して圧着する(図1(g)〜(h))。
加熱、加圧工程では、例えば、真空プレスを用いて、半田層105が、その半田の融点温度以上にまで加熱されるが、このとき、接着剤層108が金属表面表面清浄化機能を有することが好ましい。すなわち、少なくとも半田表面に形成されている酸化膜を除去することができる機能である。該接着剤を用いることにより、半田層105の表面の酸化膜が還元されて溶融し、溶融半田の表面張力により凸形状を形成する(図1(g))。この時、凸形状は、最安定なドーム状、滴状であることが、より好ましい。その後、加圧して凸形状を形成した半田層105の頂点部と層間接続用ランド107とを接触させ、その接点から、同心円状に半田が濡れ広がり、導体ポストが金属ランドにあたるまで加圧される。このとき濡れ広がった半田によって、導体ポスト接合部周囲にフィレットが形成されて、接合部が半田または半田の金属を含む合金のフィレットによって補強されたような形になる。
Next, the connection layer 110 and the connected layer 120 are heated to a temperature equal to or higher than the melting point of the solder forming the solder layer 105 to melt the solder, and then pressurized and pressed (FIGS. 1 (g) to (h)). ).
In the heating and pressing steps, for example, the solder layer 105 is heated to a temperature equal to or higher than the melting point of the solder by using a vacuum press. At this time, the adhesive layer 108 has a metal surface surface cleaning function. Is preferred. That is, the function is to remove at least the oxide film formed on the solder surface. By using the adhesive, the oxide film on the surface of the solder layer 105 is reduced and melted, and a convex shape is formed by the surface tension of the molten solder (FIG. 1 (g)). At this time, it is more preferable that the convex shape is the most stable dome shape or drop shape. Thereafter, the apexes of the solder layer 105 having a convex shape formed by pressing are brought into contact with the interlayer connection lands 107, and the solder is wet and spread concentrically from the contact points, and the conductor posts are pressed until they hit the metal lands. . At this time, a fillet is formed around the joint portion of the conductor post by the spread solder, so that the joint portion has a shape reinforced by the fillet of the solder or the alloy containing the metal of the solder.

さらに、加圧工程で溶融した半田は、接合部周辺部に押し出されるため、導体ポストの真下には、半田そのものは存在しない。接合部には、半田および導体ポストおよび層間接続用ランドを構成する金属の合金が形成される。
例えば、導体ポストと層間接続用ランドが銅、半田が錫を主成分とする金属からなる場合、半田接合部には、合金層が形成されるが、このような場合、半田接合部は、CuSn、CuSnのような典型的な銅錫の合金が形成される。これらの合金の融点は、いずれも400℃以上である。
Furthermore, since the solder melted in the pressing step is extruded to the periphery of the joint, the solder itself does not exist directly below the conductor post. At the joint portion, an alloy of solder and a metal constituting the conductor post and the interlayer connection land is formed.
For example, when the conductor posts and the lands for interlayer connection are made of copper, and the solder is made of a metal containing tin as a main component, an alloy layer is formed at the solder joint. In such a case, the solder joint is made of Cu. A typical copper-tin alloy such as 3 Sn, Cu 6 Sn 5 is formed. The melting points of these alloys are all 400 ° C. or higher.

また、半田層と導体ポストと層間接続用ランドとの半田接合部に、主として金とニッケルと錫の合金が形成されていることが高融点合金接続部を得る上で好ましく、この場合、例えば、それぞれの層を形成する金属層における拡散速度の差により発生するカーケンダルボイドを抑制することを目的として、導体層および銅ポストと半田層の間に拡散防止金属層となるニッケル層を形成し、さらに半田濡れ性を向上させるために拡散防止金属層表面に金層を形成して接合することにより、合金を得ることができるが、さらに具体的には、銅層、ニッケル層、金層で形成した層間接続用ランドあるいは接続層の導体回路と、銅ポストと錫を主成分とする半田層との間にもニッケル層を形成し、接合することにより、導体ポストと被接続層との間に前記合金を得ることができる。また、接合部周囲に形成されるフィレット部分は主にAuSnとAuSnを主成分とする金と錫の合金が形成される。これらの合金の融点は、合金状態図によれば、それぞれ約420℃、350℃である。
従って、半導体チップ実装工程、半導体パッケージ実装工程等において、本発明の半田接合部の金属が再溶融して断線する心配が無い。
上記多層配線板の例においては、2層の半田接合の例を示したが、3層以上であっても各層をそれぞれ準備し同様方法により得られる。
In addition, it is preferable that an alloy of gold, nickel, and tin is mainly formed at a solder joint between the solder layer, the conductor post, and the land for interlayer connection in order to obtain a high-melting-point alloy joint. In this case, for example, For the purpose of suppressing Kirkendall voids generated due to the difference in diffusion rate in the metal layer forming each layer, a nickel layer serving as a diffusion preventing metal layer is formed between the conductor layer and the copper post and the solder layer, An alloy can be obtained by forming and joining a gold layer on the surface of the diffusion preventing metal layer to further improve solder wettability, but more specifically, a copper layer, a nickel layer, and a gold layer are formed. The nickel layer is also formed between the conductor circuit of the interlayer connection land or the connection layer and the copper layer and the solder layer containing tin as a main component, and by joining, a nickel layer is formed between the conductor post and the connection layer. It is possible to obtain the serial alloy. The fillet formed around the joint is mainly made of an alloy of gold and tin containing AuSn and AuSn 2 as main components. The melting points of these alloys are about 420 ° C. and 350 ° C., respectively, according to the alloy phase diagram.
Therefore, in the semiconductor chip mounting step, the semiconductor package mounting step, and the like, there is no fear that the metal of the solder joint of the present invention is remelted and disconnected.
In the above example of the multilayer wiring board, the example of the solder bonding of two layers is shown, but even if there are three or more layers, each layer is prepared and obtained by the same method.

以下、実施例により更に具体的に説明するが、本発明はこれによって何ら限定されるものではない。   Hereinafter, the present invention will be described more specifically with reference to Examples, but the present invention is not limited thereto.

<接続層110の作製>
銅箔(金属箔101、厚み18μm)、ポリイミド樹脂絶縁膜(絶縁膜102、厚み25μm)からなるフレキシブルプリント配線用基板(住友ベークライト製、A1フレキ)のポリイミド樹脂絶縁膜に、UV−YAGレーザーを用いて、トップ径が45μm、ボトム径が25μmのビア(ビア103)を、300個形成した。ビア内部およびビア周辺部を、過マンガン酸樹脂エッチング液にて清浄化した後、裏面の銅箔を、電解めっき用リード(給電用電極)として、電解銅めっきを行って、ビアを銅で充填し、銅ポスト(導体ポスト104)を形成した。ここで、銅ポストの直径が45μmとなるよう、電解銅めっきの時間を調整した。次に、銅ポストの表面に、Sn−Pb共晶半田層(半田層105)を電解めっきによって、4μmの厚みで形成した。なお、半田層の先端表面の絶縁膜表面から突出している高さは、10μmであった。次に、銅箔を選択的にエッチングして、配線パターン(導体回路106)を形成した。以上の工程により、接続層(接続層110)を得ることができた。
<Preparation of connection layer 110>
UV-YAG laser was applied to the polyimide resin insulation film of a flexible printed wiring board (Sumitomo Bakelite, A1 flexible) composed of copper foil (metal foil 101, thickness 18 μm) and polyimide resin insulation film (insulation film 102, thickness 25 μm). Using this, 300 vias (vias 103) having a top diameter of 45 μm and a bottom diameter of 25 μm were formed. After cleaning the inside of the via and the periphery of the via with a permanganate resin etching solution, electrolytic copper plating is performed using the copper foil on the back as a lead (electrode for power supply) for electrolytic plating, and the via is filled with copper. Then, a copper post (conductor post 104) was formed. Here, the time of electrolytic copper plating was adjusted so that the diameter of the copper post was 45 μm. Next, a Sn-Pb eutectic solder layer (solder layer 105) was formed on the surface of the copper post with a thickness of 4 µm by electrolytic plating. The height of the tip surface of the solder layer protruding from the insulating film surface was 10 μm. Next, the copper foil was selectively etched to form a wiring pattern (conductor circuit 106). Through the above steps, a connection layer (connection layer 110) was obtained.

<接着剤ワニスの調合>
クレゾールノボラック樹脂(住友デュレズ(株)製,PR−HF−3)106gと、フェノールフタリン(東京化成製)105gと、ジアリルビスフェノールA型エポキシ樹脂(日本化薬(株)製、RE−810NM)450gとを、メチルエチルケトン165gに溶解し、金属接合接着剤ワニスを作製した。
<Formulation of adhesive varnish>
106 g of cresol novolak resin (PR-HF-3, manufactured by Sumitomo Durez Co., Ltd.), 105 g of phenolphthaline (manufactured by Tokyo Chemical Industry), and diallyl bisphenol A type epoxy resin (RE-810NM, manufactured by Nippon Kayaku Co., Ltd.) 450 g were dissolved in 165 g of methyl ethyl ketone to prepare a metal bonding adhesive varnish.

次に、上記で得られた接続層に対して、バーコートにより、上記で得た金属接合接着剤ワニスを、絶縁膜の表面、すなわちSn−Ag(2.5%)の共晶半田層が形成された面に塗布後、80℃で20分間乾燥し、30μm厚の接着剤層(接着剤層108)を形成した。   Next, the metal bonding adhesive varnish obtained above was applied to the surface of the insulating film, that is, a eutectic solder layer of Sn-Ag (2.5%) by bar coating on the connection layer obtained above. After coating on the formed surface, it was dried at 80 ° C. for 20 minutes to form an adhesive layer (adhesive layer 108) having a thickness of 30 μm.

さらに、厚み12μm銅箔が両面に形成されたFR−5相当のガラスエポキシ両面銅張積層板(住友ベークライト製、ELC)を被接続層として、上記工程で得られた接続層を、100℃の温度で仮圧着して、接続層表面と、相対する被接続層の表面とを接触させた。仮圧着したサンプルを断面観察したところ、半田層と層間接続用ランドとは非接触であり、約30μm程度の間隙(接着剤層)があった。
最後に、仮圧着したサンプルを、半田の融点(219℃)以上に加熱した後、加圧して、本圧着して多層配線板を得た。
Further, using a glass epoxy double-sided copper-clad laminate equivalent to FR-5 (manufactured by Sumitomo Bakelite, ELC) having 12 μm-thick copper foil formed on both sides as a layer to be connected, the connecting layer obtained in the above step was heated at 100 ° C. Preliminary pressure bonding was performed at a temperature to bring the surface of the connection layer into contact with the surface of the opposing connected layer. When the cross-section of the temporarily pressed sample was observed, the solder layer was not in contact with the land for interlayer connection, and there was a gap (adhesive layer) of about 30 μm.
Finally, the preliminarily pressure-bonded sample was heated to a temperature equal to or higher than the melting point of the solder (219 ° C.), pressurized, and finally pressure-bonded to obtain a multilayer wiring board.

<半田接合部の観察>
上記実施例おいて得られた、半田接合部の断面のSEM観察を行った。結果を図2に示す。また、銅ポストと接続用ランドの間の半田接合部、並びにフィレット部分をエネルギー分散型X線分光法(EDX)による元素分析を行った。
<Observation of solder joint>
The SEM observation of the cross section of the solder joint obtained in the above example was performed. FIG. 2 shows the results. In addition, the solder joints between the copper posts and the connection lands and the fillet portions were subjected to elemental analysis by energy dispersive X-ray spectroscopy (EDX).

断面SEM写真から、接続層の導体回路層201と被接続層の層間接続用ランド204とが、絶縁層202を貫通した層間接続用銅ポスト205と、その先端に形成された半田接合部206により接続され、半田接合部周辺には、フィレット207が形成されている様子が確認できた。また、接合部のEDXの分析結果によると、銅ポストと接続用ランドの間には、CuSnおよびCuSnの合金が形成されていた。また、フィレット部分からは、ほぼSnのみが検出され、一部に偏在したSnAgの合金が形成されていた。 From the cross-sectional SEM photograph, the conductor circuit layer 201 of the connection layer and the interlayer connection land 204 of the connected layer are formed by the interlayer connection copper post 205 penetrating the insulating layer 202 and the solder joint 206 formed at the tip thereof. It was confirmed that a fillet 207 was formed around the connected and soldered portions. According to the EDX analysis result of the joint, an alloy of Cu 3 Sn and Cu 6 Sn 5 was formed between the copper post and the connection land. Further, almost only Sn was detected from the fillet portion, and a Sn 3 Ag alloy unevenly distributed was formed partially.

本発明の実施形態による多層配線板の製造方法の例を示す断面図である。FIG. 4 is a cross-sectional view illustrating an example of a method for manufacturing a multilayer wiring board according to an embodiment of the present invention. 本発明の実施例における半田接合部周辺の断面SEM写真である。4 is a SEM photograph of a cross section around a solder joint in an example of the present invention.

符号の説明Explanation of reference numerals

101 金属箔
102 絶縁膜
103 ビア
104 導体ポスト
105 半田層
106 導体回路
107 層間接続用ランド
108 接着剤層
110 接続層
120 被接続層
130 多層配線板
201 導体回路層
202 絶縁膜
203 接着剤層
204 層間接続用ランド
205 層間接続用銅ポスト
206 層間接合部(半田接合部)
207 フィレット
101 Metal foil 102 Insulating film 103 Via 104 Conductor post 105 Solder layer 106 Conductor circuit 107 Interlayer connection land 108 Adhesive layer 110 Connection layer 120 Connected layer 130 Multilayer wiring board 201 Conductor circuit layer 202 Insulating film 203 Adhesive layer 204 Interlayer Connection land 205 Interlayer connection copper post 206 Interlayer joint (solder joint)
207 fillet

Claims (9)

絶縁層を貫通して、該絶縁層から突出している導体ポストの先端表面に形成された半田層と、該導体ポストに相対する層間接続用ランドを有する被接続層とを、接着剤層を介して半田接合させて得られる半田接合部であって、前記導体ポストと前記層間接続用ランドとの接合部に、前記半田層、前記導体ポスト、および前記層間接続用ランドを形成する金属成分から構成される合金が形成され、さらに前記半田接合部周辺に半田または半田の金属を含む合金からなるフィレットが形成されていることを特徴とする半田接合部。   A solder layer formed on the tip surface of a conductor post projecting from the insulating layer, penetrating the insulating layer, and a connected layer having an interlayer connection land opposed to the conductor post are connected via an adhesive layer. And a metal component forming the solder layer, the conductor post, and the interlayer connection land at a junction between the conductor post and the interlayer connection land. A solder joint, wherein a fillet made of solder or an alloy containing solder metal is formed around the solder joint. 導体ポストと被接続層の間に形成された合金が、半田よりも高い融点を有するものである請求項1記載の半田接合部。   2. The solder joint according to claim 1, wherein the alloy formed between the conductor post and the connected layer has a higher melting point than solder. 半田層が、導体ポストの断面積よりも大きく濡れ広がって、層間接続用ランドと半田接合される請求項1または2に記載の半田接合部。   3. The solder joint according to claim 1, wherein the solder layer spreads more than the cross-sectional area of the conductor post and is solder-bonded to the interlayer connection land. 4. 半田の濡れ広がり面積が、導体ポストの断面積よりも2倍以上7倍以下である請求項3記載の半田接合部。   4. The solder joint according to claim 3, wherein the spread area of the solder is 2 to 7 times the cross-sectional area of the conductor post. 半田接合部が、少なくとも半田層を接着剤層と接触させ、半田層を形成する半田の融点以上の温度で加熱して、半田層を溶融させて、次いで、圧着して半田接合させて得られたものである請求項1〜4のいずれかに記載の半田接合部。   A solder joint is obtained by contacting at least the solder layer with the adhesive layer, heating at a temperature equal to or higher than the melting point of the solder forming the solder layer, melting the solder layer, and then pressing and joining the solder. The solder joint according to any one of claims 1 to 4, wherein: 導体ポストと被接続層の間に形成された合金が、銅と錫の合金である請求項1〜5のいずれかに記載の半田接合部。   The solder joint according to claim 1, wherein the alloy formed between the conductor post and the connected layer is an alloy of copper and tin. 導体ポストと被接続層の間に形成された合金が、金とニッケルと錫の合金である請求項1〜5のいずれかに記載の半田接合部。   The solder joint according to any one of claims 1 to 5, wherein the alloy formed between the conductor post and the connected layer is an alloy of gold, nickel, and tin. フィレットを形成する合金が、金と錫の合金である請求項1〜7のいずれかに記載の半田接合部。   The solder joint according to claim 1, wherein the alloy forming the fillet is an alloy of gold and tin. 請求項1〜8のいずれかに記載の半田接合部を有することを特徴とする多層配線板。   A multilayer wiring board comprising the solder joint according to claim 1.
JP2003430642A 2002-12-26 2003-12-25 Solder joint part and multilayer wiring board Pending JP2004221567A (en)

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006278991A (en) * 2005-03-30 2006-10-12 Sumitomo Bakelite Co Ltd Manufacturing method of multilayer wiring board
JP2006278964A (en) * 2005-03-30 2006-10-12 Brother Ind Ltd Method of manufacturing board jointing structure and terminal forming board
JP2007048825A (en) * 2005-08-08 2007-02-22 Sumitomo Bakelite Co Ltd Joining method, joint part structure, wiring board, and manufacturing method thereof
WO2008032386A1 (en) * 2006-09-14 2008-03-20 Sumitomo Bakelite Co., Ltd. Junction structure, method of joining, wiring board and process for producing the same
JP2014130969A (en) * 2012-12-28 2014-07-10 Fujikura Ltd Wiring board and method of manufacturing the same

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006278991A (en) * 2005-03-30 2006-10-12 Sumitomo Bakelite Co Ltd Manufacturing method of multilayer wiring board
JP2006278964A (en) * 2005-03-30 2006-10-12 Brother Ind Ltd Method of manufacturing board jointing structure and terminal forming board
JP4501752B2 (en) * 2005-03-30 2010-07-14 ブラザー工業株式会社 Substrate bonding structure manufacturing method and inkjet head manufacturing method
JP2007048825A (en) * 2005-08-08 2007-02-22 Sumitomo Bakelite Co Ltd Joining method, joint part structure, wiring board, and manufacturing method thereof
WO2008032386A1 (en) * 2006-09-14 2008-03-20 Sumitomo Bakelite Co., Ltd. Junction structure, method of joining, wiring board and process for producing the same
JPWO2008032386A1 (en) * 2006-09-14 2010-01-21 住友ベークライト株式会社 Junction structure, joining method, wiring board, and manufacturing method thereof
US8241760B2 (en) 2006-09-14 2012-08-14 Sumitomo Bakelite Company, Ltd. Joint structure, joining method, wiring board and method for producing the same
JP5109977B2 (en) * 2006-09-14 2012-12-26 住友ベークライト株式会社 Junction structure, joining method, wiring board, and manufacturing method thereof
JP2014130969A (en) * 2012-12-28 2014-07-10 Fujikura Ltd Wiring board and method of manufacturing the same

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