JPH07162157A - Multilayered board - Google Patents

Multilayered board

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Publication number
JPH07162157A
JPH07162157A JP5306824A JP30682493A JPH07162157A JP H07162157 A JPH07162157 A JP H07162157A JP 5306824 A JP5306824 A JP 5306824A JP 30682493 A JP30682493 A JP 30682493A JP H07162157 A JPH07162157 A JP H07162157A
Authority
JP
Japan
Prior art keywords
filling metal
multilayer substrate
substrate
metal
power element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP5306824A
Other languages
Japanese (ja)
Other versions
JP3520540B2 (en
Inventor
Yasutomi Asai
浅井　　康富
Takashi Nagasaka
長坂　　崇
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Denso Corp
Original Assignee
NipponDenso Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NipponDenso Co Ltd filed Critical NipponDenso Co Ltd
Priority to JP30682493A priority Critical patent/JP3520540B2/en
Priority to DE4443424A priority patent/DE4443424B4/en
Publication of JPH07162157A publication Critical patent/JPH07162157A/en
Application granted granted Critical
Publication of JP3520540B2 publication Critical patent/JP3520540B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
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    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5383—Multilayer substrates
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Abstract

PURPOSE:To provide a multilayered board which can be lessened in transient and steady-state thermal resistance. CONSTITUTION:A filling metal 4 is filled in a surface insulating layer 1a as a heat transfer conductor of high thermal conductivity, and a power device 6 is arranged on the filling metal 4. Heat released from the power device 6 is transmitted to the filling metal 4 located at the surface insulating layer 1a and dissipated. The filling metal 4 is formed of mixture of Mo particles of high melting point and aluminum particles.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】この発明は多層基板に関するもの
である。FIELD OF THE INVENTION The present invention relates to a multilayer substrate.

【０００２】[0002]

【従来の技術】従来、多層基板においては、例えば、図
１２に示すように、多層よりなるセラミック基板３１上
にＣｕやＡｇよりなる厚膜導体３２が印刷焼成にて形成
され、その上に半田３３を介してＭｏやＣｕよりなるヒ
ートシンク３４が配置され、さらにその上に半田３５を
介してパワー素子３６が実装されている。尚、図中、３
７はワイヤであり、３８はチップターミナルである。2. Description of the Related Art Conventionally, in a multilayer substrate, for example, as shown in FIG. 12, a thick film conductor 32 made of Cu or Ag is formed by printing and firing on a multilayer ceramic substrate 31, and solder is formed thereon. A heat sink 34 made of Mo or Cu is arranged via 33, and a power element 36 is mounted thereon via solder 35. In the figure, 3
7 is a wire and 38 is a chip terminal.

【０００３】[0003]

【発明が解決しようとする課題】ところが、この構造で
は、過渡的な熱抵抗を下げる必要があるものは、ヒート
シンク３４を厚く（体積を増加）しなければならず、ヒ
ートシンク３４のコストアップ及び実装容積の拡大を招
いていた。さらに、定常熱抵抗を下げるためには、熱伝
導性のよい基板材料を用いる必要があり、これは材料の
コストアップにつながる。又、定常熱抵抗を下げるため
にはヒートシンク３４を薄くしてパワー素子から基板底
面までの距離を小さくし、基板底面からの放熱性を向上
させる必要があったが、ヒートシンク３４を薄くするこ
とは過渡熱抵抗を下げることと相反することとなってし
まっていた。However, in this structure, if the transient thermal resistance needs to be reduced, the heat sink 34 must be made thicker (volume increased), which increases the cost and mounting of the heat sink 34. This has led to an increase in volume. Further, in order to reduce the steady-state thermal resistance, it is necessary to use a substrate material having good thermal conductivity, which leads to an increase in material cost. Further, in order to reduce the steady-state thermal resistance, it is necessary to make the heat sink 34 thin to reduce the distance from the power element to the bottom surface of the substrate to improve the heat dissipation from the bottom surface of the substrate. It had become the opposite of reducing the transient thermal resistance.

【０００４】そこで、この発明の目的は、過渡ならびに
定常熱抵抗を下げることができる多層基板を提供するこ
とにある。Therefore, an object of the present invention is to provide a multilayer substrate which can reduce transient and steady-state thermal resistance.

【０００５】[0005]

【課題を解決するための手段】この発明は、複数の絶縁
層からなる多層基板上にパワー素子を配置し、一以上の
絶縁層のパワー素子下部領域に前記パワー素子の熱伝達
用導体を充填した多層基板をその要旨とする。According to the present invention, a power element is arranged on a multilayer substrate composed of a plurality of insulating layers, and a heat transfer conductor of the power element is filled in a lower region of the power element of one or more insulating layers. The above-mentioned multilayer substrate is the gist.

【０００６】[0006]

【作用】パワー素子で発生した熱は、基板内に充填され
た熱伝達用導体を通して伝達され放熱される。この際、
従来のヒートシンクが基板内に配置されていると考える
ならば熱伝達用導体の体積を大きくすることにより過渡
熱抵抗を下げることができ、このように過渡熱抵抗を下
げることができるのでヒートシンクを薄くして定常熱抵
抗を下げることが可能となる。換言すれば、従来のよう
に表層の上方に突出したヒートシンクは不要、もしくは
ヒートシンクを小さくすることが可能となる。The heat generated by the power element is transferred and radiated through the heat transfer conductor filled in the substrate. On this occasion,
If you think that a conventional heat sink is placed in the substrate, you can reduce the transient thermal resistance by increasing the volume of the heat transfer conductor. As a result, the steady-state thermal resistance can be reduced. In other words, it is not necessary to use a heat sink protruding above the surface layer as in the conventional case, or it is possible to reduce the size of the heat sink.

【０００７】[0007]

【実施例】以下、この発明を具体化した一実施例を図面
に従って説明する。図１に全体構成図を示す。３つのア
ルミナよりなる絶縁層１ａ，１ｂ，１ｃを重ねて多層基
板２が形成されている。多層基板２の最上層の絶縁層１
ａにおける所定領域には充填金属収納用貫通部３が形成
され、この充填金属収納用貫通部３内に熱伝導性のよい
熱伝達用導体としての充填金属４が充填されている。こ
の充填金属４は、絶縁層１ｂにおける内層配線５と電気
的に接続されている。又、充填金属４には、高融点材料
であるＭｏ（モリブデン）粒子とアルミナ粒子の混合物
が用いられている。ここで、Ｍｏ（モリブデン）は、そ
の熱伝導度が０．３２８ｃａｌ・ｃｍ-1ｄｅｇ-1ｓ
-1（２０℃）、融点が２６２２±１０℃である。他の充
填金属４としては、高融点材料であるＷ（タングステ
ン）粒子とアルミナ粒子の混合物、あるいは、Ｍｏ（モ
リブデン）粒子とＷ（タングステン）粒子とアルミナ粒
子との混合物が使用される。ここで、Ｗ（タングステ
ン）は、その熱伝導度が０．３８２ｃａｌ・ｃｍ-1ｄｅ
ｇ-1ｓ-1（２０℃）、融点が３３８２℃である。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows an overall configuration diagram. A multi-layer substrate 2 is formed by stacking three insulating layers 1a, 1b, 1c made of alumina. The uppermost insulating layer 1 of the multilayer substrate 2
A through hole 3 for storing the filled metal is formed in a predetermined region of a, and the through hole 3 for storing the filled metal is filled with the filled metal 4 as a heat transfer conductor having good thermal conductivity. The filling metal 4 is electrically connected to the inner layer wiring 5 in the insulating layer 1b. The filling metal 4 is a mixture of Mo (molybdenum) particles and alumina particles, which are high melting point materials. Here, Mo (molybdenum) has a thermal conductivity of 0.328 cal · cm −1 deg −1 s.
−1 (20 ° C.), melting point 2622 ± 10 ° C. As the other filling metal 4, a mixture of W (tungsten) particles and alumina particles, which is a high melting point material, or a mixture of Mo (molybdenum) particles, W (tungsten) particles and alumina particles is used. Here, the thermal conductivity of W (tungsten) is 0.382 cal · cm −1 de
g −1 s −1 (20 ° C.), melting point 3382 ° C.

【０００８】充填金属４の上にはパワー素子６が半田
（あるいはＡｇペースト）によりダイマウントされてい
る。又、パワー素子６はワイヤ７にて多層基板２の最上
層の絶縁層１ａ上の導体部と電気的に接続されている。A power element 6 is die-mounted on the filling metal 4 with solder (or Ag paste). The power element 6 is electrically connected by a wire 7 to a conductor portion on the uppermost insulating layer 1a of the multilayer substrate 2.

【０００９】次に、多層基板２の製造方法を図２〜図６
を用いて説明する。図２に示すように、平板状のアルミ
ナグリーンシート８を用意する。このアルミナグリーン
シート８の厚みは０．２５４ｍｍである。そして、アル
ミナグリーンシート８の所定領域に正方形状の貫通溝９
をパンチングにより形成する。尚、貫通溝９はスルーホ
ールの形成と同一工程で作ってもよい。Next, a method of manufacturing the multilayer substrate 2 will be described with reference to FIGS.
Will be explained. As shown in FIG. 2, a flat alumina green sheet 8 is prepared. The thickness of this alumina green sheet 8 is 0.254 mm. Then, a square through groove 9 is formed in a predetermined area of the alumina green sheet 8.
Are formed by punching. The through groove 9 may be formed in the same process as the formation of the through hole.

【００１０】その後、図３に示すように、２枚重ねにし
たアルミナグリーンシート１０上にアルミナグリーンシ
ート８を重ね合わせる。その結果、図４のようになる。
さらに、図５に示すように、エマルジョンマスクあるい
はメタルマスクを用いてＭｏ粒子とアルミナ粒子を混合
したペースト１１を印刷により貫通溝９に充填する。Thereafter, as shown in FIG. 3, the alumina green sheet 8 is superposed on the two alumina green sheets 10 which are superposed. As a result, the result is as shown in FIG.
Further, as shown in FIG. 5, a paste 11 in which Mo particles and alumina particles are mixed is filled in the through groove 9 by printing using an emulsion mask or a metal mask.

【００１１】その後、積層されたアルミナグリーンシー
ト８，１０を加圧し、千数百℃以上で焼成することによ
り、多層セラミック基板を得る。さらに、焼成された多
層基板の表面の導体部分（ペースト１１を焼成した充填
金属４、メタライズ）に接合性を向上させるためにメッ
キを施す。そして、多層基板の表面または裏面に厚膜導
体、厚膜抵抗体、ガラス等の印刷・焼成を繰り返す。After that, the laminated alumina green sheets 8 and 10 are pressed and fired at a temperature of not less than several thousand and several hundreds of degrees to obtain a multilayer ceramic substrate. Further, the conductor portion (filled metal 4 obtained by firing the paste 11 and metallization) on the surface of the fired multilayer substrate is plated to improve the bondability. Then, printing and firing of a thick film conductor, a thick film resistor, glass and the like are repeated on the front surface or the back surface of the multilayer substrate.

【００１２】そして、図６に示すように、ペースト１１
を焼成した充填金属４に、パワー素子６を半田（あるい
はＡｇペースト）によりダイマウントし、ワイヤ７によ
るワイヤーボンドを施す。Then, as shown in FIG.
The power element 6 is die-mounted with solder (or Ag paste) on the filled metal 4 that has been fired, and wire bonding is performed with the wire 7.

【００１３】その結果、図１に示す多層基板２が形成さ
れる。この図１の構成においては、パワー素子６に発生
する熱が充填金属４で吸収できる。又、充填金属４の成
分であるＭｏ（モリブデン）自体も極めて低抵抗である
ため、充填金属４を配線として考えた場合には基板全体
の発熱を軽減できる。As a result, the multilayer substrate 2 shown in FIG. 1 is formed. In the structure of FIG. 1, the heat generated in the power element 6 can be absorbed by the filling metal 4. Further, since Mo (molybdenum) itself which is a component of the filling metal 4 has an extremely low resistance, when the filling metal 4 is considered as a wiring, heat generation of the entire substrate can be reduced.

【００１４】さらに、充填金属４を厚くできるので、表
層導体（図１２の厚膜導体３２）を使用した場合に比べ
電気抵抗を数１０分の１にできる。さらには、熱抵抗も
例えば、Ｍｏ単体の８０〜９０％程度になるが充填金属
４の厚みや面積を大きくして充填金属４の体積を増加す
ることにより図１２のヒートシンク３４を使用したもの
よりも熱抵抗を小さくできる。Furthermore, since the filling metal 4 can be thickened, the electric resistance can be reduced to several tenths as compared with the case where the surface layer conductor (thick film conductor 32 of FIG. 12) is used. Further, the thermal resistance is, for example, about 80 to 90% of that of Mo alone, but by increasing the thickness and area of the filling metal 4 to increase the volume of the filling metal 4, the heat sink 34 of FIG. 12 is used. Can also reduce the thermal resistance.

【００１５】又、充填金属４にはＭｏ粒子に対しアルミ
ナ粒子を混合してあるので、充填金属４の熱膨張率をア
ルミナ基板の熱膨張率に近づけることができる。よっ
て、アルミナ基板と充填金属４の熱応力を低く抑えるこ
とができる。Further, since the filler metal 4 is a mixture of Mo particles and alumina particles, the coefficient of thermal expansion of the filler metal 4 can be made close to that of the alumina substrate. Therefore, the thermal stress of the alumina substrate and the filling metal 4 can be suppressed low.

【００１６】このように本実施例では、表層（絶縁層１
ａ）内に熱伝導性のよい充填金属４（熱伝達用導体）を
充填し、その充填金属４上にパワー素子６を配置した。
よって、パワー素子６で発生した熱は、表層（絶縁層１
ａ）内の充填金属４を通して伝達され放熱される。この
際、従来のヒートシンクが基板内に配置されていると考
えるならば充填金属４の体積を大きくすることにより過
渡熱抵抗を下げることができ、このように過渡熱抵抗を
下げることができるのでヒートシンクを薄くして定常熱
抵抗を下げることが可能となる。換言すれば、従来のよ
うに表層の上方に突出したヒートシンクは不要、もしく
はヒートシンクを小さくすることが可能となり、コスト
ダウンが図れるとともに実装容積を減少させることがで
きる。さらに、放熱のために高価なＡｌＮ等の基板材料
を使用する必要もなくなり安価に熱伝導性の優れた基板
を作成することが可能となる。As described above, in this embodiment, the surface layer (insulating layer 1
Filling metal 4 (heat transfer conductor) having good thermal conductivity was filled in a), and power element 6 was arranged on the filling metal 4.
Therefore, the heat generated in the power element 6 is applied to the surface layer (insulating layer 1
It is transmitted through the filling metal 4 in a) and radiated. At this time, if it is considered that the conventional heat sink is arranged in the substrate, the transient thermal resistance can be reduced by increasing the volume of the filling metal 4, and thus the transient thermal resistance can be reduced. It is possible to reduce the steady-state thermal resistance by reducing the thickness. In other words, it is not necessary to use a heat sink protruding above the surface layer as in the conventional case, or the heat sink can be downsized, which can reduce the cost and the mounting volume. Further, it is not necessary to use an expensive substrate material such as AlN for heat dissipation, and it is possible to inexpensively produce a substrate having excellent thermal conductivity.

【００１７】又、充填金属４には、高融点材料（多層基
板２の焼成温度よりも融点の高い材料）であるＭｏ（融
点；２６２２±１０℃）の粒子を使用したので、グリー
ンシートに充填金属のペーストを充填した後、グリーン
シートを千数百℃以上で焼成しても充填金属であるＭｏ
が融けることがない。Moreover, since particles of Mo (melting point; 2622 ± 10 ° C.), which is a high melting point material (a material having a melting point higher than the firing temperature of the multilayer substrate 2), are used as the filling metal 4, the green sheet is filled with the particles. After filling the metal paste, even if the green sheet is fired at a temperature of more than one thousand and several hundred degrees Celsius, the filling metal Mo
Does not melt.

【００１８】尚、この発明は上記実施例に限定されるも
のでなく、例えば、図７に示すように、一層だけでなく
複数層（図７では３層）にわたり充填金属４を充填して
もよい。この場合、パワー素子６で発生した熱は、多層
基板２の裏面を接着材により固定してある金属プレート
１２にも早急に吸収することができ、金属プレート１２
よりその熱を発散させることができる。又、この場合、
グランド電位の共通化も可能となる。The present invention is not limited to the above-described embodiment. For example, as shown in FIG. 7, not only one layer but also a plurality of layers (three layers in FIG. 7) may be filled with the filling metal 4. Good. In this case, the heat generated by the power element 6 can be immediately absorbed by the metal plate 12 having the back surface of the multilayer substrate 2 fixed by an adhesive material.
More that heat can be dissipated. Also, in this case,
It is possible to share the ground potential.

【００１９】又、図８，９のように、多層基板２の最上
層の絶縁層１ａにおいて充填金属１３を延設状態にて配
置し、その充填金属１３の上にパワー素子１４と１５と
を離間して配置する。即ち、パワー素子１４とパワー素
子１５とを充填金属１３にて電気的に接続してもよい。Further, as shown in FIGS. 8 and 9, the filler metal 13 is arranged in an extended state in the uppermost insulating layer 1a of the multilayer substrate 2, and the power elements 14 and 15 are disposed on the filler metal 13. Place them separately. That is, the power element 14 and the power element 15 may be electrically connected by the filling metal 13.

【００２０】さらに、図１０に示すように、多層基板２
の最上層の絶縁層１ａに充填金属１６を配置するととも
にその充填金属１６の上にパワー素子１７を配置する。
一方、多層基板２の最上層の絶縁層１ａにおいて充填金
属１６とは離間して充填金属１８を配置するとともにそ
の充填金属１８の上にパワー素子１９を配置する。さら
に、多層基板２の絶縁層１ｂに層内での平面方向への配
線を行わせるための配線材料２０を充填する。即ち、絶
縁層１ａの充填金属１６と充填金属１８とを、絶縁層１
ｂの配線材料２０で電気的に接続してもよい。Further, as shown in FIG.
The filling metal 16 is arranged on the uppermost insulating layer 1 a, and the power element 17 is arranged on the filling metal 16.
On the other hand, in the uppermost insulating layer 1 a of the multilayer substrate 2, the filling metal 18 is arranged apart from the filling metal 16 and the power element 19 is arranged on the filling metal 18. Further, the insulating layer 1b of the multilayer substrate 2 is filled with a wiring material 20 for performing wiring in the plane direction within the layer. That is, the filling metal 16 and the filling metal 18 of the insulating layer 1a are
Electrical connection may be made with the wiring material 20 of b.

【００２１】又、図１１に示すように、多層基板２の最
上層の絶縁層１ａには充填金属を配置せず、２層目以降
の絶縁層１ｂ，１ｃのみ充填金属を配置するようにして
もよい。Further, as shown in FIG. 11, the filling metal is not arranged in the uppermost insulating layer 1a of the multilayer substrate 2, but the filling metal is arranged only in the second and subsequent insulating layers 1b and 1c. Good.

【００２２】又、基板材質としてはガラスとセラミック
の複合材料であるガラスセラミックまたはガラス材を用
いてもよい。この場合の導体材は、Ａｇ，Ａｇ−Ｐｄ，
Ｃｕ等を用いる。製法はアルミナの場合と同一である。Further, as the substrate material, glass ceramic or glass material which is a composite material of glass and ceramic may be used. In this case, the conductor material is Ag, Ag-Pd,
Cu or the like is used. The manufacturing method is the same as that for alumina.

【００２３】[0023]

【発明の効果】以上詳述したようにこの発明によれば、
過渡ならびに定常熱抵抗を下げることができる。又、表
層の上方に突出したヒートシンクを無くす、あるいは小
さくすることができるから実装容積を減少させることが
できる。さらに、放熱のために高価なＡｌＮ等の基板材
料を使用する必要もなくなり安価に熱伝導性の優れた基
板を作成することが可能となる。As described above in detail, according to the present invention,
The transient and steady-state thermal resistance can be reduced. Further, since the heat sink protruding above the surface layer can be eliminated or made small, the mounting volume can be reduced. Further, it is not necessary to use an expensive substrate material such as AlN for heat dissipation, and it is possible to inexpensively produce a substrate having excellent thermal conductivity.

【図面の簡単な説明】[Brief description of drawings]

【図１】実施例の多層基板の断面図である。FIG. 1 is a cross-sectional view of a multilayer substrate of an example.

【図２】多層基板の製造工程図である。FIG. 2 is a manufacturing process diagram of a multilayer substrate.

【図３】多層基板の製造工程図である。FIG. 3 is a manufacturing process diagram of a multilayer substrate.

【図４】多層基板の製造工程図である。FIG. 4 is a manufacturing process diagram of a multilayer substrate.

【図５】多層基板の製造工程図である。FIG. 5 is a manufacturing process diagram of a multilayer substrate.

【図６】多層基板の製造工程図である。FIG. 6 is a manufacturing process diagram of a multilayer substrate.

【図７】別例の多層基板の断面図である。FIG. 7 is a cross-sectional view of another example of a multilayer substrate.

【図８】他の別例の多層基板の平面図である。FIG. 8 is a plan view of another example of a multilayer substrate.

【図９】他の別例の多層基板の断面図である。FIG. 9 is a cross-sectional view of another example of a multilayer substrate.

【図１０】他の別例の多層基板の断面図である。FIG. 10 is a cross-sectional view of another example of a multilayer substrate.

【図１１】他の別例の多層基板の断面図である。FIG. 11 is a cross-sectional view of another example of a multilayer substrate.

【図１２】従来の多層基板の断面図である。FIG. 12 is a cross-sectional view of a conventional multilayer substrate.

【符号の説明】[Explanation of symbols]

１ａ 表層（絶縁層） ４ 熱伝達用導体としての充填金属 ６ パワー素子 1a Surface layer (insulating layer) 4 Filling metal as heat transfer conductor 6 Power element

Claims (1)

【特許請求の範囲】[Claims] 【請求項１】 複数の絶縁層からなる多層基板上にパワ
ー素子を配置し、一以上の絶縁層のパワー素子下部領域
に前記パワー素子の熱伝達用導体を充填したことを特徴
とする多層基板。1. A multi-layer substrate comprising a power element arranged on a multi-layer substrate composed of a plurality of insulating layers, and a heat transfer conductor of the power element being filled in a lower region of the power element of one or more insulation layers. .
JP30682493A 1993-12-07 1993-12-07 Multilayer board Expired - Fee Related JP3520540B2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP30682493A JP3520540B2 (en) 1993-12-07 1993-12-07 Multilayer board
DE4443424A DE4443424B4 (en) 1993-12-07 1994-12-06 Arrangements of a multilayer substrate and a power element and method for their preparation

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP30682493A JP3520540B2 (en) 1993-12-07 1993-12-07 Multilayer board

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2003304692A Division JP2004006993A (en) 2003-08-28 2003-08-28 Multilayer substrate

Publications (2)

Publication Number Publication Date
JPH07162157A true JPH07162157A (en) 1995-06-23
JP3520540B2 JP3520540B2 (en) 2004-04-19

Family

ID=17961705

Family Applications (1)

Application Number Title Priority Date Filing Date
JP30682493A Expired - Fee Related JP3520540B2 (en) 1993-12-07 1993-12-07 Multilayer board

Country Status (2)

Country Link
JP (1) JP3520540B2 (en)
DE (1) DE4443424B4 (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
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US5731067A (en) * 1995-06-07 1998-03-24 Denso Corporation Multi-layered substrate
JP2006140360A (en) * 2004-11-12 2006-06-01 Ngk Spark Plug Co Ltd Wiring board
JP4630041B2 (en) * 2004-11-12 2011-02-09 日本特殊陶業株式会社 Wiring board manufacturing method
JP2018530161A (en) * 2015-10-01 2018-10-11 エルジー イノテック カンパニー リミテッド Light emitting device, method for manufacturing light emitting device, and light emitting module

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DE4443424B4 (en) 2009-07-09
DE4443424A1 (en) 1995-06-08

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