JP3520540B2 - Multilayer board - Google Patents

Multilayer board

Info

Publication number
JP3520540B2
JP3520540B2 JP30682493A JP30682493A JP3520540B2 JP 3520540 B2 JP3520540 B2 JP 3520540B2 JP 30682493 A JP30682493 A JP 30682493A JP 30682493 A JP30682493 A JP 30682493A JP 3520540 B2 JP3520540 B2 JP 3520540B2
Authority
JP
Japan
Prior art keywords
power element
multilayer substrate
substrate
filling
multilayer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP30682493A
Other languages
Japanese (ja)
Other versions
JPH07162157A (en
Inventor
浅井　　康富
長坂　　崇
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Denso Corp
Original Assignee
Denso Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Denso Corp filed Critical Denso Corp
Priority to JP30682493A priority Critical patent/JP3520540B2/en
Priority to DE4443424A priority patent/DE4443424B4/en
Publication of JPH07162157A publication Critical patent/JPH07162157A/en
Application granted granted Critical
Publication of JP3520540B2 publication Critical patent/JP3520540B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H—ELECTRICITY
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    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】この発明は多層基板に関するもの
である。[Field of the Invention The present invention is relates to multi-layer substrate.

【０００２】[0002]

【従来の技術】従来、多層基板においては、例えば、図
１２に示すように、多層よりなるセラミック基板３１上
にＣｕやＡｇよりなる厚膜導体３２が印刷焼成にて形成
され、その上に半田３３を介してＭｏやＣｕよりなるヒ
ートシンク３４が配置され、さらにその上に半田３５を
介してパワー素子３６が実装されている。尚、図中、３
７はワイヤであり、３８はチップターミナルである。2. Description of the Related Art Conventionally, in a multilayer substrate, for example, as shown in FIG. 12, a thick film conductor 32 made of Cu or Ag is formed by printing and firing on a multilayer ceramic substrate 31, and solder is formed thereon. A heat sink 34 made of Mo or Cu is arranged via 33, and a power element 36 is mounted thereon via solder 35. In the figure, 3
7 is a wire and 38 is a chip terminal.

【０００３】[0003]

【発明が解決しようとする課題】ところが、この構造で
は、過渡的な熱抵抗を下げる必要があるものは、ヒート
シンク３４を厚く（体積を増加）しなければならず、ヒ
ートシンク３４のコストアップ及び実装容積の拡大を招
いていた。さらに、定常熱抵抗を下げるためには、熱伝
導性のよい基板材料を用いる必要があり、これは材料の
コストアップにつながる。又、定常熱抵抗を下げるため
にはヒートシンク３４を薄くしてパワー素子から基板底
面までの距離を小さくし、基板底面からの放熱性を向上
させる必要があったが、ヒートシンク３４を薄くするこ
とは過渡熱抵抗を下げることと相反することとなってし
まっていた。However, in this structure, if the transient thermal resistance needs to be reduced, the heat sink 34 must be made thicker (volume increased), which increases the cost and mounting of the heat sink 34. This has led to an increase in volume. Further, in order to reduce the steady-state thermal resistance, it is necessary to use a substrate material having good thermal conductivity, which leads to an increase in material cost. Further, in order to reduce the steady-state thermal resistance, it is necessary to make the heat sink 34 thin to reduce the distance from the power element to the bottom surface of the substrate to improve the heat dissipation from the bottom surface of the substrate. It had become the opposite of reducing the transient thermal resistance.

【０００４】そこで、この発明の目的は、過渡ならびに
定常熱抵抗を下げることができる多層基板を提供するこ
とにある。Therefore, an object of the present invention is to provide a multilayer substrate which can reduce transient and steady-state thermal resistance.

【０００５】[0005]

【課題を解決するための手段】上記目的を達成するため
に、請求項１に記載の発明は、複数の絶縁層からなる多
層基板上に少なくとも１個のパワー素子を配置した多層
基板にあって、一以上の絶縁層の前記パワー素子下部領
域に、前記パワー素子側に開口する開口部の面積が前記
多層基板と対面配置されたパワー素子における前記多層
基板に対する対向面の面積以上となる充填部を形成し、
該充填部に前記パワー素子の熱伝達用導体を充填したも
のであって、前記多層基板上には、複数個のパワー素子
が配置され、前記絶縁層のうち所定の絶縁層に各パワー
素子の熱伝達用導体を電気的に接続する配線材料を充填
したことを要旨とする。請求項２に記載の発明は、複数
の絶縁層からなる多層基板上に少なくとも１個のパワー
素子を配置した多層基板にあって、一以上の絶縁層の前
記パワー素子下部領域に、前記パワー素子側に開口する
開口部の面積が前記多層基板と対面配置されたパワー素
子における前記多層基板に対する対向面の面積以上にな
っている前記充填部を形成し、該充填部に前記パワー素
子の熱伝達用導体を充填したものであって、前記パワー
素子と該パワー素子の熱伝達用導体の間には、少なくと
も一層の絶縁層が介在されていることを要旨とする。請
求項３に記載の発明は、請求項１又は請求項２の発明に
おいて、前記パワー素子における前記多層基板に対する
対向面の外郭形状は四角形状をなし、前記充填部の開口
部の開口形状は四角形状をなすように形成されているこ
とを要旨とする。請求項４に記載の発明は、請求項１乃
至３の何れか１つの発明において、前記充填部が形成さ
れた一以上の絶縁層の下層には、少なくとも一層の絶縁
層が介在されていることを要旨とする。請求項５に記載
の発明は、請求項１の発明において、前記充填部は、前
記多層基板の表面から裏面へ貫通形成されていることを
要旨とする。In order to achieve the above object, the invention according to claim 1 is a multi-layer substrate in which at least one power element is arranged on a multi-layer substrate including a plurality of insulating layers. A filling portion in which a surface area of an opening opening to the power element side in the power element lower region of one or more insulating layers is equal to or larger than an area of a facing surface of the power element facing the multilayer substrate. To form
The filling portion is filled with a heat transfer conductor of the power element, and a plurality of power elements are arranged on the multilayer substrate, and a predetermined insulating layer of the insulating layer is provided for each power element. The gist is that the wiring material for electrically connecting the heat transfer conductor is filled. The invention according to claim 2 is a multilayer substrate in which at least one power element is arranged on a multilayer substrate composed of a plurality of insulating layers, wherein the power element is provided in the lower region of the power element of one or more insulating layers. The filling portion is formed such that the area of the opening portion that opens to the side is equal to or larger than the area of the facing surface of the power element that faces the multilayer substrate and faces the multilayer substrate, and the heat transfer of the power element to the filling portion is formed. The gist of the present invention is that it is filled with a power conductor, and at least one insulating layer is interposed between the power element and the heat transfer conductor of the power element. According to a third aspect of the present invention, in the first or second aspect of the invention, the outer surface of the surface of the power element facing the multilayer substrate has a quadrangular shape, and the opening of the filling portion has a square shape. The gist is that it is formed to have a shape. The invention according to claim 4 is the invention according to any one of claims 1 to 3, wherein at least one insulating layer is interposed below one or more insulating layers in which the filling portions are formed. Is the gist. According to a fifth aspect of the invention, in the first aspect of the invention, the filling portion is formed so as to penetrate from the front surface to the back surface of the multilayer substrate.

【０００６】[0006]

【作用】請求項１〜請求項５の発明では、パワー素子で
発生した熱は、基板内に充填された熱伝達用導体を通し
て伝達され放熱される。この際、従来のヒートシンクが
基板内に配置されていると考えるならば熱伝達用導体の
体積を大きくすることにより過渡熱抵抗を下げることが
でき、このように過渡熱抵抗を下げることができるので
ヒートシンクを薄くして定常熱抵抗を下げることが可能
となる。換言すれば、従来のように表層の上方に突出し
たヒートシンクは不要、もしくはヒートシンクを小さく
することが可能となる。 According to the first to fifth aspects of the invention, the heat generated in the power element is transferred and radiated through the heat transfer conductor filled in the substrate. At this time, if it is considered that the conventional heat sink is arranged in the substrate, the transient thermal resistance can be lowered by increasing the volume of the heat transfer conductor, and thus the transient thermal resistance can be lowered. It becomes possible to reduce the steady-state thermal resistance by thinning the heat sink. In other words, it is not necessary to use a heat sink protruding above the surface layer as in the conventional case, or it is possible to reduce the size of the heat sink .

【０００７】[0007]

【実施例】以下、この発明を具体化した一実施例を図面
に従って説明する。図１に全体構成図を示す。３つのア
ルミナよりなる絶縁層１ａ，１ｂ，１ｃを重ねて多層基
板２が形成されている。多層基板２の最上層の絶縁層１
ａにおける所定領域には充填部としての充填金属収納用
貫通部３が形成され、この充填金属収納用貫通部３内に
熱伝導性のよい熱伝達用導体としての充填金属４が充填
されている。この充填金属４は、絶縁層１ｂにおける内
層配線５と電気的に接続されている。又、充填金属４に
は、高融点材料であるＭｏ（モリブデン）粒子とアルミ
ナ粒子の混合物が用いられている。ここで、Ｍｏ（モリ
ブデン）は、その熱伝導度が０．３２８ｃａｌ・ｃｍ
−１ｄｅｇ−１ｓ−１（２０℃）、融点が２６２２±１
０℃である。他の充填金属４としては、高融点材料であ
るＷ（タングステン）粒子とアルミナ粒子の混合物、あ
るいは、Ｍｏ（モリブデン）粒子とＷ（タングステン）
粒子とアルミナ粒子との混合物が使用される。ここで、
Ｗ（タングステン）は、その熱伝導度が０．３８２ｃａ
ｌ・ｃｍ−１ｄｅｇ−１ｓ−１（２０℃）、融点が３３
８２℃である。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows an overall configuration diagram. A multi-layer substrate 2 is formed by stacking three insulating layers 1a, 1b, 1c made of alumina. The uppermost insulating layer 1 of the multilayer substrate 2
A through hole 3 for storing the filled metal as a filling portion is formed in a predetermined region of a, and the through hole 3 for storing the filled metal is filled with the filling metal 4 as a heat transfer conductor having good thermal conductivity. . The filling metal 4 is electrically connected to the inner layer wiring 5 in the insulating layer 1b. The filling metal 4 is a mixture of Mo (molybdenum) particles and alumina particles, which are high melting point materials. Here, Mo (molybdenum) has a thermal conductivity of 0.328 cal · cm.
−1 deg −1 s −1 (20 ° C.), melting point 2622 ± 1
It is 0 ° C. As the other filling metal 4, a mixture of W (tungsten) particles and alumina particles, which are high melting point materials, or Mo (molybdenum) particles and W (tungsten).
A mixture of particles and alumina particles is used. here,
The thermal conductivity of W (tungsten) is 0.382 ca.
l · cm −1 deg −1 s −1 (20 ° C.), melting point 33
It is 82 degreeC.

【０００８】充填金属４の上にはパワー素子６が半田
（あるいはＡｇペースト）によりダイマウントされてい
る。又、パワー素子６はワイヤ７にて多層基板２の最上
層の絶縁層１ａ上の導体部と電気的に接続されている。A power element 6 is die-mounted on the filling metal 4 with solder (or Ag paste). The power element 6 is electrically connected by a wire 7 to a conductor portion on the uppermost insulating layer 1a of the multilayer substrate 2.

【０００９】次に、多層基板２の製造方法を図２〜図６
を用いて説明する。図２に示すように、平板状のアルミ
ナグリーンシート８を用意する。このアルミナグリーン
シート８の厚みは０．２５４ｍｍである。そして、アル
ミナグリーンシート８の所定領域に正方形状の貫通溝９
をパンチングにより形成する。尚、貫通溝９はスルーホ
ールの形成と同一工程で作ってもよい。Next, a method of manufacturing the multilayer substrate 2 will be described with reference to FIGS.
Will be explained. As shown in FIG. 2, a flat alumina green sheet 8 is prepared. The thickness of this alumina green sheet 8 is 0.254 mm. Then, a square through groove 9 is formed in a predetermined area of the alumina green sheet 8.
Are formed by punching. The through groove 9 may be formed in the same process as the formation of the through hole.

【００１０】その後、図３に示すように、２枚重ねにし
たアルミナグリーンシート１０上にアルミナグリーンシ
ート８を重ね合わせる。その結果、図４のようになる。
さらに、図５に示すように、エマルジョンマスクあるい
はメタルマスクを用いてＭｏ粒子とアルミナ粒子を混合
したペースト１１を印刷により貫通溝９に充填する。Thereafter, as shown in FIG. 3, the alumina green sheet 8 is superposed on the two alumina green sheets 10 which are superposed. As a result, the result is as shown in FIG.
Further, as shown in FIG. 5, a paste 11 in which Mo particles and alumina particles are mixed is filled in the through groove 9 by printing using an emulsion mask or a metal mask.

【００１１】その後、積層されたアルミナグリーンシー
ト８，１０を加圧し、千数百℃以上で焼成することによ
り、多層セラミック基板を得る。さらに、焼成された多
層基板の表面の導体部分（ペースト１１を焼成した充填
金属４、メタライズ）に接合性を向上させるためにメッ
キを施す。そして、多層基板の表面または裏面に厚膜導
体、厚膜抵抗体、ガラス等の印刷・焼成を繰り返す。After that, the laminated alumina green sheets 8 and 10 are pressed and fired at a temperature of not less than several thousand and several hundreds of degrees to obtain a multilayer ceramic substrate. Further, the conductor portion (filled metal 4 obtained by firing the paste 11 and metallization) on the surface of the fired multilayer substrate is plated to improve the bondability. Then, printing and firing of a thick film conductor, a thick film resistor, glass and the like are repeated on the front surface or the back surface of the multilayer substrate.

【００１２】そして、図６に示すように、ペースト１１
を焼成した充填金属４に、パワー素子６を半田（あるい
はＡｇペースト）によりダイマウントし、ワイヤ７によ
るワイヤーボンドを施す。Then, as shown in FIG.
The power element 6 is die-mounted with solder (or Ag paste) on the filled metal 4 that has been fired, and wire bonding is performed with the wire 7.

【００１３】その結果、図１に示す多層基板２が形成さ
れる。この図１の構成においては、パワー素子６に発生
する熱が充填金属４で吸収できる。又、充填金属４の成
分であるＭｏ（モリブデン）自体も極めて低抵抗である
ため、充填金属４を配線として考えた場合には基板全体
の発熱を軽減できる。As a result, the multilayer substrate 2 shown in FIG. 1 is formed. In the structure of FIG. 1, the heat generated in the power element 6 can be absorbed by the filling metal 4. Further, since Mo (molybdenum) itself which is a component of the filling metal 4 has an extremely low resistance, when the filling metal 4 is considered as a wiring, heat generation of the entire substrate can be reduced.

【００１４】さらに、充填金属４を厚くできるので、表
層導体（図１２の厚膜導体３２）を使用した場合に比べ
電気抵抗を数１０分の１にできる。さらには、熱抵抗も
例えば、Ｍｏ単体の８０〜９０％程度になるが充填金属
４の厚みや面積を大きくして充填金属４の体積を増加す
ることにより図１２のヒートシンク３４を使用したもの
よりも熱抵抗を小さくできる。Furthermore, since the filling metal 4 can be thickened, the electric resistance can be reduced to several tenths as compared with the case where the surface layer conductor (thick film conductor 32 of FIG. 12) is used. Further, the thermal resistance is, for example, about 80 to 90% of that of Mo alone, but by increasing the thickness and area of the filling metal 4 to increase the volume of the filling metal 4, the heat sink 34 of FIG. 12 is used. Can also reduce the thermal resistance.

【００１５】又、充填金属４にはＭｏ粒子に対しアルミ
ナ粒子を混合してあるので、充填金属４の熱膨張率をア
ルミナ基板の熱膨張率に近づけることができる。よっ
て、アルミナ基板と充填金属４の熱応力を低く抑えるこ
とができる。Further, since the filler metal 4 is a mixture of Mo particles and alumina particles, the coefficient of thermal expansion of the filler metal 4 can be made close to that of the alumina substrate. Therefore, the thermal stress of the alumina substrate and the filling metal 4 can be suppressed low.

【００１６】このように本実施例では、表層（絶縁層１
ａ）内に熱伝導性のよい充填金属４（熱伝達用導体）を
充填し、その充填金属４上にパワー素子６を配置した。
よって、パワー素子６で発生した熱は、表層（絶縁層１
ａ）内の充填金属４を通して伝達され放熱される。この
際、従来のヒートシンクが基板内に配置されていると考
えるならば充填金属４の体積を大きくすることにより過
渡熱抵抗を下げることができ、このように過渡熱抵抗を
下げることができるのでヒートシンクを薄くして定常熱
抵抗を下げることが可能となる。換言すれば、従来のよ
うに表層の上方に突出したヒートシンクは不要、もしく
はヒートシンクを小さくすることが可能となり、コスト
ダウンが図れるとともに実装容積を減少させることがで
きる。さらに、放熱のために高価なＡｌＮ等の基板材料
を使用する必要もなくなり安価に熱伝導性の優れた基板
を作成することが可能となる。As described above, in this embodiment, the surface layer (insulating layer 1
Filling metal 4 (heat transfer conductor) having good thermal conductivity was filled in a), and power element 6 was arranged on the filling metal 4.
Therefore, the heat generated in the power element 6 is applied to the surface layer (insulating layer 1
It is transmitted through the filling metal 4 in a) and radiated. At this time, if it is considered that the conventional heat sink is arranged in the substrate, the transient thermal resistance can be reduced by increasing the volume of the filling metal 4, and thus the transient thermal resistance can be reduced. It is possible to reduce the steady-state thermal resistance by reducing the thickness. In other words, it is not necessary to use a heat sink protruding above the surface layer as in the conventional case, or the heat sink can be downsized, which can reduce the cost and the mounting volume. Further, it is not necessary to use an expensive substrate material such as AlN for heat dissipation, and it is possible to inexpensively produce a substrate having excellent thermal conductivity.

【００１７】又、充填金属４には、高融点材料（多層基
板２の焼成温度よりも融点の高い材料）であるＭｏ（融
点；２６２２±１０℃）の粒子を使用したので、グリー
ンシートに充填金属のペーストを充填した後、グリーン
シートを千数百℃以上で焼成しても充填金属であるＭｏ
が融けることがない。Further, since particles of Mo (melting point; 2622 ± 10 ° C.), which is a high melting point material (a material having a melting point higher than the firing temperature of the multilayer substrate 2), are used as the filling metal 4, the green sheet is filled with the particles. After filling the metal paste, even if the green sheet is fired at a temperature of more than one thousand and several hundred degrees Celsius, the filling metal Mo
Does not melt.

【００１８】尚、この発明は上記実施例に限定されるも
のでなく、例えば、図７に示すように、一層だけでなく
複数層（図７では３層）にわたり充填金属４を充填して
もよい。この場合、パワー素子６で発生した熱は、多層
基板２の裏面を接着材により固定してある金属プレート
１２にも早急に吸収することができ、金属プレート１２
よりその熱を発散させることができる。又、この場合、
グランド電位の共通化も可能となる。The present invention is not limited to the above-described embodiment. For example, as shown in FIG. 7, not only one layer but also a plurality of layers (three layers in FIG. 7) may be filled with the filling metal 4. Good. In this case, the heat generated by the power element 6 can be immediately absorbed by the metal plate 12 having the back surface of the multilayer substrate 2 fixed by an adhesive material.
More that heat can be dissipated. Also, in this case,
It is possible to share the ground potential.

【００１９】又、図８，９のように、多層基板２の最上
層の絶縁層１ａにおいて充填金属１３を延設状態にて配
置し、その充填金属１３の上にパワー素子１４と１５と
を離間して配置する。即ち、パワー素子１４とパワー素
子１５とを充填金属１３にて電気的に接続してもよい。Further, as shown in FIGS. 8 and 9, the filler metal 13 is arranged in an extended state in the uppermost insulating layer 1a of the multilayer substrate 2, and the power elements 14 and 15 are disposed on the filler metal 13. Place them separately. That is, the power element 14 and the power element 15 may be electrically connected by the filling metal 13.

【００２０】さらに、図１０に示すように、多層基板２
の最上層の絶縁層１ａに充填金属１６を配置するととも
にその充填金属１６の上にパワー素子１７を配置する。
一方、多層基板２の最上層の絶縁層１ａにおいて充填金
属１６とは離間して充填金属１８を配置するとともにそ
の充填金属１８の上にパワー素子１９を配置する。さら
に、多層基板２の絶縁層１ｂに層内での平面方向への配
線を行わせるための配線材料２０を充填する。即ち、絶
縁層１ａの充填金属１６と充填金属１８とを、絶縁層１
ｂの配線材料２０で電気的に接続してもよい。Further, as shown in FIG.
The filling metal 16 is arranged on the uppermost insulating layer 1 a, and the power element 17 is arranged on the filling metal 16.
On the other hand, in the uppermost insulating layer 1 a of the multilayer substrate 2, the filling metal 18 is arranged apart from the filling metal 16 and the power element 19 is arranged on the filling metal 18. Further, the insulating layer 1b of the multilayer substrate 2 is filled with a wiring material 20 for performing wiring in the plane direction within the layer. That is, the filling metal 16 and the filling metal 18 of the insulating layer 1a are
Electrical connection may be made with the wiring material 20 of b.

【００２１】又、図１１に示すように、多層基板２の最
上層の絶縁層１ａには充填金属を配置せず、２層目以降
の絶縁層１ｂ，１ｃのみ充填金属を配置するようにして
もよい。Further, as shown in FIG. 11, the filling metal is not arranged in the uppermost insulating layer 1a of the multilayer substrate 2, but the filling metal is arranged only in the second and subsequent insulating layers 1b and 1c. Good.

【００２２】又、基板材質としてはガラスとセラミック
の複合材料であるガラスセラミックまたはガラス材を用
いてもよい。この場合の導体材は、Ａｇ，Ａｇ−Ｐｄ，
Ｃｕ等を用いる。製法はアルミナの場合と同一である。Further, as the substrate material, glass ceramic or glass material which is a composite material of glass and ceramic may be used. In this case, the conductor material is Ag, Ag-Pd,
Cu or the like is used. The manufacturing method is the same as that for alumina.

【００２３】[0023]

【発明の効果】以上詳述したように請求項１〜請求項５
に記載の発明によれば、過渡ならびに定常熱抵抗を下げ
ることができる。又、表層の上方に突出したヒートシン
クを無くす、あるいは小さくすることができるから実装
容積を減少させることができる。さらに、放熱のために
高価なＡｌＮ等の基板材料を使用する必要もなくなり安
価に熱伝導性の優れた基板を作成することが可能とな
る。 As described in detail above, the first to fifth aspects of the invention are described.
According to the invention described in (1), transient and steady-state thermal resistance can be reduced. Further, since the heat sink protruding above the surface layer can be eliminated or made small, the mounting volume can be reduced. Furthermore, it is possible to create a superior substrate of expensive necessary to use a substrate material such as AlN even eliminates low cost thermal conductivity for heat dissipation
It

【図面の簡単な説明】[Brief description of drawings]

【図１】実施例の多層基板の断面図である。FIG. 1 is a cross-sectional view of a multilayer substrate of an example.

【図２】多層基板の製造工程図である。FIG. 2 is a manufacturing process diagram of a multilayer substrate.

【図３】多層基板の製造工程図である。FIG. 3 is a manufacturing process diagram of a multilayer substrate.

【図４】多層基板の製造工程図である。FIG. 4 is a manufacturing process diagram of a multilayer substrate.

【図５】多層基板の製造工程図である。FIG. 5 is a manufacturing process diagram of a multilayer substrate.

【図６】多層基板の製造工程図である。FIG. 6 is a manufacturing process diagram of a multilayer substrate.

【図７】別例の多層基板の断面図である。FIG. 7 is a cross-sectional view of another example of a multilayer substrate.

【図８】他の別例の多層基板の平面図である。FIG. 8 is a plan view of another example of a multilayer substrate.

【図９】他の別例の多層基板の断面図である。FIG. 9 is a cross-sectional view of another example of a multilayer substrate.

【図１０】他の別例の多層基板の断面図である。FIG. 10 is a cross-sectional view of another example of a multilayer substrate.

【図１１】他の別例の多層基板の断面図である。FIG. 11 is a cross-sectional view of another example of a multilayer substrate.

【図１２】従来の多層基板の断面図である。FIG. 12 is a cross-sectional view of a conventional multilayer substrate.

【符号の説明】[Explanation of symbols]

１ａ 表層（絶縁層）３ 充填部としての充填金属収納用貫通部 ４ 熱伝達用導体としての充填金属 ６ パワー素子２０ 配線材料 1a Surface Layer (Insulating Layer) 3 Filled Metal Storage Penetration Part as Filling Part 4 Filling Metal as Heat Transfer Conductor 6 Power Element 20 Wiring Material

───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平５−63372（ＪＰ，Ａ) 特開 昭50−143073（ＪＰ，Ａ) 特開 昭62−224951（ＪＰ，Ａ) 特開 昭61−288448（ＪＰ，Ａ) 特開 昭64−9644（ＪＰ，Ａ) 特開 平７−130907（ＪＰ，Ａ) (58)調査した分野(Int.Cl.7，ＤＢ名) H05K 3/46 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-5-63372 (JP, A) JP-A-50-143073 (JP, A) JP-A-62-224951 (JP, A) JP-A-61-1 288448 (JP, A) JP 64-9644 (JP, A) JP 7-130907 (JP, A) (58) Fields investigated (Int.Cl. 7 , DB name) H05K 3/46

Claims (5)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】 複数の絶縁層からなる多層基板上に少な
くとも１個のパワー素子を配置した多層基板にあって、
一以上の絶縁層の前記パワー素子下部領域に、前記パワ
ー素子側に開口する開口部の面積が前記多層基板と対面
配置されたパワー素子における前記多層基板に対する対
向面の面積以上となる充填部を形成し、該充填部に前記
パワー素子の熱伝達用導体を充填したものであって、 前記多層基板上には、複数個のパワー素子が配置され、
前記絶縁層のうち所定の絶縁層に各パワー素子の熱伝達
用導体を電気的に接続する配線材料を充填したことを特
徴とする多層基板。1. A multilayer substrate in which at least one power element is arranged on a multilayer substrate composed of a plurality of insulating layers,
In the power element lower region of one or more insulating layers, a filling portion in which an area of an opening opening to the power element side is equal to or larger than an area of a surface facing the multilayer substrate in a power element facing the multilayer substrate. Which is formed by filling the filling portion with the heat transfer conductor of the power element, wherein a plurality of power elements are arranged on the multilayer substrate,
A multilayer substrate in which a predetermined insulating layer among the insulating layers is filled with a wiring material for electrically connecting the heat transfer conductors of the respective power elements. 【請求項２】 複数の絶縁層からなる多層基板上に少な
くとも１個のパワー素子を配置した多層基板にあって、
一以上の絶縁層の前記パワー素子下部領域に、前記パワ
ー素子側に開口する開口部の面積が前記多層基板と対面
配置されたパワー素子における前記多層基板に対する対
向面の面積以上になっている前記充填部を形成し、該充
填部に前記パワー素子の熱伝達用導体を充填したもので
あって、 前記パワー素子と該パワー素子の熱伝達用導体の間に
は、少なくとも一層の絶縁層が介在されていることを特
徴とする多層基板。2. A multilayer board in which at least one power element is arranged on a multilayer board composed of a plurality of insulating layers,
In the power element lower region of one or more insulating layers, an area of an opening opening to the power element side is equal to or more than an area of a facing surface of the power element facing the multilayer substrate with respect to the multilayer substrate. A filling portion is formed, and the filling portion is filled with a heat transfer conductor of the power element, wherein at least one insulating layer is interposed between the power element and the heat transfer conductor of the power element. A multi-layer substrate characterized by being formed. 【請求項３】 前記パワー素子における前記多層基板に
対する対向面の外郭形状は四角形状をなし、前記充填部
の開口部の開口形状は四角形状をなすように形成されて
いることを特徴とする請求項１又は請求項２に記載の多
層基板。3. The outer surface of the surface of the power element facing the multilayer substrate has a quadrangular shape, and the opening of the filling portion has a quadrangular shape. The multilayer substrate according to claim 1 or 2. 【請求項４】 前記充填部が形成された一以上の絶縁層
の下層には、少なくとも一層の絶縁層が介在されている
ことを特徴とする請求項１乃至３の何れか１つに記載の
多層基板。4. The at least one insulating layer is provided below the one or more insulating layers in which the filling portion is formed, according to claim 1. Multilayer board. 【請求項５】 前記充填部は、前記多層基板の表面から
裏面へ貫通形成されていることを特徴とする請求項１に
記載の多層基板。Wherein said filling unit, to claim 1, characterized in that is formed through the rear surface from the surface of the multilayer substrate
The multilayer substrate described .
JP30682493A 1993-12-07 1993-12-07 Multilayer board Expired - Fee Related JP3520540B2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP30682493A JP3520540B2 (en) 1993-12-07 1993-12-07 Multilayer board
DE4443424A DE4443424B4 (en) 1993-12-07 1994-12-06 Arrangements of a multilayer substrate and a power element and method for their preparation

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP30682493A JP3520540B2 (en) 1993-12-07 1993-12-07 Multilayer board

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2003304692A Division JP2004006993A (en) 2003-08-28 2003-08-28 Multilayer substrate

Publications (2)

Publication Number Publication Date
JPH07162157A JPH07162157A (en) 1995-06-23
JP3520540B2 true JP3520540B2 (en) 2004-04-19

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ID=17961705

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Application Number Title Priority Date Filing Date
JP30682493A Expired - Fee Related JP3520540B2 (en) 1993-12-07 1993-12-07 Multilayer board

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JP (1) JP3520540B2 (en)
DE (1) DE4443424B4 (en)

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JP3671457B2 (en) * 1995-06-07 2005-07-13 株式会社デンソー Multilayer board
US6376908B1 (en) 1997-12-10 2002-04-23 Mitsubishi Gas Chemical Company, Inc. Semiconductor plastic package and process for the production thereof
JP4630041B2 (en) * 2004-11-12 2011-02-09 日本特殊陶業株式会社 Wiring board manufacturing method
DE102007022947B4 (en) 2007-04-26 2022-05-05 OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung Optoelectronic semiconductor body and method for producing such
DE102009023849B4 (en) 2009-06-04 2022-10-20 OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung Optoelectronic semiconductor body and optoelectronic semiconductor chip
TW201319507A (en) * 2011-11-04 2013-05-16 Most Energy Corp Heat dissipating device and manufacture method thereof
KR102413224B1 (en) * 2015-10-01 2022-06-24 쑤저우 레킨 세미컨덕터 컴퍼니 리미티드 Light emitting device, manufacturing method for light emittin device, and lighting module

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JPS5563900A (en) * 1978-11-08 1980-05-14 Fujitsu Ltd Multilyaer ceramic circuit board
JPS55130198A (en) * 1979-03-30 1980-10-08 Hitachi Ltd Hybrid integrated circuit board for tuner
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Also Published As

Publication number Publication date
DE4443424A1 (en) 1995-06-08
DE4443424B4 (en) 2009-07-09
JPH07162157A (en) 1995-06-23

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