JP2874686B2 - Multilayer board - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention
It relates to a multilayer substrate used for C.

[0002]

2. Description of the Related Art Conventionally, a circuit wiring material printed on a green sheet is used for a green sheet laminated substrate. Among these, an alumina laminated substrate is formed by printing printed wiring made of a refractory metal such as W (tungsten) or Mo (molybdenum) as a circuit wiring material on an alumina green sheet, and a glass ceramic laminated substrate is formed on a glass ceramic green sheet. Printed wirings mainly composed of Ag (silver) or Cu (copper) are used as wiring materials.

[0003]

However, in the case of an alumina laminated substrate, the electrical resistivity of the wiring material, tungsten or molybdenum, is 5.5, 5.7 (μΩ ·
cm) and Ag used for other general thick film substrates.
The electric resistance has a value about three times as large as that of the (1.6) and Cu (1.67) materials. For this reason, it cannot be used for applications (circuits) that require a small electric resistance value between wirings.

Further, although a glass ceramic laminated substrate uses a material having a lower resistance than an alumina laminated substrate, a lower resistance is desired for applications such as communication and computers. Therefore, a conventional alumina laminated substrate using a printed wiring material such as W or Mo, and Ag, Cu
In a conventional glass-ceramic laminated substrate using a printed wiring material whose main constituent material is, the wiring cannot have a sufficiently low resistance.

An object of the present invention is to provide a multilayer substrate capable of reducing a wiring resistance value in a lateral direction with respect to a substrate .

[0006]

To achieve the above object, according to an aspect of, in the invention according to claim 1, in a multilayer substrate composed of a plurality of insulating layers are laminated, each of the insulating layer overlapping vertically A part of the opening has a plurality of through-holes which overlap each other and are provided continuously in the lateral direction of the insulating layer, and the through-holes are filled with a wiring material.

Therefore, the penetration through the overlapping portion
A horizontal current path with a large passage area is established through the through hole.
Therefore, the wiring resistance can be sufficiently reduced compared to the conventional in-layer wiring by printing. Further, according to the invention described in claim 2, the wiring material in the first aspect of the present invention, additives for matching the Netsu膨Zhang <br/> rate of the insulating layer constituting the multilayer substrate added be those which are, according to a further aspect of the present invention 3, the additive is characterized in that the material and Netsu膨Zhang of the insulating layer are substantially the same material.

Accordingly, it is possible to reduce the resistance of the wiring while improving the bondability with matching the thermal expansion coefficient between the substrate. As described above, according to the first to third aspects of the present invention, it is possible to easily realize a reduction in the resistance of the wiring in the lateral direction with respect to the substrate, and to configure a highly reliable multilayer substrate. it can.

[0009]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of the present invention; (First Embodiment) An embodiment of the present invention will be described below with reference to the drawings. A description will be given using an alumina laminated substrate as an example.

FIG. 1 is a cross-sectional view of a hybrid IC according to the present embodiment. In this hybrid IC, a multilayer substrate 2 is formed by stacking five insulating layers 1a, 1b, 1c, 1d and 1e made of alumina. In-layer wiring through-grooves 3a are formed in the insulating layer 1b of the multilayer substrate 2 as spaces for in-layer wirings, and the in-layer wiring through-grooves 3a are filled with the in-layer wiring material 4. Similarly, in-layer wiring through-grooves 3b as space portions for in-layer wiring are formed in insulating layer 1c of multilayer substrate 2, and in-layer wiring through-grooves 3b are filled with in-layer wiring material 4. . The in-layer wiring through-grooves 3a and 3b are in a strip shape. Chip components 7 and 8 are disposed on the upper surface of the multilayer substrate 2 via the surface conductor 5 and the solder 6, and printed resistors 10 and 11 are disposed via the surface conductor 9. In FIG. 1, reference numeral 12 denotes a through-hole wiring (interlayer wiring).

Next, a method of manufacturing the multilayer substrate 2 will be described with reference to FIGS.
This will be described with reference to FIGS. As shown in FIG. 2, a plate-like alumina green sheet 13 is prepared, and in-layer wiring through-grooves 3 are formed in the alumina green sheet 13 so as to extend along the plane direction of the alumina green sheet 13. For this molding, a punching method using a press is used. That is, as shown in FIG. 5, a movable mold 22 having a projection 21 is arranged to face a fixed mold 20 having a hole 19, and the alumina green sheet 13 is arranged on the fixed mold 20 to move the movable mold 22. Thereby, the through-grooves 3 for the in-layer wiring are formed.

[0012] Then, as shown in FIG.
Indicates the through-grooves 3 for wiring in the layer by a printing method using a screen.
Is filled with the intra-layer wiring material 4. W (Ta)
Nsten) is used, and Al is added as an additive._Two
O_ThreeIs added in an amount of 0.1 to 30%. Where Al_Two
O_ThreeWas added to the alumina and W (tungsten)
Of the thermal expansion coefficient of
By adding the material, the alumina base and the wiring material
This is for improving the bonding property. Also, Al_TwoO _ThreeAddition of
The reason for setting the rate to 0.1 to 30% is that the addition amount is from this range.
If the amount is large, the resistance value of the W wiring increases, and if the amount added is small,
This is because the bonding strength with the base material is reduced.

After forming the general wiring by the printing method,
Laminate as shown in FIG. That is, each alumina green sheet 13 is laminated and pressed under heating. Then, it is fired. As a result, the hybrid IC of FIG. 1 is manufactured .

As described above, in the present embodiment, the through-grooves 3a, 3b (spaces for intra-layer wiring) are formed in the insulating layers 1b, 1c of the multilayer substrate 2, and the through-grooves 3a for intra-layer wiring are formed. , 3
b was filled with the in-layer wiring material 4. Therefore, the insulating layers 1b,
In-layer wiring in which the wiring material 4 is filled in the through-grooves 3a and 3b for in-layer wiring of 1c, the current passage area is increased and the wiring resistance is reduced as compared with the conventionally printed in-layer wiring.

That is, generally, the wiring thickness by printing in the layer of the laminated substrate is about 10 to 15 μm, and the sheet resistance is 10 to 15 mΩ / □, but by adopting the structure of this embodiment, The thickness can be 10 to 40 times as large as the wiring thickness by printing, and the sheet resistance is 1 to 0.2.
mΩ / □. Further, in this embodiment, in addition to lowering the resistance of the wiring by disposing the intra-layer wiring material 4 in the through-layer vias 3a and 3b, W (tungsten) as the wiring material includes Au. , Cu, Ni, P
About 0 to 30% of d is added to further reduce the resistance. (Second Embodiment) Next, only the differences between the second embodiment and the first embodiment will be described.

As shown in FIG. 6, the insulating layer 1 of the multilayer substrate 2
b, an in-layer interconnect recess 14a as an in-layer interconnect space
Is formed, and the intra-layer wiring material 4 is filled in the intra-layer wiring recess 14a. Similarly, the insulating layer 1c of the multilayer substrate 2
Is formed with an in-layer wiring recess 14b as an in-layer wiring space, and the in-layer wiring recess 4b is formed in the in-layer wiring recess 14b.
Is filled. The in-layer wiring recesses 14a, 14b
Has a strip shape.

Next, a method of manufacturing the multilayer substrate 2 will be described with reference to FIGS.
9 will be described. As shown in FIG. 7, a flat alumina green sheet 13 is prepared, and in-layer wiring recesses 14 are formed in the alumina green sheet 13 so as to extend in the plane direction of the alumina green sheet 13. A press working method using a press is used for this molding. That is, FIG.
As shown in FIG. 5, a movable mold 25 having a projection 24 is arranged to face a fixed mold 23, and an alumina green sheet 13 is arranged on the fixed mold 23, and the movable mold 25 is moved to form an in-layer wiring concave portion 14. Is formed.

As shown in FIG. 8, the in-layer wiring recesses 14 are formed by press-fitting or screen printing.
Is filled with the intra-layer wiring material 4. Further, after forming the general wiring by the printing method, the wiring is laminated as shown in FIG.
Then, it is fired. As a result, the hybrid IC of FIG.
Is manufactured. As described above, in the present embodiment, the in-layer wiring recesses 14 a and 14 b (spaces for in-layer wiring) are formed in the insulating layers 1 b and 1 c of the multilayer substrate 2.
a, 14b were filled with the in-layer wiring material 4; Therefore, the in-layer wiring is formed by filling the wiring material 4 into the in-layer wiring recesses 14a and 14b of the insulating layers 1b and 1c, and the current passage area is increased and the wiring resistance is reduced as compared with the conventionally printed in-layer wiring. Become. (Third Embodiment) Next, a description will be given of only a difference between the third embodiment and the first embodiment.

As shown in FIG. 11, in the insulating layers 1f, 1g, and 1h of the multilayer substrate 2, a large number of through-holes 15, 16, and 17 for in-layer wiring are formed as spaces for in-layer wiring.
The in-layer wiring through-holes 15, 16, 17 are filled with the in-layer wiring material 4. The through-holes 15, 1 for wiring in the layer
6 and 17 are cylindrical. Through hole 1 for wiring in layer
The diameter D of 5, 16, 17 is 0.2 mmφ, and the pitch P of the through holes 15, 16, 17 for in-layer wiring is 0.3 mm (=
1.5 · D), and the laminated insulating layers 1f, 1g, 1h
The overlap L of the through-holes 15, 16 and 17 for the intra-layer wiring is 0.05 mm (= 0.25 · D).

Next, a method of manufacturing the multilayer substrate 2 will be described with reference to FIG.
This will be described with reference to 2, 13, and 14. As shown in FIG. 12, a flat alumina green sheet 13 is prepared, and the alumina green sheet 13
(16, 17) is formed. For this molding, a punching method using a press is used. That is, as shown in FIG.
A movable mold member 29 having a columnar projection 28 is arranged to face a fixed mold member 27 having a hole 26, and an alumina green sheet 13 is arranged on the fixed mold member 27. Hole 15 (16, 1
7) is formed.

Then, as shown in FIG. 13, the in-layer wiring recesses 1 are formed by press-fitting or screen printing.
5 (16, 17) is filled with the in-layer wiring material 4. Further, after the general wiring is formed by the printing method, as shown in FIG. 14, the upper and lower alumina green sheets 13 are laminated so that the in-layer wiring through holes 15, 16, 17 are shifted as a result. Then, it is fired.

As a result, the hybrid IC shown in FIG. 11 is manufactured. As described above, in this embodiment, the through-holes 15, 16, and 1 for the intra-layer wiring are formed in the insulating layers 1f, 1g, and 1h of the multilayer substrate 2.
7 (space portion for in-layer wiring) was formed, and the through-holes 15, 16, 17 for in-layer wiring were filled with the in-layer wiring material 4. Therefore, the through-holes 15 for wiring in the layers of the insulating layers 1f, 1g, 1h,
In-layer wiring in which the wiring material 4 is filled in the wirings 16 and 17 has a larger current passage area and lower wiring resistance than the conventional in-layer wiring by printing.

That is, as shown in FIG. 11, the through-holes 15, 1 for the in-layer wiring are formed in the upper and lower insulating layers 1f, 1g, 1h.
6 and 17 are arranged by overlapping (overlapping) by 0.05 mm. As a result, the current path into the layer (lateral direction) is 0.05 mm even at the narrowest point, and FIG.
6. The thickness of the wiring in the layer by the conventional printing shown in FIG.
In comparison with the above, the current passage area is increased and the wiring resistance is reduced.

FIG. 17 shows an application example of the third embodiment.
As shown in the figure, the pitch P of the through-holes 15, 16, 17 for in-layer wiring is increased, and the through-holes 15, 16, 17 for in-layer wiring in the upper and lower insulating layers are formed in the in-layer wiring material 18 by printing. May be electrically connected. In addition, as shown in FIG. 18, the through-holes 15, 16, and 17 for in-layer wiring having different diameters may be arranged in combination.

The present invention is not limited to the above embodiments. For example, in each of the above embodiments, a flat green sheet is pressed to form a wiring space in a layer. Protrusions are formed in the green sheet forming mold to form wiring space in the layer when forming the green sheet, and the space for wiring in the layer is formed when the green sheet material powder is put into the mold and molded May be.

In each of the above embodiments, the substrate is manufactured by a lamination method using ceramic green sheets. However, the substrate may be manufactured by a lamination method using glass green sheets (glass ceramic green sheets). Further, the present invention can be applied to a printed laminated substrate on which an insulating layer is formed by using a printing method. That is, it may be manufactured by a thick film multilayer method using a glass paste or by a thick film multilayer method using a ceramic paste.

As the wiring material, W and Mo may be used when ceramic is used, and Ag, Ag / Pd, Cu, etc. may be used when glass is used.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a hybrid IC according to a first embodiment.

FIG. 2 is a perspective view illustrating a manufacturing process of the substrate.

FIG. 3 is a perspective view illustrating a manufacturing process of the substrate.

FIG. 4 is a perspective view illustrating a manufacturing process of the substrate.

FIG. 5 is a diagram for explaining a manufacturing process of the substrate.

FIG. 6 is a sectional view of a hybrid IC according to a second embodiment.

FIG. 7 is a perspective view illustrating a manufacturing process of the substrate.

FIG. 8 is a perspective view illustrating a manufacturing process of the substrate.

FIG. 9 is a perspective view illustrating a manufacturing process of the substrate.

FIG. 10 is a diagram for explaining a manufacturing process of the substrate.

FIG. 11 is a sectional view of a substrate of a hybrid IC according to a third embodiment.

FIG. 12 is a perspective view illustrating a manufacturing process of the substrate.

FIG. 13 is a perspective view illustrating a manufacturing process of the substrate.

FIG. 14 is a perspective view illustrating a manufacturing process of the substrate.

FIG. 15 is a diagram for explaining the manufacturing process of the substrate.

FIG. 16 is a sectional view of a substrate for comparison.

FIG. 17 is a sectional view of a substrate of an application example of the third embodiment.

FIG. 18 is a sectional view of a substrate of an application example of the third embodiment.

[Explanation of symbols]

 1b Insulating layer 1c Insulating layer 1e Insulating layer 1f Insulating layer 1g Insulating layer 2 Multi-layer board 3a In-layer wiring through-groove as in-layer wiring space 3b In-layer wiring through-groove as intra-layer wiring space 4 layers Internal wiring material 14a In-layer wiring concave portion as intra-layer wiring space portion 14b In-layer wiring concave portion as intra-layer wiring space portion 15 In-layer wiring through hole as intra-layer wiring space portion 16 In-layer wiring Through-hole for wiring in layer as space for wiring 17 Through-hole for wiring in layer as space for wiring in layer

Claims (3)

(57) [Claims] 1. A multi-layer substrate comprising a plurality of insulating layers laminated, wherein a part of an opening overlaps with each of the insulating layers vertically overlapping and continuously extends in a lateral direction of the insulating layer. A multilayer substrate having a plurality of through holes formed therein, wherein the through holes are filled with a wiring material. Wherein said wiring material, a multilayer substrate according to claim 1, wherein the additive for matching the Netsu膨Zhang rate of the insulating layer constituting the multilayer substrate is one that was added . 3. A process according to claim wherein the additive is characterized in that the material and the heat <br/> Rise Zhang rate of the insulating layer are substantially the same material 2
2. The multilayer substrate according to item 1.