JP3508905B2 - Wiring board and its manufacturing method - Google Patents

Wiring board and its manufacturing method

Info

Publication number
JP3508905B2
JP3508905B2 JP09747697A JP9747697A JP3508905B2 JP 3508905 B2 JP3508905 B2 JP 3508905B2 JP 09747697 A JP09747697 A JP 09747697A JP 9747697 A JP9747697 A JP 9747697A JP 3508905 B2 JP3508905 B2 JP 3508905B2
Authority
JP
Japan
Prior art keywords
layer
wiring board
layers
ceramic
metallized
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP09747697A
Other languages
Japanese (ja)
Other versions
JPH10289964A (en
Inventor
和重 秋田
雅仁 森田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NGK Spark Plug Co Ltd
Original Assignee
NGK Spark Plug Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NGK Spark Plug Co Ltd filed Critical NGK Spark Plug Co Ltd
Priority to JP09747697A priority Critical patent/JP3508905B2/en
Publication of JPH10289964A publication Critical patent/JPH10289964A/en
Application granted granted Critical
Publication of JP3508905B2 publication Critical patent/JP3508905B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/49105Connecting at different heights
    • H01L2224/49109Connecting at different heights outside the semiconductor or solid-state body

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、複数のセラミック
を積層した多層配線セラミック基板に関し、その上表面
のキャビティ部内に搭載する半導体素子等の電子部品と
のワイヤボンディングによる接続が安定して行えること
を特徴とする。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer wiring ceramic substrate in which a plurality of ceramics are laminated, and stable connection by wire bonding with an electronic component such as a semiconductor element mounted in a cavity on the upper surface thereof. Is characterized by.

【0002】[0002]

【従来の技術】一般に、半導体素子等の電子部品をその
上表面に設けたキャビティ120内に搭載する配線基板
100は、図7(A)に示すように、矩形体を呈し、同図
(B)に示すように、セラミック層113の上に中央部が
打ち抜かれた複数のセラミック層101〜112を垂直
方向に積層して、内周側を階段形状とした枠部130を
形成している。上記キャビティ120内には、その底面
となるセラミック層113上に半導体素子Cが固着され
る。また、各セラミック層102〜106と同108〜
112の間には、それぞれ例えば電源用のメタライズ層
116,117が幅方向の両側端部を除き、且つ平面視
で矩形枠状にして略全面に配置されている。このメタラ
イズ層116,117がセラミック層102〜106と
同108〜112の内外両側端部に沿って配置されない
のは、追ってキャビティ120の内面等に施されるNiメ
ッキ等によって、各メタライズ層116,117同士が
短絡するのを防ぐためである。
2. Description of the Related Art In general, a wiring board 100 for mounting an electronic component such as a semiconductor element in a cavity 120 provided on the upper surface thereof has a rectangular shape as shown in FIG.
As shown in (B), a plurality of ceramic layers 101 to 112 each having a punched central portion are vertically stacked on the ceramic layer 113 to form a frame portion 130 having an inner peripheral side having a step shape. There is. In the cavity 120, the semiconductor element C is fixed on the ceramic layer 113 that is the bottom surface thereof. Further, each ceramic layer 102-106 and the same 108-
Between 112, metallization layers 116 and 117 for power supply, for example, are arranged on substantially the entire surface in a rectangular frame shape in plan view except both end portions in the width direction. The reason why the metallized layers 116 and 117 are not arranged along the inner and outer ends of the ceramic layers 102 to 106 and 108 to 112 is that the metallized layers 116 and 117 are formed on the inner surface of the cavity 120 later by Ni plating or the like. This is to prevent short circuits between 117.

【0003】更に、枠部130の階段形状の上面を形成
するセラミック層102,107の上面には、キャビテ
ィ120に沿って先端部を揃えた多数の幅狭の接続用パ
ッド122,124が互いに略平行して配置されてい
る。この接続用パッド122,124は、上記メタライ
ズ層116,117を垂直方向に貫通する図示しないビ
アを介して、基板100内の所定の回路と導通されると
共に、キャビティ120内に搭載される半導体素子Cと
ワイヤWにより接続される。また、上記配線基板100
は、セラミック層101〜113となる同数の所定形状
に打ち抜かれたグリーンシートの各表面上に、導電ペー
ストをスクリーン印刷したものを垂直方向に積層し、そ
の後に焼成することによって製造される。
Further, on the upper surfaces of the ceramic layers 102 and 107 forming the stepped upper surface of the frame portion 130, a large number of narrow connecting pads 122 and 124 whose tip portions are aligned along the cavity 120 are substantially formed. They are arranged in parallel. The connection pads 122 and 124 are electrically connected to a predetermined circuit in the substrate 100 through vias (not shown) that penetrate the metallized layers 116 and 117 in the vertical direction, and the semiconductor elements mounted in the cavity 120. It is connected to C by a wire W. In addition, the wiring board 100
Is manufactured by vertically stacking a screen-printed conductive paste on each surface of green sheets punched into the same number of predetermined shapes to be the ceramic layers 101 to 113, and then firing.

【0004】ところで、上記積層に際して各グリーンシ
ートはその厚さ方向に圧縮力を受けるため、各メタライ
ズ層116,117が平面視において存在しないセラミ
ック層102〜106,同107〜112の内周部(キ
ャビティ120側)には、上記メタライズ層116,1
17の厚みに略相当する分だけ下方に向けて緩く傾いた
傾斜面Kがそれぞれ発生してしまうことがある。係るキ
ャビティ120を囲むセラミック層102及び同107
の内周部に傾斜面Kが形成されていると、当該部分の直
上に設けられる前記接続用パッド122,124とキャ
ビティ120内に搭載される半導体素子Cの図示しない
端子とを接続するワイヤWをボンディングする際に、傾
斜面Kにより接続用パッド122等の位置が下方にずれ
てしまう。この結果、ボンディングされるワイヤWの先
端が接続用パッド122等からスリップしたり、これと
当接できないため、十分な加熱や微振動等による圧着が
行えず、配線基板100内に形成された各回路と半導体
素子Cとが導通できなくなるという不具合を生じること
があった。
By the way, since each green sheet receives a compressive force in the thickness direction during the above-mentioned lamination, the inner peripheral portions of the ceramic layers 102 to 106 and 107 to 112 in which the metallized layers 116 and 117 do not exist in plan view ( On the side of the cavity 120), the metallized layers 116, 1
In some cases, inclined surfaces K are formed that are gently inclined downward by an amount substantially equivalent to the thickness of 17. Ceramic layers 102 and 107 surrounding the cavity 120
When the inclined surface K is formed on the inner peripheral portion of the wire W, the wire W for connecting the connection pads 122 and 124 provided immediately above the portion and a terminal (not shown) of the semiconductor element C mounted in the cavity 120. When the bonding is performed, the positions of the connection pads 122 and the like shift downward due to the inclined surface K. As a result, the tip of the wire W to be bonded slips from the connection pad 122 or the like and cannot come into contact therewith, so that sufficient pressure or crimping due to microvibration cannot be performed, and each formed in the wiring board 100. There has been a problem that the circuit and the semiconductor element C cannot be electrically connected.

【0005】[0005]

【発明が解決すべき課題】本発明は、以上の従来の技術
が抱える問題点を解決し、キャビティ内に搭載される半
導体素子等の電子部品と配線基板内の回路との接続が容
易且つ確実に行えるようにした配線基板とその製造方法
を提供することを目的とする。
DISCLOSURE OF THE INVENTION The present invention solves the problems of the above conventional techniques, and makes it easy and reliable to connect an electronic component such as a semiconductor element mounted in a cavity to a circuit in a wiring board. It is an object of the present invention to provide a wiring board and a manufacturing method thereof that can be performed.

【0006】[0006]

【課題を解決するための手段】本発明は、上記の課題を
解決するため、前記セラミック層間のメタライズ層の内
周縁に沿って所要の厚さを有する絶縁層を配置すること
に着想して成されたものである。即ち、本発明の配線基
板は、電子部品を搭載するためのキャビティ部と、複数
のセラミック層を積層してなり、上記キャビティ部を囲
むように形成され、内周側が断面階段形状である枠部
と、少なくとも上記キャビティ部の底面をなすように枠
部に固着された底部と、上記枠部の階断面上に形成され
電子部品と接続するための接続用パッドと、を含む配線
基板であって、上記枠部を形成する複数のセラミック層
の層間のうち少なくとも1つ以上の層間に形成され、内
周縁が平面視にて上記接続用パッドの略直下で且つセラ
ミック層の内周縁より引き下がった位置に形成されたメ
タライズ層と、少なくとも1つ以上のメタライズ層の内
周縁とセラミック層の内周縁との間の引き下がり部のう
ち少なくとも上記接続用パッドの略直下に設けた絶縁層
と、を含み、上記絶縁層の厚みは、上記メタライズ層の
厚みよりも厚い、ことを特徴とする。
In order to solve the above problems, the present invention is conceived to arrange an insulating layer having a required thickness along the inner peripheral edge of the metallized layer between the ceramic layers. It was done. That is, the wiring board of the present invention is a frame part formed by stacking a plurality of ceramic layers with a cavity part for mounting electronic parts, surrounding the cavity part, and having an inner peripheral side having a stepped cross-section. And a bottom portion fixed to the frame portion so as to form at least the bottom surface of the cavity portion, and a connection pad formed on the floor cross section of the frame portion for connecting to an electronic component, A position formed between at least one or more layers of the plurality of ceramic layers forming the frame portion, the inner peripheral edge of which is substantially directly below the connection pad and lower than the inner peripheral edge of the ceramic layer in plan view. Of the metallized layer formed on the insulating layer, and the insulation provided at least directly under the connection pad in the pull-down portion between the inner peripheral edge of at least one or more metallized layers and the inner peripheral edge of the ceramic layer. When, only including, a thickness of the insulating layer, the metallization layer
It is characterized by being thicker than the thickness .

【0007】係る配線基板によれば、セラミック層同士
の間にメタライズ層と、その内周側に沿う引き下がり部
内に絶縁層が配置されるので、前記傾斜面K116,1
17の発生を無くすか、極く僅かに抑えることが可能に
なる。しかも、前記絶縁層の厚みは、メタライズ層の厚
みよりも厚いため、上記複数のセラミック層間の全てに
形成して、前記メタライズ層との厚みの差を各セラミッ
ク層間毎で調整することもできる。前記メタライズ層の
引き下がり部が無くセラミック層の内周縁までメタライ
ズ層を形成した場合、又はメタライズ層を形成しない場
合であっても、セラミック層のキャビティ側が若干下方
に傾く傾向にあるため、前記絶縁層の厚みを前記メタラ
イズ層の厚みよりも若干厚くしておく。尚、絶縁層は、
前記引き下がり部のうちの少なくとも前記接続用パッド
の略直下の部分に形成されていれば良く、接続用パッド
が形成されていない部分の略直下には形成しなくても良
い。或いは、接続用パッドが形成されている部分も含め
て前記引き下がり部の略全領域に設けても良い。
According to this wiring board, the metallized layer is provided between the ceramic layers, and the insulating layer is disposed in the pull-down portion along the inner peripheral side thereof.
It is possible to eliminate the occurrence of 17 or to suppress it to a very small extent. Moreover, the thickness of the insulating layer is the thickness of the metallized layer.
Since it is thicker than only
After being formed, the difference in thickness from the metallized layer is adjusted by each ceramic
It can also be adjusted for each layer. Of the metallized layer
There is no pull-down part and the metallization extends to the inner edge of the ceramic layer.
Layer is formed, or when the metallized layer is not formed.
Even if the ceramic layer is slightly downward on the cavity side of the ceramic layer
Since the thickness of the insulating layer tends to
It should be slightly thicker than the IZ layer. The insulating layer is
It suffices that it is formed at least in a portion just below the connection pad of the pull-down portion, and it does not have to be formed substantially directly in a portion where the connection pad is not formed. Alternatively, it may be provided in substantially the entire area of the pull-down portion including the portion where the connection pad is formed.

【0008】また、前記傾斜面Kは、前述の通りメタラ
イズ層116,117が形成されている領域と形成され
ていない領域(引き下がり部)の厚みの差により形成され
る。従って、セラミック層及びその層間に形成されるメ
タライズ層の層数が増せば増す程、上記厚みの差の総和
は増大する。特にメタライズ層が4層以上になると、上
記絶縁層を形成することによる厚みの差を調整し、傾斜
面Kを無くすか最小限に抑えることが重要になる。この
ため、本発明には、前記枠部が4層以上のメタライズ層
を有してい配線基板も含まれる。
The inclined surface K is formed by the difference in thickness between the region where the metallized layers 116 and 117 are formed and the region where it is not formed (pulled-down portion) as described above. Therefore, as the number of ceramic layers and the number of metallized layers formed between the ceramic layers increases, the total sum of the thickness differences increases. In particular, when the metallized layer has four or more layers, it is important to adjust the thickness difference due to the formation of the insulating layer and eliminate or minimize the inclined surface K. Therefore, the present invention, the frame portion that has have a four or more layers of metallization layers, also includes the wiring substrate.

【0009】[0009]

【0010】更に、選択的に一部のセラミック層間にの
み前記絶縁層を形成し、各セラミック層間毎のメタライ
ズ層による厚み差の和を調整するようにしても良い。例
えばメタライズ層のうちの1層飛び又は2層飛び毎に前
記絶縁層を形成しても良い。この場合、前記絶縁層の厚
みはメタライズ層の厚みの約2〜3倍にするか、それら
よりも若干厚くすると良い。このように、選択的に一部
のセラミック層間にのみ前記絶縁層を設ける形態は、こ
の絶縁層の形成を簡略化でき、且つ各セラミック層間に
設ける形態と同様の効果を得ることができる。このた
め、本発明には、前記絶縁層が前記メタライズ層のうち
の1層飛び又は2層飛び毎の引き下がり部に形成されて
いる配線基板も含まれる。
Further, the insulating layer may be selectively formed only between some of the ceramic layers, and the sum of the thickness differences due to the metallized layers between the respective ceramic layers may be adjusted. For example, the insulating layer may be formed every one or two layers of the metallized layer. In this case, the thickness of the insulating layer is preferably about 2 to 3 times the thickness of the metallized layer or slightly thicker than them. As described above, in the mode in which the insulating layer is selectively provided only between some of the ceramic layers, the formation of the insulating layer can be simplified, and the same effect as the mode in which the insulating layers are provided between the ceramic layers can be obtained. Therefore, the present invention, the insulating layer is formed on the withdraw portion of each jumping one layer jump or two layers of said metallization layer also includes a wiring board.

【0011】、前記セラミック層のうち、少なくとも
前記メタライズ層間に挟まれるセラミック層の厚みが、
0.25mm以下である配線基板としても良い。即ち、
メタライズ層を形成した領域と形成しない領域(引き下
がり部)との厚みの差は、セラミック層の厚みが小さい
と全てのセラミック層とメタライズ層の厚みの総和に占
める前記厚み差の総和の割合が大きくなり、前記傾斜面
Kへの影響も大きくなる。従って、一般にメタライズ層
は10〜30μmの厚みで形成されるので、これらに挟
まれるセラミック層の厚みが0.25mm以下の配線基
板では、前記絶縁層による厚みの調整がより重要にな
る。
[0011] Incidentally, among the ceramic layer, the thickness of the ceramic layer sandwiched between at least the metallized layers,
A wiring board having a size of 0.25 mm or less may be used . That is,
When the thickness of the ceramic layer is small, the difference in thickness between the region where the metallized layer is formed and the region where it is not formed (pulled-down portion) is large when the total thickness difference of all the ceramic layers and the metallized layer is large. Therefore, the influence on the inclined surface K also increases. Therefore, since the metallized layer is generally formed to have a thickness of 10 to 30 μm, the adjustment of the thickness by the insulating layer becomes more important in the wiring board in which the thickness of the ceramic layer sandwiched between them is 0.25 mm or less.

【0012】更に、本発明には、前記キャビティ部が平
面視で矩形状を呈し、前記引き下がり部が平面視で矩形
枠状に形成され、前記絶縁層が上記引き下がり部のうち
角部を除いてその辺部に形成される配線基板も含まれ
る。係る構成によれば、キャビティ部内に搭載された半
導体素子等と配線基板内の回路とを確実且つ効率良く接
続できる配線基板を提供することも可能となる。、前
記絶縁層が、前記セラミック層と同種のセラミックから
なる配線基板としても良い。これにより、絶縁層は上下
に隣接する各セラミック層と強固に一体化されるので、
耐久性にも優れた配線基板を得ることが可能となる。
Further, in the present invention, the cavity portion has a rectangular shape in a plan view, the pull-down portion is formed in a rectangular frame shape in a plan view, and the insulating layer except the corner portion of the pull-down portion. is formed on the side portions, the wiring board are also included. With such a configuration, it is possible to provide a wiring board that can reliably and efficiently connect the semiconductor element or the like mounted in the cavity to the circuit in the wiring board. The insulating layer may be a wiring board made of the same ceramic as the ceramic layer. As a result, the insulating layer is firmly integrated with the vertically adjacent ceramic layers,
It is possible to obtain a wiring board having excellent durability.

【0013】また、本発明は、以上の配線基板を得るた
め、焼成後に前記セラミック層となる複数のグリーンシ
ートの何れかの表面に、焼成後に前記メタライズ層とな
る導電ペーストを塗布する工程と、少なくとも一部の上
記グリーンシートの表面に、焼成後に前記絶縁層となる
絶縁ペーストを上記導電ペーストの内周側に沿って、当
該導電ペーストの厚みよりも厚く塗布する工程とを、相
前後して含む配線基板の製造方法も提供する。係る構成
によれば、前記傾斜面の発生を無くすか、極力抑えた配
線基板を所望の数量だけ確実且つ正確に製造することが
可能となる。、上記絶縁ペーストが、前記グリーンシ
ートと同種のセラミック成分からなる配線基板の製造方
としても良い。これにより、同種のセラミック原料の
みによって上記配線基板を確実且つ強固に製造すること
が可能となる。
Further, in order to obtain the above wiring board, the present invention comprises a step of applying a conductive paste, which becomes the metallized layer after firing, to any surface of a plurality of green sheets which becomes the ceramic layer after firing, at least a portion of the surface of the green sheet, the insulating layer to become an insulating paste after firing along the inner circumference side of the conductive paste, those
There is also provided a method for manufacturing a wiring board, which includes a step of applying the conductive paste thicker than the thickness of the conductive paste . According to such a configuration, it is possible to eliminate the occurrence of the inclined surface or to manufacture the wiring board in a desired quantity reliably and accurately with the number of wiring boards suppressed as much as possible. A method of manufacturing a wiring board in which the insulating paste is made of the same ceramic component as the green sheet may be used . As a result, the wiring board can be reliably and firmly manufactured using only the same kind of ceramic raw material.

【0014】[0014]

【実施の形態】以下において、本発明の実施に好適な形
態を図面と共に説明する。図1(A)は、本発明による配
線基板1の一形態を示す斜視図で、その上表面には矩形
のキャビティ部2を有し、このキャビティ部2を囲んで
上下に断面階段形状をなす階段面4,5を内周側に有す
る枠部3が形成されている。この階段面4,5上の各辺
には、上記キャビティ部2に沿って先端部を揃えた多数
の接続用パッド6,8が互いに略平行して配置されてい
る。図1(B)に示すように、上記キャビティ部2を囲む
枠部3は、垂直方向に複数のセラミック層10〜21を
積層したもので、且つ下方の底部となるセラミック層2
2上に固着されている。上記枠部3を形成するセラミッ
ク層11〜15と同16〜21は、キャビティ部2を形
成するため、中央側が同じ矩形状に打ち抜かれ、セラミ
ック層11,16のキャビティ部2寄りに前記階段面
4,5を形成している。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment for carrying out the present invention will be described below with reference to the drawings. FIG. 1 (A) is a perspective view showing an embodiment of a wiring board 1 according to the present invention, which has a rectangular cavity portion 2 on its upper surface, and surrounds the cavity portion 2, and has a vertical stepwise cross section. A frame portion 3 having the step surfaces 4 and 5 on the inner peripheral side is formed. A large number of connection pads 6, 8 whose tip portions are aligned along the cavity 2 are arranged substantially parallel to each other on each side of the step surfaces 4, 5. As shown in FIG. 1 (B), the frame portion 3 surrounding the cavity portion 2 is formed by stacking a plurality of ceramic layers 10 to 21 in the vertical direction, and serves as a lower bottom ceramic layer 2.
It is fixed on 2. The ceramic layers 11 to 15 and 16 to 21 forming the frame portion 3 are punched into the same rectangular shape at the center side to form the cavity portion 2 and the stepped surface is formed near the cavity portion 2 of the ceramic layers 11 and 16. 4 and 5 are formed.

【0015】図示において上寄りのセラミック層11〜
15の間と、下寄りのセラミック層17〜21の間に
は、これらの略全面に渉って例えば電源用のメタライズ
層24,26がそれぞれ形成されている。このメタライ
ズ層24,26の内周側にはキャビティ部2側に沿って
所定幅の上記メタライズ層24,26が形成されない引
き下がり部25,27が各々設けられるこのうち
ラミック層13,15と同18,20の上面には、絶縁
層28,29が矩形枠状に配設され、各引き下がり部2
5,27内をほぼ占有している。かかる絶縁層28,2
9の厚みは、メタライズ層24,26の厚みよりも厚く
形成されている。例えば、セラミック層13上における
メタライズ層24と絶縁層28との配置関係は、図2に
示すように、メタライズ層24の内周縁に沿ってその内
周側の引き下がり部25の幅一杯に絶縁層28が矩形枠
状に配置されている。
In the drawing, the upper ceramic layers 11 to 11 are shown.
Between 15 and between the lower ceramic layers 17 to 21, metallization layers 24 and 26 for power supply, for example, are formed over substantially the entire surfaces thereof. On the inner peripheral sides of the metallized layers 24 and 26, pull-down portions 25 and 27 having a predetermined width are formed, respectively, along the cavity 2 side, where the metallized layers 24 and 26 are not formed . Of these , the insulating layers 28 and 29 are arranged in a rectangular frame shape on the upper surfaces of the ceramic layers 13 and 15 and 18 and 20, respectively.
It almost occupies the inside of 5,27. Such insulating layers 28, 2
9 is thicker than the metallized layers 24 and 26.
Has been formed. For example, as shown in FIG. 2, the metallized layer 24 and the insulating layer 28 are arranged on the ceramic layer 13 along the inner peripheral edge of the metallized layer 24 so that the width of the pull-down portion 25 on the inner peripheral side is as wide as possible. 28 are arranged in a rectangular frame shape.

【0016】この絶縁層28等を前記図1(B)に示すよ
うに配置することにより、配線基板1の階段面4,5上
には、従来における傾斜面Kが無くなるか、極く僅かし
か出現しないので、その直上に配置される接続用パッド
6,8は本来の位置に略正確に形成される。従って、各
パッド6,8とキャビティ部2内に搭載される前記同様
の半導体素子CとのワイヤWによるボンディングを確実
に行うことができる。尚、図2中のメタライズ層24内
に位置する符号30は、該メタライズ層24との間に間
隙を置いてこれを垂直方向に貫通するビアを示し、前記
接続用パッド6と、図示しない配線基板1の下方に内設
される回路とを導通させている。これらのビア30は、
他のメタライズ層24や同26をも貫通し、各パッド
6,8と配線基板1の下方の回路を導通する。
By arranging the insulating layer 28 and the like as shown in FIG. 1 (B), the inclined surface K in the prior art is eliminated on the step surfaces 4 and 5 of the wiring board 1 or is very small. Since it does not appear, the connecting pads 6 and 8 arranged immediately above the connecting pads 6 and 8 are formed substantially accurately at their original positions. Therefore, the bonding of the pads 6, 8 and the semiconductor element C similar to the one mounted in the cavity 2 by the wire W can be reliably performed. Reference numeral 30 located in the metallized layer 24 in FIG. 2 indicates a via penetrating the metallized layer 24 in the vertical direction with a gap provided between the metallized layer 24, the connection pad 6 and the wiring not shown. It is electrically connected to a circuit provided below the substrate 1. These vias 30 are
The other metallized layers 24 and 26 are also penetrated to electrically connect the pads 6 and 8 to the circuit below the wiring board 1.

【0017】図3は、異なる配置形態の絶縁層に関する
図2と同様の位置における部分断面図で、図3(A)は
枠部40を構成するセラミック層44上にメタライズ層
46を形成し、その内周側の引き下がり部42内に、上
記メタライズ層46との間に極く狭い間隙41を保っ
、かかるメタライズ層46の厚みよりも厚い絶縁層4
8を配設した状態を示す。係る間隙41を隔てて絶縁層
48を配設すると、後述するように、製造時に同じセラ
ミック層44上において、メタライズ層46の内周縁と
絶縁層48の外周縁が内外方向に多少位置ずれしても、
互いに重なり合ってそれらの上方における階段面上に不
要な凸部が発生するのを阻止することができる。
[0017] FIG. 3 is a partial cross-sectional view at the same position as Figure 2 an insulated layer of a different arrangement form, FIG. 3 (A),
The metallized layer 46 is formed on the ceramic layer 44 that constitutes a frame part 40, on the inner peripheral side of the withdraw portion 42 thereof, while maintaining a very narrow gap 41 between the metallized layer 46, such metallized layer 46 Insulation layer 4 thicker than
8 shows a state in which 8 is provided. When the insulating layer 48 is disposed with the gap 41, the inner peripheral edge of the metallized layer 46 and the outer peripheral edge of the insulating layer 48 are slightly displaced in the inner and outer directions on the same ceramic layer 44 during manufacturing, as described later. Also,
It is possible to prevent unnecessary convex portions from being formed on the staircase surface above them by overlapping each other.

【0018】また、図3(B)は枠部50を構成するセ
ラミック層54のコーナ部を示し、その上面に略L形状
にメタライズ層56を配置すると共に、その内周縁に沿
う引き下がり部52における角部53を除いて、上記メ
タライズ層56との間に極く狭い間隙51を保って
辺部55に帯状で且つメタライズ層56の厚みよりも厚
絶縁層58,58を互いに直角に配設した状態を示
す。係る角部53の直上の図示しない階段面上には、前
記接続用パッド6,8が配置されることが少ないため、
絶縁層58を効率良く配置でき、且つ接続用パッド6等
との前記ワイヤボンディングを確実に行わしめることが
可能となる。
[0018] FIG. 3 (B) shows a corner portion of the ceramic layer 54 that constitutes a frame portion 50, withdraw unit 52 with placing the metallized layer 56 in a substantially L shape on the upper surface, along its inner peripheral edge except for the corner portion 53 in the thickness than the very narrow keep the gap 51, and the thickness of the metallized layer 56 in strip shape in the respective side portion 55 between the metallized layer 56
The insulating layers 58, 58 are arranged at right angles to each other. Since the connecting pads 6 and 8 are rarely arranged on the step surface (not shown) directly above the corner portion 53,
The insulating layer 58 can be efficiently arranged, and the wire bonding with the connection pad 6 or the like can be reliably performed.

【0019】次に、前記配線基板1の製造方法を図4に
よって説明する。図4(A)は、主にアルミナからなり中
央部が打ち抜かれた複数のグリーンシート60〜71を
用意し、このうちグリーンシート62〜65と同68〜
71の表面上に前記メタライズ層24,26となるタン
グステンやモリブデン等の高融点金属からなる導電ペー
スト84,86が略全面に渉りスクリーン印刷等により
塗布されると共に、この内周側には前記引き下がり部2
5,27が設けられた状態を示す。また、前記階段面
4,5を形成するグリーンシート61,66の表面上に
は、前記接続用パッド6,8を得るための上記と同様の
高融点金属からなる多数の導電ペースト76,78が同
様にして塗布される。
Next, a method of manufacturing the wiring board 1 will be described with reference to FIG. In FIG. 4A, a plurality of green sheets 60 to 71, which are mainly made of alumina and whose central portion is punched out, are prepared.
Conductive pastes 84 and 86 made of a refractory metal such as tungsten and molybdenum, which will be the metallized layers 24 and 26, are applied on the surface of 71 by screen printing or the like on almost the entire surface, and the inner peripheral side is provided with Pull-down part 2
The state where 5, 27 are provided is shown. On the surfaces of the green sheets 61, 66 forming the staircase surfaces 4, 5, a large number of conductive pastes 76, 78 made of the same high melting point metal as described above for obtaining the connection pads 6, 8 are formed. It is applied in the same manner.

【0020】次いで、図4(B)に示すように、グリーン
シート63,65と同68,70上の引き下がり部2
5,27内に上記と同種のアルミナからなり、焼成後に
前記絶縁層28,29となる絶縁ペースト88,89を
同様に塗布する。即ち、各導電ペースト84,86のう
ちの1層飛び毎に絶縁ペースト88,89をそれらより
もやや厚めに塗布することで、製造工程の増加を抑制し
たものである。尚、図中の符号72は底部を構成するセ
ラミック層22となるグリーンシートを示す。そして、
これらの各グリーンシート60〜72を所定の順序で垂
直方向に積層し、常法により厚さ方向に加圧しつつ焼成
すると、各グリーンシート60〜72は前記セラミック
層10〜22に、導電ペースト76,78は前記接続用
パッド6,8に、導電ペースト84,86はメタライズ
層24,26に、且つ絶縁ペースト88,89は前記絶
縁層28,29となった配線基板1が得られる。尚、同
じグリーンシート63,68上において、上記導電ペー
スト84,86と絶縁ペースト88,89を塗布する順
序は前記と逆に行うこともできる。また、導電ペースト
84,86と絶縁ペースト88,89の間に極く僅かの
間隙を設けて塗布すると、両者に多少の位置ずれが生じ
ても互いに重なることを予防することもできる。
Next, as shown in FIG. 4 (B), the pull-down portion 2 on the green sheets 63, 65 and 68, 70.
Insulating pastes 88 and 89, which are made of the same kind of alumina as described above and serve as the insulating layers 28 and 29 after firing, are similarly applied in the layers 5 and 27. That is, the insulating pastes 88 and 89 are applied to each layer of the conductive pastes 84 and 86 slightly thicker than the conductive pastes 84 and 86, thereby suppressing an increase in the number of manufacturing processes. Incidentally, reference numeral 72 in the drawing denotes a green sheet which becomes the ceramic layer 22 which constitutes the bottom portion. And
When these green sheets 60 to 72 are vertically stacked in a predetermined order and fired while applying pressure in the thickness direction by a conventional method, the green sheets 60 to 72 are applied to the ceramic layers 10 to 22 and the conductive paste 76. , 78 to the connection pads 6 and 8, the conductive pastes 84 and 86 to the metallized layers 24 and 26, and the insulating pastes 88 and 89 to the insulating layers 28 and 29, respectively, to obtain the wiring board 1. The conductive pastes 84 and 86 and the insulating pastes 88 and 89 may be applied on the same green sheets 63 and 68 in the reverse order. Further, if a very small gap is provided between the conductive pastes 84 and 86 and the insulating pastes 88 and 89, they can be prevented from overlapping each other even if some positional deviation occurs between them.

【0021】ここで、本発明の効果について比較例と共
に具体的に説明する。先ず、前記配線基板1を上記方法
によって製造した。尚、メタライズ層24,26の厚さ
は7〜12μm、絶縁層28,29の厚さは20〜30
μmとすると共に、上下表面がメタライズ層24,26
に挟まれるセラミック層12〜14と同18〜20の厚
さは何れも0.05mmとした。そして、上側の絶縁層2
8を下方のセラミック層15上のみに配置したもの(発
明例1)と、上下両方のセラミック層13,15上に配
置したもの(発明例2)をそれぞれ5個ずつ用意した。
また、下側の絶縁層29を下方のセラミック層20上の
みに配置したもの(発明例3)と、上下両方のセラミック
層18,20上に配置したもの(発明例4)をそれぞれ5
個ずつ用意した。
Here, the effect of the present invention will be specifically described together with a comparative example. First, the wiring board 1 was manufactured by the above method. The metallized layers 24 and 26 have a thickness of 7 to 12 μm, and the insulating layers 28 and 29 have a thickness of 20 to 30.
μm, and the upper and lower surfaces are metallized layers 24, 26
The thicknesses of the ceramic layers 12 to 14 and the ceramic layers 18 to 20 sandwiched between them are all 0.05 mm. And the upper insulating layer 2
Five pieces each of which 8 was arranged only on the lower ceramic layer 15 (Invention Example 1) and five pieces which were arranged on both the upper and lower ceramic layers 13 and 15 (Invention Example 2) were prepared.
Further, the lower insulating layer 29 is arranged only on the lower ceramic layer 20 (Invention Example 3) and the lower insulating layer 29 is arranged on both upper and lower ceramic layers 18 and 20 (Invention Example 4).
I prepared them individually.

【0022】一方、上記と同じ形状及び寸法等からな
り、前記絶縁層28,29となる絶縁ペースト88,8
9のみを塗布せずに製造した前記従来の基板100と同
様の比較例の配線基板を同数ずつ用意した。そして、各
基板1等における前記階段面4,5の各中央位置付近に
おいて、接続用パッド6,8のキャビティ部2寄りの先
端から0.10mmの位置とこれから外側に0.5mm離れ
た位置とで、所謂焦点法を用い光学顕微鏡により一方に
焦点を合わせた後、他方に移して再度焦点が合うまで垂
直方向に移動させた焦点の移動距離、即ち傾斜面におけ
る高さの差を各発明例1〜4と比較例について、前記階
段面4,5別に測定し、その平均値と最大及び最小値を
算出した。その結果を階段面4は図5に、階段面5は図
6の各グラフにそれぞれ示した。
On the other hand, the insulating pastes 88 and 8 having the same shape and dimensions as those described above and serving as the insulating layers 28 and 29.
The same number of wiring boards of the same comparative example as the conventional board 100 manufactured without applying only 9 were prepared. Then, in the vicinity of the central position of each of the stepped surfaces 4 and 5 of each substrate 1 and the like, a position of 0.10 mm from the tip of the connection pads 6 and 8 near the cavity 2 and a position 0.5 mm away from it. Then, after focusing on one side by an optical microscope using the so-called focusing method, it is moved to the other side and moved in the vertical direction until it comes into focus again, that is, the difference in height between inclined surfaces With respect to 1 to 4 and the comparative example, the steps 4 and 5 were measured separately, and the average value and the maximum and minimum values were calculated. The results are shown in FIG. 5 for the staircase surface 4 and each graph in FIG. 6 for the staircase surface 5.

【0023】図5のグラフによれば、発明例1,2は全
体として比較例よりも移動距離、即ち傾斜度が少なくな
っており、また発明例1よりも発明例2の方が更に少な
くなっている。また、図6のグラフでも発明例3,4は
同様に比較例よりも傾斜度が少なく、且つ発明例3より
も発明例4の方が更に少なくなっている。これらの結果
から、絶縁層28,29を配置することによる本発明の
効果が理解されると共に、絶縁層28,29の配置数の
多少によっても傾斜度の程度を制御することが可能であ
ることも明らかである。従って、前記メタライズ層2
4,26の全ての内周側に沿って、これと同様の厚さを
有する絶縁層28,29を配置すると、階断面4,5に
おける傾斜面の発生を最も抑制できるが、製造工程がか
なり増加するので、前記のように複数のメタライズ層2
4,26のうち、その1層飛び毎や、或いは2層飛び毎
にその内周側に絶縁層28,29を配置することが製造
上からは望ましい。
According to the graph of FIG. 5, Invention Examples 1 and 2 as a whole have a smaller moving distance, that is, an inclination degree than that of the Comparative Example, and Invention Example 2 has a smaller amount than Invention Example 1. ing. Also in the graph of FIG. 6, invention examples 3 and 4 similarly have a smaller degree of inclination than the comparative example, and invention example 4 is even smaller than invention example 3. From these results, it is possible to understand the effect of the present invention by arranging the insulating layers 28 and 29, and it is possible to control the degree of inclination depending on the number of the insulating layers 28 and 29 arranged. Is also clear. Therefore, the metallized layer 2
If the insulating layers 28 and 29 having the same thickness are arranged along all the inner peripheral sides of the wirings 4 and 26, the generation of the inclined surface in the floor cross sections 4 and 5 can be most suppressed, but the manufacturing process is considerably performed. As described above, the number of metallization layers 2 increases.
From the viewpoint of manufacturing, it is desirable to dispose the insulating layers 28 and 29 on the inner peripheral side of each of the layers 4 and 26 or every two layers thereof.

【0024】本発明は以上において説明した形態に限定
されるものではない。例えば、前記セラミック層や絶縁
層の材質には、アルミナに限らず、窒化アルミニウム、
ガラスセラミック、ムライト等のセラミックを用いるこ
ともできる。尚、セラミック層と絶縁層の材質は、同種
のセラミックを併用する形態に限らず、焼成収縮等を考
慮して互いに異なる材質を用いることもできる。前記メ
タライズ層の材質は前記MoやWに限らず、Mo−M
n,Cu,Ag,Ag−Pd,Ag−Pt等を適用する
こともできる。また、本発明はキャビティ部を有する所
謂ピングリッドアレイ型やリードレスチップキャリア等
を含む全ての配線基板に適用でき、更にキャビティ部に
複数の半導体素子を搭載するマルチチップモジュールに
も適用することができる。しかも、キャビティ部内に搭
載する電子部品は、トランジスタ、EFT等を含む半導
体素子に限らず、コンデンサ、抵抗、インダクタ、SA
Wフィルタ等も含まれる。
The present invention is not limited to the form described above. For example, the material of the ceramic layer and the insulating layer is not limited to alumina, aluminum nitride,
Ceramics such as glass ceramics and mullite can also be used. The material of the ceramic layer and the insulating layer is not limited to the form in which the same type of ceramic is used in combination, but different materials may be used in consideration of firing shrinkage and the like. The material of the metallized layer is not limited to Mo and W, but may be Mo-M.
It is also possible to apply n, Cu, Ag, Ag-Pd, Ag-Pt, or the like. Further, the present invention can be applied to all wiring boards including a so-called pin grid array type having a cavity portion and a leadless chip carrier, and further applied to a multi-chip module having a plurality of semiconductor elements mounted in the cavity portion. it can. Moreover, the electronic components mounted in the cavity are not limited to semiconductor elements including transistors, EFTs, etc., but capacitors, resistors, inductors, SAs, etc.
A W filter and the like are also included.

【0025】[0025]

【発明の効果】以上において説明した本発明の配線基板
によれば、複数のセラミック層を積層して形成され、
れらの層間にメタライズ層とこれよも厚い絶縁層とが所
定の位置に形成されているため、その枠部内周側の階段
面上に配置される多数の接続用パッドが本来の所定の位
置に設けられ易くなる。このため、上記パッドとキャビ
ティ部に搭載される半導体素子等の電子部品とを接続す
るためのワイヤボンディングを容易且つ確実に行うこと
が可能となる。また、本発明の製造方法によれば、上記
の配線基板を所望量に応じて確実且つ正確に提供するこ
とが可能になる
According to the wiring board of the present invention described above, according to the present invention is formed by laminating a plurality of ceramic layers, its
There is a metallization layer and a thicker insulating layer between these layers.
Since it is formed at a fixed position, it becomes easy to provide a large number of connection pads arranged on the stepped surface on the inner peripheral side of the frame portion at the original predetermined position . Therefore, it becomes possible to easily and surely perform wire bonding for connecting the pad and an electronic component such as a semiconductor element mounted in the cavity. Further, according to the manufacturing method of the present invention, it is possible to reliably and accurately provide the above wiring board in a desired amount .

【図面の簡単な説明】[Brief description of drawings]

【図1】(A)は本発明の配線基板の一形態を示す斜視
図、(B)は(A)中におけるB−B断面図である。
FIG. 1A is a perspective view showing an embodiment of a wiring board of the present invention, and FIG. 1B is a sectional view taken along line BB in FIG.

【図2】図1(B)中におけるイ−イに沿って切断した部
分端面図である。
FIG. 2 is a partial end view taken along the line EE in FIG.

【図3】(A)、(B)は共に異なる形態の絶縁層を示す図
2と同様な部分端面図である。
3 (A) and 3 (B) are partial end views similar to FIG. 2, showing different forms of insulating layers.

【図4】(A)、(B)は共に本発明の配線基板の製造工程
を示す概略断面図である。
4A and 4B are schematic cross-sectional views showing the manufacturing process of the wiring board of the present invention.

【図5】本発明例1,2及び比較例の傾斜面における高
さの差の分布を示すグラフである。
FIG. 5 is a graph showing distributions of height differences on the inclined surfaces of Inventive Examples 1 and 2 and Comparative Example.

【図6】本発明例3,4及び比較例の傾斜面における高
さの差の分布を示すグラフである。
FIG. 6 is a graph showing distributions of height differences on inclined surfaces of Inventive Examples 3 and 4 and Comparative Example.

【図7】(A)は従来の配線基板を示す斜視図、(B)は
(A)中におけるB−B断面図である。
FIG. 7A is a perspective view showing a conventional wiring board, and FIG.
It is a BB sectional view in (A).

【符号の説明】[Explanation of symbols]

1…………………………配線基板 2…………………………キャビティ部 3,40,50…………枠部 4,5……………………階段面 6,8……………………接続用パッド 10〜21,44,54…セラミック層 22………………………セラミック層(底部) 24,26,46,56……メタライズ層 25,27,42,52……引き下がり部 28,29,48,58……絶縁層 53………………………角部 55………………………辺部 60〜72………………グリーンシート 84,86………………導電ペースト 88,89………………絶縁ペースト 1 ……………………………… Wiring board 2 ……………………………… Cavity 3, 40, 50 ………… Frame part 4,5 ………………………… Stairs 6,8 ………………………… Connection pad 10-21, 44, 54 ... Ceramic layer 22 ……………………………… Ceramic layer (bottom) 24, 26, 46, 56 ... Metallized layer 25,27,42,52 ... Downward part 28,29,48,58 ... Insulating layer 53 ……………………………… Corner 55 ………………………… Hedge 60-72 ……………… Green sheet 84,86 ……………… Conductive paste 88,89 ……………… Insulation paste

───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.7,DB名) H01L 23/12 ─────────────────────────────────────────────────── ─── Continuation of front page (58) Fields surveyed (Int.Cl. 7 , DB name) H01L 23/12

Claims (5)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】電子部品を搭載するためのキャビティ部
と、 複数のセラミック層を積層してなり、上記キャビティ部
を囲むように形成され、内周側が断面階段形状である枠
部と、 少なくとも上記キャビティ部の底面をなすように枠部に
固着された底部と、 上記枠部の階断面上に形成され電子部品と接続するため
の接続用パッドと、 を含む配線基板であって、 上記枠部を形成する複数のセラミック層の層間のうち少
なくとも1つ以上の層間に形成され、内周縁が平面視に
て上記接続用パッドの略直下で且つセラミック層の内周
縁より引き下がった位置に形成されたメタライズ層と、 少なくとも1つ以上のメタライズ層の内周縁とセラミッ
ク層の内周縁との間の引き下がり部のうち少なくとも上
記接続用パッドの略直下に設けた絶縁層と、 を含み、上記絶縁層の厚みは、上記メタライズ層の厚み
よりも厚い、 ことを特徴とする配線基板。
1. A cavity portion for mounting an electronic component, and a frame portion formed by laminating a plurality of ceramic layers, surrounding the cavity portion, and having an inner peripheral side having a stepwise cross-section, at least the above. A wiring board including a bottom portion fixed to the frame portion so as to form a bottom surface of the cavity portion, and a connection pad formed on the floor cross section of the frame portion for connecting to an electronic component, the frame portion Is formed between at least one or more layers of the plurality of ceramic layers forming the inner peripheral edge, and the inner peripheral edge is formed at a position substantially directly below the connecting pad and lower than the inner peripheral edge of the ceramic layer in plan view. A metallization layer; and an insulating layer provided at least substantially directly under the connection pad in a pull-down portion between the inner edge of at least one metallization layer and the inner edge of the ceramic layer. The thickness of the insulating layer is the thickness of the metallized layer.
A wiring board characterized by being thicker than .
【請求項2】前記枠部が、4層以上の前記メタライズ層
を有している ことを特徴とする請求項1に記載の配線基板。
2. A wiring board according to claim 1, wherein the frame portion has a four or more layers of the metallization layer, and wherein the.
【請求項3】前記絶縁層が、前記メタライズ層のうちの
1層飛び又は2層飛び毎の前記引き下がり部に形成され
ていることを特徴とする請求項1又は2に記載の配線
基板。
Wherein the insulating layer is one layer jump or are formed on the withdraw portion of each jumping two-layer wiring board according to claim 1 or 2, characterized in that of said metallized layer.
【請求項4】前記キャビティ部が平面視で矩形状を呈
し、前記引き下がり部が平面視で矩形枠状に形成され、
前記絶縁層が上記引き下がり部のうち角部を除いてその
辺部に形成される、ことを特徴とする請求項1乃至3の
何れかに記載の配線基板。
4. The cavity has a rectangular shape in plan view.
The pull-down portion is formed in a rectangular frame shape in plan view,
The insulating layer is the
The wiring board according to any one of claims 1 to 3, wherein the wiring board is formed on a side portion .
【請求項5】請求項1乃至4の何れかに記載の配線基板
の製造方法であって、 焼成後に前記セラミック層となる複数のグリーンシート
の何れかの表面に、焼成後に前記メタライズ層となる導
電ペーストを塗布する工程と、 少なくとも一部の上記グリーンシートの表面に、焼成後
に前記絶縁層となる絶縁ペーストを上記導電ペーストの
内周側に沿って、当該導電ペーストの厚みよりも厚く塗
布する工程とを、相前後して含む、ことを特徴とする配
線基板の製造方法
5. The wiring board according to claim 1.
A method of manufacturing a plurality of green sheets after firing becomes the ceramic layer
On either surface of the metal, which will become the metallized layer after firing.
Step of applying an electric paste, and after firing on at least part of the surface of the green sheet
Insulating paste that becomes the insulating layer of the conductive paste
Along the inner circumference side, it should be thicker than the thickness of the conductive paste.
The step of clothing is included before and after.
Method of manufacturing line substrate .
JP09747697A 1997-04-15 1997-04-15 Wiring board and its manufacturing method Expired - Fee Related JP3508905B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP09747697A JP3508905B2 (en) 1997-04-15 1997-04-15 Wiring board and its manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP09747697A JP3508905B2 (en) 1997-04-15 1997-04-15 Wiring board and its manufacturing method

Publications (2)

Publication Number Publication Date
JPH10289964A JPH10289964A (en) 1998-10-27
JP3508905B2 true JP3508905B2 (en) 2004-03-22

Family

ID=14193356

Family Applications (1)

Application Number Title Priority Date Filing Date
JP09747697A Expired - Fee Related JP3508905B2 (en) 1997-04-15 1997-04-15 Wiring board and its manufacturing method

Country Status (1)

Country Link
JP (1) JP3508905B2 (en)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100388564B1 (en) * 2001-07-26 2003-06-25 삼성전기주식회사 High performance ball grid array substrate and method for preparing the same
JP4543374B2 (en) * 2004-07-05 2010-09-15 日立金属株式会社 Multilayer substrate and manufacturing method thereof
JP4565383B2 (en) * 2004-10-07 2010-10-20 日立金属株式会社 Multilayer ceramic substrate with cavity and method for manufacturing the same
KR20070083505A (en) 2005-05-12 2007-08-24 가부시키가이샤 무라타 세이사쿠쇼 Ceramic multilayer board
EP2255601B1 (en) * 2008-04-30 2012-05-16 Panasonic Corporation Method of producing circuit board by additive method
US8240036B2 (en) 2008-04-30 2012-08-14 Panasonic Corporation Method of producing a circuit board
US9082438B2 (en) 2008-12-02 2015-07-14 Panasonic Corporation Three-dimensional structure for wiring formation
JP2010251516A (en) * 2009-04-15 2010-11-04 Hitachi Automotive Systems Ltd Method of manufacturing multilayer ceramic substrate, and air meter using multilayer ceramic substrate

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5128663A (en) * 1974-09-02 1976-03-11 Nippon Electric Co Denshikairoyokizai no seizohoho
JPH06252558A (en) * 1993-03-01 1994-09-09 Oki Electric Ind Co Ltd Multilayered glass ceramic cavity substrate
JP3091378B2 (en) * 1994-12-27 2000-09-25 株式会社住友金属エレクトロデバイス Ceramic multilayer substrate

Also Published As

Publication number Publication date
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