JPH0380596A - Manufacture of multilayer ceramic circuit substrate - Google Patents
Manufacture of multilayer ceramic circuit substrateInfo
- Publication number
- JPH0380596A JPH0380596A JP21808289A JP21808289A JPH0380596A JP H0380596 A JPH0380596 A JP H0380596A JP 21808289 A JP21808289 A JP 21808289A JP 21808289 A JP21808289 A JP 21808289A JP H0380596 A JPH0380596 A JP H0380596A
- Authority
- JP
- Japan
- Prior art keywords
- conductor
- thin film
- ceramic insulating
- connection via
- grinding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000919 ceramic Substances 0.000 title claims abstract description 51
- 239000000758 substrate Substances 0.000 title claims description 24
- 238000004519 manufacturing process Methods 0.000 title claims description 22
- 239000004020 conductor Substances 0.000 claims abstract description 35
- 239000010409 thin film Substances 0.000 claims abstract description 23
- 238000000227 grinding Methods 0.000 claims abstract description 17
- 238000007747 plating Methods 0.000 claims abstract description 11
- 239000002184 metal Substances 0.000 claims abstract description 9
- 229910052751 metal Inorganic materials 0.000 claims abstract description 9
- 238000000034 method Methods 0.000 claims description 15
- 239000000945 filler Substances 0.000 claims description 8
- 239000000843 powder Substances 0.000 claims description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 7
- 229910052802 copper Inorganic materials 0.000 abstract description 5
- 239000010949 copper Substances 0.000 abstract description 5
- 239000011800 void material Substances 0.000 abstract description 5
- 229910000570 Cupronickel Inorganic materials 0.000 abstract description 4
- YOCUPQPZWBBYIX-UHFFFAOYSA-N copper nickel Chemical compound [Ni].[Cu] YOCUPQPZWBBYIX-UHFFFAOYSA-N 0.000 abstract description 4
- 238000001354 calcination Methods 0.000 abstract 1
- 238000009413 insulation Methods 0.000 abstract 1
- 238000007796 conventional method Methods 0.000 description 4
- 238000010304 firing Methods 0.000 description 4
- 238000004544 sputter deposition Methods 0.000 description 4
- 238000010276 construction Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 238000011049 filling Methods 0.000 description 3
- 238000010030 laminating Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 2
- 238000000137 annealing Methods 0.000 description 1
- 229910000365 copper sulfate Inorganic materials 0.000 description 1
- ARUVKPQLZAKDPS-UHFFFAOYSA-L copper(II) sulfate Chemical compound [Cu+2].[O-][S+2]([O-])([O-])[O-] ARUVKPQLZAKDPS-UHFFFAOYSA-L 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000009740 moulding (composite fabrication) Methods 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 238000005245 sintering Methods 0.000 description 1
- 239000002002 slurry Substances 0.000 description 1
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
【発明の詳細な説明】
〔概 要〕
大型電子機器の構成に広く使用される多層セラ旦ツタ回
路基板の製造方法に関し、
接続ビアと表面パターンとの接続障害を皆無にすること
ができる多層セラミック回路基板の製造方法の提供を目
的とし、
ビア充填剤の充填と内層用パターンを印刷した複数枚の
グリーンシートを積層，焼成して接続ビアを配したセラ
ミック絶縁基体を形成し、当該セラミック絶縁基体の両
面を研削して表面に所定の表面パターンを形成する回路
基板の製造方法において、上記両面を研削後に電極用の
導体薄膜を該セラミック絶縁基体の片面に施して、導電
性の優れた金属メッキ°により接続ビアと結合した補充
導体を形成し、再び両面を研削して該導体薄膜と表面よ
り突出した該補充導体を除去する工程、または上記セラ
ミック絶縁基体の両面研削により露出した接続ビアの未
充填部分に導電性の優れた金属粉を補填し、再度焼結す
ることにより当該接続ビアと結合した補充導体を形成し
て該セラミック絶縁基体の両面を再研削する工程を付加
する。[Detailed Description of the Invention] [Summary] Regarding the manufacturing method of multilayer ceramic vine circuit boards widely used in the construction of large electronic devices, the present invention relates to a method for manufacturing multilayer ceramic circuit boards that are widely used in the construction of large electronic devices. For the purpose of providing a method for manufacturing a circuit board, a ceramic insulating substrate is formed by laminating and firing a plurality of green sheets filled with a via filler and printed with patterns for inner layers, and the ceramic insulating substrate is In a method of manufacturing a circuit board in which a predetermined surface pattern is formed on the surface by grinding both sides of the substrate, a conductive thin film for electrodes is applied to one side of the ceramic insulating substrate after grinding both sides, and metal plating with excellent conductivity is formed. A step of forming a supplementary conductor combined with the connection via by °, and then grinding both sides again to remove the conductor thin film and the supplementary conductor protruding from the surface, or the process of grinding both sides of the ceramic insulating substrate to remove the exposed connection via. A step is added in which the filled portion is supplemented with metal powder having excellent conductivity and sintered again to form a supplementary conductor bonded to the connection via, and both surfaces of the ceramic insulating substrate are re-ground.
（産業上の利用分野）
本発明は、大型電子機器の構成に広く使用される多層セ
ラミック回路基板の製造方法に関する。(Industrial Application Field) The present invention relates to a method of manufacturing a multilayer ceramic circuit board widely used in the construction of large-scale electronic equipment.
最近、特に、各種電算機等のプリント仮に実装される半
導体チップが高集積化されるに伴い、その半導体チップ
を実装する回路基板も微細化された導体パターンと、微
細な内部接続用のビアが高密度に形成されているがその
接続用ビアには抵抗が低く、且つ低コストが望まれてい
る。そのためグリーンシートのピアホールに銅よりなる
粉末を充填して焼成しているが、基板表面近傍の空洞。Recently, in particular, as semiconductor chips temporarily mounted on various computers have become more highly integrated, the circuit boards on which the semiconductor chips are mounted are also becoming more and more sophisticated, with finer conductor patterns and finer vias for internal connections. Although they are formed in high density, the connection vias are desired to have low resistance and low cost. For this reason, the peer holes of the green sheet are filled with copper powder and fired, but the cavities near the surface of the substrate.
あるいは充填不足による引は等が生じて、基板表面に形
成する薄膜パターンとの間に接続障害が発生するので、
接続ビアと表面薄膜パターンとの接続障害を皆無にする
ことができる新しい多層セラミック回路基板の製造方法
が必要とされている。Alternatively, pulling may occur due to insufficient filling, which may cause a connection failure between the thin film pattern formed on the substrate surface.
There is a need for a new method for manufacturing multilayer ceramic circuit boards that can completely eliminate connection failures between connection vias and surface thin film patterns.
［従来の技術］
従来の多層セラミック基板の製造方法を第３図の工程順
側断面図に示す。[Prior Art] A conventional method for manufacturing a multilayer ceramic substrate is shown in step-by-step side cross-sectional views in FIG.
（ａ）は、一定１蓼みのスラリーを乾燥して加熱と加圧
により焼鈍と密度の均一化を行った絶縁基体となるグリ
ーンシート１に、パンチングシステム等により多数個の
微細なピアホール１−１を穿孔した状態、
（ｂ）は、グリーンシート１の上面にビア充填用の図示
していないスクリーンを被せ、その上に導電性の優れた
金属粉末９例えば銅よりなるビア充填剤２″を搭載し、
図示していないスキージ等により前記ピアホール１−１
に当該ビア充填剤２°を充填して、その片面、または両
面に内層パターン３を印刷した状態ッ
（ｃ）は、内装パターン３の印刷とビア充填剤２″を充
填したグリーンシート１を複数枚積層して押圧すること
によりグリーンシートの積層体４′を形成した状態、
（ｄ）は、上記積層体４゛を高温で焼成することにより
セラミック絶縁基体４に接続ビア２を形成した状態、
（ｅ）は、上記ビア２を形成したセラミック絶縁基体４
の表裏両面を平面状に研削し、その両面にスパッタ、ま
たはメッキにより銅の導体ｍ［５′を形成した状態、
（ｆ）は、上記導体薄膜５′をエツチングして所定の表
面パターン５を形成した状態、
の工程順により多層セラミック回路基板を製造している
。(a) shows a green sheet 1, which serves as an insulating substrate, which is made by drying a slurry of a certain thickness, annealing it by heating and pressurizing it, and making the density uniform. In (b), a screen (not shown) for filling vias is placed on the top surface of the green sheet 1, and a via filler 2'' made of highly conductive metal powder 9, for example, copper is placed on top of the screen. Equipped with
The pier hole 1-1 is removed using a squeegee or the like (not shown).
The state in which the via filler 2° is filled and the inner layer pattern 3 is printed on one or both sides of the inner layer pattern 3 is shown in (c). (d) shows a state in which a green sheet laminate 4' is formed by stacking and pressing the green sheets; (d) shows a state in which connecting vias 2 are formed in the ceramic insulating base 4 by firing the laminate 4' at a high temperature; (e) shows the ceramic insulating base 4 on which the via 2 is formed.
(f) is a state in which the front and back surfaces of the etching are ground into a flat shape, and a copper conductor m[5' is formed on both surfaces by sputtering or plating. A multilayer ceramic circuit board is manufactured according to the following steps in the formed state.
［発明が解決しようとする課題〕
以上説明した従来の多層セラミック回路基板の製造方法
で問題となるのは、銅よりなる粉末のビア充填剤をピア
ホールに充填したグリーンシートを焼成すると、ビア充
填剤の充填量不足、或いは気泡等により、第４図に示す
ようにセラミック絶縁基体４に形成された接続ビア２に
引けが生じたり表面近傍にボイド（空洞）が発生して、
セラミック絶縁基体４の表面に形成する表面パターン５
との間に接続障害が発生している。そのため、接続障害
が発生した個所は電子部品実装時において予備の接続ビ
ア２を介して基板表面に改造ワイヤを布線することによ
り回路を接続しているので、その布線作業に熟練と多く
の時間を要するという問題が生じている。[Problems to be Solved by the Invention] A problem with the conventional method for manufacturing multilayer ceramic circuit boards described above is that when a green sheet whose peer holes are filled with via filler made of copper powder is fired, the via filler Due to insufficient filling amount or air bubbles, the connection via 2 formed in the ceramic insulating base 4 may shrink or voids may occur near the surface, as shown in FIG.
Surface pattern 5 formed on the surface of ceramic insulating substrate 4
There is a connection failure between the Therefore, when mounting electronic components, the circuit is connected to the location where the connection failure has occurred by wiring modified wires on the board surface via the spare connection vias 2. The problem is that it takes time.
本発明は上記のような問題点に鑑み、接続ビアと表面パ
ターンとの接続障害を皆無にすることができる多層セラ
ミック回路基板の製造方法の提供を目的とする。In view of the above-mentioned problems, the present invention aims to provide a method for manufacturing a multilayer ceramic circuit board that can completely eliminate connection failures between connection vias and surface patterns.
本発明は、第１図に示すようにビア充填剤の充填と内層
用パターン３を印刷した複数枚のグリーンシート１を積
層、焼成して接続ビア２を配したセラミック絶縁基体４
を形成し、当該セラ果ツク絶縁基体４の両面を研削して
所定の表面パターン５を形成する回路基板の製造方法に
おいて、上記両面を研削後に電極用の導体薄膜１６を該
セラミック絶縁基体４の片面に施して、導電性の優れた
金属メッキにより接続ビア２と結合した補充導体１７を
形成し、再び両面を研削して該導体薄膜１６と表面より
突出した該補充導体１７を除去する工程、または、上記
セラミック絶縁基体４の両面研削により露出した接続ビ
ア２の未充填部分に導電性の優れた金属粉を補填し、再
度焼結することにより当該接続ビア２と結合した補充導
体２７を形成して、該セラミック絶縁基体４の両面を再
研削する工程を付加する。As shown in FIG. 1, a plurality of green sheets 1 filled with a via filler and printed with an inner layer pattern 3 are laminated and fired to form a ceramic insulating base 4 on which connection vias 2 are arranged.
In the method for manufacturing a circuit board in which a predetermined surface pattern 5 is formed by grinding both surfaces of the ceramic insulating substrate 4, a conductive thin film 16 for an electrode is formed on the ceramic insulating substrate 4 after grinding both surfaces. A step of forming a supplementary conductor 17 coupled to the connection via 2 by applying metal plating with excellent conductivity on one side, and grinding both sides again to remove the conductor thin film 16 and the supplementary conductor 17 protruding from the surface; Alternatively, the unfilled portion of the connection via 2 exposed by grinding both sides of the ceramic insulating base 4 is supplemented with highly conductive metal powder, and the supplementary conductor 27 combined with the connection via 2 is formed by sintering it again. Then, a step of re-grinding both surfaces of the ceramic insulating substrate 4 is added.
本発明では、セラミック絶縁基体４に形成された接続ビ
ア２の未充填部分に補充導体１７．２７を形成して、そ
の補充導体１７．２７とともにセラミック絶縁基体４の
両面を再研削することにより、セラミック絶縁基体４の
両面と補充された接続ビア２のそれぞれ端面が同一平面
となり、その後にセラミック絶縁基体４の両面に表面パ
ターン５を形成しているため、接続ビア２と表面パター
ン５が密着して接続障害を皆無にすることが可能となる
。In the present invention, a supplementary conductor 17.27 is formed in the unfilled portion of the connection via 2 formed in the ceramic insulating substrate 4, and both surfaces of the ceramic insulating substrate 4 are reground together with the supplementary conductor 17.27. Both sides of the ceramic insulating base 4 and the end faces of the supplemented connection vias 2 are on the same plane, and then the surface patterns 5 are formed on both sides of the ceramic insulating base 4, so the connection vias 2 and the surface patterns 5 are in close contact with each other. This makes it possible to completely eliminate connection failures.
以下第１図および第２図について本発明の詳細な説明す
る。The present invention will be described in detail below with reference to FIGS. 1 and 2.
第１図は本発明の第一実施例による多層セラミック回路
基板の製造方法を示す工程順側断面図、第２図は第二実
施例による多層セラミック回路基板製造方法の工程順側
断面図を示す。FIG. 1 is a step-by-step side cross-sectional view showing a method for manufacturing a multilayer ceramic circuit board according to a first embodiment of the present invention, and FIG. 2 is a step-by-step side cross-sectional view of a method for manufacturing a multilayer ceramic circuit board according to a second embodiment of the present invention. .
第一実施例による多層セラミック回路基板の製造方法は
第１図に示すように、
（ａ）は、ピアホールに銅粉末のビア充填剤を充填する
とともにその表面に内層パターン３を印刷したグリーン
シート１を複数枚積層して、その積層体４′を高温で焼
成する従来と同一方法により接続ビア２を配したセラミ
・ンク絶縁基体４を形成し、その両面を研削することに
より接続ビア２の引け。The method for manufacturing a multilayer ceramic circuit board according to the first embodiment is as shown in FIG. A ceramic insulating base 4 with connection vias 2 arranged thereon is formed by the same conventional method of laminating a plurality of layers and firing the laminate 4' at high temperature. .
およびボイドを表面に露出させた状態、（ｂ）は、その
セラミック絶縁基体４の片面にスパッタ、または無電解
メッキにより銅−ニッケルメッキの薄膜を施して、前記
接続ビア２と導通した導体薄８１６を形成した状態、
（ｃ）は、セラミック絶縁基体４を硫酸銅のメッキ浴に
浸漬し、上記導体薄膜１６を一電極として当該導体薄膜
１６と接続ビア２に銅メッキを施すことにより、接続ビ
ア２の引け、およびボイド部に補充導体１７を形成した
状態、
（ｄ）は、再び両面を研削して前記銅−ニッケルの導体
薄膜１６を除去するとともに、前記補充導体１７の表面
より突出した部分を除去して平面を形成した状態、
（ｅ）は、その両面にスパッタ、またはメッキにより接
続ビア２と導通した銅の導体薄膜を形成して、エツチン
グにより所定の表面パターン５を形成した状態、
また、第二実施例の多層セラトンク回路基板の製造方法
は第２図に示すように、
（ａ）は、第一実施例と同様にビア充填剤の充填と内層
パターン３を印刷した複数枚のグリーンシート１を積層
して焼成したセラミック絶縁基体４の両面を研削して、
接続ビア２の引け、およびボイドを表面に露出させた状
態、
（ｂ）は、その接続ビア２の引け、およびボイド部に前
記ビア充填剤と同質の金属粉を充填して、再度焼結によ
り接続ビア２と結合した補充導体２７を形成した状態、
（ｃ）は、再び両面を研削して前記補充導体２７の表面
より突出した部分を除去して平面を形成した状態、
（ｄ）は、その両面にスパッタ、またはメッキにより接
続ビア２と導通した導体薄膜を形成して、エツチングに
より所定の表面パターン５を形成した状態、
の工程順により多層セラミック回路基板を製造する。and a state in which voids are exposed on the surface, (b) shows a conductor thin film 816 which is electrically connected to the connection via 2 by applying a thin film of copper-nickel plating on one side of the ceramic insulating base 4 by sputtering or electroless plating. In (c), the ceramic insulating substrate 4 is immersed in a copper sulfate plating bath, and the conductor thin film 16 and the connection via 2 are plated with copper using the conductor thin film 16 as one electrode, thereby forming the connection via. 2, and the state in which the supplementary conductor 17 is formed in the void part. (d) shows the state in which the copper-nickel conductor thin film 16 is removed by grinding both sides again, and the part protruding from the surface of the supplementary conductor 17 is removed. (e) is a state in which a copper conductive thin film electrically connected to the connecting via 2 is formed on both surfaces by sputtering or plating, and a predetermined surface pattern 5 is formed by etching. In addition, the method for manufacturing the multilayer Ceratonk circuit board of the second embodiment is as shown in FIG. Grinding both sides of the ceramic insulating base 4 made by laminating and firing the green sheets 1,
The state in which the connection via 2 is closed and the void is exposed on the surface, (b) is the state in which the connection via 2 is closed and the void is filled with metal powder of the same quality as the via filler, and then sintered again. A state in which the supplementary conductor 27 combined with the connection via 2 is formed; (c) a state in which both surfaces are ground again to remove the portion protruding from the surface of the supplementary conductor 27 to form a flat surface; (d), A multilayer ceramic circuit board is manufactured by following the steps of forming a conductive thin film electrically connected to the connecting via 2 on both surfaces by sputtering or plating, and forming a predetermined surface pattern 5 by etching.
その結果、セラｌ ７り絶縁基体４の両面と補充された
接続ビア２のそれぞれ端面が同一平面となるので、セラ
ミック絶縁基体４の表面に形成される表面パターン５と
の接続障害を皆無にすることができる。As a result, both sides of the ceramic insulating base 4 and the respective end faces of the supplemented connection vias 2 become on the same plane, thereby eliminating any connection failure with the surface pattern 5 formed on the surface of the ceramic insulating base 4. be able to.
以上の説明から明らかなように本発明によれば極めて簡
単な工程を付加することにより、基板内接続ビアと表面
パターンとの接続障害を皆無にすることができて、改造
ワイヤの布線がなくなる等の利点があり、著しい経済的
及び、信頼性向上の効果が期待できる多層セラミック回
路基板の製造方法を提供することができる。As is clear from the above explanation, according to the present invention, by adding an extremely simple process, it is possible to completely eliminate connection failures between the connection vias in the board and the surface pattern, eliminating the need for wiring modified wires. It is possible to provide a method for manufacturing a multilayer ceramic circuit board, which has the following advantages and can be expected to have significant economical and reliability improvement effects.
第１図は本発明の第一実施例による多層セラ亀ツタ回路
基板の製造方法を示す工程順側断面図、第２図は第二実
施例による多層セラミック回路基板の製造方法を示す工
程順側断面図、第３図は従来の多層セラミック回路基板
の製造方法を示す工程順側断面図、
第４図は課題を説明する断面図である。
図において、
１はグリーンシート、
２は接続ビア、
３は内層パターン、
４はセラミック絶縁基体、
５は表面パターン、
５゛１６は導体薄膜、
１７．２７は補充導体、
を示す。
第
図
第
図
工昶慢倒時面図
第３図FIG. 1 is a step-by-step sectional view showing a method for manufacturing a multilayer ceramic circuit board according to a first embodiment of the present invention, and FIG. 2 is a step-by-step side view showing a method for manufacturing a multilayer ceramic circuit board according to a second embodiment of the present invention. 3 is a cross-sectional view showing a conventional method for manufacturing a multilayer ceramic circuit board in the order of steps, and FIG. 4 is a cross-sectional view illustrating a problem. In the figure, 1 is a green sheet, 2 is a connecting via, 3 is an inner layer pattern, 4 is a ceramic insulating substrate, 5 is a surface pattern, 5, 16 is a conductive thin film, and 17.27 is a supplementary conductor. Figure 3 Figure 3
Claims (2)
した複数枚のグリーンシート（１）を積層，焼成して接
続ビア（２）を配したセラミック絶縁基体（４）を形成
し、当該セラミック絶縁基体（４）の両面を研削して表
面に所定の表面パターン（５）を形成する回路基板の製
造方法において、 上記両面を研削後に電極用の導体薄膜（１６）を該セラ
ミック絶縁基体（４）の片面に施して、導電性の優れた
金属メッキにより接続ビア（２）と結合した補充導体（
１７）を形成し、再び両面を研削して該導体薄膜（１６
）と表面より突出した該補充導体（１７）を除去する工
程を付加したことを特徴とする多層セラミック回路基板
の製造方法。(1) A plurality of green sheets (1) filled with a via filler and printed with an inner layer pattern (3) are laminated and fired to form a ceramic insulating substrate (4) on which connection vias (2) are arranged; In the method for manufacturing a circuit board, which comprises grinding both surfaces of the ceramic insulating substrate (4) to form a predetermined surface pattern (5) on the surface, after grinding both surfaces, a conductive thin film (16) for an electrode is applied to the ceramic insulating substrate. A supplementary conductor (4) is attached to one side of the connecting via (2) by highly conductive metal plating.
17) and then grinding both surfaces again to form the conductor thin film (16).
) and a step of removing the supplementary conductor (17) protruding from the surface.
露出した接続ビア（２）の未充填部分に導電性の優れた
金属粉、補填し、再度焼結することにより当該接続ビア
（２）と結合した補充導体（２７）を形成して、該セラ
ミック絶縁基体（４）の両面を再研削する工程を付加し
たことを特徴とする請求項１記載の多層セラミック回路
基板の製造方法。(2) Fill the unfilled portion of the connection via (2) exposed by grinding both sides of the ceramic insulating substrate (4) with highly conductive metal powder, and sinter it again to form the connection via (2). 2. The method of manufacturing a multilayer ceramic circuit board according to claim 1, further comprising the additional step of forming bonded supplementary conductors (27) and regrinding both sides of the ceramic insulating substrate (4).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21808289A JPH0380596A (en) | 1989-08-23 | 1989-08-23 | Manufacture of multilayer ceramic circuit substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21808289A JPH0380596A (en) | 1989-08-23 | 1989-08-23 | Manufacture of multilayer ceramic circuit substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0380596A true JPH0380596A (en) | 1991-04-05 |
Family
ID=16714357
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21808289A Pending JPH0380596A (en) | 1989-08-23 | 1989-08-23 | Manufacture of multilayer ceramic circuit substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0380596A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011009716A (en) * | 2009-05-28 | 2011-01-13 | Denka Agsp Kk | Method of manufacturing substrate for light emitting element mounting |
| US8009536B2 (en) | 2006-12-25 | 2011-08-30 | Hitachi, Ltd. | Recording and reproducing apparatus |
| EP2960007A2 (en) | 2014-04-08 | 2015-12-30 | Toyota Jidosha Kabushiki Kaisha | Laser weld method and weld structure |
| JPWO2015029951A1 (en) * | 2013-08-26 | 2017-03-02 | 日立金属株式会社 | Wafer for mounting substrate, multilayer ceramic substrate, mounting substrate, chip module, and method for manufacturing wafer for mounting substrate |
-
1989
- 1989-08-23 JP JP21808289A patent/JPH0380596A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8009536B2 (en) | 2006-12-25 | 2011-08-30 | Hitachi, Ltd. | Recording and reproducing apparatus |
| JP2011009716A (en) * | 2009-05-28 | 2011-01-13 | Denka Agsp Kk | Method of manufacturing substrate for light emitting element mounting |
| JPWO2015029951A1 (en) * | 2013-08-26 | 2017-03-02 | 日立金属株式会社 | Wafer for mounting substrate, multilayer ceramic substrate, mounting substrate, chip module, and method for manufacturing wafer for mounting substrate |
| EP2960007A2 (en) | 2014-04-08 | 2015-12-30 | Toyota Jidosha Kabushiki Kaisha | Laser weld method and weld structure |
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