JP2007173627A - Capacitor incorporated into wiring board, and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method of a capacitor incorporated into a wiring board capable of forming a plated film on an external electrode layer efficiently by electrolytic plating, and to provide the capacitor incorporated into a wiring board suitable for incorporation into the wiring board. <P>SOLUTION: When manufacturing the capacitor 1, a laminate 29 is formed first, and external electrode patterns 30, 31 are formed on the laminate 29 over a plurality of capacitor formation regions R, are electrically connected to internal electrode patterns 21, 23 in each capacitor formation region R, and are baked to external electrode layers 8, 9. Then, perforated break grooves 29c penetrating the external electrode patterns 30, 31 are formed for baking in the laminate 29 along at least one portion of the boundary of respective capacitor formation regions R. Then, current is supplied to the external electrode layers 8, 9, plated films 10, 11 are formed on the external electrode layers 8, 9 by electrolytic plating, and the laminate 29 is divided along the break groove 29c. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a wiring board built-in capacitor and a wiring board built-in capacitor.

  In recent years, the operation of semiconductor chips has been increasingly accelerated due to advances in integrated circuit technology. As a result, noise may be superimposed on the power supply wiring and the like, causing malfunction. Therefore, a capacitor is mounted on the upper surface or the lower surface of the wiring substrate on which the semiconductor chip is mounted to remove noise.

  However, in the above method, it is necessary to separately mount a capacitor after the wiring board is completed, so that the number of processes increases. In addition, it is necessary to secure a region for mounting the capacitor on the wiring board in advance, which reduces the degree of freedom of other electronic components. Furthermore, by being limited to other wirings, the wiring distance between the capacitor and the semiconductor chip becomes long, and the wiring resistance and inductance increase. For this reason, a technique for incorporating a capacitor in a wiring board has been proposed (see, for example, Patent Document 1).

  A capacitor built in such a wiring board is manufactured by forming a laminated body having a plurality of laminated dielectric layers and internal electrode layers arranged between the dielectric layers, and firing the laminated body. However, warping may occur during firing. For this reason, it has been proposed to produce an assembly of capacitors and divide each capacitor after firing.

  By the way, in the capacitor built in the wiring board, it is necessary to form an external electrode layer for electrical connection to the wiring formed on the wiring board, and the external electrode layer plating film is formed on the external electrode layer. However, in order to improve adhesion between the build-up layer and the insulating layer and to prevent oxidation of the external electrode layer, a plating film may be formed. This plating film is currently formed by electroless plating.

  However, when a plating film is formed by electroless plating, a long time is required. In addition, when the distance between the external electrode layers is as narrow as 150 μm, the external electrode layers may be connected by a plating film, resulting in an electrical short circuit.

  For this reason, it has been proposed to form a plating film by electrolytic plating instead of electroless plating. However, when producing a capacitor assembly as described above, it is necessary to form a break groove in the assembly to divide each capacitor. Therefore, between the adjacent capacitors, the external electrode layers are mutually connected. They are separated by a break groove. For this reason, when forming a plating film by electrolytic plating, an electrode etc. must be contacted for every external electrode layer, and a plating film cannot be formed efficiently by electrolytic plating.

It is to be noted that, when a printed wiring board is manufactured, a technique is disclosed in which a perforation is formed at the boundary between a main body on which a wiring pattern is formed and a discard plate, and then electrolytic plating or the like is applied to the wiring pattern (for example, a patent) Reference 2). However, the perforation in this technique is only for dividing the main body and the discard plate, and has nothing to do with electrolytic plating.
JP-A-2005-39243 JP-A-61-276396

  The present invention has been made to solve the above problems. That is, it is possible to provide a method for manufacturing a wiring board built-in capacitor capable of efficiently forming a plating film on an external electrode layer by electrolytic plating, and a wiring board built-in capacitor suitable for being built in a wiring board. Objective.

  According to one aspect of the present invention, a capacitor body having a plurality of stacked dielectric layers and a plurality of internal electrode layers disposed between different dielectric layers, and an external formed on the capacitor body. A method of manufacturing a wiring board built-in capacitor comprising an electrode layer, comprising a plurality of ceramic green sheets including a plurality of capacitor forming regions, laminated and fired to form the dielectric layer, and each capacitor A step of forming a laminate having a plurality of internal electrode patterns which are disposed in the formation region and between the different ceramic green sheets and are fired to form the internal electrode layer; Across the capacitor forming region, and electrically connected to the internal electrode pattern in each capacitor forming region and firing. And forming the external electrode pattern to be the external electrode layer, and forming the external electrode along the at least part of the boundary of each capacitor forming region on the laminate on which the external electrode pattern is formed. Forming a perforated first break groove penetrating the pattern; firing the laminated body on which the external electrode pattern is formed after forming the first break groove; and the external electrode After firing the laminated body on which the pattern is formed, supplying a current to the external electrode layer and forming a plating film on the external electrode layer by electrolytic plating; and the plating film on the external electrode layer And a step of dividing the laminated body formed with the first break groove along the first break groove.

  According to another aspect of the present invention, the plurality of stacked dielectric layers, the first internal electrode layer disposed between the dielectric layers, and the first internal electrode in the stacking direction of the dielectric layers A capacitor body comprising layers and second internal electrode layers arranged alternately via the dielectric layers, and formed on the capacitor body and electrically connected to the first internal electrode layer A first external electrode layer formed on the capacitor body and substantially flush with the first external electrode layer, spaced apart from the first external electrode layer, and electrically connected to the second internal electrode layer; A wiring board built-in capacitor comprising: a second external electrode layer to be electrically connected; and a plating film formed by electrolytic plating on the first external electrode layer and the second external electrode layer, The amount of warpage of the capacitor for wiring board is less than 100μm And the plating film formed on the first external electrode layer and the plating film formed on the second external electrode layer include the first external electrode layer and the second external electrode. A wiring board built-in capacitor is provided, wherein the capacitor is separated at a portion where the distance between the layers is 30 to 300 μm.

  According to one aspect of the present invention, the perforated first break groove penetrating the external electrode layer is formed in the laminate in which the external electrode layer is formed. Therefore, the electrolytic plating is efficiently performed on the external electrode layer. Thus, it is possible to provide a method for manufacturing a wiring board built-in capacitor capable of forming a plating film.

  According to another aspect of the present invention, the amount of warpage of the wiring board built-in capacitor is less than 100 μm, and the first plating film and the second plating film are formed of the first external electrode layer and the second external electrode. Since the distance between the layers is 30 to 300 μm, the wiring board built-in capacitor suitable for being built in the wiring board can be provided.

(First embodiment)
Hereinafter, a first embodiment of the present invention will be described with reference to the drawings. FIG. 1A and FIG. 1B are schematic plan views of a wiring board built-in capacitor according to this embodiment, and FIG. 2A and FIG. 2B are related to this embodiment. It is a typical side view of the capacitor for wiring board incorporation. FIG. 3A is a schematic longitudinal sectional view of the capacitor with a built-in wiring board taken along line AA in FIG. 1A, and FIG. 3B is a cross-sectional view taken along line B- in FIG. FIG. 4 is a schematic longitudinal cross-sectional view of a wiring board built-in capacitor when cut along line B, and FIG. 4 is a schematic enlarged view of the vicinity of an external electrode layer according to the present embodiment.

  A wiring board built-in capacitor 1 (hereinafter simply referred to as “capacitor”) shown in FIGS. 1A to 3B is a multilayer capacitor having a rectangular parallelepiped shape and a warpage amount of less than 100 μm. The capacitor 1 includes a capacitor body 2 that forms the core of the capacitor 1. The capacitor body 2 includes a plurality of dielectric layers 3 stacked in the vertical direction, a plurality of internal electrode layers 4 (first internal electrode layers) and internal electrode layers 5 (second internal layers) disposed between the dielectric layers 3. Electrode layer).

  The dielectric layer 3 is made of a dielectric ceramic such as barium titanate, lead titanate, or strontium titanate. In addition, it can also be composed of low-temperature fired ceramics such as borosilicate glass or lead borosilicate glass added with an inorganic ceramic filler such as alumina. Depending on the required characteristics, alumina, aluminum nitride, boron nitride It can also be composed of a high-temperature fired ceramic such as silicon, silicon carbide, or silicon nitride.

  The internal electrode layers 4 and 5 are alternately arranged via the dielectric layers 3 in the stacking direction of the dielectric layers 3. The internal electrode layer 4 and the internal electrode layer 5 are electrically insulated by the dielectric layer 3. The total number of internal electrode layers 4 and 5 is about 100 layers.

  The internal electrode layers 4 and 5 are mainly made of a conductive material such as Ni, but contain a ceramic material similar to the ceramic material constituting the dielectric layer 3. By including such a ceramic material in the internal electrode layers 4 and 5, adhesion between the dielectric layer 3 and the internal electrode layers 4 and 5 can be enhanced. The internal electrode layers 4 and 5 may not contain such a ceramic material. The thickness of the internal electrode layers 4 and 5 is, for example, 2 μm or less.

  In the capacitor main body 2, a plurality of via conductors 6 (through the capacitor main body 2 extending from the first main surface 2 a located in the stacking direction of the dielectric layer 3 to the second main surface 2 b opposite to the first main surface 2 a ( A first via conductor) and a via conductor 7 (second via conductor) are formed. The via conductors 6, 7 need only penetrate at least one dielectric layer 3 in the thickness direction of the dielectric layer 3, and do not necessarily penetrate the capacitor body 2.

  A side surface of the via conductor 6 is connected to the internal electrode layer 4, and a side surface of the via conductor 7 is connected to the internal electrode layer 5. Here, as shown in FIG. 3A, the internal electrode layer 5 is formed with clearance holes 5a (holes) in a region through which the via conductor 6 penetrates, and the internal electrode layer 5 and the via conductor 6 are It is electrically insulated. Similarly, as shown in FIG. 3B, clearance holes 4a (holes) are formed in the internal electrode layer 4 in the region through which the via conductors 7 penetrate, and the internal electrode layer 4 and the via conductors 7 Are electrically insulated. The dielectric layer 3 is interposed between the internal electrode layers 4 and 5 and the via conductors 6 and 7 in the clearance holes 4a and 5a.

  The via conductors 6 and 7 are mainly made of a conductive material such as Ni or Cu, but contain a ceramic material similar to the ceramic material forming the dielectric layer 3. By including such a ceramic material in the via conductors 6 and 7, respectively, the adhesion between the dielectric layer 3 and the via conductors 6 and 7 can be enhanced. The via conductors 6 and 7 may not contain such a ceramic material.

  On the first main surface 2a and the second main surface 2b, for example, an external electrode layer 8 (first external electrode layer) and an external electrode layer 9 (second electrode) used as a power supply terminal or a ground connection terminal are used. External electrode layers) are respectively formed. The external electrode layers 8 and 7 do not necessarily have to be formed on both the first main surface 2a and the second main surface 2b of the capacitor body 2, and either the first main surface 2a or the second main surface 2b. It may be formed on either side.

  On the first main surface 2a side, as shown in FIG. 1A, the external electrode layer 8 is formed so as to surround a plurality of island-shaped external electrode layers 9, and on the second main surface 2b side. As shown in FIG. 1B, the external electrode layer 9 is formed so as to surround the plurality of island-shaped external electrode layers 8.

  The external electrode layer 8 is formed on the via conductor 6 and is electrically connected to the via conductor 6. On the other hand, the external electrode layer 9 is formed on the via conductor 7 and is electrically connected to the via conductor 7.

On either the first main surface 2a side or the second main surface 2b side, the external electrode layer 8 and the external electrode layer 9 are separated from each other and are electrically insulated from each other. There is a portion where the distance d ₁ between the external electrode layer 8 and the external electrode layer 9 is 30 to 300 μm.

  On the first main surface 2a side, the total surface area of the external electrode layers 8 and 9 is 45% or more and 90% or less of the area of the first main surface 2a, and on the second main surface 2b side, the external electrode layer The total surface area of 8, 9 is 45% or more and 90% or less of the area of the second main surface 2b. By setting the total surface area of the external electrode layers 8 and 9 in such a range with respect to the areas of the first main surface 2a and the second main surface 2b, the first main surface 1a and the second main surface 1b of the capacitor 1 The exposed area of the dielectric layer 3 can be reduced. Thereby, the adhesiveness of the capacitor | condenser 1 and the insulating layers 44 and 48 mentioned later can be improved.

  The external electrode layers 8 and 9 are mainly composed of a conductive material such as Ni, but the external electrode layers 8 and 9 contain a ceramic material similar to the ceramic material that constitutes the dielectric layer 3. By including such a ceramic material in the external electrode layers 8 and 9, respectively, the adhesion between the dielectric layer 3 and the external electrode layers 8 and 9 can be enhanced. The external electrode layers 8 and 9 may not contain such a ceramic material.

  On the surface of the external electrode layers 8 and 9, as shown in FIG. 4, a plating film 10 is formed for improving adhesion with insulating layers 44 and 48, via conductors 61 and 62, which will be described later. . The plating film 10 also has a function of preventing the external electrode layers 8 and 9 from being oxidized. The plating film 10 is formed by electrolytic plating. The plating film 10 is made of a conductive material such as Au or Cu.

  A plating film 11 is formed between the external electrode layers 8 and 9 and the plating film 10 to suppress a decrease in adhesion between the external electrode layers 8 and 9 and the plating film 10. More specifically, when the external electrode layers 8 and 9 contain a ceramic material as described above, the ceramic material is exposed on the surfaces of the external electrode layers 8 and 9, and the external electrode layers 8 and 9 and the plating film 10 are exposed. There is a possibility that the adhesiveness with the lowering. In order to suppress this, the plating film 11 is formed. The plating film 11 is formed by electrolytic plating.

  The plating film 11 is preferably made of, for example, the same conductive material as the conductive material that is the main component of the external electrode layers 8 and 9. When the external electrode layers 8 and 9 to which the ceramic material is added can be directly plated and the adhesion strength is high, the plating film need not be formed. Here, when the plating film 11 is formed, at least one of the plating films 10 and 11 may be formed by electrolytic plating, and when the plating film 11 is not formed, the plating film 10 may be formed by electrolytic plating.

The external appearance of the capacitor 1 is the first main surface 1a, the second main surface 1b located on the opposite side of the first main surface 1a, and the outer peripheral surface 1c located between the first main surface 1a and the second main surface 1b. etc. are composed of the outer circumferential surface 1c is mainly the first side 1c _1, opposite the side surface 1c ₁ (facing) the second side surface 1c _2, substantially to the side surface 1c ₁ and the side surface 1c ₂ and a third side 1c _3, and positioned on the opposite side of the side surface 1c ₃ (opposite) _4, etc. fourth side 1c adjacent.

The side surfaces 1c _{1 to} 1c ₃ have a semi-cylindrical groove 1d extending in the thickness direction of the capacitor 1 and an outer peripheral direction of the capacitor 1 as shown in FIGS. 2 (a) and 2 (b), respectively. An extended groove 1e is formed. In the present embodiment, the grooves 1d and 1e are formed by dividing the laminate 29 along break grooves 29c and 29d described later. In the present embodiment, grooves 1d on the side surface 1c _4, but 1e is not formed, the groove 1d in the side surface 1c _4, may 1e is formed.

A plurality of grooves 1d are formed along the outer periphery of the capacitor 1 at a predetermined interval. The groove 1d does not have to be semi-cylindrical. Groove 1e is formed from a respective one end edge of the side 1c ₁ ~1c ₃ to the other edge. For example, the groove 1e of the side 1c ₃ are formed from the edge of the side surface 1c ₁ side to the end edge of the side surface 1c ₂ side. That is, it is formed so as to extend from the edge on the side surface 1c ₁ side in the direction of the edge on the side surface 1c ₂ side (outer peripheral direction).

In the side surface 1c ₁ , as shown in FIG. 2A, the groove 1d is formed on the first main surface 1a side (from the first main surface 1a), and the groove 1e is formed on the second main surface 1b side. Has been. More specifically, in the side surface 1 c ₁ , the side surface of the groove 1 d is composed of the dielectric layer 3, the external electrode layer 8, and the plating films 10 and 11, and the side surface of the groove 1 e is the dielectric layer 3. It is composed of Although not illustrated, the side surface 1c ₂ is the same as the side surface 1c ₁ .

In aspects 1c _3, groove 1d as shown in FIG. 2 (b) is formed on the second principal surface 1b side (from the second principal surface 1b), a groove 1e is formed on the first principal surface 1a side Has been. More specifically, in the side surface 1c ₃ , the side surface of the groove 1d is composed of the dielectric layer 3, the external electrode layer 9, and the plating films 10 and 11, and the side surface of the groove 1e is the dielectric layer 3 It is composed of

The corners of the four positions of the outer peripheral surface 1c of the capacitor 1, the chamfer dimension C ₁ is formed flat chamfered portion 1f of the above 0.6mm, as shown in FIG. 1 (a). The chamfer dimension C _1, the length shown in FIG. 1 (a). Chamfer dimension C ₁ may be actually measured, it is possible to determine from the C face length C _2. The C face length C ₂ is the length of the line as shown in FIG. 1 (a), a value obtained by dividing the C face length C ₂ in √2 is chamfer dimension C _1.

Chamfer dimension _{C 1} is preferably from the viewpoint of the capacitor fabrication is 0.8mm or more 1.2mm or less. Instead of the chamfered portion 1 f or together with the chamfered portion 1 f, a rounded portion having a radius of curvature of 0.6 mm or more may be formed at at least one corner of the outer peripheral surface 1 c of the capacitor 1. In this case, the radius of curvature of the rounded portion is desirably 0.8 mm or greater and 1.2 mm or less from the viewpoint of manufacturing a capacitor.

  The capacitor 1 can be manufactured, for example, by the following procedure. 5 (a) and 5 (b) are schematic plan views of the ceramic green sheet on which the internal electrode pattern according to the present embodiment is formed. FIGS. 6 (a), 6 (b), and FIG. 7 (b), FIG. 8 (b), FIG. 10, and FIG. 12 (b) are schematic longitudinal sectional views of the laminate according to the present embodiment. 7A, FIG. 8A, FIG. 9A, FIG. 9B, FIG. 11, FIG. 12A, FIG. 13A, FIG. 13B, and FIG. It is a typical top view of the layered product concerning the form. FIG. 15 is a schematic view showing a state when the laminate according to the present embodiment is divided.

  First, a plurality of ceramic green sheets 22 on which internal electrode patterns 21 are formed and ceramic green sheets 24 on which internal electrode patterns 23 are formed are prepared (FIGS. 5A and 5B). The internal electrode patterns 21 and 23 are before the internal electrode layers 4 and 5 are fired, and the ceramic green sheets 22 and 24 are before the dielectric layer 3 is fired.

  The internal electrode patterns 21 and 23 are respectively formed in the capacitor forming region R. The capacitor formation region R is a region for forming the capacitor 1, and a plurality of the capacitor formation regions R exist in the dielectric layer 3. In the drawing, the boundary of the capacitor forming region R is indicated by a two-dot chain line. Examples of the internal electrode patterns 21 and 23 include a conductor paste layer. Examples of the ceramic green sheets 22 and 24 include ceramic green sheets.

  The internal electrode patterns 21 and 23 are formed in the capacitor formation region R by, for example, screen printing. Further, the internal electrode patterns 21 and 23 have clearance holes 21a and 23a (holes) that become the clearance holes 4a and 5a after firing.

  Moreover, the two cover layers 25 shown by Fig.6 (a) are prepared. The cover layer 25 is produced by laminating a predetermined number of dielectric layers on which the internal electrode patterns 21, 23, etc. are not formed.

  After the ceramic green sheets 22 and 24 and the cover layer 25 are prepared, the ceramic green sheets 22 and the ceramic green sheets 24 are alternately laminated on the cover layer 25, and the cover layer 25 is further laminated thereon. Then, these are pressurized and the laminated body 26 is formed (FIG. 6 (a)).

  After the multilayer body 26 is formed, a via hole penetrating from the main surface 26a to the main surface 26b of the multilayer body 26 is formed, and a conductive paste is pressed into the via hole to form via conductor pastes 27 and 28 (FIG. 6 ( b)).

  Next, the laminated body 26 formed by the same procedure is stacked on the laminated body 26 on which the via conductor pastes 27 and 28 are formed so that the via conductor pastes 27 and the via conductor pastes 28 communicate with each other, and is pressed. Thus, the laminated body 29 is formed (FIGS. 7A and 7B). The communicating via conductor paste 27 and the communicating via conductor paste 28 are those before firing the via conductors 6 and 7.

  Thereafter, external electrodes connected to the via conductor paste 27 in the capacitor formation region R, for example, by screen printing or the like on the first main surface 29a of the multilayer body 29 and the second main surface 29b opposite to the first main surface 29a. A pattern 30 and an external electrode pattern 31 connected to the via conductor paste 28 in the capacitor formation region R are formed (FIGS. 8A and 8B). The external electrode patterns 30 and 31 are those before the external electrode layers 8 and 9 are fired.

  The external electrode pattern 30 on the first main surface 29a side is formed so as to straddle the plurality of capacitor forming regions R, and the external electrode pattern 31 on the second main surface 29b side is formed so as to straddle the plurality of capacitor forming regions R. Is done. In the present embodiment, the external electrode pattern 30 on the first main surface 29a side is formed so as to straddle a plurality of capacitor forming regions R arranged in the longitudinal direction of the first main surface 29a, and on the second main surface 29b side. The external electrode pattern 31 is formed so as to straddle a plurality of capacitor formation regions R aligned in the short direction of the second major surface 29b.

  After the external electrode patterns 30 and 31 are formed on the first main surface 29a and the second main surface 29b, the external electrode patterns 30 and 31 are formed on the laminate 29 along the boundary of the capacitor formation region R by, for example, a laser. A perforated break groove 29c (first break groove) and a continuous line break groove 29d (second break groove) are respectively formed (FIGS. 9A, 9B, and 10). And FIG. 11).

  On the first main surface 29a side, the break groove 29c is formed at the boundary along the short direction of the first main surface 29a in the capacitor forming region R, and the break groove 29d is formed on the second main surface 29b in the capacitor forming region R. It is formed at the boundary along the longitudinal direction.

  On the second main surface 29b side, the break groove 29c is formed at the boundary along the longitudinal direction of the second main surface 29b in the capacitor forming region R, and the break groove 29d is a short portion of the second main surface 29b in the capacitor forming region R. It is formed at the boundary along the hand direction.

  Break groove 29d is formed on each first main surface 29a and second main surface 29b side so as to be orthogonal to break groove 29c. Here, the break groove 29c formed on the second main surface 29b side corresponds to the break groove 29d formed on the first main surface 29a side at a position corresponding to the break groove 29d formed on the first main surface 29a side. Formed along. Further, the break groove 29d formed on the second main surface 29b side is along the break groove 29c formed on the first main surface 29a side at a position corresponding to the break groove 29c formed on the first main surface 29a side. It is formed.

  The depth of the break groove 29 c is desirably 20% or more and 70% or less of the thickness of the stacked body 29. The reason why such a range is desirable is that if it is 20% or more, it can be easily divided along the break groove 29c when dividing the laminate 29, and if it is 70% or less, This is because cracking or chipping in the break groove 29c can be reduced in degreasing, firing, conveyance, and the like after the formation of the break groove 29c.

  When the break groove 29c is cylindrical, the radius r of the break groove 29c is preferably 30 to 75 μm. This range is preferable because if the thickness is less than 30 μm, the plating solution cannot be removed by subsequent cleaning when the plating solution enters the break groove 29c. If the thickness exceeds 75 μm, the internal electrode layer 4 , 5 is reduced, which causes a reduction in capacity.

The distance _{d 2} between the break groove 29c is preferably less than 150-2 × radius r ([mu] m) to exceed 500-2 × radius r ([mu] m). The reason why this range is preferable is that, when it is 150-2 × radius r (μm) or less, the plating thicknesses 10 and 11 will be uneven when the plating films 10 and 11 described later are formed. This is because it is difficult to divide the stacked body 29 when it is divided by the capacitor forming region R when the radius is 2 × radius r (μm) or more.

  After the break grooves 29c and 29d are formed in the multilayer body 29, a rectangular hole 29e that penetrates the multilayer body 29 in the thickness direction is formed along the corner boundary of the capacitor formation region R by, for example, a laser or the like. (FIG. 12A). A chamfered portion 1 f is formed in the capacitor 1 by forming the hole 29 e. In this embodiment, the hole 29e is formed after the break grooves 2c and 2d are formed. However, the break grooves 29c and 29d may be formed after the hole 29e is formed.

  After forming the hole 29e in the laminated body 29, the laminated body 29 on which the external electrode layers 8 and 9 are formed is degreased and further baked at a predetermined temperature for a predetermined time. By this firing, the internal electrode patterns 21 and 23, the ceramic green sheets 22 and 24, the via conductor pastes 27 and 28, and the external electrode patterns 30 and 31 are sintered, and the internal electrode layers 4 and 5, the dielectric layer 3, and the via Conductors 6 and 7 and external electrode layers 8 and 9 are formed (FIG. 12B).

  Thereafter, the oxide film formed on the surfaces of the external electrode layers 8 and 9 by firing is removed by polishing such as jet blasting, and then a current is passed through the external electrode layers 8 and 9 to electrolyze the external electrode layers 8 and 9. Plating films 10 and 11 are formed by plating. Here, a break groove 29c is formed on the first main surface 29a side. However, since the break groove 29c is formed in a perforation, the external electrode layer 8 is formed in the longitudinal direction of the first main surface 29a. They are electrically connected to each other. As a result, a current flows from the external electrode layer 8 in the capacitor formation region R located at one end in the longitudinal direction of the first main surface 29a to the external electrode layer 8 in the capacitor formation region R located at the other end (FIG. 13A). ), The plating films 10 and 11 can be formed on the external electrode layer 8 by electrolytic plating all at once in the longitudinal direction of the first main surface 29a. The same applies to the second main surface 29b side, but on the second main surface 29b side, the other end from the external electrode layer 8 of the capacitor forming region R located at one end of the second main surface 29b in the short direction. A current flows through the external electrode layer 8 in the capacitor formation region R located at (FIG. 13B). In addition, the arrow in the figure of Fig.13 (a) and FIG.13 (b) has shown the direction through which an electric current flows.

  Finally, the multilayer body 29 is divided for each capacitor formation region R along the break grooves 29c and 29d to produce the capacitor 1 and the like shown in FIG. 1 (FIG. 14). Here, in the thickness direction of the laminated body 29, a break groove 29d is formed at a position corresponding to the break groove 29c. In the laminated body 29, the portion near the break groove 29c is more than the portion near the break groove 29d. It is desirable to divide so as to be separated first (FIG. 15). This is because, since the external electrode layer 8 and the plating films 10 and 11 exist between the break grooves 29c, if the portion in the vicinity of the break groove 29d is cut off before the portion in the vicinity of the break groove 29c, the break groove 29c. This is because the nearby external electrode layer 8 and the plating films 10 and 11 may not be cut along the break groove 29c.

  Specifically, first, the portion near the break groove 29c on the first main surface 29a side is divided for each row so that the portion near the break groove 29d on the second main surface 29b side is separated, and then The portion near the break groove 29c on the second main surface 29b side is divided so as to be cut off earlier than the portion near the break groove 29d on the first main surface 29a side. The first main surface 29a is divided for each row so that the portion near the break groove 29c on the second main surface 29b side is separated earlier than the portion near the break groove 29d on the first main surface 29a side. The portion near the break groove 29c on the side may be divided so as to be cut off before the portion near the break groove 29d on the second main surface 29b side.

  The capacitor 1 is used by being built in a wiring board. Hereinafter, a wiring board incorporating the capacitor 1 will be described. FIG. 16 is a schematic longitudinal sectional view of a wiring board in which the wiring board built-in capacitor according to the present embodiment is built.

  A wiring substrate 40 shown in FIG. 16 is an organic substrate formed in a rectangular parallelepiped shape. The wiring board 40 is mainly composed of a polymer material reinforced with ceramic particles or fibers as fillers, for example.

  The wiring board 40 includes, for example, a core board 41 as a wiring board body that forms the core of the wiring board 40. The core substrate 41 includes a core material 41a formed of, for example, a glass-epoxy resin composite material, and a wiring layer 41b made of, for example, Cu having a desired pattern, formed on both surfaces of the core material 41a.

  The core substrate 41 has a plurality of through holes penetrating in the vertical direction of the core substrate 41, and a through hole conductor 41c electrically connected to the wiring layer 41b is formed in the through hole.

  For example, an opening 41 d as a capacitor housing portion for housing the capacitor 1 is formed in the central portion of the core substrate 41. The opening 41d is formed in, for example, a rectangular parallelepiped shape larger than the capacitor 1, and the capacitor 1 is accommodated in the opening 41d. The capacitor housing portion of the core substrate 41 is not limited to the opening 41d, and may be a recess.

  Round corners with a radius of curvature of 0.1 mm or more and 2 mm or less or chamfered portions with a chamfer dimension of 0.1 mm or more and 2 mm or less are formed at the corners of four inner side surfaces of the core substrate 41.

  A gap between the core substrate 41 and the capacitor 1 is filled with a resin filler 42 made of, for example, a polymer material as a filler, and the capacitor 1 is attached to the core substrate 41 via the resin filler 42. It is fixed against.

  Here, the filling of the resin filler 42 into the gap between the core substrate 41 and the capacitor 1 is performed, for example, by sticking an adhesive tape to the back surface of the core substrate 41 and attaching the back surface of the capacitor 1 to the adhesive tape. In this manner, the capacitor 1 is disposed in the opening 41d of the core substrate 41, and the position of the capacitor 1 with respect to the core substrate 41 is fixed with an adhesive tape. The resin filler 42 also has an action of absorbing the thermal expansion difference between the in-plane direction and the thickness direction between the core substrate 41 and the capacitor 1 by its own elastic deformation.

  A buildup wiring layer 43 is formed above the first main surface 1a of the core substrate 41 and the capacitor 1 and below the second main surface 1b of the core substrate 41 and the capacitor 1. The build-up wiring layer 43 includes insulating layers 44 to 50 made of a thermosetting resin such as an epoxy resin. Wiring layers 51 to 56 made of a conductive material such as Cu are formed between the insulating layers 44 and 45, for example.

  The upper surface of the insulating layer 47 and the lower surface of the insulating layer 50 are covered with solder resists 57 and 58 made of, for example, a photosensitive resin composition. Openings are formed in the solder resists 57 and 58, and terminals 59 for electrically connecting to the semiconductor chip (not shown) from the openings and terminals 60 for connecting to, for example, a main substrate (not shown) or the like. Is exposed. The external electrode layers 8 and 9 and the wiring layer 41b are electrically connected to the terminal 59 via the via conductor 61, and the external electrode layers 8 and 9 and the wiring layer are connected to the terminal 60 via the via conductor 62. 41b etc. are electrically connected.

  In the present embodiment, since the perforated break groove 29c penetrating the external electrode layer 8 is formed in the laminate 29 on the first main surface 29a side, the external electrode is formed in the longitudinal direction of the first main surface 29a. Layers 8 are electrically connected to each other. Thereby, since the plating films 10 and 11 can be formed collectively in the longitudinal direction of the first main surface 29a by electrolytic plating, the plating films 10 and 11 can be formed efficiently. Since the break groove 29c is also formed on the second main surface 29b side, the same effect as described above can be obtained.

In the present embodiment, since the plating films 10 and 11 are formed by electrolytic plating, the plating films 10 and 11 can be accurately formed on the external electrode layers 8 and 9. Thus, even when the distance d ₁ between the external electrode layer 8 and the external electrode layer 9 is as narrow as 30 to 300 μm, the external electrode layer 8 and the external electrode layer 9 are separated by the plating films 10 and 11. Since it becomes difficult to connect, an electrical short circuit can be suppressed.

  If a capacitor with a warp amount of 100 μm or more is to be built in the wiring substrate 40, it is difficult to incorporate the capacitor into the wiring substrate 40, and cracks may occur in the dielectric layer constituting the capacitor. On the other hand, in the present embodiment, since the amount of warping of the capacitor 1 is less than 100 μm, the dielectric layer 3 can be easily built into the wiring board 40 and the capacitor 1 is built into the wiring board 40. Cracks are unlikely to occur.

In this embodiment, the plating films 10 and 11 are also able to accurately deposit the distance d ₁ between the external electrode layer 8 and the external electrode layer 9 has relatively narrow and 30 to 300 [mu] m, also, Plating can be performed in the state of the product aggregate, and the entire aggregate can be uniformly plated.

In the present embodiment, since the grooves 1d are formed in the side surfaces 1c _{1 to} 1c ₃ of the capacitor 1, the resin filler 42 enters the grooves 1d when the capacitor 1 is built in the wiring board 40. Thereby, the adhesiveness of the capacitor | condenser 1 and the resin filler 42 can be improved.

In this embodiment, since the chamfered portion 1f chamfer dimension C ₁ at a corner is more than 0.6mm of the outer peripheral surface 1c of the capacitor 1 are formed, the thermal stress on the corners of the capacitor 1 side of the resin filler 42 Are less likely to concentrate, and the occurrence of cracks at the corner of the resin filler 42 on the capacitor 1 side can be suppressed. Even when a rounded portion having a radius of curvature of 0.6 mm or more is formed at the corner of the outer peripheral surface 1c of the capacitor 1, the same effect as the chamfered portion 1f can be obtained.

  In this embodiment, since the chamfered portion 1f and the rounded portion are formed at the corner of the outer peripheral surface 1c of the capacitor 1, the corner of the capacitor 1 is compared with the case where the chamfered portion 1f and the rounded portion are not formed. The distance from the nearby signal line to the dielectric layer 3 is increased. Thereby, the signal delay of the signal line existing near the corner of the capacitor 1 can be reduced.

(Second Embodiment)
Hereinafter, a second embodiment of the present invention will be described with reference to the drawings. In this embodiment, an example in which capacitors are arranged between insulating layers on a core substrate will be described. In the present embodiment, the same members as those described in the first embodiment are denoted by the same reference numerals, and the same contents as those described in the first embodiment are the same. May be omitted. FIG. 17 is a schematic longitudinal sectional view of a wiring board in which the wiring board built-in capacitor according to the present embodiment is built.

  As shown in FIG. 17, the opening 41 d is not formed in the core substrate 41, and the capacitor 1 is disposed between the insulating layers 44 and 45 on the core substrate 41. In the capacitor 1 of the present embodiment, the total number of internal electrode layers 4 and 5 is about 10 layers, which is thinner than the thickness of the capacitor 1 described in the first embodiment.

  The capacitor 1 can be disposed between the insulating layers 44 and 45 by the following procedure, for example. First, the capacitor body 2 in which the plated films 10 and 11 are formed on the external electrode layers 8 and 9 is disposed on the insulating layer 44 formed on the core substrate 41. Thereafter, the insulating layer 45 is placed on the capacitor body 2 and pressed while heating. As a result, the insulating layer 45 on the capacitor main body 2 flows to the side of the capacitor body 2, and the capacitor body 2 is disposed between the insulating layers 44 and 45. Thereafter, via holes penetrating the insulating layers 44 and 45 and the capacitor body 2 are formed, and via conductors 6 and 7 connected to the wiring layer 41b are formed in the via holes, thereby completing the capacitor 1.

  In the present embodiment, since the capacitor 1 is disposed between the insulating layers 44 and 45 formed on the core substrate 41, the distance between the capacitor 1 and the semiconductor chip can be further shortened. Thereby, wiring resistance and an inductance can be reduced more.

  The present invention is not limited to the description of the above embodiment, and the structure, material, arrangement of each member, and the like can be appropriately changed without departing from the gist of the present invention.

(A) And (b) is a typical top view of the capacitor | condenser for wiring board built-in which concerns on 1st Embodiment. (A) And (b) is a typical side view of the capacitor | condenser for wiring board built-in which concerns on 1st Embodiment. (A) is a typical longitudinal cross-sectional view of the capacitor | condenser for a wiring board when cut | disconnected by the AA line in Fig.1 (a), (b) is cut | disconnected by the BB line in Fig.1 (a). It is a typical longitudinal cross-sectional view of the capacitor | condenser for wiring board built in. It is a typical enlarged view near the external electrode layer according to the first embodiment. (A) And (b) is a typical top view of the ceramic green sheet in which the internal electrode pattern which concerns on 1st Embodiment was formed. (A) And (b) is a typical longitudinal cross-sectional view of the laminated body which concerns on 1st Embodiment. (A) is a schematic plan view of the laminated body which concerns on 1st Embodiment, (b) is a typical longitudinal cross-sectional view of the laminated body which concerns on 1st Embodiment. (A) is a schematic plan view of the laminated body which concerns on 1st Embodiment, (b) is a typical longitudinal cross-sectional view of the laminated body which concerns on 1st Embodiment. (A) And (b) is a typical top view of the laminated body which concerns on 1st Embodiment. It is a typical longitudinal section of the layered product concerning a 1st embodiment. It is a typical top view of the layered product concerning a 1st embodiment. (A) is a schematic plan view of the laminated body which concerns on 1st Embodiment, (b) is a typical longitudinal cross-sectional view of the laminated body which concerns on 1st Embodiment. (A) And (b) is a typical top view of the laminated body which concerns on 1st Embodiment. It is a typical top view of the layered product concerning a 1st embodiment. It is the schematic diagram which showed the mode at the time of dividing | segmenting the laminated body which concerns on 1st Embodiment. 1 is a schematic longitudinal sectional view of a wiring board in which a wiring board built-in capacitor according to a first embodiment is built. It is a typical longitudinal cross-sectional view of the wiring board with which the wiring board built-in capacitor | condenser concerning 2nd Embodiment was incorporated.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Capacitor, 2 ... Capacitor body, 3 ... Dielectric layer, 4, 5 ... Internal electrode layer, 8, 9 ... External electrode layer, 10, 11 ... Plating film, 21, 23 ... Internal electrode pattern, 22, 24 ... Ceramic green sheet, 26, 29 ... laminate, 29a ... first main surface, 29b ... second main surface, 29c, 29d ... break groove, 30, 31 ... external electrode pattern, 40 ... wiring substrate, 41 ... core substrate, 43 ... Build-up layer.

Claims (7)

A capacitor with a built-in wiring board, comprising: a capacitor body having a plurality of laminated dielectric layers; and a plurality of internal electrode layers disposed between different dielectric layers; and an external electrode layer formed on the capacitor body A manufacturing method of
A plurality of ceramic green sheets including a plurality of capacitor forming regions, stacked and fired to form the dielectric layer, and disposed between the ceramic green sheets different from each other in the capacitor forming regions and fired. A step of forming a laminate having a plurality of internal electrode patterns to be the internal electrode layers,
On the laminated body, an external electrode pattern that forms the external electrode layer is formed by straddling a plurality of the capacitor formation regions, being electrically connected to the internal electrode pattern in each capacitor formation region, and being baked. And a process of
Forming a perforated first break groove penetrating through the external electrode pattern along at least a part of a boundary of each capacitor forming region in the laminate in which the external electrode pattern is formed;
Firing the laminated body on which the external electrode pattern is formed after forming the first break groove;
After firing the laminate in which the external electrode pattern is formed, supplying a current to the external electrode layer, and forming a plating film on the external electrode layer by electrolytic plating;
Dividing the laminated body in which the plating film is formed on the external electrode layer along the first break groove. A method for manufacturing a capacitor with a built-in wiring board, comprising: The laminate further includes a first main surface located in the thickness direction of the laminate, and a second main surface opposite to the first main surface,
2. The method for manufacturing a capacitor with a built-in wiring board according to claim 1, wherein the external electrode layer is formed on each of the first main surface and the second main surface of the multilayer body. The first break grooves are respectively formed on the first main surface side and the second main surface side of the laminate,
After forming the external electrode pattern and before firing the laminated body on which the external electrode pattern is formed, the boundary between the first main surface side and the second main surface side of the laminated body Along the portion, forming a continuous second break groove substantially orthogonal to the first break groove;
The method further comprises: after forming the plating film, dividing the laminated body in which the plating film is formed on the external electrode layer along the second break groove. The manufacturing method of the capacitor | condenser for wiring board description of description. The first break groove formed on the second main surface side is formed at a position corresponding to the second break groove formed on the first main surface side and on the first main surface side. Formed along the second break groove,
The second break groove formed on the second main surface side is formed at a position corresponding to the first break groove formed on the first main surface side and on the first main surface side. Formed along the first break groove,
The laminated body is divided so that a portion in the vicinity of the first break groove in the thickness direction of the laminated body is cut before a portion in the vicinity of the second break groove. 3. A method for producing a capacitor for wiring board according to 3. The internal electrode pattern includes: a first internal electrode pattern; and second internal electrode patterns alternately arranged via the first internal electrode pattern and the ceramic green sheet in the stacking direction of the ceramic green sheets. Configured,
The external electrode pattern is spaced apart from the first external electrode pattern electrically connected to the first internal electrode pattern, the first external electrode pattern, and the second internal electrode pattern. 5. The method for manufacturing a wiring board built-in capacitor according to claim 1, wherein the second external electrode pattern is electrically connected.   6. The wiring board built-in capacitor according to claim 1, wherein a depth of the first break groove is not less than 20% and not more than 70% of a thickness of the multilayer body. Production method. A plurality of laminated dielectric layers, first internal electrode layers disposed between the dielectric layers, and alternately in the stacking direction of the dielectric layers via the first internal electrode layers and the dielectric layers A capacitor body comprising a second internal electrode layer disposed on
A first external electrode layer formed on the capacitor body and electrically connected to the first internal electrode layer;
A second electrode formed on the capacitor body and substantially flush with the first external electrode layer, spaced apart from the first external electrode layer and electrically connected to the second internal electrode layer; An external electrode layer, a plating film formed by electrolytic plating on the first external electrode layer and the second external electrode layer;
A wiring board built-in capacitor comprising:
The amount of warping of the wiring board built-in capacitor is less than 100 μm, and the plating film formed on the first external electrode layer and the plating film formed on the second external electrode layer include: 1. A wiring board built-in capacitor, wherein a distance between one external electrode layer and the second external electrode layer is separated in a portion of 30 to 300 μm.

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