JP4965237B2 - Wiring board built-in capacitor and wiring board - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a capacitor incorporated in a wiring board, of which adhesion to a resin material is improved, and to provide a wiring board whose reliability is sufficiently assured. <P>SOLUTION: The capacitor 1 which is incorporated in the wiring board comprises a capacitor body 2 consisting of a plurality of dielectric layers 3 stacked together, and internal electrode layers 4 and 5 arranged between different dielectric layers 3. A recess 2d extending in thickness direction of the capacitor body 2 is formed on side surfaces 2c1-2c3 of the capacitor body 2. <P>COPYRIGHT: (C)2007,JPO&amp;INPIT

Description

  The present invention relates to a wiring board built-in capacitor and a wiring board.

  In recent years, the operation of semiconductor chips has been increasingly accelerated due to advances in integrated circuit technology. As a result, noise may be superimposed on the power supply wiring and the like, causing malfunction. Therefore, a capacitor is mounted on the upper surface or the lower surface of the wiring substrate on which the semiconductor chip is mounted to remove noise.

  However, in the above method, it is necessary to separately mount a capacitor after the wiring board is completed, so that the number of processes increases. In addition, it is necessary to secure a region for mounting the capacitor on the wiring board in advance, which reduces the degree of freedom of other electronic components. Furthermore, by being limited to other wirings, the wiring distance between the capacitor and the semiconductor chip becomes long, and the wiring resistance and inductance increase.

For this reason, it has been proposed to incorporate a capacitor in the wiring board (see, for example, Patent Document 1). Here, the capacitor may be built in the opening of the core substrate that forms the core of the wiring board. In this case, in order to fix the capacitor to the core substrate, the gap between the core substrate and the capacitor is filled with resin. Filled with material. However, since the side surface of the capacitor is mainly composed of ceramic, the adhesion between the capacitor and the resin filler is low, and sufficient reliability cannot be ensured.
JP-A-2005-39243

  The present invention has been made to solve the above problems. That is, it is an object of the present invention to provide a wiring board built-in capacitor capable of improving adhesion to the wiring board and a wiring board with sufficiently ensured reliability.

According to one aspect of the present invention, a wiring board built-in capacitor comprising a capacitor body having a plurality of laminated dielectric layers and internal electrode layers disposed between different dielectric layers, wherein the capacitor A concave portion is formed on at least the first side surface of the main body and the third side surface adjacent to the first side surface, and the concave portion formed on the first side surface is formed on the first main surface side of the capacitor main body. The concave portion formed on the third side surface is formed so as to extend in the thickness direction of the capacitor main body, and the second concave portion is located on the side of the capacitor main body opposite to the first main surface. A wiring board built-in capacitor is provided which is formed so as to extend in the thickness direction of the capacitor body on the main surface side .

  According to another aspect of the present invention, there is provided a wiring board including the wiring board built-in capacitor.

  According to the wiring board built-in capacitor of one aspect of the present invention, the concave portion extending in the thickness direction of the capacitor body from at least one main surface is formed on at least one side surface of the capacitor body. When the wiring board built-in capacitor is built in the actual wiring board, the contact area with the resin material to be bonded and fixed to the core board is increased by filling the resin material in the recess. be able to. Thereby, adhesiveness with the said core board | substrate can be improved. Therefore, the reliability of the wiring board in another aspect of the present invention can be sufficiently ensured.

(First embodiment)
Hereinafter, a first embodiment of the present invention will be described with reference to the drawings. FIG. 1A and FIG. 1B are schematic plan views of a wiring board built-in capacitor according to this embodiment, and FIG. 2A and FIG. 2B are related to this embodiment. It is a typical side view of the capacitor for wiring board incorporation. FIG. 3A is a schematic longitudinal sectional view of the capacitor with a built-in wiring board taken along line AA in FIG. 1A, and FIG. 3B is a cross-sectional view taken along line B- in FIG. FIG. 4 is a schematic longitudinal cross-sectional view of a wiring board built-in capacitor when cut along line B, and FIG. 4 is a schematic enlarged view of the vicinity of the outer periphery of the capacitor body according to the present embodiment.

  A wiring board built-in capacitor 1 (hereinafter simply referred to as “capacitor”) shown in FIGS. 1A to 3B is a multilayer capacitor having a rectangular parallelepiped shape and a warpage amount of less than 100 μm. The capacitor 1 includes a capacitor body 2 that forms the core of the capacitor 1. The capacitor body 2 includes a plurality of dielectric layers 3 stacked in the vertical direction, a plurality of internal electrode layers 4 (first internal electrode layers) and internal electrode layers 5 (second electrodes) disposed between the dielectric layers 3. Internal electrode layer).

  The dielectric layer 3 is made of a dielectric ceramic such as barium titanate, lead titanate, or strontium titanate. In addition, it can also be composed of low-temperature fired ceramics such as borosilicate glass or lead borosilicate glass added with an inorganic ceramic filler such as alumina. Depending on the required characteristics, alumina, aluminum nitride, boron nitride It can also be composed of a high-temperature fired ceramic such as silicon, silicon carbide, or silicon nitride.

  The internal electrode layers 4 and 5 are alternately arranged via the dielectric layers 3 in the stacking direction of the dielectric layers 3. The internal electrode layer 4 and the internal electrode layer 5 are electrically insulated by the dielectric layer 3. The total number of internal electrode layers 4 and 5 is about 100 layers.

  The internal electrode layers 4 and 5 are mainly made of a conductive material such as Ni, but contain a ceramic material similar to the ceramic material constituting the dielectric layer 3. By including such a ceramic material in the internal electrode layers 4 and 5, adhesion between the dielectric layer 3 and the internal electrode layers 4 and 5 can be enhanced. The internal electrode layers 4 and 5 may not contain such a ceramic material. The thickness of the internal electrode layers 4 and 5 is, for example, 2 μm or less.

  The external appearance of the capacitor body 2 includes a first main surface 2a located in the thickness direction of the capacitor body 2, a second main surface 2b located on the opposite side of the first main surface 2a, and the first main surface 2a. And an outer peripheral surface 2c positioned between the first main surface 2b and the second main surface 2b. The outer peripheral surface 2c is mainly composed of a first side surface 2c1, a second side surface 2c2 located opposite (opposite) to the side surface 2c1, a side surface 2c1, a third side surface 2c3 adjacent to the side surface 2c2, and a side surface 2c3. The second side 2c4 is located on the opposite side (opposite) and adjacent to the side 2c1 and the side 2c2. The side surfaces 2c1 to 2c4 are composed only of the dielectric layer 3. Note that the side surfaces of the recesses 2d and the notches 2e, which will be described later, on the side surfaces 2c1 to 2c3 are also composed of only the dielectric layer 3.

  The side surfaces 2c1 to 2c3 are respectively provided with a semicircular recess 2d extending in the thickness direction of the capacitor body 2 and an outer peripheral direction of the capacitor body 2 as shown in FIGS. 2 (a) and 2 (b). An extended notch 2e is formed. The side surfaces 2c1 to 2c3 may be provided with convex portions extending in the thickness direction of the capacitor body 2 in place of the concave portion 2d or together with the concave portion 2d. The side surface 2c4 may also be formed with a recess 2d and a notch 2e.

  A plurality of the recesses 2d are formed at predetermined intervals along the outer periphery of the capacitor body 2. The recesses 2d in the side surfaces 2c1 and 2c2 are preferably formed from the first main surface 2a to a position of 20% to 70% of the thickness of the capacitor body 2, and the recesses 2d in the side surface 2c3 It is desirable to form from the main surface 2b to a position of 20% to 70% of the thickness of the capacitor body 2. The reason why such a range is desirable is that if it is 20% or more, the adhesion to the resin filler 42 described later can be sufficiently improved, and if it is 70% or less, the capacitor 1 This is because cracks or chips in the recess 2d can be reduced during conveyance or the like.

  The radius r of the recess 2d shown in FIG. 4 is preferably 30 to 75 μm. This range is preferable because if it is less than 30 μm, the resin filler 42 described later does not enter well, and if the adhesiveness is insufficient or a void is formed, the product has low reliability due to the influence of that part. This is because if the thickness exceeds 75 μm, the area of the internal electrode becomes small, which causes a decrease in capacity. The recess 2d does not have to be semicircular. The notch 2e is formed from one edge of each of the side surfaces 2c1 to 2c3 to the other edge. For example, the notch 2e on the side surface 2c3 is formed from the end edge on the side surface 2c1 side to the end edge on the side surface 2c2 side. That is, it is formed extending from the edge on the side surface 2c1 side in the direction of the edge on the side surface 2c2 side (outer peripheral direction).

  Further, the distance d1 between the recesses 2d shown in FIG. 4 is preferably more than 150-2 × radius r (μm) and less than 500-2 × radius r (μm). The reason why this range is preferable is that if it is 150-2 × radius r (μm) or less, the dimensional accuracy of the outer shape of the product will be impaired, and if it is 500-2 × radius r (μm) or more. This is because it becomes difficult to perform break cutting with high accuracy.

  In the side surface 2c1, the recess 2d is formed on the first main surface 2a side (extending in the thickness direction from the first main surface 2a) as shown in FIG. 2e is formed on the second main surface 2b side. Although not shown, the side surface 2c2 is the same as the side surface 2c1. In the side surface 2c3, as shown in FIG. 2B, the recess 2d is formed on the second main surface 2b side (extending in the thickness direction from the second main surface 2b), and is notched. 2e is formed on the first main surface 2a side.

  As shown in FIG. 1A, planar chamfered portions 2f having a chamfered dimension C1 of 0.6 mm or more are formed at four corners of the outer peripheral surface 2c of the capacitor body 2. The chamfer dimension C1 is the length shown in FIG. The chamfer dimension C1 may be actually measured, but can also be obtained from the C surface length C2. The C-plane length C2 is the length of the line segment as shown in FIG. 1A, and the value obtained by dividing the C-plane length C2 by √2 is the chamfer dimension C1.

  The chamfer dimension C1 is desirably 0.8 mm or more and 1.2 mm or less from the viewpoint of manufacturing a capacitor. Instead of the chamfered portion 2 f or together with the chamfered portion 2 f, a rounded portion having a radius of curvature of 0.6 mm or more may be formed at at least one corner of the outer peripheral surface 2 c of the capacitor body 2. In this case, the radius of curvature of the rounded portion is desirably 0.8 mm or greater and 1.2 mm or less from the viewpoint of manufacturing a capacitor.

  In the capacitor body 2, a plurality of via conductors 6 (first via conductors) and via conductors 7 (second via conductors) penetrating the capacitor body 2 from the first main surface 2 a to the second main surface 2 b. Is formed. The via conductors 6, 7 need only penetrate at least one dielectric layer 3 in the thickness direction of the dielectric layer 3, and do not necessarily penetrate the capacitor body 2.

  A side surface of the via conductor 6 is connected to the internal electrode layer 4, and a side surface of the via conductor 7 is connected to the internal electrode layer 5. Here, as shown in FIG. 3A, the internal electrode layer 5 is formed with clearance holes 5a (holes) in a region through which the via conductor 6 penetrates, and the internal electrode layer 5 and the via conductor 6 are It is electrically insulated. Similarly, as shown in FIG. 3B, clearance holes 4a (holes) are formed in the internal electrode layer 4 in the region through which the via conductors 7 penetrate, and the internal electrode layer 4 and the via conductors 7 Are electrically insulated. The dielectric layer 3 is interposed between the internal electrode layers 4 and 5 and the via conductors 6 and 7 in the clearance holes 4a and 5a.

  The via conductors 6 and 7 are mainly made of a conductive material such as Ni or Cu, but contain a ceramic material similar to the ceramic material forming the dielectric layer 3. By including such a ceramic material in the via conductors 6 and 7, respectively, the adhesion between the dielectric layer 3 and the via conductors 6 and 7 can be enhanced. The via conductors 6 and 7 may not contain such a ceramic material.

  On the first main surface 2a and the second main surface 2b, for example, an external electrode layer 8 (first external electrode layer) and an external electrode layer 9 (first electrode) used as a power supply terminal or a ground connection terminal are used. 2 external electrode layers) are respectively formed. The external electrode layers 8 and 9 are not necessarily formed on both the first main surface 2a and the second main surface 2b of the capacitor body 2, and the first main surface 2a and the second main surface 2b are not necessarily formed. It may be formed on any one of the surfaces 2b.

  On the first main surface 2a side, as shown in FIG. 1A, the external electrode layer 8 is formed so as to surround a plurality of island-shaped external electrode layers 9, and the second main surface 2b side. In FIG. 1, the external electrode layer 9 is formed so as to surround a plurality of island-shaped external electrode layers 8 as shown in FIG.

  The external electrode layer 8 is formed on the via conductor 6 and is electrically connected to the via conductor 6. On the other hand, the external electrode layer 9 is formed on the via conductor 7 and is electrically connected to the via conductor 7.

  On either the first main surface 2a side or the second main surface 2b side, the external electrode layer 8 and the external electrode layer 9 are separated from each other and are electrically insulated from each other. The distance d2 between the external electrode layer 8 and the external electrode layer 9 is preferably as narrow as possible if insulation is ensured, and there is a portion where the distance is 150 μm.

  On the first main surface 2a side, the total surface area of the external electrode layers 8 and 9 is not less than 45% and not more than 90% of the area of the first main surface 2a, and on the second main surface 2b side, The total surface area of the external electrode layers 8 and 9 is 45% or more and 90% or less of the area of the second main surface 2b. By setting the total surface area of the external electrode layers 8 and 9 in such a range with respect to the areas of the first main surface 2a and the second main surface 2b, the first main surface 2a and the second main surface 2b are set. The exposed area of the dielectric layer 3 can be reduced. Thereby, the adhesiveness of the capacitor | condenser 1 and the insulating layers 44 and 48 mentioned later can be improved.

  On the first main surface 2a side, the external electrode layer 8 is formed from the end on the side surface 2c1 side to the end on the side surface 2c2 side. The external electrode layer 8 is formed with a recess 8a communicating with the recess 2d of the side surfaces 2c1 and 2c2. The recess 8a has the same radius as the radius r of the recess 2d and is concentric with the recess 2d. Further, on the second main surface 2b side, the external electrode layer 9 is formed from the end on the side surface 2c3 side to the end on the side surface 2c4 side. The external electrode layer 9 has a recess 9a communicating with the recess 2d of the side surface 2c3. The recess 9a has the same radius as the radius r of the recess 2d and is concentric with the recess 2d.

  On the other hand, on the first main surface 2a side, the external electrode layer 8 may be formed from the end on the side surface 2c3 side to the end on the side surface 2c4 side. In this case, the first main surface 2a becomes flat, and it is possible to improve adhesion with insulating layers 44 and 48, which will be described later, and to form stable via conductors 61 and 62. Similarly, on the second main surface 2b side, the external electrode layer 9 may be formed from the end on the side surface 2c1 side to the end on the side surface 2c2 side.

  The external electrode layers 8 and 9 are mainly composed of a conductive material such as Ni, but the external electrode layers 8 and 9 contain a ceramic material similar to the ceramic material that constitutes the dielectric layer 3. By including such a ceramic material in the external electrode layers 8 and 9, respectively, the adhesion between the dielectric layer 3 and the external electrode layers 8 and 9 can be enhanced. The external electrode layers 8 and 9 may not contain such a ceramic material.

  On the surface of the external electrode layers 8 and 9, a first plating film (not shown) is formed for improving adhesion to insulating layers 44 and 48, via conductors 61 and 62, which will be described later. . The first plating film also has a function of preventing oxidation of the external electrode layers 8 and 9. The first plating film is formed by electrolytic plating. Note that the first plating film may be formed by electroless plating. The first plating film is preferably made of, for example, a conductive material such as Au or Cu. More preferably, the outermost surface is made of Cu in order to improve the adhesion with the insulating layer 44 described later. It is preferable that

  Between the external electrode layers 8 and 9 and the 1st plating film, the 2nd plating film (not shown) for suppressing the fall of the adhesiveness of the external electrode layers 8 and 9 and the 1st plating film ) Is formed. More specifically, when the external electrode layers 8 and 9 contain a ceramic material as described above, the ceramic material is exposed on the surfaces of the external electrode layers 8 and 9, and the external electrode layers 8 and 9 and the first There is a possibility that the adhesion with the plating film may be lowered. In order to suppress this, a second plating film is formed. The second plating film is formed by electrolytic plating. The second plating film may be formed by electroless plating as long as it is formed by a plating method.

  The second plating film is preferably made of, for example, the same conductive material as the conductive material that is the main component of the external electrode layers 8 and 9. If the external electrode layers 8 and 9 to which the ceramic material is added can be directly plated and the adhesion strength is high, the second plating film need not be formed.

  The capacitor 1 can be manufactured, for example, by the following procedure. 5 (a) and 5 (b) are schematic plan views of the ceramic green sheet on which the internal electrode pattern according to the present embodiment is formed. FIGS. 6 (a), 6 (b), and FIG. 7 (b), FIG. 8 (b), FIG. 9 (b), and FIG. 10 (b) are schematic longitudinal sectional views of the laminate according to the present embodiment. FIG. 7A, FIG. 8A, FIG. 9A, FIG. 10A, and FIG. 11 are schematic plan views of the laminate according to the present embodiment.

  First, a plurality of ceramic green sheets 22 on which internal electrode patterns 21 are formed and ceramic green sheets 24 on which internal electrode patterns 23 are formed are prepared (FIGS. 5A and 5B). The internal electrode patterns 21 and 23 are before the internal electrode layers 4 and 5 are fired, and the ceramic green sheets 22 and 24 are before the dielectric layer 3 is fired.

  The internal electrode patterns 21 and 23 are respectively formed in the capacitor forming region R. The capacitor forming region R is a region for forming the capacitor 1, and a plurality of the capacitor green regions 22 and 24 exist. In the drawing, the boundary of the capacitor forming region R is indicated by a two-dot chain line. The internal electrode patterns 21 and 23 are made of, for example, a conductor paste.

  The internal electrode patterns 21 and 23 are formed in the capacitor formation region R by, for example, screen printing. Further, the internal electrode patterns 21 and 23 have clearance holes 21a and 23a (holes) that become the clearance holes 4a and 5a after firing.

  Moreover, the two cover layers 25 shown by Fig.6 (a) are prepared. The cover layer 25 is produced by laminating a predetermined number of dielectric layers on which the internal electrode patterns 21, 23, etc. are not formed.

  After the ceramic green sheets 22 and 24 and the cover layer 25 are prepared, the ceramic green sheets 22 and the ceramic green sheets 24 are alternately laminated on the cover layer 25, and the cover layer 25 is further laminated thereon. Then, these are pressurized and the laminated body 26 is formed (FIG. 6 (a)).

  After the multilayer body 26 is formed, a via hole penetrating from the main surface 26a to the main surface 26b of the multilayer body 26 is formed, and a conductive paste is pressed into the via hole to form via conductor pastes 27 and 28 (FIG. 6 ( b)). The via conductor pastes 27 and 28 are before the via conductors 6 and 7 are fired.

  Next, the laminated body 26 formed by the same procedure is stacked on the laminated body 26 on which the via conductor pastes 27 and 28 are formed so that the via conductor pastes 27 and the via conductor pastes 28 communicate with each other, and is pressed. Thus, the laminated body 29 is formed (FIGS. 7A and 7B).

  After that, the external electrode pattern 30 connected to the via conductor paste 27 in the capacitor formation region R and the capacitor formation are formed on the main surface 29a of the multilayer body 29 and the main surface 29b opposite to the main surface 29a by, for example, screen printing. In the region R, external electrode patterns 31 connected to the via conductor paste 28 are formed (FIGS. 8A and 8B). The external electrode patterns 30 and 31 are those before the external electrode layers 8 and 9 are fired.

  The external electrode pattern 30 on the main surface 29a side is formed so as to straddle the plurality of capacitor forming regions R, and the external electrode pattern 31 on the main surface 29b side is formed so as to straddle the plurality of capacitor forming regions R. In the present embodiment, the external electrode pattern 30 on the main surface 29a side is formed so as to straddle a plurality of capacitor forming regions R aligned in the longitudinal direction of the main surface 29a, and the external electrode pattern 31 on the main surface 29b side is It is formed so as to straddle a plurality of capacitor forming regions R aligned in the short direction of the main surface 29b.

  After the external electrode patterns 30 and 31 are formed on the main surfaces 29a and 29b, perforations that penetrate the external electrode patterns 30 and 31 along the boundary of the capacitor formation region R are formed on the stacked body 29 by, for example, a laser. A break groove 29c (first break groove) and a continuous linear break groove 29d (second break groove) are formed (FIGS. 9A and 9B), respectively.

  On the main surface 29a side, the break groove 29c is formed at a boundary along the short direction of the main surface 29a in the capacitor forming region R, and the break groove 29d is a boundary along the longitudinal direction of the main surface 29a in the capacitor forming region R. Formed.

  On the main surface 29b side, the break groove 29c is formed at a boundary along the longitudinal direction of the main surface 29b in the capacitor formation region R, and the break groove 29d is a boundary along the short direction of the main surface 29b in the capacitor formation region R. Formed.

As shown in FIG. 9B, the depth a of the perforated break groove 29C with respect to the product thickness can be 20 to 70% of the thickness of the entire product. In this case, the depth b of the continuous linear break groove 29d can be a / b = 0.25 to 35. Specifically, the ratio can be set as shown in Table 1. In the present embodiment, the depth a is 63% of the thickness of the entire product, and the depth b of the continuous linear break groove 29d is 25% of the thickness of the entire product.

  Break groove 29d is formed on each main surface 29a, 29b side so as to be orthogonal to break groove 29c. Here, the break groove 29c formed on the main surface 29b side is formed at a position corresponding to the break groove 29d formed on the main surface 29a side and along the break groove 29d formed on the main surface 29a side. The break groove 29d formed on the main surface 29b side is formed along the break groove 29c formed on the main surface 29b side at a position corresponding to the break groove 29c formed on the main surface 29b side.

  After the break grooves 29c and 29d are formed in the multilayer body 29, the holes 29e that penetrate the multilayer body 29 in the thickness direction and extend in the thickness direction at the corners of the capacitor formation region R, for example, by a laser or the like. A groove 29f is formed (FIG. 10A). Thereby, a portion that becomes the chamfered portion 2 f is formed in the stacked body 29.

  After the hole 29e and the groove 29f are formed in the laminate 29, the laminate 29 in which the external electrode layers 8 and 9 are formed is degreased and further baked at a predetermined temperature for a predetermined time. By this firing, the internal electrode patterns 21 and 23, the ceramic green sheets 22 and 24, the via conductor pastes 27 and 28, and the external electrode patterns 30 and 31 are sintered, and the internal electrode layers 4 and 5, the dielectric layer 3, and the via Conductors 6 and 7 and external electrode layers 8 and 9 are formed (FIG. 10B).

  Thereafter, the oxide film formed on the surface of the external electrode layers 8 and 9 by firing is removed by, for example, polishing such as jet blasting, and then an electric current is passed through the external electrode layers 8 and 9 to electrolyze the external electrode layers 8 and 9. First and second plating films are formed by plating. Here, a break groove 29c is formed on the main surface 29a side. However, since the break groove 29c is formed in a perforation, the external electrode layers 8 are electrically connected to each other in the longitudinal direction of the main surface 29a. It is connected. As a result, a current flows from the external electrode layer 8 in the capacitor formation region R located at one end in the longitudinal direction of the main surface 29a to the external electrode layer 8 in the capacitor formation region R located at the other end, and in the longitudinal direction of the main surface 29a. A first plating film or the like can be formed on the external electrode layer 8 by electrolytic plating all at once. Therefore, the first plating film or the like can be efficiently formed on the external electrode layer 8. The same applies to the main surface 29b side, but on the main surface 29b side, the capacitor forming region located at the other end from the external electrode layer 8 of the capacitor forming region R located at one end of the main surface 29b in the short direction. A current flows through the R external electrode layer 8.

  Finally, the multilayer body 29 is divided for each capacitor formation region R along the break grooves 29c and 29d to produce the capacitor 1 and the like shown in FIG. 1 (FIG. 11). Here, in the thickness direction of the laminated body 29, a break groove 29d is formed at a position corresponding to the break groove 29c. In the laminated body 29, the portion near the break groove 29c is more than the portion near the break groove 29d. It is desirable to divide so as to be separated first. This is because the external electrode layer 8 and the like are present between the break grooves 29c, so that when the portion near the break groove 29d is cut off before the portion near the break groove 29c, the external electrode layer near the break groove 29c. This is because 8 or the like may not be cut along the break groove 29c.

  12 and 13 are diagrams showing a modification of the method for manufacturing the capacitor 1 described above. Note that FIGS. 12 and 13 show only process steps of the manufacturing method according to this modification different from the manufacturing method described above. In addition, Fig.12 (a) is a typical top view of the laminated body which concerns on this modification, and FIG.12 (b) is a typical longitudinal cross-sectional view of the said laminated body.

  As shown in FIG. 12, in this example, the perforated break groove 29c (first break groove) and the continuous linear break groove 29d (second break groove) are formed on the main surface 29a side as described above. , The break grooves 29 d are formed substantially parallel to the break grooves 29 c on the back side of the laminate 29. Further, the break groove 29c is formed so as to penetrate the laminated body 29 in the thickness direction.

  Therefore, the shape of the break groove 29c is, for example, cut along the break grooves 29c and 29d to form the capacitor 1, and as shown in FIG. However, as shown in FIG. 13B, since the hole shape of the break groove 29c is made uniform by the break groove 29d on the back surface side, the central portion including the diameter portion of the substantially radial portion is formed. It becomes arc shape like chipped.

  In this example, in the manufacturing method described above, the break groove 29c penetrates the stacked body 29, and the break groove 29d is also formed on the back surface side of the stacked body 29 along the break groove 29c. Therefore, the division of the multilayer body 29 for each capacitor formation region R can be performed more easily. Further, in the laminated body 29, the portion in the vicinity of the break groove 29c can be easily divided so as to be cut off before the portion in the vicinity of the break groove 29d. Therefore, the possibility that the external electrode layer 8 and the like near the break groove 29c may not be cut along the break groove 29c due to the portion near the break groove 29d being cut before the part near the break groove 29c is wiped away. it can.

  14 and 15 are diagrams showing another modification of the method for manufacturing the capacitor 1 described above. Note that FIGS. 14 and 15 show only the process steps of the manufacturing method according to this modification different from the manufacturing method described above. FIG. 14A is a schematic plan view of a laminate according to this modification, and FIG. 14B is a schematic longitudinal sectional view of the laminate as described above.

  As shown in FIG. 14, in this example, the perforated break groove 29c (first break groove) and the continuous linear break groove 29d (second break groove) are orthogonal to each other on the main surface 29a side. In addition, the break groove 29d is formed substantially parallel to the break groove 29c on the back surface side of the multilayer body 29. Further, the break groove 29c is formed so as to penetrate the laminated body 29 in the thickness direction. Further, in this example, the break groove 29c does not exist alone on the main surface 29a side, and a part of the break groove 29c is replaced with an additional linear (specifically rectangular) break groove 29h. It has a composition.

  Therefore, when the laminate shown in FIG. 14 is cut along the break grooves 29c, 29d and 29h to form the capacitor 1, as shown in FIG. 15, the main surface 29a side has an abbreviation due to the break groove 29c. A semicircular diameter portion and a rectangular portion due to the break groove 29h are mixed.

  In this example, in the manufacturing method described above, the break groove 29c penetrates the stacked body 29, and the break groove 29d is also formed on the back surface side of the stacked body 29 along the break groove 29c. Further, on the main surface 29a side, a part of the break groove 29c is replaced with a linear (rectangular) break groove 29h similar to the break groove 29d. Therefore, the division of the multilayer body 29 for each capacitor formation region R can be performed more easily. Further, in the laminated body 29, the portion in the vicinity of the break groove 29c can be easily divided so as to be cut off before the portion in the vicinity of the break groove 29d. Therefore, the possibility that the external electrode layer 8 and the like near the break groove 29c may not be cut along the break groove 29c due to the portion near the break groove 29d being cut before the part near the break groove 29c is wiped away. it can.

  The capacitor 1 is used by being built in a wiring board. Hereinafter, a wiring board incorporating the capacitor 1 will be described. FIG. 16 is a schematic longitudinal sectional view of a wiring board in which the wiring board built-in capacitor according to the present embodiment is built.

  A wiring substrate 40 shown in FIG. 16 is an organic substrate formed in a rectangular parallelepiped shape. The wiring board 40 is mainly composed of a polymer material reinforced with ceramic particles or fibers as fillers, for example.

  The wiring board 40 includes, for example, a core board 41 as a wiring board body that forms the core of the wiring board 40. The core substrate 41 includes a core material 41a formed of, for example, a glass-epoxy resin composite material, and a wiring layer 41b made of, for example, Cu having a desired pattern, formed on both surfaces of the core material 41a.

  The core substrate 41 has a plurality of through holes penetrating in the vertical direction of the core substrate 41, and a through hole conductor 41c electrically connected to the wiring layer 41b is formed in the through hole.

  For example, an opening 41 d as a capacitor housing portion for housing the capacitor 1 is formed in the central portion of the core substrate 41. The opening 41d is formed in, for example, a rectangular parallelepiped shape larger than the capacitor 1, and the capacitor 1 is accommodated in the opening 41d. The capacitor housing portion of the core substrate 41 is not limited to the opening 41d, and may be a recess.

  Round corners having a radius of curvature of 0.1 mm or more and 2 mm or less or chamfered portions having a chamfer dimension of 0.1 mm or more and 2 mm or less are formed at the corners of the four inner side surfaces of the core substrate 41.

  A gap between the core substrate 41 and the capacitor 1 is filled with a resin filler 42 made of, for example, a polymer material as a filler, and the capacitor 1 is attached to the core substrate 41 via the resin filler 42. It is fixed against. Here, the resin filler 42 enters the recess 2d.

  The filling of the resin filler 42 into the gap between the core substrate 41 and the capacitor 1 is performed by, for example, attaching the adhesive tape to the back surface of the core substrate 41 and the core so that the back surface of the capacitor 1 is attached to the adhesive tape. The capacitor 1 is disposed in the opening 41d of the substrate 41, and the position of the capacitor 1 with respect to the core substrate 41 is fixed with an adhesive tape. The resin filler 42 also has an action of absorbing the thermal expansion difference between the in-plane direction and the thickness direction between the core substrate 41 and the capacitor 1 by its own elastic deformation.

  A buildup wiring layer 43 is formed above the main surface 1 a of the core substrate 41 and the capacitor 1 and below the main surface 1 b of the core substrate 41 and the capacitor 1. The build-up wiring layer 43 includes insulating layers 44 to 50 made of a thermosetting resin such as an epoxy resin. Wiring layers 51 to 56 made of a conductive material such as Cu are formed between the insulating layers 44 and 45, for example.

  The upper surface of the insulating layer 47 and the lower surface of the insulating layer 50 are covered with solder resists 57 and 58 made of, for example, a photosensitive resin composition. Openings are formed in the solder resists 57 and 58, and terminals 59 for electrically connecting to the semiconductor chip (not shown) from the openings and terminals 60 for connecting to, for example, a main substrate (not shown) or the like. Is exposed. The external electrode layers 8 and 9 and the wiring layer 41b are electrically connected to the terminal 59 via the via conductor 61, and the external electrode layers 8 and 9 and the wiring layer are connected to the terminal 60 via the via conductor 62. 41b etc. are electrically connected.

  In the present embodiment, since the concave portion 2d extending in the thickness direction of the capacitor body 2 is formed on the side surface 2c1 or the like, the concave portion 2d can be filled with the resin filler 42. The contact area with the material 42 can be increased. Thereby, the adhesiveness of the resin filler 42 and the capacitor | condenser 1 can be improved, and also the adhesiveness of the resin filler 42 and the core board | substrate 41 can be improved. As a result, the core substrate 41 and the capacitor 1 can be reliably fixed, and the highly reliable wiring substrate 40 can be provided. Note that the same effect as described above can be obtained when a convex portion extending in the thickness direction of the capacitor body 2 is formed on the side surface 2c1 or the like instead of the concave portion 2d or together with the concave portion 2d.

  Further, as the number of the recesses 2d increases within a range in which the strength of the capacitor 1 is not deteriorated, the filling amount of the resin filler 42 can be increased. As a result, the core substrate 41 and the capacitor 1 can be more securely fixed. Therefore, the highly reliable wiring board 40 can be provided.

  In the present embodiment, the recess 2d is formed on the first main surface 2a side on the side surfaces 2c1 and 2c2, and the recess 2d is formed on the second main surface 2b side on the side surface 2c3. The vertical movement of the capacitor 1 relative to the substrate 41 can be suppressed. That is, when the capacitor 1 is built in the wiring board 40, the side surfaces 2c1 and 2c2 are formed on the first main surface 2a side, and the resin filler 42 enters the recess 2d. Therefore, even when a force in a direction from the second main surface 2b toward the first main surface 2a is applied, the capacitor 1 is difficult to move upward. Further, the side surface 2c3 is formed with a recess 2d on the second main surface 2b side, and the resin filler 42 enters the recess 2d, so that the first main surface 2a to the second main surface. Even when a force in a direction toward 2b is applied, the capacitor 1 is difficult to move downward. Therefore, the vertical movement of the capacitor 1 with respect to the core substrate 41 can be suppressed.

  If the side surface 2c1 or the like is composed only of the dielectric layer 3 as in the present embodiment, the scraps of the external electrode patterns 30 and 31 discharged when forming the break grooves 29c and 29d are formed on the side surface 2c1. Even if it adheres to the external main electrode 2a, the external electrode layer 8 on the first main surface 2a side and the external electrode layer 9 on the second main surface 2b side are not easily short-circuited.

  If a capacitor with a warp amount of 100 μm or more is to be built in the wiring substrate 40, it is difficult to incorporate the capacitor into the wiring substrate 40, and cracks may occur in the dielectric layer constituting the capacitor. On the other hand, in the present embodiment, since the amount of warping of the capacitor 1 is less than 100 μm, the dielectric layer 3 can be easily built into the wiring board 40 and the capacitor 1 is built into the wiring board 40. Cracks are unlikely to occur.

  In the present embodiment, since the chamfered portion 2f having a chamfer dimension C1 of 0.6 mm or more is formed at the corner of the outer peripheral surface 2c of the capacitor body 2, thermal stress is applied to the corner on the capacitor 1 side of the resin filler 42. Are less likely to concentrate, and the occurrence of cracks at the corner of the resin filler 42 on the capacitor 1 side can be suppressed. Even when a rounded portion having a radius of curvature of 0.6 mm or more is formed at the corner of the outer peripheral surface 2c of the capacitor body 2, the same effect as the chamfered portion 2f can be obtained.

  In the present embodiment, since the chamfered portion 2f and the rounded portion are formed at the corner of the outer peripheral surface 2c of the capacitor body 2, the corner of the capacitor 1 is compared with the case where the chamfered portion 2f and the rounded portion are not formed. The distance from the signal line existing near the portion to the dielectric layer 3 is increased. Thereby, the signal delay of the signal line existing near the corner of the capacitor 1 can be reduced.

  There is a so-called castellation technique in which a recess is formed at an end of a wiring board and a terminal electrode is formed in the recess. In the castellation, a terminal electrode is formed in the recess instead of a resin material. Therefore, in this specific configuration and usage of the recess, the present invention is different from the technique of castellation.

(Second Embodiment)
Hereinafter, a second embodiment of the present invention will be described with reference to the drawings. In the present embodiment, an example will be described in which a dummy electrode layer is formed on the capacitor body on the outer peripheral side of the dielectric layer from the internal electrode layer. In the second to fourth embodiments, the same members as those described in the first embodiment are denoted by the same reference numerals, and the contents described in the first embodiment. The content that overlaps with may be omitted. FIG. 17A and FIG. 17B are schematic side views of the wiring board built-in capacitor according to the present embodiment. FIG. 18 is a schematic vertical cross-sectional view of a wiring board built-in capacitor.

  As shown in FIGS. 17A to 18, dummy electrode layers 10 and 11 that do not function as electrodes are arranged in the capacitor body 2. Specifically, the dummy electrode layers 10 and 11 are disposed between the internal electrode layers 4 and 5 between the dielectric layers 3 and on the outer peripheral side of the dielectric layer 3 from the internal electrode layers 4 and 5 (that is, from the outer peripheral surface 2c). They are arranged at a predetermined interval.

  The dummy electrode layer 10 (first dummy electrode layer) is disposed in substantially the same plane as the internal electrode layer 4, and the dummy electrode layer 11 (second dummy electrode layer) is formed in substantially the same plane as the internal electrode 5. ing. Specifically, the dummy electrode layer 10 is disposed between the same layers as the dielectric layer 3 in which the internal electrode layer 4 is disposed, and the dummy electrode layer 11 is disposed in the dielectric layer 3 in which the internal electrode layer 5 is disposed. It is arranged between the same layers. The dummy electrode layers 10 and 11 may be formed between different layers from between the dielectric layers 3 on which the internal electrode layers 4 and 5 are disposed.

  The internal electrode layer 4 and the dummy electrode layer 10 and the internal electrode layer 5 and the dummy electrode layer 11 are electrically insulated from each other. The dielectric layer 3 is inserted into the gaps s1 and s2 between the internal electrode layers 4 and 5 and the dummy electrode layers 10 and 11, respectively. The internal electrode layers 4 and 5 and the dummy electrode layers 10 and 11 are Ensures electrical insulation.

  The gap s1 between the internal electrode layer 4 and the dummy electrode layer 10 and the gap s2 between the internal electrode layer 5 and the dummy electrode layer 11 are in a positional relationship shifted in the thickness direction of the capacitor body 2, There is no overlap. The gaps s1 between the internal electrode layer 4 and the dummy electrode layer 10 are aligned in the thickness direction of the capacitor body 2, and the gaps s2 between the internal electrode layer 5 and the dummy electrode layer 11 are respectively set. They are aligned in the thickness direction of the capacitor body 2.

  The dummy electrode layers 10 and 11 are formed so as to surround the internal electrode layers 4 and 5. The outer peripheral surfaces 10 a and 11 a of the dummy electrode layers 10 and 11 are exposed from between the dielectric layers 3. Accordingly, the side surfaces 2c1 to 2c4 are composed of the dielectric layer 3 and the dummy electrode layers 10 and 11. The side surfaces of the recess 2d and the notch 2e on the side surfaces 2c1 to 2c3 are also composed of the dielectric layer 3 and the dummy electrode layers 10 and 11.

  In consideration of relaxation of the step formed near the end of the capacitor 1, it is preferable that all the outer peripheral surfaces 10a, 11a of the dummy electrode layers 10, 11 are exposed from between the dielectric layers 3. Only the outer peripheral surfaces 10a and 11a of the part may be exposed.

  The total number of dummy electrode layers 10 and 11 is preferably at least half (about 50 layers) of the total number of internal electrode layers 4 and 5 in consideration of the relief of the step formed near the end of capacitor 1. It is more preferable that the total number of internal electrode layers 4 and 5 is approximately the same (about 100 layers).

  Although the dummy electrode layers 10 and 11 are made of a conductive material, the conductive material constituting the dummy electrode layers 10 and 11 is determined in consideration of the influence during the firing of the ceramic green sheets 22 and 24 and the formation process. The same material as the conductive material constituting the internal electrode layers 4 and 5 is preferable. For the same reason, the thickness of the dummy electrode layers 10 and 11 is preferably substantially the same as the thickness of the internal electrode layers 4 and 5 (for example, 2 μm or less).

  Also in the present embodiment, since the concave portion 2d extending in the thickness direction of the capacitor body 2 is formed on the side surface 2c1 and the like, substantially the same effect as the first embodiment can be obtained. Also in the present embodiment, similarly to the first embodiment, a convex portion extending in the thickness direction of the capacitor main body 2 may be formed on the side surface 2c1 or the like instead of the concave portion 2d or together with the concave portion 2d. In this case, the same effect as described above can be obtained.

  In the present embodiment, since the dummy electrode layers 10 and 11 are formed on the outer peripheral side of the dielectric layer 3 from the internal electrode layers 4 and 5, the thickness of the end portion of the capacitor body 2 can be increased. It is possible to provide the capacitor 1 in which the step formed near the end of the capacitor is relaxed. Thereby, when the resin filler 42 is filled in the gap between the core substrate 41 and the capacitor 1, the resin filler 42 is less likely to sink into the back surface side (second main surface 2 b side) of the capacitor 1. As a result, it becomes possible to reduce defects in the subsequent build-up process.

  When the gap s1 between the internal electrode layer 4 and the dummy electrode layer 10 and the gap s2 between the internal electrode layer 5 and the dummy electrode layer 11 overlap in the thickness direction of the capacitor body 2, the capacitor In the thickness direction of the main body 2, there are portions where neither the internal electrode layers 4 and 5 nor the dummy electrode layers 10 and 11 exist. Since the internal electrode layers 4 and 5 and the dummy electrode layers 10 and 11 do not exist in such a portion, the thickness becomes thinner than the other portions, resulting in a locally recessed shape. If the dent is formed at a location relatively close to the outer periphery of the capacitor 1, the resin filler 42 may sink into the back side of the capacitor 1. On the other hand, in the present embodiment, the gap s1 between the internal electrode layer 4 and the dummy electrode layer 10 and the gap s2 between the internal electrode layer 5 and the dummy electrode layer 11 are laminated on the dielectric layer 3. Since they do not overlap in the direction, it is difficult to form such a local recess, and the resin filler 42 can be prevented from entering.

  In the second embodiment, instead of forming the dummy electrode layers 10 and 11, at least one of the internal electrode layers 4 and 5 may be formed up to the side surfaces 2 c 1 to 2 c 4 of the capacitor body 2. When the internal electrode layers 4 and 5 are exposed on the side surfaces 2c1 to 2c4, if the scraps of the external electrode patterns 30 and 31 adhere to the side surfaces 2c1 to 2c4, a short circuit or the like may occur. The end portion of the main body 2 can be formed thick. Thereby, the level | step difference formed in the edge part vicinity of the capacitor | condenser 1 is relieve | moderated. When the shavings adhere to the side surfaces 2c1 to 2c4, it is possible to add a process for removing the shavings.

(Third embodiment)
Hereinafter, a third embodiment of the present invention will be described with reference to the drawings. In the present embodiment, an example will be described in which a concave portion extending from one main surface to the other main surface is formed on the side surface of the capacitor body. FIG. 19A and FIG. 19B are schematic side views of the wiring board built-in capacitor according to the present embodiment.

  As shown in FIGS. 19A and 19B, the recesses 2d provided on the side surfaces 2c1 to 2c3 are formed from the first main surface 2a to the second main surface 2b of the capacitor body 2. Yes. In addition, the convex part extended from the 1st main surface 2a of the capacitor | condenser main body 2 to the 2nd main surface 2b with the recessed part 2d instead of the recessed part 2d may be formed in the side surfaces 2c1-2c3. In the present embodiment, the notch 2e is not formed. Furthermore, in this embodiment, the dummy electrode layers 10 and 11 are not arranged, but the dummy electrode layers 10 and 11 may be arranged.

  Also in the present embodiment, since the recess 2d extending from the first main surface 2a of the capacitor body 2 to the second main surface 2b is formed on the side surface 2c1 and the like, it is almost the same as the first embodiment. An effect is obtained. The same effects as described above can be obtained when the side surface 2c1 or the like is provided with a convex portion extending from the first main surface 2a of the capacitor body 2 to the second main surface 2b instead of the concave portion 2d or together with the concave portion 2d. Is obtained.

(Fourth embodiment)
Hereinafter, a fourth embodiment of the present invention will be described with reference to the drawings. In this embodiment, an example in which capacitors are arranged between insulating layers on a core substrate will be described. FIG. 20 is a schematic longitudinal sectional view of a wiring board in which the wiring board built-in capacitor according to the present embodiment is built.

  As shown in FIG. 20, the opening 41 d is not formed in the core substrate 41, and the capacitor 1 is disposed between the insulating layers 44 and 45 on the core substrate 41. In the capacitor 1 of the present embodiment, the total number of internal electrode layers 4 and 5 is about 10 layers, which is thinner than the thickness of the capacitor 1 described in the first embodiment.

  The capacitor 1 can be disposed between the insulating layers 44 and 45 by the following procedure, for example. First, the capacitor body 2 in which the plated films 10 and 11 are formed on the external electrode layers 8 and 9 is disposed on the insulating layer 44 formed on the core substrate 41. Thereafter, the insulating layer 45 is placed on the capacitor body 2 and pressed while heating. As a result, the insulating layer 45 on the capacitor main body 2 flows to the side of the capacitor main body 2, and the capacitor main body 2 is disposed between the insulating layers 44 and 45. Thereafter, via holes penetrating the insulating layers 44 and 45 and the capacitor body 2 are formed, and via conductors 6 and 7 connected to the wiring layer 41b are formed in the via holes, thereby completing the capacitor 1.

  In the present embodiment, since the capacitor 1 is disposed between the insulating layers 44 and 45 formed on the core substrate 41, the distance between the capacitor 1 and the semiconductor chip can be further shortened. Thereby, wiring resistance and an inductance can be reduced more.

  The present invention is not limited to the description of the above embodiment, and the structure, material, arrangement of each member, and the like can be appropriately changed without departing from the gist of the present invention.

(A) And (b) is a typical top view of the capacitor | condenser for wiring board built-in which concerns on 1st Embodiment. (A) And (b) is a typical side view of the capacitor | condenser for wiring board built-in which concerns on 1st Embodiment. (A) is a typical longitudinal cross-sectional view of the capacitor | condenser for a wiring board when cut | disconnected by the AA line in Fig.1 (a), (b) is cut | disconnected by the BB line in Fig.1 (a). It is a typical longitudinal cross-sectional view of the capacitor | condenser for wiring board built in. It is a typical enlarged view of the outer periphery vicinity of the capacitor | condenser main body which concerns on 1st Embodiment. (A) And (b) is a typical top view of the ceramic green sheet in which the internal electrode pattern which concerns on 1st Embodiment was formed. (A) And (b) is a typical longitudinal cross-sectional view of the laminated body which concerns on 1st Embodiment. (A) is a schematic plan view of the laminated body which concerns on 1st Embodiment, (b) is a typical longitudinal cross-sectional view of the laminated body which concerns on 1st Embodiment. (A) is a schematic plan view of the laminated body which concerns on 1st Embodiment, (b) is a typical longitudinal cross-sectional view of the laminated body which concerns on 1st Embodiment. (A) is a schematic plan view of the laminated body which concerns on 1st Embodiment, (b) is a typical longitudinal cross-sectional view of the laminated body which concerns on 1st Embodiment. (A) is a schematic plan view of the laminated body which concerns on 1st Embodiment, (b) is a typical longitudinal cross-sectional view of the laminated body which concerns on 1st Embodiment. It is a typical top view of the layered product concerning a 1st embodiment. (A) is a typical top view of the layered product concerning the modification of a 1st embodiment, and (b) is the typical longitudinal section of the layered product concerning the modification of a 1st embodiment. It is. (A) is a general-view figure when it sees from the surface side of the perforated break groove after cut | disconnecting a laminated body in the said modified example, and being a capacitor | condenser, (b) is a laminated body in the said modified example FIG. 3 is an overview diagram when viewed from the back side of a perforated break groove after cutting a capacitor. (A) is a typical top view of the layered product concerning other modifications of a 1st embodiment, and (b) is a typical plan of a layered product concerning other modifications of a 1st embodiment. FIG. It is a general-view figure at the time of seeing from the surface side of a perforated break groove after cutting a layered product in the above-mentioned modification to make a capacitor. 1 is a schematic longitudinal sectional view of a wiring board in which a wiring board built-in capacitor according to a first embodiment is built. (A) And (b) is a typical side view of the capacitor | condenser for wiring board built-in which concerns on 2nd Embodiment. It is a typical longitudinal cross-sectional view of the capacitor | condenser for wiring board built-in which concerns on 2nd Embodiment. (A) And (b) is a typical side view of the capacitor | condenser for wiring board built-in which concerns on 3rd Embodiment. It is a typical longitudinal section of a wiring board in which a capacitor for wiring board built-in according to a fourth embodiment is built.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Capacitor, 2 ... Capacitor main body, 2a ... 1st main surface, 2b ... 2nd main surface, 2c1-2c4 ... Side surface, 2d ... Recessed part, 2e ... Notch, 3 ... Dielectric layer, 4, 5 ... Internal electrode layer, 8, 9 ... External electrode layer, 10, 11 ... Dummy electrode layer, 21, 23 ... Internal electrode pattern, 22, 24 ... Ceramic green sheet, 27, 28 ... Via conductor paste, 26, 29 ... Laminate 29a, 29b ... main surface, 29c, 29d ... break groove, 30, 31 ... external electrode pattern, 40 ... wiring board, 41 ... core substrate, 42 ... resin filler, 43 ... build-up layer.

Claims (12)

A wiring board built-in capacitor comprising a capacitor body having a plurality of laminated dielectric layers and internal electrode layers arranged between different dielectric layers,
A recess is formed on at least a first side surface of the capacitor body and a third side surface adjacent to the first side surface,
The concave portion formed on the first side surface is formed so as to extend in the thickness direction of the capacitor main body on the first main surface side of the capacitor main body, and is formed on the third side surface. The concave portion is formed so as to extend in the thickness direction of the capacitor main body on the second main surface side of the capacitor main body which is located on the side facing the first main surface. Wiring board built-in capacitor.   The notch formed along the outer peripheral surface of at least one of the first main surface and the second main surface of the capacitor body in which the concave portion is formed is included. 1. A capacitor for wiring board according to 1. The concave portion is formed on a second side surface facing the first side surface and a fourth side surface facing the third side surface, and the concave portion formed on the second side surface is formed on the capacitor body. The concave portion formed on the first main surface side and formed on the fourth side surface is formed on the second main surface side opposite to the first main surface of the capacitor body. 3. The wiring board built-in capacitor according to claim 1 or 2 . A wiring board built-in capacitor comprising a capacitor body having a plurality of laminated dielectric layers and internal electrode layers arranged between different dielectric layers,
At least one side surface of the capacitor body has a thickness of the capacitor body from at least one of the first main surface of the capacitor body and the second main surface located on the side opposite to the first main surface. A recess is formed so as to extend in the direction,
The side surface of the capacitor body in which the recess is formed includes a notch formed along the outer peripheral direction of the capacitor body on at least one side of the first main surface and the second main surface. A wiring board built-in capacitor .   The recess is formed from at least one end surface side of the first main surface and the second main surface of the capacitor body to a position of 20% to 70% of the thickness of the capacitor body. The wiring board built-in capacitor according to claim 1, wherein: Said dielectric layer is made mainly of a ceramic, the concave portion, any one of claims 1 to 5, characterized in that the ceramic forming the dielectric layer on the side surface of the capacitor body is exposed Wiring board built-in capacitor as described in 4. The recess, the wiring board built capacitor according to any one of claims 1 to 6, characterized in that a plurality of formed at predetermined intervals in the side surface of the capacitor body. The capacitor body further includes a dummy electrode layer disposed at a predetermined distance from the internal electrode layer on an outer peripheral side of the dielectric layer from the internal electrode layer. 7 wiring board built capacitor according to any one of. Wherein at least a portion of the internal electrode layer, the wiring board built capacitor according to any one of claims 1 to 8, characterized in that it is exposed at the side surface of the capacitor body. 9. The wiring board built-in capacitor according to claim 8, wherein the dummy electrode layer is exposed on a side surface of the capacitor body.   A wiring board comprising the wiring board built-in capacitor according to any one of claims 1 to 10.   The wiring board built-in capacitor includes a core board, and is configured to be fixed and built in the core board through a resin material filled in the concave portion formed in the capacitor body. The wiring board according to claim 11.

Images