JP5524680B2 - Manufacturing method of capacitor for wiring board - Google Patents

Description

  The present invention relates to a method for manufacturing a wiring board built-in capacitor built in a wiring board.

  In recent years, semiconductor integrated circuit elements (IC chips) used as computer microprocessors and the like have become increasingly faster and more functional, with an accompanying increase in the number of terminals and a tendency to narrow the pitch between terminals. . In general, a large number of terminals are densely arranged on the bottom surface of an IC chip, and such a terminal group is connected to a terminal group on the motherboard side in the form of a flip chip. However, it is difficult to connect the IC chip directly on the mother board because there is a large difference in the pitch between the terminals on the IC chip side terminal group and the mother board side terminal group. For this reason, a method is generally employed in which a package is prepared by mounting an IC chip on an IC chip mounting wiring board, and the package is mounted on a motherboard. In a wiring board for mounting an IC chip constituting this type of package, it has been proposed to provide a capacitor (also referred to as a “capacitor”) in order to reduce switching noise of the IC chip and stabilize the power supply voltage. . For example, wiring boards in which capacitors are embedded in a resin core substrate (see, for example, Patent Documents 1 and 2) and wiring boards in which capacitors are embedded in build-up layers formed on the front and back surfaces of a resin core substrate have been proposed in the past. ing.

  In the wiring substrates of Patent Document 1 and Patent Document 2, a capacitor is housed in an opening formed in the core substrate, and a build-up layer formed by laminating a resin interlayer insulating layer and a conductor layer on the front surface and the back surface of the core substrate. Is formed. The capacitor built in the wiring substrate of Patent Document 1 has a rough surface formed on the ceramic surface or the surface of the electrode portion, and has improved adhesion with a resin material provided around the capacitor. In addition, the capacitor built in the wiring board of Patent Document 2 has a recess formed on the side surface thereof, and has improved adhesion with a resin material provided around the capacitor.

JP 2001-332437 A JP 2007-194617 A

  By the way, in the capacitor | condenser of patent document 1, when forming a rough surface in a ceramic surface and an electrode part, it is necessary to perform a different process with respect to two or more types of materials, and to form a rough surface. Specifically, a rough surface is formed on the surface of the electrode portion by performing plating treatment, oxidation reduction treatment, etching treatment, or the like, and a rough surface is formed on the ceramic surface by embossing. . For this reason, the manufacturing process of the capacitor becomes complicated.

  The capacitor disclosed in Patent Document 2 is formed by dividing (breaking) a multi-piece ceramic sintered body in which perforated break grooves are formed by laser processing along the break grooves. And a recessed part is formed in the side surface of the capacitor which appeared as a break fracture surface. That is, the break groove portion is formed as a recess on the side surface of the capacitor. In this capacitor, the surface roughness is different between the surface of the break groove (recess) formed by laser processing and the break fracture surface. Specifically, the surface of the recess is roughened to some extent by laser processing, but the break fracture surface has a low roughness and cannot sufficiently secure the adhesion to the resin material. Further, in this capacitor, the boundary portion 403 between the recess-unformed portion 402 and the recess 401 is squared on the side surface 400 that appears as a break fracture surface (see FIG. 30). In this case, there is a problem that stress concentrates on the boundary portion 403 between the recess-unformed portion 402 and the recess 401 and a crack 405 is generated on the resin material 404 side.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a method of manufacturing a wiring board built-in capacitor that can sufficiently ensure adhesion to the wiring board.

And as means (means 1) for solving the above-mentioned problem, there are a first main surface, a second main surface located on the opposite side of the first main surface, and the first main surface and the second main surface. and has a side surface located between, comprising a plate-shaped capacitor body having a multilayered structure by stacking the internal electrodes and the ceramic dielectric layer, the side surface of the capacitor body, the ceramic dielectric layer A capacitor with a built-in wiring board is manufactured in which a ceramic to be exposed is exposed and a plurality of recesses extending in a thickness direction of the capacitor body from at least one of the first main surface and the second main surface are formed. a method, by fixing in a state so as to expose the side surface which the recess is formed and arranged by superimposing a plurality of the capacitor body in the thickness direction, with respect to the side After Hanaretogi grains loose grains with respect to the first main surface and the second major surface while acting has set condition does not act, the surface for performing wet abrasive to the side surface of the capacitor body There is a method of manufacturing a wiring board built-in capacitor characterized by including a processing step.

  Therefore, according to the invention described in the means 1, the surface of the side surface is appropriately roughened by performing wet abrasive grain processing on the side surface of the capacitor body in the surface treatment step. When this wiring board built-in capacitor is built in the wiring board, the contact area with the resin material becomes large, so that the adhesion to the wiring board can be improved.

  The method for manufacturing a wiring board built-in capacitor includes a non-fired ceramic laminate having a multi-layered structure in which an unfired conductor part to be the internal electrode later and an unfired ceramic part to be the ceramic dielectric layer are laminated. A laminated body producing step for producing a body, and a break groove forming step for forming a break groove formed by arranging a plurality of holes to be part of the concave portion in a perforated form in the unfired ceramic laminated body, By sintering the green ceramic laminate to obtain a capacitor body aggregate having the internal electrode and the ceramic dielectric layer, and dividing the capacitor body aggregate along the break grooves, And a dividing step of obtaining a plurality of capacitor main bodies and forming the concave portions on the side surfaces that appear as break fracture surfaces.Then, the surface treatment process is performed after the laminated body manufacturing process, the break groove forming process, the firing process, and the dividing process are sequentially performed. When the capacitor is manufactured in this manner, the boundary portion between the recess-unformed portion and the recess becomes an angular shape on the side surface of the capacitor body that becomes the break fracture surface. Then, by performing wet abrasive grain processing in the surface treatment step, the boundary portion between the concave portion-unformed portion and the concave portion on the side surface of the capacitor body is scraped, and the boundary portion has a rounded shape. Therefore, when the capacitor is built in the wiring board, it is possible to avoid the problem that the stress applied to the boundary portion between the recess-unformed portion and the recess is dispersed and a crack is generated on the resin material side. Moreover, since the side surface that appeared as the break fracture surface can be roughened, the contact area with the resin material is increased, and the adhesion with the wiring board can be improved.

  In the break groove forming step, it is preferable to form perforated break grooves by laser processing. In this case, the surface of the concave portion is a processed surface subjected to laser processing, and is in a state roughened to some extent by laser processing. Therefore, before the surface treatment step, the surface roughness of the recess-unformed portion on the side surface is smaller than the surface roughness of the inner wall surface of the recess. And if the said surface treatment process is passed, the said recessed part non-formation part will be roughened and the difference of the surface roughness of the said 2 site | part will reduce. As described above, by increasing the roughness of the non-recessed portion in the surface treatment step, it is possible to more reliably improve the adhesion with the resin material.

  In the surface treatment step, it is preferable to perform wet abrasive processing using loose abrasive particles having an average particle size smaller than the maximum width of the recess. In this case, since the free abrasive grains reliably hit the inner wall surface of the concave portion, the inner wall surface of the concave portion can be reliably roughened, and foreign matters such as smear adhered to the inner wall surface of the concave portion during laser processing. Can be reliably removed. For this reason, the adhesiveness of the inner wall surface of a recessed part and a resin material can be improved.

  Specifically, the average particle size of the free abrasive grains is preferably 8 μm or more and 200 μm or less. Here, polishing efficiency will fall that the average particle diameter of a loose abrasive grain is less than 8 micrometers. Further, when the average grain size of the loose abrasive grains is larger than 200 μm, it may be overpolished and the external electrode may be peeled off. Therefore, the side surfaces can be efficiently and reliably polished by using moderately sized free abrasive grains having an average particle size of 8 μm or more and 200 μm or less.

  The wet abrasive processing is wet blasting, and the air pressure during blasting is preferably 0.05 MPa or more and 0.6 MPa or less. This is because if the air pressure at the time of blasting is less than 0.05 MPa, the polishing efficiency is lowered, and if the air pressure at the time of blasting is higher than 0.6 MPa, it becomes an over-polished state.

  Examples of the material for forming the free abrasive grains include alumina, silicon carbide, and glass. In the wet blasting process, a muddy slurry obtained by uniformly stirring the free abrasive grains and water is used. The content (volume concentration) of the free abrasive grains contained in the slurry is 5 vol% or more and 40 vol%. It is preferable to be within the following range. This is because if the content of free abrasive is less than 5 vol%, the polishing efficiency is lowered, and if the content of free abrasive exceeds 40 vol%, the free abrasive in the slurry is precipitated. This is because work efficiency decreases.

  The nozzle diameter of the injection nozzle used in the wet blasting is preferably 15 mm or less. When the injection nozzle having such a nozzle diameter is used, a relatively narrow side surface of the capacitor body can be efficiently and uniformly polished.

In the surface treatment step, the wet abrasive is selectively set by setting a condition in which loose abrasives act on the side surface but no loose abrasive grains act on the first main surface and the second main surface. since that row Tsu grain processing, without external electrodes provided on the first main surface and second main surface peeling can be reliably roughening the side surface of the capacitor body.

The capacitor body is plate-shaped, and in the surface treatment step, the capacitor body is fixed in a state where a plurality of the capacitor bodies are stacked in the thickness direction so as to expose the side surface where the recess is formed. because Life has the wet abrasive to the side surface of the capacitor body, it can be simultaneously subjected to wet abrasive to a plurality of capacitor bodies, performing the polishing side efficiently and securely Can do.

  In the surface treatment step, it is preferable that a plurality of the capacitor main bodies are fixed on a fixing plate using a solder with at least one of the side surfaces exposed. Since the wax melts at a relatively low temperature and hardens at room temperature (for example, a temperature of about 50 ° C.), a plurality of capacitor bodies can be easily fixed on the fixing plate. Further, since the hardened solder is softer than the capacitor body, there is little damage due to wet abrasive processing, and the capacitor body can be securely fixed during the processing. Furthermore, since the wax is easily dissolved by the organic solvent, the wax adhering to the capacitor body can be easily removed by washing with the organic solvent after the wet abrasive processing.

  The wiring board built-in capacitor preferably has an outer dimension of 3 mm to 40 mm. Here, when the outer dimension is less than 3 mm, it becomes difficult to reliably perform wet abrasive grain processing on the capacitor body and the side surface, and work efficiency deteriorates. Further, when the outer dimension is larger than 40 mm, the warpage of the capacitor main body increases, so that a gap is generated between the capacitor main bodies when a plurality of capacitor main bodies are stacked in the thickness direction and fixed. If wet abrasive processing is performed in this state, the free abrasive grains enter the gaps between the capacitor bodies, so that the free abrasive grains act on the first main surface and the second main surface, and the external electrodes and the like. There is a risk of damaging it. Therefore, if the external dimensions of the wiring board built-in capacitor are 3 mm or more and 40 mm or less, the wet abrasive grain processing on the side surface can be performed efficiently and reliably.

  The capacitor body is disposed outside the internal electrode between the ceramic dielectric layers, and has a dummy internal electrode electrically independent from the internal electrode, and a part of the dummy internal electrode is not formed with the recess. It may be exposed at the portion and the boundary portion. Then, after the surface treatment step, the outer peripheral edge of the dummy internal electrode exposed at the recess-unformed portion and the boundary portion is crushed, and the recess-unformed portion and the boundary portion are partially covered. The As described above, when the recess-unformed portion and the boundary portion are partially covered by a part of the dummy internal electrode, the strength of the portion can be increased. Therefore, even when stress is concentrated at the boundary between the recess-unformed portion and the recess when the capacitor is built in the wiring board, it is possible to avoid the problem that the ceramic of the portion is lost, and the adhesion to the resin material. Sufficient sex can be secured.

  The capacitor includes a plurality of via conductors in a capacitor electrically connected to both the internal electrode and the external electrode, and the plurality of via conductors in the capacitor are arranged in an array as a whole. A capacitor is preferred. With such a structure, the inductance of the capacitor can be reduced, and high-speed power supply for absorbing noise and smoothing power fluctuations can be performed.

  The ceramic dielectric layer is made of a dielectric ceramic such as barium titanate, lead titanate, or strontium titanate. In addition, it can also be composed of low-temperature fired ceramics such as borosilicate glass or lead borosilicate glass added with an inorganic ceramic filler such as alumina. Depending on the required characteristics, alumina, aluminum nitride, boron nitride It can also be composed of a high-temperature fired ceramic such as silicon, silicon carbide, or silicon nitride.

  The internal electrode, the dummy internal electrode, and the via conductor in the capacitor are not particularly limited, but are preferably metallized conductors. The metallized conductor is formed by applying a conductive paste containing metal powder by a conventionally well-known method, for example, a metallized printing method, followed by baking. When the metallized conductor and the ceramic dielectric layer are formed by the co-firing method, the metal powder in the metallized conductor needs to have a melting point higher than the firing temperature of the ceramic dielectric layer. For example, when the ceramic dielectric layer is made of a so-called high-temperature fired ceramic (for example, alumina or the like), nickel (Ni), tungsten (W), molybdenum (Mo), manganese (Mn), or the like is used as the metal powder in the metallized conductor. And their alloys can be selected. When the ceramic dielectric layer is made of a so-called low-temperature fired ceramic (for example, glass ceramic), copper (Cu) or silver (Ag) or an alloy thereof can be selected as the metal powder in the metallized conductor.

Sectional drawing which shows schematic structure of the wiring board in 1st Embodiment. The top view which shows schematic structure of the capacitor | condenser for wiring board built-in in 1st Embodiment. The top view which shows schematic structure of the capacitor | condenser for wiring board built-in in 1st Embodiment. The side view which shows schematic structure of the capacitor | condenser for wiring board incorporation in 1st Embodiment. The side view which shows schematic structure of the capacitor | condenser for wiring board incorporation in 1st Embodiment. Sectional drawing in the AA of the capacitor | condenser for wiring board incorporation in FIG. Sectional drawing in the BB line of the capacitor | condenser for wiring board incorporation in FIG. The expanded sectional view which shows the recessed part of the side surface in a capacitor | condenser main body. The typical top view of the ceramic green sheet in which the internal electrode pattern was formed. The typical top view of the ceramic green sheet in which the internal electrode pattern was formed. The typical longitudinal section of a non-fired ceramic layered product. The typical longitudinal section of a non-fired ceramic layered product. The typical top view of a non-fired ceramic laminated body. The typical top view of a non-fired ceramic laminated body. The typical longitudinal section of a non-fired ceramic layered product. The typical top view of a non-fired ceramic laminated body. The typical longitudinal section of a non-fired ceramic layered product. The typical top view of a non-fired ceramic laminated body. The typical longitudinal section of a ceramic sintered compact. The typical top view which shows the some capacitor | condenser main body after a division | segmentation. The expanded sectional view which shows the recessed part after a division | segmentation process. The top view which shows the some capacitor | condenser main body fixed on the stainless steel plate. The side view which shows the some capacitor | condenser main body fixed on the stainless steel plate. The typical side view of the ceramic capacitor of 2nd Embodiment. The typical side view of the ceramic capacitor of 2nd Embodiment. The typical longitudinal section showing the ceramic capacitor of a 2nd embodiment. The enlarged plan view which shows the recessed part of the side surface in a capacitor | condenser main body. The typical side view which shows the ceramic capacitor of another embodiment. The typical top view which shows the ceramic capacitor of another embodiment. Explanatory drawing which shows the recessed part and crack in a prior art.

[First Embodiment]
DESCRIPTION OF EMBODIMENTS A first embodiment embodying the present invention will be described below in detail with reference to the drawings.

  As shown in FIG. 1, the wiring board 10 of the present embodiment is a wiring board for mounting an IC chip. The wiring substrate 10 includes a resin core substrate 11 made of glass epoxy, a first buildup layer 31 (wiring laminated portion) formed on the core main surface 12 (upper surface in FIG. 1) of the resin core substrate 11, a resin core It consists of a second buildup layer 32 (wiring laminate) formed on the core back surface 13 (lower surface in FIG. 1) of the substrate 11.

  Through holes 15 penetrating in the thickness direction are formed at a plurality of locations in the resin core substrate 11, and through hole conductors 16 are formed in the through hole 15. The through-hole conductor 16 connects the core main surface 12 side and the core back surface 13 side of the resin core substrate 11. Further, a conductor layer 41 made of copper is patterned on the core main surface 12 and the core back surface 13 of the resin core substrate 11, and each conductor layer 41 is electrically connected to the through-hole conductor 16.

  The first buildup layer 31 formed on the core main surface 12 of the resin core substrate 11 includes two resin interlayer insulating layers 33 and 35 made of thermosetting resin (epoxy resin), and a conductor layer 42 made of copper. Are alternately stacked. Terminal pads 44 are formed in an array at a plurality of locations on the surface of the second resin interlayer insulation layer 35. Further, the surface of the resin interlayer insulating layer 35 is almost entirely covered with a solder resist 37. An opening 46 for exposing the terminal pad 44 is formed at a predetermined position of the solder resist 37. A plurality of solder bumps 45 are provided on the surface of the terminal pad 44. Each solder bump 45 is electrically connected to the surface connection terminal 22 of the IC chip 21 having a rectangular flat plate shape. The region where each terminal pad 44 and each solder bump 45 is formed is an IC chip mounting region 23 on which the IC chip 21 can be mounted. A plurality of via conductors 43 are formed in the first resin interlayer insulation layer 33, and a plurality of via conductors 43 are also formed in the second resin interlayer insulation layer 35. Each via conductor 43 electrically connects the conductor layers 41 and 42 and the terminal pad 44 to each other.

  The second buildup layer 32 formed on the core back surface 13 of the resin core substrate 11 has substantially the same structure as the first buildup layer 31 described above. That is, the second buildup layer 32 has a structure in which two resin interlayer insulating layers 34 and 36 made of thermosetting resin (epoxy resin) and conductor layers 42 are alternately laminated. BGA pads 48 electrically connected to the conductor layer 42 via the via conductors 43 are formed in an array at a plurality of locations on the lower surface of the resin interlayer insulating layer 36. The lower surface of the resin interlayer insulating layer 36 is almost entirely covered with a solder resist 38. An opening 40 for exposing the BGA pad 48 is formed at a predetermined portion of the solder resist 38. A plurality of solder bumps 49 that can be electrically connected to a mother board (not shown) are disposed on the surface of the BGA pad 48. The wiring board 10 shown in FIG. 1 is mounted on a mother board (not shown) by each solder bump 49.

  The resin core substrate 11 has a substantially rectangular plate shape in plan view of 25 mm in length × 25 mm in width × 0.9 mm in thickness, and has a rectangular shape in plan view that opens at the center of the core main surface 12 and the center of the core back surface 13. The receiving hole 90 is provided. That is, the accommodation hole 90 is a through hole. The accommodating hole 90 has chamfered portions with chamfer dimensions of 0.1 mm or more and 2.0 mm or less at the four corners. The ceramic capacitor 101 (wiring board built-in capacitor) is housed in the housing hole 90 in an embedded state. The ceramic capacitor 101 is accommodated with the capacitor main surface 102 facing the same side as the core main surface 12 and the capacitor back surface 103 facing the same side as the core back surface 13.

  The ceramic capacitor 101 according to the present embodiment has a substantially rectangular plate shape in plan view of 12.0 mm long × 12.0 mm wide × 0.9 mm thick. The ceramic capacitor 101 is disposed in a region immediately below the IC chip mounting region 23 in the resin core substrate 11. The area of the IC chip mounting region 23 (the area of the surface on which the surface connection terminals 22 are formed in the IC chip 21) is set to be smaller than the area of the capacitor main surface 102 of the ceramic capacitor 101. When viewed from the thickness direction of the ceramic capacitor 101, the IC chip mounting region 23 is located in the capacitor main surface 102 of the ceramic capacitor 101.

  As shown in FIG. 1, the gap between the inner surface of the accommodation hole 90 and the capacitor side surface 106 of the ceramic capacitor 101 is a resin filler made of a polymer material (in this embodiment, a thermosetting resin such as epoxy). It is filled with 92. The resin filler 92 has a function of fixing the ceramic capacitor 101 to the resin core substrate 11. Further, the resin filler 92 may be added with ceramic powder such as silica in order to relieve the thermal expansion difference from the ceramic capacitor 101. Moreover, in order to improve heat dissipation, metal powders, such as Cu, may be added.

  Hereinafter, the configuration of the ceramic capacitor 101 of the present embodiment will be described in detail. FIG. 2 is a schematic plan view of the ceramic capacitor 101 viewed from the capacitor main surface 102 side, and FIG. 3 is a schematic plan view of the ceramic capacitor 101 viewed from the capacitor back surface 103 side. 4 and 5 are schematic side views of the ceramic capacitor 101. FIG. 6 is a schematic longitudinal sectional view of the ceramic capacitor 101 when cut along line AA in FIG. 2, and FIG. 7 is a schematic view of the ceramic capacitor 101 when cut along line BB in FIG. It is a longitudinal cross-sectional view. FIG. 8 is a schematic enlarged view of the vicinity of the outer periphery of the ceramic capacitor 101.

  The ceramic capacitor 101 shown in FIGS. 2 to 7 is a so-called via array type ceramic capacitor. The ceramic capacitor 101 includes a capacitor body 104 that forms the core of the capacitor 101. The capacitor body 104 has a structure in which a power supply internal electrode layer 141 (internal electrode), a ground internal electrode layer 142 (internal electrode), and a ceramic dielectric layer 105 are laminated to form a multilayer. The ceramic dielectric layer 105 is made of a sintered body of barium titanate, which is a kind of high dielectric constant ceramic, and functions as a dielectric (insulator) between the power supply internal electrode layer 141 and the ground internal electrode layer 142. That is, the power supply internal electrode layer 141 and the ground internal electrode layer 142 are electrically insulated via the ceramic dielectric layer 105. Further, the power supply internal electrode layers 141 and the ground internal electrode layers 142 are alternately arranged via the ceramic dielectric layers 105 in the stacking direction of the ceramic dielectric layers 105. The total number of internal electrode layers 141 and 142 is about 100 layers.

  In the present embodiment, a capacitor forming layer portion 144 having a structure in which a plurality of ceramic dielectric layers 105 and a plurality of internal electrode layers 141 and 142 are alternately stacked is divided into two regions on the capacitor body 104, the upper side and the lower side. It is divided and provided. Between the upper capacitor formation layer portion 144 and the lower capacitor formation layer portion 144, an intermediate layer portion 145 composed of a plurality of ceramic dielectric layers 105 is provided. Further, a cover layer portion 146 made of a plurality of ceramic dielectric layers 105 is provided on the surface layer portion on the capacitor main surface 102 side so as to cover the upper surface of the upper capacitor forming layer portion 144. A cover layer portion 146 made of a plurality of ceramic dielectric layers 105 is also provided on the surface layer portion on the capacitor back surface 103 side so as to cover the lower surface of the lower capacitor forming layer portion 144. The intermediate layer portion 145 and the cover layer portion 146 are not provided with the internal electrode layers 141 and 142 like the capacitor forming layer portion 144.

  The internal electrode layers 141 and 142 are both formed of nickel as a main component, and contain a ceramic material similar to the ceramic material (barium titanate) constituting the ceramic dielectric layer 105. By including such a ceramic material in the internal electrode layers 141 and 142, respectively, adhesion between the ceramic dielectric layer 105 and the internal electrode layers 141 and 142 can be enhanced. The internal electrode layers 141 and 142 need not contain such a ceramic material. The thickness of the internal electrode layers 141 and 142 is, for example, 2 μm or less.

  The external appearance of the capacitor body 104 is as follows. The capacitor main surface 102 (first main surface) positioned in the thickness direction of the capacitor main body 104, the capacitor back surface 103 (second main surface) positioned on the opposite side of the capacitor main surface 102, and the capacitor It is composed of a side surface 106 positioned between the main surface 102 and the capacitor back surface 103. The side surface 106 is mainly the first side surface 106a, the second side surface 106b positioned opposite (opposite) the side surface 106a, the side surface 106a and the third side surface 106c adjacent to the side surface 106b, and the opposite side surface 106c. It is comprised from the 4th side surface 106d located in the side (opposite) and adjacent to the side surface 106a and the side surface 106b. Each of the side surfaces 106a to 106d of the present embodiment is composed only of the ceramic dielectric layer 105, and the ceramic is exposed.

  As shown in FIGS. 2 to 5, the side surfaces 106 a to 106 c are respectively formed with a recess 107 extending in the thickness direction of the capacitor main body 104 and a notch 108 extending in the outer peripheral direction of the capacitor main body 104. Yes. Specifically, as shown in FIG. 4, in the side surface 106a, the recess 107 is formed on the capacitor main surface 102 side (extending in the thickness direction from the capacitor main surface 102), and the notch 108 is It is formed on the capacitor back surface 103 side. Further, in the side surface 106b, a recess 107 and a notch 108 are formed in the same manner as the side surface 106a. Further, as shown in FIG. 5, on the side surface 106 c, the recess 107 is formed on the capacitor back surface 103 side (extending in the thickness direction from the capacitor back surface 103), and the notch 108 is formed on the capacitor main surface 102. Formed on the side.

  The surfaces of the recess 107 and the notch 108 are also composed only of the ceramic dielectric layer 105, and the ceramic is exposed. The recess 107 is a groove having a substantially semicircular cross section, and the width gradually decreases from the capacitor main surface 102 and the capacitor back surface 103 in the thickness direction. The side surface 106d may also be formed with a recess 107 and a notch 108. Further, the notch 108 is formed from one end edge of each of the side surfaces 106a to 106c to the other end edge.

  A plurality of recesses 107 are formed at predetermined intervals along the outer periphery of the capacitor body 104. The recesses 107 on the side surfaces 106a and 106b are preferably formed from the capacitor main surface 102 to a position not less than 20% and not more than 70% of the thickness of the capacitor body 104, and the recesses 107 on the side surface 106c are formed from the capacitor back surface 103 to the capacitor. It is desirable that the main body 104 is formed up to a position of 20% to 70% of the thickness. The reason why such a range is desirable is that if it is 20% or more, the adhesion with the resin filler 92 can be sufficiently improved, and if it is 70% or less, in the conveyance of the capacitor 101, etc. This is because cracking or chipping in the recess 107 can be reduced.

  As shown in FIG. 8, in the present embodiment, the boundary portion 110 between the recess-unformed portion 109 and the recess 107 on the side surfaces 106a to 106c has a rounded shape. The radius of curvature of the boundary portion 110 between the recess-unformed portion 109 and the recess 107 is preferably 0.005 mm or more and 0.2 mm or less, and is, for example, about 0.05 mm in the present embodiment. In addition, the surface of each side surface 106a-106d in the capacitor body 104 is a rough surface subjected to surface roughening.

  Further, in the cut surface that appears when the capacitor body 104 is cut in parallel to the capacitor main surface 102 and the capacitor back surface 103, the width of the recess 107 is X, and the depth of the recess 107 with respect to the non-recessed portion 109 is set. When defined as Y, the relationship X> Y holds. The width X of the concave portion 107 on the main surface 102 and the back surface 103 is preferably 60 to 150 μm. The reason why this range is preferable is that if it is less than 60 μm, the resin filler 92 does not enter well, and if the adhesiveness is insufficient or a void is formed, it becomes a product with low reliability due to the influence of that portion. If the thickness exceeds 150 μm, the area of the internal electrode layers 141 and 142 becomes small, which causes a reduction in capacity. In the present embodiment, the width X of the recess 107 is about 100 μm, and the depth Y of the recess 107 is about 35 μm. Further, the interval Z between the adjacent concave portions 107 is about 75 μm.

  As shown in FIGS. 2 and 3, chamfered portions 104 a having a chamfer dimension of 0.6 mm or more are formed at four corners of the capacitor body 104. Instead of the chamfered portion 104a or together with the chamfered portion 104a, a rounded portion having a radius of curvature of 0.6 mm or more may be formed at at least one corner of the capacitor body 104. Thus, by forming the chamfered portion 104a and the rounded portion, when the ceramic capacitor 101 is built in the wiring substrate 10 or when the resin filler 92 is deformed due to a temperature change, Since stress concentration can be relaxed, the occurrence of cracks in the resin filler 92 can be prevented.

  A large number of via holes 130 are formed in the capacitor body 104. These via holes 130 penetrate the capacitor body 104 in the thickness direction and are arranged in an array over the entire surface of the capacitor body 104. In each via hole 130, a plurality of in-capacitor via conductors 131 and 132 are formed to communicate between the capacitor main surface 102 and the capacitor back surface 103 of the capacitor body 104. In this embodiment, since the diameter of the via hole 130 is set to about 100 μm, the diameter of the via conductors 131 and 132 in the capacitor is also set to about 100 μm. Each power supply capacitor internal via conductor 131 passes through each power supply internal electrode layer 141 and electrically connects them to each other. Each ground capacitor via conductor 132 passes through each ground internal electrode layer 142 and electrically connects them to each other. Each power source capacitor via conductor 131 and each ground capacitor inner via conductor 132 are arranged in an array as a whole.

  As shown in FIG. 6, a clearance hole 133 (hole) is formed in the internal electrode layer 142 in a region where the via conductor 131 penetrates, and the internal electrode layer 142 and the via conductor 131 are electrically insulated. Yes. Similarly, as shown in FIG. 7, the internal electrode layer 141 has a clearance hole 134 (hole) in a region through which the via conductor 132 passes, and the internal electrode layer 141 and the via conductor 132 are electrically connected to each other. Is insulated. The ceramic dielectric layer 105 is interposed between the internal electrode layers 141 and 142 and the via conductors 131 and 132 in the clearance holes 133 and 134.

  The via conductors 131 and 132 are formed using nickel as a main material, and contain a ceramic material similar to the ceramic material constituting the ceramic dielectric layer 105. By including such a ceramic material in the via conductors 131 and 132, adhesion between the ceramic dielectric layer 105 and the via conductors 131 and 132 can be improved. The via conductors 131 and 132 may not contain such a ceramic material.

  On the capacitor main surface 102, for example, a main surface side power external electrode 111 and a main surface side ground external electrode 112 used as an external terminal for power supply and an external terminal for ground connection are formed, respectively. On the capacitor back surface 103, for example, a back-side power external electrode 121 and a back-side ground external electrode 122 used as a power supply external terminal and a ground connection external terminal are formed. The external electrodes 111, 112, 121, and 122 are not necessarily formed on both the capacitor main surface 102 and the capacitor back surface 103 of the capacitor body 104, and are not provided on either the capacitor main surface 102 or the capacitor back surface 103. It may be formed.

  As shown in FIG. 2, a plurality of substantially circular power supply external electrodes 111 are formed in an array on the capacitor main surface 102, and the ground external electrode 112 surrounds each power supply external electrode 111. Is formed. As shown in FIG. 3, on the capacitor back surface 103, a plurality of substantially circular ground external electrodes 122 are formed in an array, and the power external electrode 121 surrounds each ground external electrode 122. Is formed.

  The main-surface-side power external electrode 111 is directly connected to the end surface of the power-capacitor via conductor 131 on the capacitor main surface 102 side, and the main-surface-side ground external electrode 112 The via conductor 132 is directly connected to the end surface on the capacitor main surface 102 side. The back-side power external electrode 121 is directly connected to the end surface on the capacitor back surface 103 side of the plurality of power-source capacitor via conductors 131, and the back-side ground external electrode 122 is inside the ground capacitor. The via conductor 132 is directly connected to the end surface on the capacitor back surface 103 side. Therefore, the power supply external electrodes 111 and 121 are electrically connected to the power supply capacitor internal via conductor 131 and the power supply internal electrode layer 141, and the ground external electrodes 112 and 122 are connected to the ground capacitor internal via conductor 132 and the ground internal electrode. Conductive to layer 142.

  On both the capacitor main surface 102 side and the capacitor back surface 103 side, the power external electrodes 111 and 121 and the ground external electrodes 112 and 122 are separated from each other and are electrically insulated from each other. The distance (clearance) between the power supply external electrodes 111 and 121 and the ground external electrodes 112 and 122 is preferably as small as possible as long as insulation is ensured, and is, for example, about 150 μm.

  On the capacitor main surface 102 side, the total surface area of the external electrodes 111 and 112 is not less than 45% and not more than 90% of the area of the capacitor main surface 102, and on the capacitor back surface 103 side, the total surface area of the external electrodes 121 and 122. The surface area is 45% or more and 90% or less of the area of the capacitor back surface 103. By setting the total surface area of the external electrodes 111, 112, 121, 122 to the area of the capacitor main surface 102 and the capacitor back surface 103 in such a range, the ceramic dielectric layer 105 on the capacitor main surface 102 and the capacitor back surface 103 The exposed area can be reduced. Thus, by reducing the exposed area of the ceramic dielectric layer 105, the adhesion between the capacitor 101 and the resin interlayer insulating layers 33 and 34 can be improved.

  On the capacitor main surface 102, the ground external electrode 112 is formed from the end on the side surface 106a to the end on the side surface 106b side, and from the end on the side surface 106c side to the end on the side surface 106d side. The ground external electrode 112 has a recess 107 formed at the end corresponding to the side surfaces 106a and 106b. On the capacitor back surface 103, the power supply external electrode 121 is formed from the end on the side surface 106a to the end on the side surface 106b and from the end on the side surface 106c side to the end on the side surface 106d side. The power supply external electrode 121 also has a recess 107 at the end corresponding to the side surface 106c.

  The external electrodes 111, 112, 121, and 122 are made of nickel as a main component and contain a ceramic material similar to the ceramic material that constitutes the ceramic dielectric layer 105. By including such a ceramic material in the external electrodes 111, 112, 121, and 122, respectively, the adhesion between the ceramic dielectric layer 105 and the external electrodes 111, 112, 121, and 122 can be enhanced. The external electrodes 111, 112, 121, and 122 may not contain such a ceramic material.

  A first plating film (not shown) is formed on the surfaces of the external electrodes 111, 112, 121, and 122 to improve adhesion with the resin interlayer insulating layers 33 and 34, the via conductors 43, and the like. Yes. The first plating film also has a function of preventing oxidation of the external electrodes 111, 112, 121, and 122. The first plating film is formed by electrolytic plating. Note that the first plating film may be formed by electroless plating. The first plating film is preferably made of a conductive material such as Au or Cu, but more preferably the outermost surface is Cu in order to improve the adhesion with the resin interlayer insulating layers 33 and 34. It is preferable that it is comprised.

  Between the external electrodes 111, 112, 121, 122 and the first plating film, a second for suppressing a decrease in adhesion between the external electrodes 111, 112, 121, 122 and the first plating film. A plating film (not shown) is formed. More specifically, when the external electrode 111, 112, 121, 122 contains a ceramic material as described above, the ceramic material is exposed on the surface of the external electrode 111, 112, 121, 122, and the external electrode 111, 112 is exposed. , 121, 122 and the first plating film may be deteriorated. In order to suppress this, a second plating film is formed. The second plating film is formed by electrolytic plating. The second plating film may be formed by electroless plating as long as it is formed by a plating method.

  The second plating film is preferably made of, for example, the same conductive material as the conductive material that is the main component of the external electrodes 111, 112, 121, and 122. If the external electrodes 111, 112, 121, and 122 to which the ceramic material is added can be directly plated and the adhesion strength is high, the second plating film need not be formed.

  As shown in FIG. 1, the external electrodes 111 and 112 on the capacitor main surface 102 side are connected via the via conductor 43, the conductor layer 42, the terminal pad 44, the solder bump 45, and the surface connection terminal 22 of the IC chip 21. It is electrically connected to the IC chip 21. On the other hand, the external electrodes 121 and 122 on the capacitor back surface 103 side are electrically connected to electrodes of a mother board (not shown) via the via conductor 43, the conductor layer 42, the BGA pad 48 and the solder bump 49. .

  For example, when energization is performed from the mother board side through the external electrodes 121 and 122 and a voltage is applied between the power supply internal electrode layer 141 and the ground internal electrode layer 142, for example, positive charges accumulate in the power supply internal electrode layer 141. For example, negative charges accumulate in the ground internal electrode layer 142. In the ceramic capacitor 101, the via-conductor 131 for power supply capacitor and the via-conductor 132 for ground capacitor are alternately arranged adjacent to each other, and the via-conductor 131 for power-supply capacitor and the via-conductor 132 for ground capacitor are connected to each other. The directions of the flowing currents are set to be opposite to each other. Thereby, the inductance component is reduced.

  The ceramic capacitor 101 of the present embodiment is manufactured, for example, by the following procedure. 9 and 10 are schematic plan views of the ceramic green sheet on which the internal electrode pattern according to the present embodiment is formed, and FIGS. 11, 12, 15, and 17 show the present embodiment. It is a typical longitudinal cross-sectional view of the unbaking ceramic laminated body which concerns. 13, FIG. 14, FIG. 16, and FIG. 18 are schematic plan views of the green ceramic laminate according to the present embodiment. FIG. 19 is a schematic longitudinal sectional view of the ceramic sintered body according to the present embodiment, and FIG. 20 is a schematic plan view showing a plurality of divided capacitor bodies.

  First, a plurality of ceramic green sheets 152 (see FIG. 9) on which internal electrode patterns 151 are formed and ceramic green sheets 154 (see FIG. 10) on which internal electrode patterns 153 are formed are prepared. The internal electrode patterns 151 and 153 are unsintered conductor portions that are to become the internal electrode layers 141 and 142 later. Further, the ceramic green sheets 152 and 154 are unfired ceramic portions that are to become the ceramic dielectric layer 105 later.

  The internal electrode patterns 151 and 153 are formed in the capacitor formation region R, respectively. The capacitor formation region R is a region for forming the capacitor 101, and a plurality of the capacitor green regions 152 and 154 exist. In the drawing, the boundary of the capacitor forming region R is indicated by a two-dot chain line. The internal electrode patterns 151 and 153 are made of nickel paste, for example.

  The internal electrode patterns 151 and 153 are formed in the capacitor formation region R by, for example, screen printing. Further, the internal electrode pattern 151 has a clearance hole 151a (hole) that becomes the clearance hole 134 after firing, and the internal electrode pattern 153 has a clearance hole 153a (hole) that becomes the clearance hole 133 after firing. doing. Further, nickel paste may be applied outside the capacitor forming region R.

  Further, two cover layers 155 and an intermediate layer 156 shown in FIG. 11 are prepared. The cover layer 155 and the intermediate layer 156 are produced by laminating a predetermined number of ceramic green sheets on which the internal electrode patterns 151, 153 and the like are not formed.

  After preparing the ceramic green sheets 152, 154, the cover layer 155, and the intermediate layer 156, the ceramic green sheets 152 and the ceramic green sheets 154 are alternately stacked on the cover layer 155, and the intermediate layer 156 is stacked thereon. . Further, the ceramic green sheets 152 and the ceramic green sheets 154 are alternately stacked on the intermediate layer 156, and the cover layer 155 is stacked thereon. Thereafter, these are pressurized to form an unfired ceramic laminate 159 (see FIG. 11).

  After forming the unfired ceramic laminate 159, a via hole penetrating from the main surface 159a to the back surface 159b of the unfired ceramic laminate 159 is formed, and a conductive paste is pressed into the via hole to form a via conductor paste 157 ( (See FIG. 12 and FIG. 13). Further, the unfired ceramic laminate 159 on which the via conductor paste 157 is formed is pressed by a high pressure press. The via conductor paste 157 is a conductor portion to be the via conductors 131 and 132 later.

  Thereafter, external electrode patterns 160 and 161 connected to the via conductor paste 157 in the capacitor formation region R, for example, by screen printing or the like on the main surface 159a of the unfired ceramic laminate 159 and the back surface 159b opposite to the main surface 159a. (See FIGS. 14 and 15). The external electrode patterns 160 and 161 are conductor portions that should be the external electrodes 111, 112, 121, and 122 later. The external electrode pattern 161 on the main surface 159a side is formed so as to straddle the plurality of capacitor forming regions R, and the external electrode pattern 160 on the back surface 159b side is formed so as to straddle the plurality of capacitor forming regions R.

  In the green ceramic laminate 159, after forming the external electrode patterns 160 and 161 on the main surface 159a and the back surface 159b, a plurality of external electrode patterns 161 penetrating the external electrode pattern 161 along the boundary of the capacitor forming region R by, for example, a laser or the like. A perforated break groove 163 comprising a hole and a continuous line break groove 164 (see FIGS. 16 and 17) are formed (break groove forming step).

  On the main surface 159a side, the break groove 163 is formed at the boundary along the short direction of the main surface 159a in the capacitor formation region R, and the break groove 164 is the boundary along the longitudinal direction of the main surface 159a in the capacitor formation region R. Formed. On the back surface 159b side, the break groove 163 is formed at the boundary along the longitudinal direction of the back surface 159b in the capacitor forming region R, and the break groove 164 is formed at the boundary along the short side direction of the back surface 159b in the capacitor forming region R. The

  As shown in FIG. 17, the depth a of the perforated break grooves 163 with respect to the product thickness is preferably 20 to 70% of the thickness of the entire product. Moreover, it is preferable that the depth b of the continuous linear break groove | channel 164 shall be a / b = 0.25-35. In the present embodiment, the depth a of the break groove 163 is about 50% of the thickness of the entire product, and the depth b of the continuous linear break groove 164 is about 20% of the thickness of the entire product. It is.

  Break groove 164 is formed on main surface 159a and back surface 159b so as to be orthogonal to break groove 163. Here, the break groove 163 formed on the back surface 159b side is formed at a position corresponding to the break groove 164 formed on the main surface 159a side and along the break groove 164 formed on the main surface 159a side. Break groove 164 formed on the back surface 159b side is formed at a position corresponding to break groove 163 formed on the main surface 159a side and along the break groove 163 formed on the main surface 159a side.

  After forming the break grooves 163 and 164 in the unfired ceramic laminate 159, the hole 165 and the thickness that penetrates the unfired ceramic laminate 159 in the thickness direction at the corners of the capacitor formation region R, for example, by a laser or the like A groove 166 extending along the direction is formed (see FIG. 18). These holes 165 and grooves 166 are portions that will later become chamfered portions 104a.

  After forming the hole 165 and the groove 166 in the unfired ceramic laminate 159, the unfired ceramic laminate 159 is degreased and fired at a predetermined temperature for a predetermined time (firing step). As a result, the unfired ceramic laminate 159 is sintered to obtain a ceramic sintered body 168 (capacitor body aggregate) (see FIG. 19). Specifically, the internal electrode patterns 151 and 153, the ceramic green sheets 152 and 154, the via conductor paste 157, and the external electrode patterns 160 and 161 in the unfired ceramic laminate 159 are sintered and the internal electrode layers 141 and 142, Ceramic dielectric layer 105, via conductors 131 and 132, and external electrodes 111, 112, 121, and 122 are formed.

  Thereafter, the oxide films formed on the surfaces of the external electrodes 111, 112, 121, and 122 by polishing are removed by polishing, and then the first and second electrodes are electrolessly or electroplated on the external electrodes 111, 112, 121, and 122. A second plating film is formed.

  And the ceramic sintered body 168 is divided | segmented for every capacitor | condenser formation area R along the break grooves 163 and 164, and the some capacitor | condenser main body 104 (refer FIG. 20) is obtained (division | segmentation process). Here, in the thickness direction of the ceramic sintered body 168, the break groove 164 is formed at a position corresponding to the break groove 163, but the ceramic sintered body 168 has a portion near the break groove 163 at the break groove 164. It is desirable to divide so that it may be cut off before the vicinity. This is because the external electrodes 112 and 122 exist between the break grooves 163, so that when the portion near the break groove 164 is cut off before the portion near the break groove 163, the external electrode 112 near the break groove 163. , 122 may not be cut along the break groove 163.

  After the step of dividing the ceramic sintered body 168, a part of the perforated break groove 163 becomes the recess 107, and a part of the continuous line break groove 164 becomes the notch 108. That is, after the dividing process, the capacitor body 104 is in a state in which the recess 107 and the notch 108 are formed on the side surfaces 106a to 106c that have appeared as break fracture surfaces. On these side surfaces 106a to 106c, the boundary portion 110 between the recess-unformed portion 109 and the recess 107 has an angular shape (see FIG. 21). Further, the surface roughness of the recess-unformed portion 109 is smaller than the surface roughness of the inner wall surface of the recess 107.

  For this reason, in the present embodiment, after the ceramic sintered body 168 is divided, wet blasting is performed to hit the loose abrasive grains in a wet state on the obtained side surface 106 of the capacitor body 104 (surface treatment step). Here, a condition is set such that the loose abrasive grains act on the side surface 106 of the capacitor body 104 while the loose abrasive grains do not act on the capacitor main surface 102 and the capacitor back surface 103, and wet blasting is selectively performed. Do.

  Specifically, as shown in FIGS. 22 and 23, a plurality of capacitor bodies 104 are formed on a stainless plate 180 (SUS plate) as a fixing plate so that the side surface 106 in which the recess 107 is formed is exposed. It fixes using the row | line | column 181 in the state arrange | positioned in the vertical direction. Also, here, dummy sample capacitors 182 are arranged on both sides of each capacitor body 104 so that the capacitor main surface 102 and the capacitor back surface 103 of the capacitor body 104 located at the ends are covered with the dummy sample capacitor 182. To do. Then, wet blasting is performed on the side surface 106 of each capacitor body 104 fixed to the stainless steel plate 180.

  In this wet blasting process, a muddy slurry obtained by uniformly stirring loose abrasive grains 183 and water 184 is used, and the slurry is sprayed from a dedicated spray nozzle 186 using the force of compressed air (see FIG. 23). ). In the present embodiment, the air pressure during blasting is 0.15 MPa. As the free abrasive grains 183, alumina abrasive grains of # 400 (average particle diameter is about 40 μm) are used. Furthermore, the content rate (volume concentration) of the free abrasive grains 183 in the slurry is about 20 vol%. The injection nozzle 186 is a nozzle formed using a tungsten carbide nozzle material, and has a nozzle diameter of 15 mm or less.

  In the present embodiment, the processing time for one side surface 106 of the capacitor body 104 is about 60 seconds. After blasting for 60 seconds, each capacitor body 104 is once removed from the stainless steel plate 180, and the untreated side surface 106 is Each capacitor body 104 is fixed again to the stainless steel plate 180 so as to face upward. Then, wet blasting is performed on the untreated side surface 106.

  In this way, by performing wet blasting on each side surface 106, the angular portion of the boundary portion 110 between the recess-unformed portion 109 and the recess 107 is polished, and the boundary portion 110 becomes rounded. (See FIG. 8). In addition, on the side surfaces 106a to 106c, the boundary portion between the not-formed part of the notch part 108 and the notch part 108 also has a rounded shape.

  Furthermore, by performing wet blasting, the surface of the recess-unformed portion 109 is roughened, and the surface roughness increases. Since the non-recessed portion 109 is a break fracture surface, a shell-like crack may remain. Since the strength of the crack is relatively weak, the crack is removed when the loose abrasive grains 183 collide with each other during the wet blast process. In addition, foreign matters such as smear generated during laser processing adhere to the inner wall surface of the recess 107, but these foreign particles are removed by the contact of the free abrasive grains 183 with the inner wall surface during wet blasting. For this reason, after wet blasting, the surface roughness of the recess-unformed portion 109 and the recess 107 is reduced as compared with the state before the processing.

  Then, after the wet blasting process is completed, each capacitor body 104 is removed from the stainless steel plate 180 and washed. In this cleaning process, the capacitor main bodies 104 are arranged on a cleaning tray, and ultrasonic cleaning is performed using an organic solvent (acetone, isopropyl alcohol, etc.). At this time, the wax 181 adhering to the capacitor main body 104 is melted with the organic solvent, and further, processing waste adhering during the blasting process is removed from the surface of the capacitor main body 104. The ceramic capacitor 101 is manufactured through the above manufacturing process.

  Therefore, according to the present embodiment, the following effects can be obtained.

  (1) In the present embodiment, the surface of the side surfaces 106a to 106d is appropriately roughened by performing wet blasting on the side surface 106 of the capacitor body 104 in the surface treatment step. If the ceramic capacitor 101 is used, the contact area with the resin filler 92 is increased, and the adhesion with the wiring board 10 can be improved. Further, in the wet blasting process, the boundary portion 110 between the recess-unformed portion 109 and the recess 107 on the side surfaces 106a to 106c of the capacitor main body 104 is shaved so that the boundary portion 110 has a rounded shape. Therefore, when the ceramic capacitor 101 is built in the wiring substrate 10, the stress applied to the boundary portion 110 between the recess-unformed portion 109 and the recess 107 is dispersed, and the problem that a crack is generated on the resin filler 92 side can be avoided. it can.

  (2) In the ceramic capacitor 101 of the present embodiment, the surface of the concave portion 107 on the side surfaces 106a to 106c is a processed surface subjected to laser processing, and thus is roughened by laser processing. Therefore, the surface roughness of the recess-unformed portion 109 on the side surface 106 is smaller than the surface roughness of the inner wall surface of the recess 107 before the surface treatment process. Then, after the surface treatment step, the surface of the recess-unformed portion 109 is roughened, and the difference in surface roughness between the two portions 107 and 109 is reduced. As described above, by roughening the surface of the recess-unformed portion 109, sufficient adhesion with the resin filler 92 can be ensured.

  (3) In the surface treatment process of the present embodiment, wet is performed using loose abrasive grains 183 having an average particle size (specifically 40 μm) smaller than the maximum width (specifically, 100 μm) of the recess 107. Blasting is performed. In this way, since the loose abrasive grains 183 reliably hit the inner wall surface of the recess 107, the inner wall surface of the recess 107 can be reliably roughened, and smear adhered to the inner wall surface of the recess 107 during laser processing. It is possible to reliably remove foreign matters such as. For this reason, the adhesiveness of the inner wall surface of the recessed part 107 and the resin filler 92 can fully be improved.

  (4) In the present embodiment, the air pressure at the time of blasting is 0.15 MPa, and wet blasting is performed at an appropriate air pressure, so that the side surface 106 can be roughened efficiently and quickly.

  (5) In the present embodiment, on the stainless steel plate 180, the capacitor body 104 is fixed in a state where a plurality of capacitor main bodies 104 are arranged in the thickness direction so as to expose the side surfaces 106a to 106c in which the recesses 107 are formed. After that, wet blasting is performed on the side surface 106 of the capacitor body 104. In this way, wet blasting can be simultaneously performed on the plurality of capacitor main bodies 104, and each side surface 106 can be efficiently and reliably roughened. Further, since the stainless steel plate 180 used as the fixing plate is a hard metal plate, the stainless steel plate 180 is not damaged even if the loose abrasive grains 183 collide with each other during wet blasting. Further, even if the stainless steel plate 180 is heated when being fixed by the solder 181, the capacitor main body 104 can be reliably fixed without being deformed.

(6) In the present embodiment, the capacitor body 104 is fixed on the stainless steel plate 180 using the wax 181. Since the solder 181 melts at a relatively low temperature and hardens at room temperature, the plurality of capacitor bodies 104 can be easily fixed on the stainless steel plate 180. Further, since the hardened wax 181 is softer than the capacitor main body 104, damage due to wet blasting is small, and the capacitor main body 104 can be securely fixed during the processing. Further, since the wax 181 is easily dissolved by the organic solvent, the wax 181 adhering to the capacitor main body 104 can be easily removed by washing with the organic solvent after the wet blast processing.
[Second Embodiment]

  Next, a second embodiment that embodies this embodiment will be described with reference to the drawings. The ceramic capacitor according to the present embodiment is different from the first embodiment in that a dummy internal electrode that is electrically independent from the internal electrode is formed on the capacitor body. 24 and 25 are schematic side views of the ceramic capacitor 101A of the present embodiment, and FIG. 26 is a schematic longitudinal sectional view of the ceramic capacitor 101A. In the present embodiment, the same components as those in the first embodiment are denoted by the same reference numerals. Hereinafter, the difference from the first embodiment will be mainly described.

  As shown in FIGS. 24 to 26, dummy electrode layers 171 and 172 (dummy internal electrodes) that do not function as electrodes are arranged in the capacitor main body 104. Specifically, the dummy electrode layers 171 and 172 are disposed between the ceramic dielectric layers 105 and on the outer peripheral side of the ceramic dielectric layer 105 (that is, from the side surface 106) than the internal electrode layers 141 and 142. Are arranged at predetermined intervals.

  The dummy electrode layer 171 is disposed on the same plane as the internal electrode layer 141, and the dummy electrode layer 172 is formed on the same plane as the internal electrode layer 142. That is, the dummy electrode layer 171 is disposed between the same ceramic dielectric layer 105 where the internal electrode layer 141 is disposed, and the dummy electrode layer 172 is disposed between the ceramic dielectric layer 105 where the internal electrode layer 142 is disposed. Are arranged between the same layers. The dummy electrode layers 171 and 172 may be formed between layers different from the ceramic dielectric layer 105 where the internal electrode layers 141 and 142 are disposed.

  The internal electrode layer 141 and the dummy electrode layer 171, and the internal electrode layer 142 and the dummy electrode layer 172 are electrically insulated from each other. The ceramic dielectric layer 105 enters the gaps S1 and S2 between the internal electrode layers 141 and 142 and the dummy electrode layers 171 and 172, respectively, and the internal electrode layers 141 and 142 and the dummy electrode layers 171 and 172 Are electrically insulated.

  The gap S1 between the internal electrode layer 141 and the dummy electrode layer 171 and the gap S2 between the internal electrode layer 142 and the dummy electrode layer 172 are in a positional relationship shifted in the thickness direction of the capacitor body 104, There is no overlap. The gaps S1 between the internal electrode layer 141 and the dummy electrode layer 171 are aligned in the thickness direction of the capacitor body 104, and the gaps S2 between the internal electrode layer 142 and the dummy electrode layer 172 are respectively The capacitor body 104 is aligned in the thickness direction.

  The dummy electrode layers 171 and 172 are formed so as to surround the internal electrode layers 141 and 142. Further, on the side surfaces 106 a to 106 d of the capacitor body 104, the outer peripheral ends of the dummy electrode layers 171 and 172 are exposed from between the ceramic dielectric layers 105. Therefore, the side surfaces 106a to 106d are composed of the ceramic dielectric layer 105 and the dummy electrode layers 171 and 172. Note that the side surfaces of the recess 107 and the cutout portion 108 in the side surfaces 106a to 106c are also composed of the ceramic dielectric layer 105 and the dummy electrode layers 171 and 172.

  In consideration of relaxation of the step formed near the end of the ceramic capacitor 101A, it is preferable that all the outer peripheral ends of the dummy electrode layers 171 and 172 are exposed from between the ceramic dielectric layers 105. Only the outer peripheral edge may be exposed.

  The total number of dummy electrode layers 171 and 172 is preferably at least half (about 50 layers) of the total number of internal electrode layers 141 and 142 in consideration of the relief of the step formed near the end of ceramic capacitor 101A. More preferably, the total number of internal electrode layers 141 and 142 is approximately the same (about 100 layers).

  Although the dummy electrode layers 171 and 172 are made of a conductive material, the conductive material constituting the dummy electrode layers 171 and 172 is determined in consideration of the influence during the firing of the ceramic green sheets 152 and 154 and the formation process. The same material as the conductive material constituting the internal electrode layers 141 and 142 is preferable. For the same reason, the thicknesses of the dummy electrode layers 171 and 172 are preferably substantially the same as the thicknesses of the internal electrode layers 141 and 142 (for example, 2 μm or less).

  Also in the present embodiment, a plurality of capacitor main bodies 104 are manufactured by dividing a ceramic sintered body 168 having a plurality of capacitor forming regions R. In the present embodiment, since the dummy electrode layers 171 and 172 are provided, the strength of the ceramic sintered body 168 is increased. Therefore, the depth of the perforated break grooves 163 with respect to the product thickness is set to 70% of the thickness of the entire product, and the ceramic sintered body 168 is surely divided in the dividing step. Accordingly, the length of the recess 107 formed in the present embodiment, the side surfaces 106 a to 106 c is half or more of the thickness of the capacitor body 104. That is, the recess 107 is formed on the side surface of the capacitor body 104 so as to extend beyond the intermediate layer portion 145.

  Also in the capacitor main body 104 of the present embodiment, a surface treatment process by wet blasting is performed as in the first embodiment. As a result, on the side surfaces 106a to 106c, the boundary portion 110 between the recess-unformed portion 109 and the recess 107 has a rounded shape. Furthermore, the outer peripheral ends of the dummy electrode layers 171 and 172 exposed at the recess-unformed portion 109 and the boundary portion 110 are crushed by wet blasting to cover the recess-unformed portion 109 and the boundary portion 110.

  On the other hand, in the recess 107, the dummy electrode layers 171 and 172 are pulled down from the inner wall surface (see FIG. 27). The inner wall surface of the recess 107 is a portion that is laser-processed by the unfired ceramic laminate 159, and the end portions of the dummy electrode layers 171 and 172 are pulled down during the laser processing. Further, since the conductive material constituting the dummy electrode layers 171 and 172 has a larger shrinkage rate than the ceramic green sheets 152 and 154, the outer periphery of the dummy electrode layers 171 and 172 is caused by the difference in shrinkage rate during firing. The end is located on the inner side of the inner wall surface of the recess 107. Therefore, in the present embodiment, when the capacitor main body 104 is viewed from the side, the coverage ratio of the dummy electrode layers 171 and 172 in the recess-unformed portion 109 and the boundary portion 110 is higher. It becomes larger than the coverage.

  Therefore, according to the present embodiment, the following effects can be obtained.

  (1) Also in the ceramic capacitor 101A of the present embodiment, the surface of the side surfaces 106a to 106d is appropriately roughened by performing wet blasting on the side surface 106 of the capacitor body 104 in the surface treatment step. . Therefore, when the ceramic capacitor 101A is used, the contact area with the resin filler 92 is increased, and the adhesion with the wiring board 10 can be improved. Further, in this embodiment, the concave portion 109 and the boundary portion 110 are partially covered with a part of the dummy electrode layers 171 and 172. Furthermore, the coverage of the dummy electrode layers 171 and 172 in the recess-unformed portion 109 and the boundary portion 110 is larger than the coverage of the dummy electrode layers 171 and 172 on the inner wall surface of the recess 107. As described above, the dummy electrode layers 171 and 172 cover the recess-unformed portion 109 and the boundary portion 110, so that the strength of the portions can be increased. Therefore, even when stress is concentrated on the boundary portion 110 between the recess-unformed portion 109 and the recess 107 when the ceramic capacitor 101 is built in the wiring board 10 or when the resin filler 92 is deformed due to a temperature change, It is possible to avoid the problem that a portion of the ceramic is missing, and to sufficiently secure the adhesion to the resin filler 92.

  (2) In this embodiment, since the dummy electrode layers 171 and 172 are formed on the outer peripheral side of the ceramic dielectric layer 105 from the internal electrode layers 141 and 142, the thickness of the end portion of the capacitor body 104 is increased. Thus, it is possible to provide the ceramic capacitor 101A in which the step formed near the end portion is relaxed. When the ceramic capacitor 101A is built in the wiring board 10, when the resin filler 92 is filled in the gap between the core substrate 11 and the capacitor 101, the resin filler 92 is less likely to sink into the back surface 103 side of the capacitor 101A. As a result, defects in the build-up process for forming the build-up layers 31 and 32 can be reduced.

  (3) In the present embodiment, gaps S1 and S2 are formed between the internal electrode layers 141 and 142 and the dummy electrode layers 171 and 172. Here, when the gap S1 between the internal electrode layer 141 and the dummy electrode layer 171 and the gap s2 between the internal electrode layer 142 and the dummy electrode layer 172 overlap in the thickness direction of the capacitor body 104. In the thickness direction of the capacitor body 104, there are portions where both the internal electrode layers 141 and 142 and the dummy electrode layers 171 and 172 do not exist. Since the internal electrode layers 141 and 142 and the dummy electrode layers 171 and 172 do not exist in such a portion, the thickness becomes thinner than other portions, and a locally recessed shape is obtained. If the dent is formed at a location relatively close to the outer periphery of the capacitor, the resin filler 92 may sink into the capacitor back surface 103 side. On the other hand, in the present embodiment, the gap S1 between the internal electrode layer 141 and the dummy electrode layer 171 and the gap S2 between the internal electrode layer 142 and the dummy electrode layer 172 are included in the ceramic dielectric layer 105. Since they do not overlap in the stacking direction, it is difficult to form such local dents, and the resin filler 92 can be prevented from entering.

  In addition, you may change each embodiment of this invention as follows.

  In each of the above embodiments, in the surface treatment step, the plurality of capacitor main bodies 104 are fixed on the stainless steel plate 180 with the wax 181 to perform the wet blasting. However, the present invention is not limited to this. For example, the internal electrode layers 141 and 142 and the dummy electrode layers 171 and 172 formed on the capacitor main body 104 are mainly made of nickel, which is a magnetic material. Therefore, the capacitor main body 104 is fixed using a magnet and wetted. You may comprise so that blast processing may be performed.

  In each of the above embodiments, in each of the side surfaces 106a to 106c of the capacitor body 104, the concave portion 107 is formed on one of the capacitor main surface 102 and the capacitor back surface 103, and the notch portion 108 is formed on the other side. It is not limited to this. For example, a recess 107 extending from the capacitor main surface 102 to the capacitor back surface 103 may be formed on the side surface 106 of the capacitor main body 104 as in a ceramic capacitor 101B shown in FIG. In the present embodiment, notch 108 is not formed. Further, in the ceramic capacitor 101B of FIG. 28, the dummy electrode layers 171 and 172 are not disposed, but the dummy electrode layers 171 and 172 may be disposed. Also in this ceramic capacitor 101B, the side surface 106 is subjected to wet blasting, so that the surface of the recess-unformed portion 109 and the inner wall surface of the recess 107 are roughened. Further, the boundary portion 110 between the recess-unformed portion 109 and the recess 107 on the side surface 106 has a rounded shape. Even if the ceramic capacitor 101B is configured in this manner, the adhesion to the wiring board 10 can be improved. Further, since the stress applied to the boundary portion 110 is dispersed, it is possible to avoid a problem that a crack is generated on the resin filler 92 side.

  In the ceramic capacitors 101, 101 </ b> A, 101 </ b> B of the above embodiments, the external electrodes 111, 122 are formed in a substantially circular shape, and the external electrodes 112, 121 are solid having a circular punch pattern around the external electrodes 111, 122. Although formed to be a pattern, the shape of the external electrodes 111, 112, 121, 122 can be changed as appropriate. FIG. 29 shows a modification of the external electrode. In the ceramic capacitor 101C shown in FIG. 29, the power supply external electrode 111 is a belt-like pattern having a substantially rectangular shape in plan view, and four power supply external electrodes 111 are arranged in parallel to each other on the capacitor main surface 102. Yes. The ground external electrode 112 is disposed so as to surround each power supply external electrode 111.

  The power supply external electrode 111 is directly connected to the end faces of the plurality of power supply capacitor via conductors 131. The ground external electrode 112 is directly connected to the end faces of the plurality of ground capacitor via conductors 132. Although not shown, on the capacitor back surface 103 side, the ground external electrode 122 connected to the ground capacitor internal via conductor 132 is a belt-like pattern having a substantially rectangular shape in plan view. On the capacitor back surface 103 side, the power supply external electrode 121 connected to the power supply capacitor internal via conductor 131 is a wide area pattern formed in a plain shape so as to surround each power supply external electrode 111.

  Next, in addition to the technical ideas described in the claims, the technical ideas grasped by the respective embodiments described above are listed below.

  (1) A first main surface, a second main surface located on the opposite side of the first main surface, a side surface located between the first main surface and the second main surface, and an internal electrode and a ceramic A capacitor body having a multilayered structure in which dielectric layers are laminated is provided, and the ceramic constituting the ceramic dielectric layer is exposed on the side surface of the capacitor body, and the first main surface and the second main surface are exposed. A method of manufacturing a wiring board built-in capacitor in which a plurality of recesses extending in the thickness direction of the capacitor body from at least one side of a main surface is formed, the capacitor body in a state where the recesses are formed A surface treatment step of performing wet abrasive grain processing on the side surface, and the surface roughness of the recess-unformed portion on the side surface is smaller than the surface roughness of the inner wall surface of the recess before the surface treatment step. The method of manufacturing a wiring board built capacitor which is characterized in that the difference in surface roughness of the two parts the recess unformed portion and undergoes the surface treatment step is roughened is reduced.

  (2) In the technical idea (1), the average particle size of the free abrasive grains used in the wet abrasive grain processing is 8 μm or more and 200 μm or less.

  (3) In the technical idea (1) or (2), the capacitor main body is plate-shaped, and in the surface treatment step, the capacitor main body is made thick so as to expose the side surface on which the concave portion is formed. A plurality of capacitors are stacked in the vertical direction, and dummy sample capacitors are arranged so as to cover the main surfaces located at the ends of the capacitor bodies, and the side surfaces of the capacitor bodies are processed. A method of manufacturing a capacitor for wiring board built-in.

DESCRIPTION OF SYMBOLS 101,101A-101C ... Ceramic capacitor as a capacitor | condenser for wiring board built-in 102 ... Capacitor main surface as 1st main surface 103 ... Capacitor back surface as 2nd main surface 104 ... Capacitor main body 105 ... Ceramic dielectric layer 106, 106a- 106d ... Side face 107 ... Concave 109 ... Concave not formed part 151, 153 ... Internal electrode pattern as unfired conductor part 152, 154 ... Ceramic green sheet as unfired ceramic part 159 ... Unsintered ceramic laminate 163 ... Break groove 168 ... Ceramic sintered body as a capacitor body aggregate 180 ... Stainless steel plate as a fixed plate 181 ... Wax 183 ... Free abrasive grains

Claims (5)

A first main surface, a second main surface located on the opposite side of the first main surface, a side surface located between the first main surface and the second main surface, and an internal electrode and a ceramic dielectric layer the laminated with a plate-shaped capacitor body having a multilayered structure, the side surface of the capacitor body, together with the ceramic is exposed constituting the ceramic dielectric layer, wherein the first main surface and the second A method of manufacturing a wiring board built-in capacitor in which a plurality of recesses extending in the thickness direction of the capacitor body from at least one side of two main surfaces are formed,
While fixing the plurality of capacitor bodies in a state of being stacked in the thickness direction so as to expose the side surface in which the recess is formed, free abrasive grains act on the side surface. A surface treatment step of performing wet abrasive machining on the side surface of the capacitor main body after setting conditions under which free abrasive grains do not act on the first main surface and the second main surface; Method for manufacturing a built-in wiring board capacitor. A laminated body production step of producing an unfired ceramic laminate having a multilayered structure by laminating an unfired conductor part to be the internal electrode later and an unfired ceramic part to be the ceramic dielectric layer later;
A break groove forming step for forming a break groove formed by arranging a plurality of holes to be a part of the concave portion in the perforated shape in the unfired ceramic laminate,
A firing step of sintering the green ceramic laminate to obtain a capacitor body assembly having the internal electrode and the ceramic dielectric layer;
By dividing the capacitor body aggregate along the break groove, a plurality of capacitor bodies are obtained, and a dividing step is sequentially performed in which the concave portions are formed on the side surface that appears as a break fracture surface. The method for manufacturing a capacitor for a wiring board according to claim 1, wherein the surface treatment step is performed thereafter.   3. The wiring board built-in capacitor according to claim 1, wherein in the surface treatment step, wet abrasive grain processing is performed using loose abrasive grains having an average grain size smaller than a maximum width of the concave portion. Production method.   4. The wiring board built-in capacitor according to claim 1, wherein the wet abrasive processing is wet blasting, and an air pressure at the time of blasting is 0.05 MPa or more and 0.6 MPa or less. Manufacturing method. In the surface treatment step, in a state of exposing the at least one of said sides, to any one of claims 1 to 4 characterized by securing the plurality of the capacitor body on the fixed plate with wax The manufacturing method of the capacitor | condenser for wiring board description of description.

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