JP2005183466A - Multilayer printed wiring board - Google Patents

Multilayer printed wiring board Download PDF

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Publication number
JP2005183466A
JP2005183466A JP2003418162A JP2003418162A JP2005183466A JP 2005183466 A JP2005183466 A JP 2005183466A JP 2003418162 A JP2003418162 A JP 2003418162A JP 2003418162 A JP2003418162 A JP 2003418162A JP 2005183466 A JP2005183466 A JP 2005183466A
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layer
conductor
hole
core substrate
conductor layer
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Shinobu Kato
忍 加藤
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Ibiden Co Ltd
イビデン株式会社
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Abstract

PROBLEM TO BE SOLVED: To propose a multilayer printed wiring board in which malfunction or error does not occur even if it exceeds 3 GHz.
SOLUTION: A distance D1 between a conductor layer 34P on the surface of a multilayer core substrate 30 and an inner conductor layer 16E, a distance D2 between the inner conductor layer 16E and the metal plate 12, and a metal plate 12 and an inner conductor layer 16P. And the distance D4 between the inner conductor layer 16P and the back conductor layer 34E are made uniform. By arranging the conductor layer and the metal plate so that the distances are uniform, the mutual inductance between the conductor layer and the metal plate is made constant, and the inductance of the core substrate 30 as a whole is lowered.
[Selection] Figure 8

Description

  The present invention relates to a multilayer printed wiring board, and improves electrical characteristics and reliability without causing malfunction or error even when a high-frequency IC chip, particularly an IC chip in a high-frequency region of 3 GHz or more is mounted. The present invention relates to a multilayer printed wiring board which can

  In the build-up type multilayer printed wiring board constituting the IC chip package, as shown in FIG. 19, a conductor circuit 34, a conductor layer 34P are provided on the upper surface of the core substrate 30 provided with the through holes 36, and a conductor circuit 34 is provided on the rear surface. A conductor layer 34E is formed. The upper conductor layer 34P is formed as a power source plane layer, and the lower conductor layer 34E is formed as a ground plane layer. On the conductor layers 34P and 34E on the surface of the core substrate 30, the interlayer insulating layer 50 in which the via hole 60 and the conductor circuit 58 are formed, and the interlayer insulating layer 150 in which the via hole 160 and the conductor circuit 158 are formed. It is arranged. A solder resist layer 70 is formed on the via hole 160 and the conductor circuit 158, and bumps 76 U and 76 D are formed on the via hole 160 and the conductor circuit 158 through the opening 71 of the solder resist layer 70. ing. An IC chip (not shown) is electrically connected by performing C4 (flip chip) mounting on the bump 76U.

  As conventional techniques of such a build-up type multilayer printed wiring board, there are Patent Document 1, Patent Document 2, and the like. Both lands are formed on the core substrate filled with the filling resin with through holes, an interlayer insulating layer having via holes on both sides is applied, a conductor layer is applied by an additive method, and connected to the lands, A multilayer printed wiring board on which high density and fine wiring are formed can be obtained.

JP-A-6-260756 JP-A-6-275959

However, the generated noise has become higher as the IC chip becomes higher in frequency. In particular, since the frequency exceeds 3 GHz, the degree is increasing. Further, the tendency is further increased when the frequency exceeds 5 GHz.
For this reason, a desired function cannot be performed due to a delay such as an operation that should be performed (for example, image recognition, switch switching, transmission of data to the outside, etc.).
If you want to perform nondestructive inspection or disassembly of an IC chip or board that cannot perform the desired function, the IC chip and board itself are free from problems such as short circuits and open circuits, and have a low frequency (particularly less than 1 GHz). When the chip was mounted, there was no malfunction or error.

  That is, the high-frequency IC chip enables high-speed computation while suppressing heat generation by intermittently increasing or decreasing the power consumption. For example, even though it is usually about several watts, it consumes several tens of watts of power instantaneously. When the power consumption of this tens of watts is high, if the impedance of the power line of the package substrate is high, it is considered that the supply voltage is lowered at the rise of the power that increases consumption, causing malfunction.

  The object of the present invention is to propose an IC chip in a high frequency region, in particular, a multilayer printed wiring board or a package substrate that does not cause malfunction or error even if it exceeds 3 GHz.

As a result of intensive research aimed at realizing the above object, the inventors have come up with an invention having the following contents as a gist. That is, an interlayer insulation layer and a conductor layer are formed on both sides or one side on a multilayer metal core substrate having a plurality of through holes and comprising a plurality of insulation layers and a conductor layer. In multilayer printed wiring boards to be connected,
A technical feature is that each insulating layer of the multilayer metal core substrate has a uniform thickness.

The thickness of each insulating layer of the multilayer metal core substrate is made uniform. Thereby, by arranging the thickness of each insulating layer of the multilayer metal core substrate uniformly, the mutual inductance between the conductor layer and the metal plate can be made constant, and the inductance of the entire core substrate can be reduced.
Further, by using the conductor layer as the power supply layer, the power supply capability to the IC chip can be improved. By using the conductor layer as the ground layer, it is possible to reduce the signal superimposed on the signal to the IC chip and the noise superimposed on the power supply. That is, the reduction of the inductance of the conductor layer does not hinder the supply of power. Therefore, when an IC chip is mounted on the multilayer printed board, the loop inductance from the IC chip to the board to the power source can be reduced. For this reason, the shortage of power supply in the initial operation is reduced, so that the shortage of power supply is less likely to occur. Therefore, even if an IC chip in a high frequency region is mounted, malfunctions and errors at the initial start-up are not caused. Moreover, by using a multilayer metal core substrate, the area of the conductor layer can be increased as compared with a conventional double-sided core substrate. Furthermore, if the conductor layer is used as a power supply layer or a ground layer, the area of each conductor layer can be increased. Therefore, the factor that inhibits the resistance is reduced, and the electrical characteristics are improved.

  Moreover, it is desirable that the adjacent conductor layers of the multilayer metal core substrate are an array of a power supply layer conductor layer and a ground conductor layer. For example, if the conductor layer on the surface is a conductor layer for power supply, the first conductor layer on the adjacent inner layer is a ground layer, and if the second conductor layer on the inner layer is a conductor layer for power supply, The conductor layer on the back surface is preferably a ground layer. By arranging the power supply layer and the ground adjacent to each other, the directions of the induced electromotive forces generated in the respective layers are made opposite to each other, and each induced electromotive force is canceled out. Therefore, noise is reduced and the function as a substrate does not deteriorate. In addition, malfunctions and delays are eliminated. In other words, the mutual inductance can be reduced. At this time, the distance between the two conductor layers is preferably as short as possible. That is, the relative inductance can be reduced by shortening the distance.

  The conductor layer adjacent to the power supply layer (or ground layer) is preferably a ground layer (or power supply layer), and another ground layer (or power supply layer) is preferably disposed on the other conductor layer. By arranging the conductor layer of the power supply layer and the conductor layer of the ground layer, the inductance of the entire core substrate can be reduced.

  The thickness of the insulating layer of the multilayer metal core substrate is preferably 15 to 300 μm. If the thickness is less than 15 μm, it is difficult to maintain insulation, causing problems in electrical connectivity. If the thickness is 300 μm or more, the multilayer metal core substrate becomes thick, the through hole becomes long, and the inductance in the through hole increases. In addition, the relative inductance decrease at the distance between the conductor layers is canceled out, and the effect does not appear. More preferably, the thickness of the insulating layer is 30 to 250 μm. This is because the inductance can be reduced and the insulation between the conductor circuits can be ensured during that time.

  In this case, it is desirable to increase the conductor thickness of the ground (GND) layer and the conductor thickness of the power supply (VCC) layer formed on the core substrate. The thickness is desirably over 25 μm. In particular, the thickness of the conductor layer of the core substrate is more desirably thicker than the thickness of the conductor layer on the interlayer insulating layer.

Increasing the thickness of the conductor layer of the core substrate increases the strength of the core substrate by increasing the thickness of the conductor layer of the power source layer of the core substrate. Can be relaxed by the substrate itself.
In addition, the volume of the conductor itself can be increased. By increasing the volume, the resistance in the conductor can be reduced. For this reason, electrical transmission such as a flowing signal line is not hindered. Therefore, no loss occurs in the transmitted signal. This is achieved by increasing the thickness of only the substrate serving as the core.
Furthermore, the ability to supply power to the IC chip can be improved by using the conductor layer as the power supply layer. In addition, by using the conductor layer as a ground layer, it is possible to reduce a signal to the IC chip and noise superimposed on the power source. That is, the reduction in the resistance of the conductor does not hinder the supply of power. Therefore, when an IC chip is mounted on the multilayer printed board, the loop inductance from the IC chip to the board to the power source can be reduced. For this reason, the shortage of power supply in the initial operation is reduced, so that the shortage of power supply is less likely to occur. Therefore, even if an IC chip in a high frequency region is mounted, malfunctions and errors at the initial start-up are not caused.
The same effect can be obtained when power is supplied to the IC chip via the IC chip to the substrate to the capacitor or the power supply layer to the power source. The aforementioned loop inductance can be reduced.

  In particular, when the thickness of the conductor layer used as the power supply layer of the core substrate is thicker than the thickness of the conductor layer on the interlayer insulating layer on one or both sides of the core substrate, the above effect can be maximized. is there. In this case, the conductor layer on the interlayer insulating layer is a via hole that is a non-through hole for connecting the layers in the interlayer insulating layer formed of a resin not impregnated with the core material in the insulating layer. It mainly means a conductor layer formed by plating, sputtering or the like. Other than this, there is no particular limitation, but any via hole formed corresponds to the above conductor layer.

  The power supply layer of the core substrate may be disposed on the surface layer, the inner layer, or both of the substrate. In the case of the inner layer, it may be multi-layered over two or more layers. Basically, if the power layer of the core substrate is thicker than the conductor layer of the interlayer insulating layer, the effect is obtained. However, it is desirable to form in the inner layer.

The thickness of the conductor layer of the core substrate is preferably α1, and the thickness of the conductor layer on the interlayer insulating layer is preferably α2 <α1 ≦ 40α2.
In the case of α1 ≦ α2, there is no effect on power shortage. In other words, it is not clear to suppress the degree of voltage drop that occurs during initial operation.
The case where α1> 40α2 was also examined, but basically the electrical characteristics are almost equivalent to 10α2. In other words, it can be understood as a critical point of effect. Even if it is thicker than this, an improvement in electrical effect cannot be expected. However, if this thickness is exceeded, when a conductor layer is formed on the surface layer of the core substrate, it becomes difficult to form lands or the like for connection with the core substrate. Further, when the upper interlayer insulating layer is formed, the unevenness becomes large, and the interlayer insulating layer is swelled, so that impedance cannot be matched.

  The thickness α1 of the conductor layer is more preferably 1.2α2 ≦ α1 ≦ 20α2. Within this range, it has been confirmed that no malfunction or error of the IC chip occurs due to power shortage (voltage drop). In the multilayer metal core substrate, it is preferable that the thickness of the inner conductor is thicker than the thickness of the surface conductor. Since the effect on the power shortage is the sum of the conductor layers, it can be eliminated by increasing the thickness of the surface conductor layer. However, if the surface conductor layer is thickened, it is difficult to form lands or the like that are connected to the multilayer metal core substrate when the conductor layer is formed on the surface layer of the multilayer metal core substrate. Further, when the upper interlayer insulating layer is formed, the unevenness becomes large, and the interlayer insulating layer is swelled, so that impedance cannot be matched.

  In the multilayer metal core substrate, it is preferable that two GND layers or VCC layers are formed, and a VCC layer or GND layer is formed between the layers. Further, the distances between the GND layer (or the VCC layer) and the VCC layer (or the GND layer) are preferably uniform. Thereby, since the action of reducing both inductances works uniformly, it is easy to lower the overall inductance. Furthermore, impedance matching can be easily achieved and electrical characteristics can be improved.

  The distance between the GND layer and the VCC layer (the thickness of the insulating layer) is preferably between 15 and 300 μm. If the thickness is less than 15 μm, it is difficult to ensure insulation regardless of the material, and if a reliability test such as heat cycle is performed, a short circuit may occur between the conductor layers. If it exceeds 300 μm, the effect of reducing the inductance is reduced. That is, the effect of mutual inductance is canceled out because the distance is long. More preferably, the distance between the GND layer and the VCC layer is between 30 and 250 μm. This is because the inductance can be reduced and the insulation between the conductor circuits can be ensured during this period.

  Both the GND layer and the VCC layer are preferably thicker conductor layers. This is because the effect of reducing the resistance value can be easily obtained by increasing both volumes. The thickness of the conductor is preferably 25 to 300 μm. If it is less than 25 μm, the effect of reducing the resistance value tends to be thin. If it exceeds 300 μm, the conductor circuit such as a signal line formed on the upper layer may be swelled, causing a problem in terms of impedance matching. The demand for thinning the substrate itself cannot be answered because the substrate itself becomes thicker.

  The material of the core substrate was verified with a resin substrate, but it was found that the same effect was obtained with a ceramic substrate. In addition, although the conductor layer was made of a metal made of copper, it has not been confirmed that other metals offset the effect and increase the number of malfunctions and errors. The difference or the difference in the material forming the conductor layer seems not to have an effect on the effect. More preferably, the conductor layer of the core substrate and the conductor layer of the interlayer insulating layer are formed of the same metal. This effect can be achieved because characteristics such as electrical characteristics and thermal expansion coefficient and physical properties do not change.

  Furthermore, the through holes of the multilayer metal core substrate have two or more ground through holes and two or more power supply through holes, which are arranged in a grid or zigzag at adjacent positions. Is desirable.

  A ground (or power supply) is arranged at each diagonal position, and a power supply (or ground) is arranged at other positions. With this configuration, the induced electromotive force is canceled in the X direction and the Y direction.

A ground (or power supply) is arranged at each diagonal position, and a power supply (or ground) is arranged at other positions. With this configuration, the induced electromotive force is canceled in the X direction and the Y direction.
This will be described with reference to FIG. 11 (A) schematically showing an example in which through holes are arranged in a lattice pattern. In the through holes arranged in a grid pattern, the power supply through holes VCC1 and VCC2 are arranged at equal intervals of the ground through hole GND1, and the power supply through hole GND2 is arranged on the diagonal line of the ground through hole GND1. Make it. By adopting this four-core (quad) structure, the induced electromotive force generated by two power supply through holes VCC (or ground through holes GND) is reduced with respect to one ground through hole GND (or power supply through hole VCC). It will be countered. Therefore, the mutual inductance in the through hole can be reduced and is not affected by the induced electromotive force, so that malfunctions and delays are less likely to occur.

  Further, description will be made with reference to FIG. 11B schematically showing an example in which the through holes are arranged in a staggered pattern. In the through holes arranged in a staggered manner, the ground through holes GND2 and GND3 are arranged at equal intervals with the ground through hole GND1, and the power supply through holes VCC1 and VCC2 are arranged at the same distance as the ground through hole GND2. Is disposed. With this structure, the induced electromotive force is canceled by the two power supply through holes VCC (or ground through hole GND) with respect to one ground through hole GND (or power supply through hole VCC). Therefore, the mutual inductance of the through holes can be reduced and is not affected by the induced electromotive force, so that malfunctions and delays are less likely to occur.

  Arranging in a grid pattern can lower the inductance than arranging in a staggered pattern. Even when two or more of the same number of ground through holes and power supply through holes are arranged, a maximum of 4 for one ground through hole GND (or power supply through hole VCC) can be obtained by using a lattice. The locations can be arranged at equal intervals, and the opposite power supply through-holes VCC can be arranged at the same maximum four locations at equal intervals to cancel the induced electromotive force in each case. It can be lowered.

  Originally, the ground through hole GND and the power supply through hole VCC are easily affected by a magnetic field or the like. For this reason, when the frequency and speed of the IC chip are increased, the inductance increases, which causes a problem in the operation as a substrate. Therefore, it is necessary to consider an arrangement for suppressing the influence of the inductance of the ground through hole GND and the power supply through hole VCC. For example, in order to meet the demand for higher density (higher density, fine wiring), it is not necessary to simply arrange the through holes narrowly. Arranging as described above can reduce the respective inductances.

  The distance between the ground through hole and the power through hole (pitch shown in FIG. 11C: the distance between the center of the ground through hole GND and the center of the power through hole VCC) is between 60 and 600 μm. It is desirable that By reducing the distance between the through hole and the wall of the through hole, the mutual inductance can be reduced. At this time, when the thickness is less than 60 μm, an insulation gap between the through holes cannot be secured, and a short circuit or the like is caused. In addition, due to an insulation gap or the like, it may be difficult to set the mutual inductance within the design allowable range. The effect of reducing the mutual inductance exceeding 600 μm is reduced. If it is between 60-550 micrometers, an insulation gap can be ensured with a through hole, a mutual inductance can be reduced, and an electrical property can be improved.

The diameter of the through hole for grant (the outer diameter of the through hole shown in FIG. 11C) is 50 to 500 μm, and similarly, the diameter of the through hole for power supply is preferably 50 to 500 μm.
If it is less than 50 μm, it tends to be difficult to form a conductor layer in the through hole. In addition, the self-inductance is increased.
If it exceeds 500 μm, the amount of self-inductance per line can be reduced, but the number of ground lines and power supply lines that can be arranged in a limited area is reduced, and the total number of ground lines and power supply lines is increased. Inductance cannot be reduced. This is because, particularly when arranged in a lattice or zigzag pattern, defects such as a short circuit occur depending on the through-hole pitch. That is, it is difficult to form a through hole itself.
It is further desirable to form between 75 and 485 μm. In the meantime, the self-inductance can be reduced, and by increasing the number of wirings, the inductance as a whole can be lowered and the electrical characteristics can be improved. Furthermore, the through-hole pitch can be narrowed.

  It is desirable that the through hole has a full-layer stack structure from one or more through holes directly above or from the land of the through hole to the outermost layer. It is desirable to form it immediately above the through hole. The through-hole connection is made by forming a land having a lid structure on the through hole by lid plating or the like, and a via-on-through hole in which a via hole is formed in a stack shape, and the IC chip has a stack structure. This is because the distance from the terminal to the external terminal or capacitor is a straight line, the shortest distance is achieved, and the inductance can be further reduced. In that case, it is more desirable to form a through hole for GND and a through hole for VCC in a lattice pattern or on a staggered pattern. The ideal is that all four through-holes arranged in a grid or zigzag form are stacked.

It is desirable that the grant through hole and the power supply through hole are disposed directly under the IC chip.
By disposing the IC chip immediately below the IC chip, the distance between the IC and the external terminal or the capacitor can be shortened, and the inductance can be reduced.

The core substrate in this case is a resin substrate impregnated with a core material such as glass epoxy resin, a ceramic substrate, a metal substrate, a composite core substrate using a composite of resin, ceramic, and metal, and an inner layer of these substrates (power supply For example, a substrate provided with a conductor layer, or a multilayer metal core substrate formed with three or more layers of conductor layers can be used.
In order to increase the thickness of the conductor of the power supply layer, it is possible to use a printed wiring board formed by a generally performed conductor layer such as plating or sputtering on a metal-embedded substrate. Good.

  In the multilayer metal core substrate, the thickness obtained by adding the outer layer and the inner conductor layer of the core substrate is the thickness of the core conductor layer. If necessary, an electronic component housing core substrate in which components such as capacitors, dielectric layers, and resistors are embedded in the inner layer of the core substrate may be used. The core insulating material may be a dielectric material.

  The core substrate in the present invention is defined as follows. It is a hard base material impregnated with a core material, etc., and a via hole is formed by a photo via or a laser on both sides or one side using an insulating resin layer that does not include a core material, and a conductor layer is formed, This is for electrical connection between layers. In comparison, the thickness of the core substrate is thicker than the thickness of the resin insulating layer. Basically, the core substrate is formed with a conductor layer mainly composed of a power supply layer, and other signal lines are formed only for connecting the front and back sides.

  In addition, if it is the multilayer printed wiring board formed by the material of the same thickness and is laminated | stacked, the layer or board | substrate which has a power supply layer as a conductor layer in a printed circuit board is defined as a core board | substrate.

  In the present invention, the thicknesses of the first insulating layer, the second insulating layer, the third insulating layer, and the fourth insulating layer of the multilayer metal core substrate are made uniform. Accordingly, the distance D1 between the conductor layer on the surface and the first conductor layer on the inner layer, the distance D2 between the first conductor layer and the metal plate, the distance D3 between the metal plate and the second conductor layer on the inner layer, the inner layer By arranging the distance D4 between the second conductor layer and the conductor layer on the back surface at a uniform distance, the mutual inductance between the conductor layer and the metal plate can be made constant, and the overall inductance can be reduced. For this reason, the power supply capability to the IC chip can be improved by using the conductor layer as the power supply layer. In addition, by using the conductor layer as a ground layer, it is possible to reduce a signal to the IC chip and noise superimposed on the power source.

A multilayer printed wiring board according to a first embodiment of the present invention will be described with reference to FIGS.
[First Example-1]
First, the configuration of the multilayer printed wiring board 10 according to the first embodiment will be described with reference to FIGS. 8 shows a cross-sectional view of the multilayer printed wiring board 10 and FIG. 9 shows a state in which the IC chip 90 is attached to the multilayer printed wiring board 10 shown in FIG. As shown in FIG. 8, the multilayer printed wiring board 10 uses a multilayer metal core substrate 30. An electrically isolated metal plate 12 is accommodated in the center of the multilayer metal core substrate 30. The metal plate 12 also serves as a core material, but is not electrically connected such as a through hole or a via hole. Mainly, the rigidity against the warp of the substrate is improved. Further, when a low thermal expansion material such as 36 alloy or 42 alloy is used for the metal plate, the thermal expansion coefficient of the multilayer printed wiring board can be made close to that of the IC, and the stress can be relieved. The metal plate 12 has a first conductive layer 16E as an inner layer on the front side through a front side insulating resin layer (first insulating layer) 14a, and a rear side through a back side insulating resin layer (second insulating layer) 14b. An inner second conductor layer 16P is disposed. Furthermore, the conductor circuit 34 and the conductor layer 34P on the front surface side are insulated on the second conductor layer 16P on the inner layer via the surface side insulating resin layer (third insulating layer) 18a on the first conductor layer 16E as the inner layer. A conductor circuit 34 and a conductor layer 34E on the back surface side are formed through a resin layer (fourth insulating layer) 18b. The conductor layer 34P on the front surface side is formed as a power source plane layer, and the conductor layer 34E on the back surface side is formed as a ground plane layer. The inner conductor layer 16E on the front side is formed as a ground plane layer, and the inner conductor layer 16P on the back side is formed as a power source plane layer. Connection to the power plane layers 34P and 16P is made through a power through hole 36P or a via hole. Connection to the ground plane layers 34E and 16P is made through ground through holes 36E and via holes. Signal connection between the upper and lower sides of the multi-layered metal core substrate 30 is performed by signal through holes 36S and via holes. The plain layer may be a single layer on one side or may be arranged in two or more layers. It is desirable to form with 2-6 layers. Since the improvement of the electrical characteristics has not been confirmed for seven layers or more, the effect is the same as that of six layers even if the number of layers is increased. In particular, the formation of four layers is excellent in electrical characteristics and substrate flatness.

  On the conductor layer 34P on the front surface of the multilayer metal core substrate 30 and the conductor layer 34E on the back surface, the interlayer insulating layer 50 in which the via hole 60 and the conductor circuit 58 are formed, and the via hole 160 and the conductor circuit 158 are formed. An interlayer insulating layer 150 is provided. A solder resist layer 70 is formed on the via hole 160 and the conductor circuit 158, and bumps 76 U and 76 D are formed on the via hole 160 and the conductor circuit 158 through the opening 71 of the solder resist layer 70. ing.

   As shown in FIG. 9, the bumps 76U on the upper surface side of the multilayer printed wiring board 10 are connected to the signal land 92S, the power land 92P, and the ground land 92E of the IC chip 90. Further, a chip capacitor 98 is mounted. On the other hand, the lower external terminal 76D is connected to the signal land 96S, the power land 96P, and the ground land 96E of the daughter board 94. The external terminals in this case refer to PGA, BGA, solder bumps, and the like.

  Here, as shown in FIG. 8, in the multilayer metal core substrate 30, the first insulating layer (front surface side insulating resin layer 14a), the second insulating layer (back surface side insulating resin layer 14a), and the third insulating layer of the multilayer metal core substrate. The thicknesses of the layer (front surface side insulating resin layer 18a) and the fourth insulating layer (back surface side insulating resin layer 18b) are substantially uniform. Thus, the distance D1 between the conductor layer 34P on the surface and the first conductor layer 16E on the inner layer, the distance D2 between the first conductor layer 16E and the metal plate 12, and the second conductor layer 16P on the metal plate 12 and the inner layer. And the distance D3 between the second conductor layer 16P on the inner layer and the conductor layer 34E on the back surface are set to be a uniform distance, so that the mutual inductance between the conductor layers 16E, 16P, 34E, 34P and the metal plate 12 can be obtained. And the inductance of the core substrate 30 as a whole can be reduced. For this reason, the power supply capability to the IC chip 90 can be improved by using the conductor layers 34P and 16P as the power supply layer. Further, by using the conductor layers 34E and 16E as the ground layer, it is possible to reduce noise superimposed on the signal to the IC chip 90 and the power source. That is, the reduction of the inductance of the conductor layer does not hinder the supply of power. Therefore, when an IC chip is mounted on the multilayer printed board, the loop inductance from the IC chip to the multilayer printed wiring board to the power source can be reduced. For this reason, the shortage of power supply in the initial operation is reduced, so that the shortage of power supply is less likely to occur. Therefore, even if an IC chip in a high frequency region is mounted, malfunctions and errors at the initial start-up are not caused.

  Note that the distances (insulating layer thicknesses) D1, D2, D3, and D4 between the conductor layers of the multilayer metal core substrate 30 are preferably 15 to 300 μm. If it is less than 15 μm, it is difficult to maintain insulation, and if it exceeds 300 μm, the effect of reducing the inductance between the conductor layers is offset, the thickness of the multilayer metal core substrate becomes thick, the through hole becomes long, and the through hole This is because the inductance in the hole increases. As an example of this, the distance between the conductor layers (the thickness of the insulating layer) was 220 μm.

  FIG. 10 shows an XX cross section of the multilayer printed wiring board 10 of FIG. That is, FIG. 10 shows a cross section of the multilayer metal core substrate 30. In the figure, for convenience of understanding, an upward mark (black circle in the center) is attached to the power supply through hole 36P, and a downward mark (+ in the figure) is attached to the ground through hole 36E. Nothing is marked on the through hole 36S. FIG. 11A is an explanatory diagram showing an enlarged view of a dotted line I portion in FIG. In the first embodiment, the power supply through holes 36P and the ground through holes 36E are arranged in a grid pattern at adjacent positions. That is, the ground (or power supply) is arranged at diagonal positions, and the power supply (or ground) is arranged at other positions. With this configuration, the induced electromotive force is canceled in the X direction and the Y direction.

  As described above with reference to FIG. 11A, the power supply through holes 36P (VCC1, VCC2) are arranged at equal intervals in the ground through holes 36E (GND1) in the through holes arranged in a grid pattern as described above. Thus, the ground through hole 36E (GND2) is disposed on the diagonal line of GND1. By adopting this four-core (quad) structure, the induced electromotive force due to two VCCs (or GND) is canceled out with respect to one GND (or VCC). For this reason, the mutual inductance can be reduced and the influence of noise can be reduced because it is not affected by the induced electromotive force. Further, by reducing the inductance, the IC chip can be increased or decreased intermittently. Thus, no voltage drop occurs even when power consumption increases, and malfunctions and delays are less likely to occur.

  Further, as shown in FIG. 8, the power supply through hole 36P and the ground through hole 36E arranged in the center of the multilayer metal core substrate 30 have a stacked structure in which a via hole 60 and a via hole 160 are provided immediately above the through hole. It has become. The through holes 36E and 36P are connected to the via hole 60 by forming a land 25 having a lid structure on the through hole 36E and the through hole 36P by lid plating or the like, and the via hole 60 is formed in a stack on the land 25. The Further, a via hole 160 is provided immediately above the upper via hole 60, and the via hole 160 is connected to the power source land 92E and the ground land 92E of the IC chip 90 via bumps 76U. Similarly, a via hole 160 is provided immediately below the lower via hole 60, and the via hole 160 is connected to the power land 96P and the ground land 96E of the daughter board 94 via bumps 76D.

  This is because the via on through hole and the stack structure are straight from the IC chip 90 to the bumps (external terminals) 76E and 76P of the daughter board or a capacitor (not shown), the shortest distance, and the inductance can be further reduced. . In that case, ideally, all of the four through-holes arranged in a lattice form have a stack structure.

  The distance (pitch) between the through holes 36E, 36P, and 36S was set to 60 to 600 μm, and the signal through hole diameter 36S (outer diameter) was formed to 50 to 500 μm. The distance (pitch) between the ground through hole 36E and the power through hole 36P is set to 60 to 600 μm, the diameter of the ground through hole 36E (outer diameter) is 50 to 500 μm, and the diameter of the power through hole 36P is It formed in 50-500 micrometers. The through holes 36E, 36P, and 36S were formed by forming a through-hole conductor layer formed in the core substrate 30 and filling the gaps with insulating resin. In addition, the through hole may be completely filled with conductive paste or plating.

  The grant through hole 36E and the power supply through hole 36P are arranged directly below the IC chip 90. By disposing the IC chip 90 immediately below the IC chip 90, the distance between the IC 90 and the bumps (external terminals) 96E, 96P of the daughter board 94 or a capacitor (not shown) can be shortened. Therefore, inductance can be reduced.

  Here, the conductor layers 34P and 34E on the surface layer of the core substrate 30 are formed to a thickness of 7.5 to 75 μm, and the inner conductor layers 16P and 16E are formed to a thickness of 15 to 300 μm. The conductor circuit 58 and the conductor circuit 158 on the interlayer insulating layer 150 are formed to 5 to 25 μm.

  In the multilayer printed wiring board of the first embodiment, the surface power layer (conductor layer) 34P, the conductor layer 34, the inner power layer (conductor layer) 16P, the conductor layer 16E, and the metal plate 12 of the core substrate 30 are thickened. This increases the strength of the core substrate. As a result, even if the core substrate itself is thinned, it is possible to relieve warpage and the generated stress by the substrate itself.

  Further, by increasing the thickness of the conductor layers 34P and 34E and the conductor layers 16P and 16E, the volume of the conductor itself can be increased. By increasing the volume, resistance in the conductor can be reduced.

  Furthermore, by mounting the capacitor 98, the power source stored in the capacitor can be used supplementarily, so that it becomes difficult to cause power shortage.

  In the first embodiment, the multilayer metal core substrate 30 has thick conductor layers 16P and 16E on the inner layer and thin conductor layers 34P and 34E on the surface, and the inner conductor layers 16P and 16E and the surface conductor layers 34P and 34E. Are used as a conductor layer for a power supply layer and a conductor layer for a ground. That is, even if the thick conductor layers 16P and 16E are arranged on the inner layer side, an insulating layer covering the conductor layer is formed. Therefore, the surface of the multilayer metal core substrate 30 can be flattened by canceling out the irregularities due to the conductor layer. For this reason, even if the thin conductor layers 34P and 34E are arranged on the surface of the multilayer metal core substrate 30 so that the conductor layers 58 and 158 of the interlayer insulating layers 50 and 150 do not waviness, the inner conductor layers 16P, A thickness sufficient as a conductor layer of the core can be ensured by the thickness added to 16E. Since no undulation occurs, there is no problem with the impedance of the conductor layer on the interlayer insulating layer. By using the conductor layers 16P and 34P as the power supply layer conductor layers and the conductor layers 16E and 34E as the ground conductor layers, the electrical characteristics of the multilayer printed wiring board can be improved.

  That is, the thickness of the inner conductor layers 16P and 16E of the core substrate is made thicker than the conductor layers 58 and 158 on the interlayer insulating layers 50 and 150. Thereby, even if the thin conductor layers 34E and 34P are arranged on the surface of the multilayer metal core substrate 30, a sufficient thickness as the conductor layer of the core can be secured by adding the thick conductor layers 16P and 16E. The ratio is desirably 1 <(total thickness of conductor layers of core substrate / conductor layer of interlayer insulating layer) ≦ 40. It is further desirable that 1.2 ≦ (total thickness of conductor layers of core substrate / conductor layer of interlayer insulating layer) ≦ 20. Further, in this case, it is desirable that the ratio of the sum of the conductor layers serving as the power supply layer of the core substrate to the conductor layer of the interlayer insulating layer is the above relationship. That is, it is desirable that 1 <(total thickness of the power supply conductor layers of the core substrate / conductor layer of the interlayer insulating layer) ≦ 40. It is further desirable that 1.2 ≦ (total thickness of power supply conductor layers of the core substrate / conductor layer of interlayer insulating layer) ≦ 20. As a result, the inductance can be reduced, making it difficult to cause malfunction of the IC chip.

  The multi-layered metal core substrate 30 has inner conductor layers 16P and 16E interposed on both surfaces of the electrically isolated metal plate 12 with an insulating layer 14 interposed therebetween, and further insulated outside the inner conductor layers 16P and 16E. The conductor layers 34P and 34E on the surface are formed with the layer 18 interposed. By disposing the electrically isolated metal plate 12 in the center, sufficient mechanical strength can be ensured. Further, when a low thermal expansion material such as 36 alloy, 42 alloy or the like is used for the metal plate 12, the thermal expansion coefficient of the resin substrate can be lowered, so that it can approach the thermal expansion coefficient of an electronic component such as an IC. Furthermore, the insulating layers 14 are interposed on both surfaces of the metal plate 12, and inner conductor layers 16P and 16E are provided. Further, the insulating layers 18 are provided outside the inner conductor layers 16P and 16E, and the surface conductor layers 34P are provided. By forming 34E, symmetry is provided on both surfaces of the metal plate 12, and warpage and undulation can be prevented from occurring in a heat cycle or the like.

  FIG. 10B shows a through hole arrangement according to a modification of the first embodiment. FIG. 11B is an explanatory diagram showing an enlarged dotted line II portion in FIG. In the modified example of the first embodiment, the power supply through holes 36P and the ground through holes 36E are arranged in a staggered manner at adjacent positions. That is, the ground (or power supply) is arranged at diagonal positions, and the power supply (or ground) is arranged at other positions. With this configuration, the induced electromotive force is canceled in the X direction and the Y direction.

  That is, as described above with reference to FIG. 11B, in the through holes 36P and 36E arranged in a staggered manner, GND2 and GND3 are arranged at equal intervals of GND1, and during the same distance of GND2, VCC1 and VCC2 are disposed. By adopting this structure, the induced electromotive force due to two VCCs (or GNDs) is canceled for one GND (or VCC). Therefore, the mutual inductance can be reduced and is not affected by the induced electromotive force, so that malfunctions and delays are less likely to occur.

Next, a method for manufacturing the multilayer printed wiring board 10 shown in FIG. 8 will be described with reference to FIGS.
(1) Formation of Metal Layer An opening 12a penetrating the front and back is provided in the inner metal layer (metal plate) 12 having a thickness of 50 to 400 μm shown in FIG. 1 (A) (FIG. 1 (B)). As the material of the metal layer, metals such as copper, nickel, zinc, aluminum, iron, and alloys thereof can be used. The opening 12a is formed by punching, etching, drilling, laser, or the like. In some cases, the entire surface of the metal layer 12 in which the opening 12a is formed may be coated with the metal film 13 by electrolytic plating, electroless plating, displacement plating, or sputtering (FIG. 1C). The metal plate 12 may be a single layer or a plurality of layers of two or more layers. The metal film 13 is preferably formed with a curved surface. Thereby, there is no point where stress is concentrated, and it is difficult to cause defects such as cracks in the vicinity.

(2) Formation of inner insulating layer Insulating resin is used to cover the entire metal layer 12 and fill the opening 12a. As a formation method, for example, the insulating resin layers (insulating layers) 14a and 14b can be formed after sandwiching a B-stage resin film having a thickness of about 15 to 300 μm between the metal plates 12 and then thermocompression bonding ( FIG. 1D). Furthermore, it is better to disperse the inorganic filler in the resin. In some cases, coating, mixing of coating and film crimping, or coating only a quiet part, and then forming with a film.
As a material laminated on the metal plate, it is desirable to use a prepreg obtained by impregnating a core material such as glass cloth or glass nonwoven fabric with a thermosetting resin such as polyimide resin, epoxy resin, phenol resin, or BT resin. In this case, an inorganic filler such as glass, alumina or zirconia may be dispersed. Besides that, a resin may be used.

(3) Affixing the metal foil The inner metal layer 16α is formed on both surfaces of the metal layer 12 covered with the insulating layers 14a and 14b (FIG. 1E). As an example, a metal foil having a thickness of 12 to 275 μm was laminated. As a method other than forming a metal foil, a prepreg with a single-sided copper foil is laminated. As the insulating layer of the prepreg with a single-sided copper foil, the same layer as in the step (2) can be used.

(4) Two or more circuit formation layers of the inner metal layer may be used. The metal layer may be formed by an additive method.
Through the tenting method, the etching process, and the like, the inner conductor layers 16, 16P, and 16E were formed from the inner metal layer 16α (FIG. 1 (F)). At this time, the inner conductor layer had a thickness of 7.5 to 250 μm. However, the above range may be exceeded.

(5) Formation of outer insulating layer Insulating resin is used to cover the entire inner conductor layers 16, 16P and 16E and fill the gaps between the circuits. As a forming method, for example, a B-stage resin film having a thickness of about 15 to 300 μm is sandwiched between the inner conductor layers 16, 16P, and 16E, and then thermocompression-bonded to form outer insulating insulating layers 18a and 18b (FIG. 2). (A)). In some cases, application, mixing of application and film crimping, or application of only the opening may be performed, and then the film may be formed. The surface can be flattened by applying pressure.
As a material to be laminated on the inner conductor layer, it is desirable to use a prepreg in which a thermosetting resin such as polyimide resin, epoxy resin, phenol resin, or BT resin is impregnated in a core material such as glass cloth or glass nonwoven fabric. In this case, an inorganic filler such as glass, alumina or zirconia may be dispersed. Besides that, a resin may be used.

(6) Affixing the outermost metal foil The outermost metal layer 34α is formed on both surfaces of the substrate covered with the outer insulating layers 18a and 18b (FIG. 2B). As an example, a metal foil having a thickness of 10 to 275 μm is laminated. As a method other than forming a metal foil, a prepreg with a single-sided copper foil is laminated. Two or more layers may be formed on the metal foil by plating or the like. The metal layer may be formed by an additive method. As the prepreg with a single-sided copper foil, the same prepreg as in the above step (2) can be used.

(7) Through-hole formation A through-hole 36α having an opening diameter of 50 to 400 μm penetrating the front and back of the substrate is formed (FIG. 2C). As a forming method, it is formed by drill, laser, or a combination of laser and drill (the outermost insulating layer is opened with a laser, and in some cases, the laser opening is used as a target mark, and then drilled. Open and penetrate). As a shape, it is desirable to have a straight side wall. In some cases, it may be tapered.

In order to ensure the conductivity of the through hole, the plated film 22 is formed in the through hole 36α (formed by electroless plating, electrolytic plating, etc.) and the surface is roughened (FIG. 2D). It is desirable to fill the filling resin 23 (FIG. 2E). Filling resins include electrically insulated resin materials (for example, those containing resin components, curing agents, particles, etc.), and conductive materials that are electrically connected by metal particles (for example, Any of those containing metal particles such as gold and copper, resin materials, curing agents, etc.) can be used.
As plating, electrolytic plating, electroless plating, panel plating (electroless plating and electrolytic plating), or the like can be used. The metal is formed because it contains copper, nickel, cobalt, phosphorus, or the like. The thickness of the plated metal is preferably formed between 5 and 30 μm.

  As the filling resin 23 to be filled in the through hole 36α for the through hole, it is desirable to use an insulating material made of a resin material, a curing agent, particles and the like. As the particles, inorganic particles such as silica and alumina, metal particles such as gold, silver and copper, and resin particles are used alone or in combination. A mixture of particles having a particle diameter of 0.1 to 5 μm having the same diameter or a composite diameter can be used. The resin material is a single or mixed epoxy resin (for example, bisphenol type epoxy resin, novolac type epoxy resin, etc.), thermosetting resin such as phenol resin, photosensitive ultraviolet curable resin, thermoplastic resin, etc. Can be used. As the curing agent, an imidazole curing agent, an amine curing agent, or the like can be used. In addition, a curing stabilizer, a reaction stabilizer, particles, and the like may be included. A conductive material may be used. In this case, what consists of a metal particle, a resin component, a hardening | curing agent, etc. becomes the electrically conductive paste which is an electroconductive material. Depending on the case, a material in which a conductive metal film is formed on the surface layer of an insulating material such as solder or insulating resin may be used. It is also possible to fill the through-hole through hole 36α by plating. This is because the conductive paste undergoes curing shrinkage, and may form recesses in the surface layer.

(8) Formation of outermost conductor circuit Cover plating 25 may be formed immediately above through holes 36S, 36E, and 36P by covering the entire surface with a plating film (FIG. 3A). Thereafter, the outer layer conductor circuits 34, 34P, and 34E are formed through a tenting method, an etching process, and the like (FIG. 3B). Thereby, the multilayer metal core substrate 30 is completed.
At this time, although not shown, electrical connection with the inner conductor layers 16P, 16E, etc. of the multilayer metal core substrate may be made by via holes, blind through holes, or blind via holes. The thickness of the multilayer metal core substrate at this time is preferably formed between 500 μm and 800 μm. In this case, it was formed at 700 μm.

(9) The multilayer metal core substrate 30 on which the conductor circuit 34 is formed is blackened and reduced to form a roughened surface 34β on the entire surface of the conductor circuit 34 and the conductor layers 34P and 34E (FIG. 3 ( C)).

(10) A layer of the resin filler 40 is formed on the conductor circuit non-formation portion of the multilayer metal core substrate 30 (FIG. 4A).

(11) Polishing one side of the substrate after the above processing by polishing with a belt sander or the like so that the resin filler 40 does not remain on the outer edges of the conductor layers 34P and 34E, and then removing scratches due to the polishing Further, the entire surfaces (including the land surfaces of the through holes) of the conductor layers 34P and 34E were further polished with a buff or the like. Such a series of polishing was similarly performed on the other surface of the substrate. Subsequently, heat treatment was performed at 100 ° C. for 1 hour and 150 ° C. for 1 hour to cure the resin filler 40 (FIG. 4B).
In addition, it is not necessary to perform resin filling between conductor circuits. In this case, an insulating layer is formed with a resin layer and a conductor circuit is filled.

(12) Spray the etching solution onto both surfaces of the multilayer metal core substrate 30 by spraying the surface of the conductor circuit 34, the conductor layers 34P, 34E and the land surfaces and inner walls of the through holes 36S, 36E, 36P. A roughened surface 36 竈 was formed on the entire surface of the conductor circuit by etching or the like (FIG. 4C).

(13) An interlayer insulation layer resin film 50 に is placed on both sides of the multilayer metal core substrate 30, placed on the substrate, cut by provisional pressure bonding, and further adhered by using a vacuum laminator device. A layer was formed (FIG. 5A).

  At this time, a thermosetting resin, a thermoplastic resin, a photosensitive resin, or a resin composite thereof (for example, a resin composite of a thermosetting resin and a thermoplastic resin) is used for the resin film for the interlayer insulating layer. be able to. As the thermosetting resin, an epoxy resin, a polyimide resin, a phenol resin, or the like can be used. As the thermoplastic resin, phenoxy resin, polyethersulfone (PES), or the like can be used. As the photosensitive resin, a resin mixed with a (meth) acryl group can be used. In addition to the resin, particles having a particle size of about 0.1 μm to 20 μm, a reaction stabilizer, and the like, which are made of a curing agent, a resin, an inorganic material, a metal, and the like, are added as necessary.

(14) Next, with a CO2 gas laser with a wavelength of 10.4 μm, a beam diameter of 4.0 mm, top hat mode, pulse, through a mask having a 1.2 mm thick through hole formed on the interlayer insulating layer A via hole opening 50a having a diameter of 80 μm was formed in the interlayer insulating layer 50 under the conditions of a width of 7.9 μs, a mask through-hole diameter of 1.0 mm, and one shot (FIG. 5B).

(15) A roughening layer is provided on the surface layer of the multilayer metal core substrate 30. As the roughening solution, an acid such as sulfuric acid or acetic acid or an oxidizing agent such as chromic acid or permanganic acid can be used. As an example, the multilayer metal core substrate 30 is immersed in an 80 ° C. solution containing 60 g / l permanganic acid for 10 minutes, and the roughened surface 50 is formed on the surface of the interlayer insulating layer 50 including the inner wall of the via hole opening 50a. A wrinkle was formed (FIG. 5C). The roughened surface was formed between 0.1 and 5 μm.

(16) Next, the multilayer metal core substrate 30 having been subjected to the above treatment was immersed in a neutralization solution (manufactured by Shipley Co., Ltd.) and then washed with water. Furthermore, a catalyst such as palladium was applied to the surface of the substrate that had been roughened (roughening depth: 3 μm) to attach catalyst nuclei to the surface of the interlayer insulating layer and the inner wall surface of the via hole opening. .

(17) Next, a substrate provided with a catalyst is immersed in an electroless copper plating aqueous solution to form an electroless copper plating film having a thickness of 0.6 to 3.0 μm on the entire rough surface. A substrate having an electroless copper plating film 52 formed on the surface of the interlayer insulating layer 50 including the inner wall of the opening 50a is obtained (FIG. 5D).

(18) A commercially available photosensitive dry film is attached to the substrate on which the electroless copper plating film 52 is formed, a mask is placed, and development processing is performed to provide a plating resist 54 (FIG. 6A). . The thickness of the plating resist was between 10 and 30 μm.

(19) Next, electrolytic plating was performed on the multilayer metal core substrate 30 to form an electrolytic copper plating film 56 having a thickness of 7 to 25 μm in the portion where the plating resist 54 was not formed (FIG. 6B).

(20) Further, after removing the plating resist with about 5% KOH, the electroless plating film under the plating resist is removed by etching with a mixed solution of sulfuric acid and hydrogen peroxide to remove an independent conductor. A circuit 58 and a via hole (fill via hole) 60 were formed (FIG. 6C).

(21) Next, the same processing as in the above (12) was performed to form roughened surfaces 58 痾 and 60 に on the surfaces of the conductor circuit 58 and the via hole 60. The upper conductor circuit 58 was formed to have a thickness of 5 to 25 μm. The thickness this time was 15 μm (FIG. 6D).

(22) By repeating the steps (14) to (21), an upper interlayer insulating layer 150, a conductor circuit 158, and a via hole 160 were formed to obtain a multilayer wiring board (FIG. 7A). .

(23) Next, after applying a solder resist composition 70 to a thickness of 12 to 30 μm on both surfaces of the multilayer wiring board and performing a drying treatment at 70 ° C. for 20 minutes and 70 ° C. for 30 minutes ( FIG. 7 (B)), a photomask having a thickness of 5 mm in which the pattern of the opening of the solder resist is drawn is brought into close contact with the solder resist layer 70, exposed to 1000 mJ / cm 2 of ultraviolet light, developed with DMTG solution, and 200 μm. An opening 71 having a diameter of 5 mm was formed (FIG. 7C).
Further, the solder resist layer 70 is cured by heat treatment under the conditions of 80 ° C. for 1 hour, 100 ° C. for 1 hour, 120 ° C. for 1 hour, and 150 ° C. for 3 hours. A solder resist pattern layer 70 having a thickness of 10 to 25 μm was formed. Moreover, you may use the film type thing marketed as a soldering resist layer.

(24) Next, the substrate on which the solder resist layer 70 was formed was immersed in an electroless nickel plating solution to form a nickel plating layer 72 having a thickness of 5 μm in the opening 71. Further, the substrate was immersed in an electroless gold plating solution to form a 0.03 μm thick gold plating layer 74 on the nickel plating layer 72 (FIG. 7D). In addition to the nickel-gold layer, a single layer of tin or a noble metal layer (gold, silver, palladium, platinum, etc.) may be formed.

(25) After that, a solder paste containing tin-lead is printed in the opening 71 of the solder resist layer 70 on the surface on which the IC chip of the substrate is placed, and further, tin-lead is formed in the opening of the solder resist layer on the other surface. After printing solder paste containing antimony and the like, external terminals were formed by reflowing at 200 ° C. to produce a multilayer printed wiring board having solder bumps 76U and 76D (FIG. 8).

  FIG. 18 shows a multilayer printed wiring board according to a modification of the first embodiment. In the first embodiment described above with reference to FIG. 8, the multilayer metal core substrate 30 is provided with two inner conductor layers. In contrast, in the modified example, four inner conductor layers 16E, 16EE, 16P, and 16PP are provided. Also in this modified example, the thicknesses D5, D6, D7, D8, D9, and D10 of the insulating layers 18a, 18c, 14a, 14b, 18b, and 18d between the adjacent conductor layers are set to D5 = D6 = D7 = D8 = D9 = D10. By doing so, the same effect as the first embodiment is obtained.

[First Example-2]
It is the same as the first embodiment, and is the same except that the thickness of the insulating layer between the conductors of the surface layer conductor circuit and the inner layer conductor circuit is 300 μm.

[First Example-3]
The same as in the first embodiment, except that the thickness of the insulating layer between the conductors of the surface conductor circuit and the inner conductor circuit is 100 μm.

[First Example-4]
The same as in the first embodiment, except that the thickness of the insulating layer between the conductors of the surface conductor circuit and the inner conductor circuit is 30 μm.

[First Example-5]
The same as in the first embodiment, except that the thickness of the insulating layer between the conductors of the surface conductor circuit and the inner conductor circuit is 15 μm.

[Comparative Example 1]
19 is a printed wiring board (core substrate thickness 800 μm) in which conductor circuits are arranged on both surfaces (surfaces) according to the prior art described above with reference to FIG.

[Comparative Example 2]
The same as in the first embodiment-1, except that the thickness of the insulating layer between one (front side) conductor circuit and the inner layer conductor circuit is 300 μm, and the opposite side (back side) conductor circuit and inner layer conductor circuit The thickness of the insulating layer between the conductors was set to 350 μm.

[Reference Example 1]
This is the same as Example 1, except that the thickness of the insulating layer between the conductors of the surface layer conductor circuit and the inner layer conductor circuit is 350 μm.

[Reference Example 2]
This is the same as Example 1, except that the thickness of the insulating layer between the conductors of the surface conductor circuit and the inner conductor circuit is 10 μm.

[Reference Example 3-1]
As in the first embodiment-1, the through holes are arranged in a staggered manner, and the distance between the ground through hole and the power through hole is 600 μm, 500 μm, 400 μm, 300 μm, 100 μm, 75 μm, and 60 μm. A total of 7 types were formed. Everything except this through hole is the same.

[Reference Example 3-2]
Although it is the same as that of 1st Example-1, the arrangement | positioning of a through hole was formed by the staggered pattern, and the distance between the ground through hole and the power supply through hole was 650 μm. Everything except this through hole is the same.

[Reference Example 3-3]
Although it is the same as that of 1st Example-1, the arrangement | positioning of a through hole was formed by the staggered pattern, and the distance between the ground through hole and the power supply through hole was 50 μm. Everything except this through hole is the same.

[Reference Example 3-4]
Although it is the same as that of 1st Example-1, the through-hole was arrange | positioned at random and the thing of 650 micrometers, 600 micrometers, and 550 micrometers in the shortest distance of the ground through hole and the power supply through hole was formed. Everything except this through hole is the same.

[Reference Example 4-1]
As in the first embodiment-1, the through holes are arranged in a grid pattern, and the distance between the ground through hole and the power through hole is 600 μm, 500 μm, 400 μm, 300 μm, 100 μm, 75 μm, 60 μm. A total of 7 types were formed. Everything except this through hole is the same.

[Reference Example 4-2]
Although it is the same as that of 1st Example-1, the arrangement | positioning of a through hole was formed in the grid | lattice form, and the thing of the distance of 650 micrometers of ground through holes and power supply through holes was formed. Everything except this through hole is the same.

[Reference Example 4-3]
Although the same as in the first embodiment-1, the through holes were arranged in a lattice shape, and the distance between the ground through hole and the power through hole was 50 μm. Everything except this through hole is the same.

  A loop inductance and a reliability test under high temperature and high humidity were performed by the first example group, the comparative example, and the reference example group, respectively. The results are shown in the chart in FIG. 12 and the graph in FIG. In the figure, the value of loop inductance is a value per 10 mm square, and reliability test (heat cycle: (−65 ° C./3 minutes) ⇔ (135 ° C./3 minutes is one cycle, 1500 cycles and 3000 cycles) In the results of the continuity test, ○ indicates that the rate of change in resistance is within 10%, and x indicates that the rate of change in resistance exceeds 10%, provided that the measurement results in FIG. In order to prevent variations due to the above factors, measurement was performed by selecting a region where no through hole was formed, thereby eliminating the factor due to the through hole pitch.

  Here, the through-hole grid arrangement of the multilayer printed wiring board in the first embodiment, the staggered arrangement of the modified example of the first embodiment, the through-holes for the random arrangement of the through-holes of Reference Example 1, Reference Example 3, and Comparative Example 1 FIG. 13 shows the result of measuring the loop inductance while changing the hole distance (through hole pitch) and the through hole diameter. Here, the value of the loop inductance is a value per 10 mm square.

When the loop inductance is 90 pH or less, the power supply capability to the IC chip is improved and noise and delay are not caused. Therefore, it is desirable that the thickness of the insulating layer between adjacent conductors in the core substrate is 300 μm or less. Even if the reliability test was performed, the occurrence of a short circuit or the like was not confirmed in the conduction result, so there was no problem in electrical connectivity.
In Comparative Example 1, the loop inductance exceeded 100 pH. In the comparative example 2, the thing in which the distance between conductor circuits differs was arrange | positioned. For this reason, the pH obtained was higher than 90 pH because the effect obtained in the multilayer was offset.
In Reference Example 1, since the distance between the conductors was 350, it seems that 90 pH was exceeded. In Reference Example 2, there was no problem with the loop inductance itself, but a short circuit was caused in the reliability result test. Again, it was difficult to ensure insulation between the conductor layers, and part of the conductor layers were in contact. Therefore, the result of the reliability test was bad. Considering this, it is more desirable that the thickness of the insulating layer between the conductor layers is 15 to 300 μm. This range is more desirable in terms of reliability. This is because within this range, the reliability is also excellent.
Furthermore, it is more desirable that the thickness of the insulating layer between the conductor layers is 30 to 250 μm. This is because within this range, the reliability result is stable over a long period of time, and the inductance is reliably 90 pH or less.

  FIG. 13 shows the relationship between the arrangement of the through holes and the loop inductance. From this result, even if the through-hole pitch is changed, a grid arrangement or a staggered arrangement (a ground through hole and a power supply through hole are adjacent to each other) rather than a random arrangement (a structure in which a ground through hole and a power supply through hole are not adjacent to each other). The matching structure) can reduce the loop inductance. As a result, noise can be suppressed, malfunctions and delays can be suppressed, and the mutual inductance itself can be reduced.

  In addition, regardless of the through-hole pitch, the lattice arrangement can reduce the loop inductance as compared with the staggered arrangement. Therefore, it can be said that it is superior in electrical characteristics. Also from the values in FIG. 13, the mutual inductance value can be reduced if the ground through hole 36E and the power through hole 36P are arranged diagonally.

Further, the loop inductance was calculated from the simulated rate by changing the through-hole pitch, and the results are shown in FIG. 14B and FIG. Here, the value of the loop inductance is a value per 10 mm square.
Furthermore, through a reliability test under high-temperature and high-humidity conditions (85 ° C., humidity 85 wt%, 500 hr implementation) on the substrate at each through-hole pitch in the lattice arrangement and the staggered arrangement, the presence or absence of cracks in the through-hole insulating layer The resistance value measurement result in the continuity test is shown in FIG.

When the loop inductance is 75 pH or less, the characteristics of the substrate in the IC chip with a frequency of 3 GHz can be improved. In this case, according to the result of FIG. 13, such a result is obtained when the through-hole pitch is 600 μm or less. In addition, considering the result of FIG. 14A, it can be said that the electrical characteristics can be appropriately improved and reliability can be ensured when the distance is 60 to 600 μm.
Moreover, when it forms in a grid | lattice arrangement | positioning, it is desirable that a through-hole pitch is between 60-600 micrometers. This is because the loop inductance can be reduced to a certain level (75 pH) or less and the reliability can be secured. Further, if the through-hole pitch is between 75 and 550 μm, it is possible to ensure reliability at the same time as the inside of the corresponding loop inductance region.

  Moreover, when it forms in zigzag arrangement | positioning, it is desirable that a through-hole pitch is between 60-550 micrometers. This is because, within this range, the loop inductance can be reduced to a certain level (75 pH) or less, and the reliability can be ensured. Furthermore, if the through-hole pitch is between 75 and 500 μm, it is possible to reliably ensure reliability as well as inside the corresponding loop inductance region.

  Moreover, when the loop inductance is 60 pH or less, the characteristics of the substrate in the IC chip having a frequency of 5 GHz can be improved. In this case, according to the result of FIG. 13, such a result is obtained when the through-hole pitch is 550 μm or less. In addition, considering the result of FIG. 14A, it can be said that the electrical characteristics can be appropriately improved and reliability can be ensured when it is between 60 and 550 μm.

  In addition, when it forms in a grid | lattice arrangement | positioning, it is desirable for a through-hole pitch to be between 60-550 micrometers. This is because within this range, the loop inductance level can be reduced to 60 pH or less, and reliability can be ensured. Furthermore, if the through-hole pitch is between 75 and 500 μm, reliability can be ensured at the same time as the inside of the corresponding loop inductance region.

  Moreover, when it forms in zigzag arrangement | positioning, it is desirable that a through-hole pitch is between 60-425 micrometers. This is because within this range, the loop inductance level can be reduced to 60 pH or less, and reliability can be ensured. Furthermore, if the through-hole pitch is between 75 and 500 μm, reliability can be ensured at the same time as the inside of the corresponding loop inductance region.

  Furthermore, when the loop inductance is 55 pH or less, the characteristics of the substrate can be improved regardless of the frequency of the IC chip. In this case, according to the result of FIG. 13, such a result is obtained when the through-hole pitch is 450 μm or less. In addition, considering the result of FIG. 14A, it can be said that the electrical characteristics can be appropriately improved and reliability can be ensured when it is between 60 and 450 μm.

  In addition, when it forms in a grid | lattice arrangement | positioning, it is desirable that a through-hole pitch is between 60-450 micrometers. This is because within this range, the loop inductance level can be reduced to 60 pH or less, and reliability can be ensured. Furthermore, if the through-hole pitch is between 75 and 425 μm, it is possible to ensure reliability at the same time as the inside of the corresponding loop inductance region.

  Moreover, when it forms in zigzag arrangement | positioning, it is desirable that a through-hole pitch is between 60-400 micrometers. This is because within this range, the loop inductance level can be reduced to 60 pH or less, and reliability can be ensured. Furthermore, if the through-hole pitch is between 75 and 350 μm, it is possible to reliably ensure reliability at the same time as the inside of the corresponding loop inductance region.

An IC chip having a frequency of 3.1 GHz is mounted on the substrates of the respective examples, comparative examples, and reference examples, and the same amount of power is supplied. The result of simulating the amount of voltage drop when starting is shown in FIG. Here, the conductor thickness of the conductor layer was verified. Set the horizontal axis (ratio of the thickness of at least one conductor of the core power supply layer or ground layer / the thickness of the conductor of the conductor circuit layer of the interlayer insulation layer) and the maximum voltage drop (V) on the vertical axis. If the thickness of the conductor is thin, peeling at the via connection portion will occur and reliability will be reduced. However, when the ratio of the thickness of at least one conductor of the power supply layer or the ground layer of the core substrate / the thickness of the conductor of the conductor layer of the interlayer insulating layer exceeds 1.2, the reliability is improved. On the other hand, if the ratio of the thickness of the conductor of the power source layer of the core substrate or the conductor of the earth layer / the thickness of the conductor of the conductor layer of the interlayer insulating layer exceeds 40, a fault in the upper conductor circuit (for example, stress on the upper conductor circuit) This causes a decrease in adhesion due to the occurrence of undulations and undulations), resulting in a decrease in reliability.
When the power supply voltage is 1.0 V, if the fluctuation allowable range is ± 10%, the voltage behavior is stable, and the IC chip does not malfunction. That is, in this case, if the voltage drop amount is within 0.1V, malfunctions to the IC chip due to the voltage drop will not be caused. If it is 0.09 V or less, stability will increase. Therefore, the ratio of (the thickness of at least one conductor of the power source layer or the ground layer of the core substrate / the thickness of the conductor of the conductor layer of the interlayer insulating layer) should preferably exceed 1.2. Furthermore, since the numerical value tends to decrease if it is in the range of 1.2 ≦ (the thickness of at least one conductor of the power supply layer or the ground layer of the core substrate / the thickness of the conductor of the conductor layer of the interlayer insulating layer) ≦ 40, This means that the effect is easy to obtain. In addition, the voltage drop amount increases in a range of 40 <(thickness of at least one conductor of the power source layer or ground layer of the core substrate / thickness of conductor of the conductor layer of the interlayer insulating layer).
Further, if 5.0 <(the thickness of at least one conductor of the power supply layer or the ground layer of the core substrate / the thickness of the conductor of the conductor layer of the interlayer insulating layer) ≦ 40, the voltage drop amount is substantially the same. Therefore, it is stable. That is, it can be said that this range is the most desirable ratio range.

It is process drawing which shows the manufacturing method of the multilayer printed wiring board of 1st Example of this invention. It is process drawing which shows the manufacturing method of the multilayer printed wiring board of 1st Example. It is process drawing which shows the manufacturing method of the multilayer printed wiring board of 1st Example. It is process drawing which shows the manufacturing method of the multilayer printed wiring board of 1st Example. It is process drawing which shows the manufacturing method of the multilayer printed wiring board of 1st Example. It is process drawing which shows the manufacturing method of the multilayer printed wiring board of 1st Example. It is process drawing which shows the manufacturing method of the multilayer printed wiring board of 1st Example. It is sectional drawing of the multilayer printed wiring board which concerns on 1st Example. It is sectional drawing which shows the state which mounted the IC chip in the multilayer printed wiring board which concerns on 1st Example. 10A is a cross-sectional view taken along line XX of the multilayer printed wiring board in FIG. 8, and FIG. 10B is a cross-sectional view of the multilayer printed wiring board according to the modified example of the first embodiment. . 11A is an explanatory diagram showing an enlarged view of a dotted line I portion in FIG. 10A, and FIG. 11B is an explanatory diagram showing an enlarged view of a dotted line II portion in FIG. 11B. FIG. 11C is an explanatory diagram showing the pitch. It is a graph which shows the result of having performed the reliability test under a loop inductance and high temperature, high humidity by a 1st Example group, a comparative example, and a reference example group, respectively. It is the graph which showed the result of having simulated the loop inductance with respect to the lattice arrangement of a through hole, and a staggered arrangement. (A), (B) is the chart which showed the result of having simulated the loop inductance to the lattice arrangement of a through hole, and a staggered arrangement. It is the graph which showed the result of having simulated the loop inductance to the lattice arrangement of a through hole, and a staggered arrangement. It is the graph which showed the result of having simulated the maximum voltage drop amount (V) with respect to (ratio of the thickness of at least one of a power supply layer of a core or an earth layer / thickness of the conductor layer of an interlayer insulation layer). It is a graph which shows the result of having calculated loop inductance by the 1st example group, a comparative example, and a reference example group, respectively. It is sectional drawing of the multilayer printed wiring board which concerns on the modification of 1st Example. It is sectional drawing of the multilayer printed wiring board which concerns on a prior art.

Explanation of symbols

12 Metal layer (metal plate)
14a Front side insulating layer 14b Back side insulating layer 16P Conductor layer (second conductor layer)
16E Conductor layer (first conductor layer)
18a Front side insulating layer 18b Back side insulating layer 30 Multilayer metal core substrate 32 Copper foil 34 Conductor circuit 34P Conductor layer 34E Conductor layer 36P Power supply through hole 36E Ground through hole 40 Resin filled layer 50 Interlayer insulating layer 58 Conductor circuit 60 Via Hole 70 Solder resist layer 71 Opening 76U, 76D Solder bump 90 IC chip 94 Daughter board 98 Chip capacitor

Claims (9)

  1. An interlayer insulation layer and a conductor layer are formed on both sides or one side on a multilayer metal core substrate having a plurality of through-holes and comprising a plurality of insulation layers and conductor layers, and electrical connection is made via via holes. In the multilayer printed wiring board to be performed,
    A multilayer printed wiring board, wherein the thickness of each insulating layer of the multilayer metal core substrate is uniform.
  2. 2. The multilayer printed wiring board according to claim 1, wherein adjacent conductor layers of the multilayer metal core substrate are an arrangement of a conductor layer for a power supply layer and a conductor layer for a ground.
  3. 2. The multilayer printed wiring board according to claim 1, wherein the thickness of the conductor layer of the multilayer metal core substrate is greater than the thickness of the conductor layer on the interlayer insulating layer.
  4. 4. The multilayer printed wiring board according to claim 3, wherein the thickness of the conductor layer of the multilayer metal core substrate is α1 and the thickness of the conductor layer on the interlayer insulation layer is α2 <α1 ≦ 40α2. .
  5. 2. The multilayer printed wiring board according to claim 1, wherein the thickness of each insulating layer of the multilayer metal core substrate is 15 to 300 [mu] m.
  6. 2. The multilayer printed wiring board according to claim 1, wherein the conductor layer of the multilayer metal core substrate has two or more conductor layers for power supply or conductor for ground.
  7. The through holes of the multi-layer metal core substrate have two or more ground through holes and two or more power supply through holes, which are arranged in a grid pattern or a staggered pattern in adjacent positions. The multilayer printed wiring board according to claim 1.
  8. The multilayer printed wiring board according to claim 7, wherein a distance between the ground through hole and the power through hole is between 50 and 550 μm.
  9. The multilayer printed wiring board according to claim 7, wherein the diameter of the through hole for the grant is 50 to 400 μm and the diameter of the through hole for the power source is 50 to 400 μm.



JP2003418162A 2003-12-16 2003-12-16 Multilayer printed wiring board Pending JP2005183466A (en)

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Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007115809A (en) * 2005-10-19 2007-05-10 Ngk Spark Plug Co Ltd Wiring board
JP2007128929A (en) * 2005-10-31 2007-05-24 Furukawa Electric Co Ltd:The Metal core substrate, method of manufacturing same, and electrical connection box
JP2008198867A (en) * 2007-02-14 2008-08-28 Furukawa Electric Co Ltd:The Multilayer printed wiring board having metal core
JP2008235375A (en) * 2007-03-16 2008-10-02 Furukawa Electric Co Ltd:The Metal core multilayer printed wiring board
US7497694B2 (en) 2005-12-09 2009-03-03 Ibiden Co., Ltd. Printed board with a pin for mounting a component
US7773388B2 (en) 2005-12-09 2010-08-10 Ibiden Co., Ltd. Printed wiring board with component mounting pin and electronic device using the same
US8181341B2 (en) 2005-07-07 2012-05-22 Ibiden Co., Ltd. Method of forming a multilayer printed wiring board having a bulged via
US8212363B2 (en) 2005-07-07 2012-07-03 Ibiden Co., Ltd. Multilayer printed wiring board
US8320135B2 (en) 2005-12-16 2012-11-27 Ibiden Co., Ltd. Multilayer printed circuit board
JP2012253227A (en) * 2011-06-03 2012-12-20 Shinko Electric Ind Co Ltd Wiring board and manufacturing method of the same
US8409461B2 (en) 2005-12-09 2013-04-02 Ibiden Co., Ltd. Method of manufacturing printed wiring board with component mounting pin
JP2013193123A (en) * 2012-03-22 2013-09-30 Jtekt Corp Soldering device and soldering method
US8973259B2 (en) 2005-10-14 2015-03-10 Ibiden Co., Ltd. Method for manufacturing a multilayered circuit board

Cited By (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8181341B2 (en) 2005-07-07 2012-05-22 Ibiden Co., Ltd. Method of forming a multilayer printed wiring board having a bulged via
US8481424B2 (en) 2005-07-07 2013-07-09 Ibiden Co., Ltd. Multilayer printed wiring board
JP5172340B2 (en) * 2005-07-07 2013-03-27 イビデン株式会社 Multilayer printed wiring board
US8212363B2 (en) 2005-07-07 2012-07-03 Ibiden Co., Ltd. Multilayer printed wiring board
US8973259B2 (en) 2005-10-14 2015-03-10 Ibiden Co., Ltd. Method for manufacturing a multilayered circuit board
JP2007115809A (en) * 2005-10-19 2007-05-10 Ngk Spark Plug Co Ltd Wiring board
JP2007128929A (en) * 2005-10-31 2007-05-24 Furukawa Electric Co Ltd:The Metal core substrate, method of manufacturing same, and electrical connection box
US7773388B2 (en) 2005-12-09 2010-08-10 Ibiden Co., Ltd. Printed wiring board with component mounting pin and electronic device using the same
US7891089B2 (en) 2005-12-09 2011-02-22 Ibiden Co., Ltd. Printed board with component mounting pin
US7497694B2 (en) 2005-12-09 2009-03-03 Ibiden Co., Ltd. Printed board with a pin for mounting a component
US8409461B2 (en) 2005-12-09 2013-04-02 Ibiden Co., Ltd. Method of manufacturing printed wiring board with component mounting pin
US7731504B2 (en) 2005-12-09 2010-06-08 Ibiden Co., Ltd. Printed board with component mounting pin
US8320135B2 (en) 2005-12-16 2012-11-27 Ibiden Co., Ltd. Multilayer printed circuit board
US8705248B2 (en) 2005-12-16 2014-04-22 Ibiden Co., Ltd. Multilayer printed circuit board
JP2008198867A (en) * 2007-02-14 2008-08-28 Furukawa Electric Co Ltd:The Multilayer printed wiring board having metal core
JP2008235375A (en) * 2007-03-16 2008-10-02 Furukawa Electric Co Ltd:The Metal core multilayer printed wiring board
JP2012253227A (en) * 2011-06-03 2012-12-20 Shinko Electric Ind Co Ltd Wiring board and manufacturing method of the same
JP2013193123A (en) * 2012-03-22 2013-09-30 Jtekt Corp Soldering device and soldering method

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