JPH0763109B2 - Ceramic circuit board manufacturing method - Google Patents

Ceramic circuit board manufacturing method

Info

Publication number
JPH0763109B2
JPH0763109B2 JP2877394A JP2877394A JPH0763109B2 JP H0763109 B2 JPH0763109 B2 JP H0763109B2 JP 2877394 A JP2877394 A JP 2877394A JP 2877394 A JP2877394 A JP 2877394A JP H0763109 B2 JPH0763109 B2 JP H0763109B2
Authority
JP
Japan
Prior art keywords
wiring
circuit board
ceramic circuit
fired body
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP2877394A
Other languages
Japanese (ja)
Other versions
JPH0758456A (en
Inventor
哲雄 野村
英明 荒木
Original Assignee
株式会社住友金属セラミックス
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Filing date
Publication date
Application filed by 株式会社住友金属セラミックス filed Critical 株式会社住友金属セラミックス
Priority to JP2877394A priority Critical patent/JPH0763109B2/en
Publication of JPH0758456A publication Critical patent/JPH0758456A/en
Publication of JPH0763109B2 publication Critical patent/JPH0763109B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/03Use of materials for the substrate
    • H05K1/0306Inorganic insulating substrates, e.g. ceramic, glass
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/02Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4611Manufacturing multilayer circuits by laminating two or more circuit boards
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4611Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4626Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
    • H05K3/4629Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials laminating inorganic sheets comprising printed circuits, e.g. green ceramic sheets

Description

【発明の詳細な説明】 【産業上の利用分野】本発明は実装用マザーボード、高
周波用または大電力用基板等のセラミック回路基板の製
造方法に関する。 【従来の技術】通常、上記のマザーボード、高周波用ま
たは大電力用基板等のセラミック回路基板としては、焼
成したアルミナ板に、Ag/Pd、Ag/Pt、Au等
の導体を含むペーストと絶縁用のガラスを印刷して焼成
し、配線パターンを形成させた基板(以下、厚膜法基板
と記す)が用いられている。また、セラミックグリーン
シート表面にW、Mo等の導体を含むペーストにより配
線パターンを印刷した後積層し、セラミックグリーンシ
ートと配線パターンを同時焼成することによって得られ
るセラミック回路基板(以下、同時焼成法基板と記す)
も用いられている。さらに、同時焼成によって形成され
た焼成基板の表面に、低導通抵抗形成用のペーストを印
刷し、焼成することによって作製されたセラミック回路
基板(以下、ハイブリッド基板と記す)も提案されてい
る。 【発明が解決しようとする課題】上記の回路基板の内、
厚膜法基板では、導体とガラスを積層した場合、槓層部
の耐絶縁性が低いため、複雑な回路の形成、容量素子等
の回路素子の低コストでの形成が困難であった。一方、
同時焼成法基板は、配線パターンを印刷した後焼成する
ので、配線パターンの寸法精度が悪く、また、表面に反
りあるいはうねりが生じるため、高精度の実装、例え
ば、フリップチップ方式によるIC実装用基板への適用
は難しかった。 さらに、ハイブリッド基板では、焼成
基板面に反り、うねりがあるため高精度のパターンを得
ることができないという問題があった。また、上記いず
れの基板についても、寸法精度が良く、かつ大電流を流
すことが可能な表面配線を得ることができなかった。 【発明の目的】本発明は、高い寸法精度と平坦度を有す
る表面配線と、高密度の内部配線を備えた高周波用、大
電力用等の素子を実装できる多層構造のセラミック回路
基板の製造方法を提供することを目的とする。 【課題を解決するための手段】本発明のセラミック回路
基板の製造方法は、導体ペーストからなる内部配線用パ
ターンを備えたセラミックグリーンシートを積層し、得
られたセラミックグリーンシート積層体を焼成して、内
部配線を有する焼成体を形成させた後、焼成体の表面に
表面配線を形成させるセラミック回路基板の製造方法に
おいて、焼成体の表面および/または裏面を研磨して平
坦化した後、焼成体の平坦化面に、直接接合法によって
銅板を接合することにより、表面配線を形成することを
特徴とする。また、上記製造方法において、表面配線と
なるパターンは、直接接合法によって接合された銅板
に、エッチングを施すことによって形成することを特徴
とする。さらに、上記製造方法において、直接接合法に
よって接合される銅板に、予め表面配線パターンを形成
させておくことを特徴とする。 【作用】本発明の方法では、内部配線はグリーンシート
との同時焼成によって形成し、表面配線は、焼成体の表
面に表面配線となる銅板を直接接合法によって接合して
形成する。表面配線パターンは、接合された銅板にエッ
チングを施すか、または予めエッチング等により配線パ
ターンを形成させた銅板を接合することによって形成す
る。一般に、焼成の際に積層体は収縮し、その収縮には
ばらつきが大きいため、1%程度の寸法公差が生じる。
しかし、本発明の方法では、表面配線は、積層体を焼成
し、焼成体の表面および裏面またはいずれか一面を研磨
して平坦化した後に、平坦化した面に銅板を接合するこ
とによって形成するので、表面配線パターンの寸法精度
が極めて良い。さらに、表面配線は、前述の厚膜法基
板、同時焼成法基板、ハイブリッド基板等に比較して、
厚さの厚い銅板で形成されるので、表面配線に対して大
電流を流すことができる。 【実施例】(実施例1)第1図は、本発明の方法によっ
てセラミック回路基板を製造する場合の工程を示す図で
ある。第1図の製造工程で得られる回路基板は、2枚の
グリーンシートを積層して得られる回路基板の例であ
る。この回路基板を製造する場合には、まず、大きさ1
50mm×150mm、厚み0.3mmの2枚のアルミ
ナグリーンシート1、2を用意し、目的の配線パターン
に応じたスルーホール3、4を各シートに形成する。次
に、各シートのスルーホール3、4にW、Mo等の導体
を含むペースト(以下、導体ペーストと記す)を充填す
る(第1図(a))。さらに、シート2に上記導体ペー
ストで内部配線5となる厚さ約20μmの配線パターン
を印刷する。スルーホール3、4に導体ペーストを充填
し、内部配線5となる導体パターンを印刷した状態で積
層し、積層体8を得る。この積層体8を、温度1600
℃前後、還元性雰囲気の条件下で焼成し、焼成体8を作
製する。この状態で、焼成体8には、内部にW、Mo等
の導体からなる厚さ約12μmの内部配線5が形成され
る。焼成体8の表面には、スルーホール部の導体が露出
しており、また、反り、うねりが存在することがある
(同図(b))。この反り、うねりを取り除くために、
焼成体の表面と裏面またはいずれか一面を、研磨材を用
いたバフ研磨等によって研磨して平坦化する。次に、表
面に露出したスルーホールの導体部に、必要に応じてN
i、Cu等のめっきを施した後、平坦化した面全面に、
表面配線パターンを形成するための厚さ0.3mmの銅
板6、7を直接接合法によって接合する(同図
(c))。スルーホールの導体部にめっきを施すのは、
W、Mo等の導体と銅板との接合性を高めるためであ
り、めっきがない場合でも接合することは可能である。
直接接合法に用いる銅板は、タフピッチ銅または表面に
酸化膜を形成させた無酸素銅が適している。直接接合
は、焼成体の表面に上記の銅板を配置した状態で、窒素
ガス、アルゴンガス等の不活性ガス雰囲気中で、106
5℃〜1083℃の温度で加熱すれば良い。この加熱処
理により、銅板は焼成体であるアルミナおよびスルーホ
ール部の導体と接合する。加熱による接合の際、多少の
酸素が必要であるが、タフピッチ銅は酸素を含有してい
るので、その他に酸素を供給する必要はない。また、無
酸素銅の場合には、上述のように表面に酸化膜を形成さ
せておくことによって、接合部に酸素が供給されるの
で、これ以外に酸素を供給する必要はない。次に、焼成
体に直接接合された銅板にフォトレジストを利用したエ
ッチングを施し、表面配線パターンを形成する。エッチ
ングの具体的な工程は、次のとおりである。まず、銅板
の表面に均一に液状のフォトレジストを塗布した後、フ
ォトレジスト塗布面に配線パターンに応じたパターンマ
スクを置いて、露光する。これを現像することによっ
て、配線パターン部のみにレジストを残す。この状態
で、例えば、塩化第二鉄溶液で非配線パターン部を溶解
し除去する。その後、配線パターン部に残っているレジ
ストを剥離液を用いて除去する。このようにして形成さ
れた表面配線パターン9、10は、スルーホール3、4
内の導体によって内部配線5と電気的に接続されている
(同図(d))。 (実施例2)第2図は、本発明の他の製造工程を示す図
である。実施例上と同じ工程で内部配線とそれに接続す
るスルーホール部の導体を備え、表面が研磨により平坦
化された焼成体8を得る(同図(a)、(b))。次
に、予め表面配線パターンの形状に加工した厚さ0.3
mmの銅板を直接接合法によって、焼成体8の表面に接
合する。なお、銅板および直接接合の条件は、実施例1
の場合と同じである。このようにして形成された表面配
線パターン9、10は、スルーホール3、4内の導体に
よって内部配線5と電気的に接続されている(同図
(c))。実施例1または2で得られた表面配線パター
ンには、必要に応じて厚さ3μm程度のNiめっき、さ
らにその上に厚さ1.5μm程度のAuめっきを施して
も良い。上層めっきとしてAuめっきを施すのは、素子
とのボンディング配線を行う際のボンディング性を高め
るためであり、めっき下層としてNiめっきを行うの
は、銅とAuめっきとの付着強度を高めるためである。
なお、上記実施例では、グリーンシート2枚を積層する
例を示したが、積層する枚数には特に制限はない。ま
た、内部配線には、容量素子、抵抗素子等を含ませても
良い。本発明の方法で得られるセラミック回路基板は、
焼成体の表面を平坦化した後銅板を接合するので、焼成
体と銅板の密着性が良く、接合部に非接着部(ボイド)
が生じることがない。また、高密度の内部配線と、スル
ーホールを介して接続された銅板からなる表面配線とを
備えた多層構造のセラミック回路基板が得られる。その
ために、この回路基板には次の特長がある。まず第一
に、表面が平坦であり、かつ表面配線の寸法精度が極め
て良いので、フリップチップ方式によるICの実装用基
板への適用等、寸法精度が要求される用途への活用が可
能である。第二に、厚膜法等で形成される表面配線に比
べて、厚さの厚い表面配線を形成することができるの
で、表面配線は内部配線に比べて導通抵抗が低い。した
がって、高周波用あるいは大電力用基板としての利用が
可能である。ちなみに、厚さ18〜35μmの表面配線
は、電流5mA以下でかつ周波数1〜4GHzで使用さ
れる場合に有効であるのに対し、厚さ0.3mm(本発
明の実施例)の表面配線は、25Aまでの電流が流れる
回路を構成できる。同様に、厚さ0.5mm以上の表面
配線は、30A以上の電流が流れる回路にも適用可能で
ある。一方、内部配線は、グリーンシートに印刷法で配
線パターンを被着させた後、複数枚を積層し、焼成する
ことによって形成するので、多層化、高密度化が可能で
あり、小電流用の配線に適している。したがって、大電
流用の表面配線と小電流用の内部配線を組み合わせた回
路基板とすることができため、大電流用でありながら、
コンパクトな回路基板が得られる。この他、本発明の方
法で得られる表面配線は、銅によって形成されているの
で、アルミニウム等に比べて電気特性が良く、金、銀等
に比べて安価という特長がある。さらに、表面処理なし
でも、半田付け、ボンディング等の実装が可能という利
点もある。 【発明の効果】本発明の方法によれば、印刷法で形成さ
れた内部配線と、平坦で寸法精度の良い銅板からなる表
面配線とを備えた多層構造のセラミック回路基板が得ら
れる。そのために、この回路基板は、フリップチップ方
式によるICの実装用基板への適用等、寸法精度が要求
される用途への活用が可能である。また、表面配線の導
通抵抗が低いために、高周波用あるいは大電力用基板と
しての利用が可能であるとともに、小電流用の高密度な
内部配線とを組み合わせた回路基板とすることができた
め、大電流用でありながら、コンパクトな回路基板が得
られる。この他、本発明の方法で得られる表面配線は、
銅によって形成されているので、電気特性が良く、コス
ト的にも安価という特長がある。
Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a ceramic circuit board such as a mounting mother board and a high frequency or high power board. 2. Description of the Related Art Usually, as a ceramic circuit board for the above-mentioned mother board, high frequency board or high power board, a paste containing conductors such as Ag / Pd, Ag / Pt and Au is used for insulation with a fired alumina plate. A substrate (hereinafter referred to as a thick film method substrate) on which a wiring pattern is formed by printing and baking the glass of No. 1 is used. Also, a ceramic circuit board obtained by printing a wiring pattern on the surface of the ceramic green sheet with a paste containing a conductor such as W or Mo and then laminating the ceramic green sheet and the wiring pattern at the same time (hereinafter referred to as a co-firing substrate Will be written)
Is also used. Further, a ceramic circuit board (hereinafter referred to as a hybrid board) produced by printing a paste for forming a low conductive resistance on the surface of a fired substrate formed by co-firing and firing it is also proposed. Of the above circuit boards,
In the thick film method substrate, when a conductor and glass are laminated, it is difficult to form a complicated circuit and a circuit element such as a capacitive element at low cost because the insulation resistance of the laminated layer portion is low. on the other hand,
Since the co-firing method substrate is printed and then fired after the wiring pattern is printed, the dimensional accuracy of the wiring pattern is poor, and the surface warps or undulates, so high-precision mounting, for example, a flip-chip type IC mounting substrate. Was difficult to apply to. Further, in the hybrid substrate, there is a problem that a highly accurate pattern cannot be obtained because the surface of the fired substrate is warped and undulated. Further, for any of the above-mentioned substrates, it was not possible to obtain a surface wiring having good dimensional accuracy and capable of passing a large current. SUMMARY OF THE INVENTION An object of the present invention is to provide a method of manufacturing a ceramic circuit board having a multi-layer structure in which surface wiring having high dimensional accuracy and flatness and high-density internal wiring can be mounted on devices for high frequency, large power, etc. The purpose is to provide. According to the method for manufacturing a ceramic circuit board of the present invention, a ceramic green sheet having an internal wiring pattern made of a conductor paste is laminated, and the obtained ceramic green sheet laminate is fired. In a method for manufacturing a ceramic circuit board, which comprises forming a fired body having internal wiring and then forming surface wiring on the surface of the fired body, the front and / or back surface of the fired body is polished to be flat, The surface wiring is formed by joining a copper plate to the flattened surface of 1 by a direct joining method. Further, in the above manufacturing method, the pattern to be the surface wiring is formed by etching a copper plate joined by the direct joining method. Further, in the above manufacturing method, a surface wiring pattern is formed in advance on the copper plate to be bonded by the direct bonding method. According to the method of the present invention, the internal wiring is formed by co-firing with the green sheet, and the surface wiring is formed by directly bonding the copper plate to be the surface wiring to the surface of the fired body by the direct bonding method. The surface wiring pattern is formed by etching the joined copper plates or by joining the copper plates on which the wiring patterns have been previously formed by etching or the like. In general, the laminate shrinks during firing, and the shrinkage varies widely, so a dimensional tolerance of about 1% occurs.
However, in the method of the present invention, the surface wiring is formed by firing the laminated body, polishing the surface and / or the back surface of the fired body to planarize the surface, and then joining a copper plate to the planarized surface. Therefore, the dimensional accuracy of the surface wiring pattern is extremely good. Furthermore, the surface wiring, compared to the thick film method substrate, co-firing method substrate, hybrid substrate, etc.,
Since it is formed of a thick copper plate, a large current can be applied to the surface wiring. (Embodiment 1) FIG. 1 is a diagram showing a process of manufacturing a ceramic circuit board by the method of the present invention. The circuit board obtained in the manufacturing process of FIG. 1 is an example of a circuit board obtained by laminating two green sheets. When manufacturing this circuit board, size 1
Two alumina green sheets 1 and 2 having a size of 50 mm × 150 mm and a thickness of 0.3 mm are prepared, and through holes 3 and 4 are formed in each sheet according to a target wiring pattern. Next, the through holes 3 and 4 of each sheet are filled with a paste containing a conductor such as W and Mo (hereinafter referred to as a conductor paste) (FIG. 1 (a)). Further, a wiring pattern having a thickness of about 20 μm to be the internal wiring 5 is printed on the sheet 2 with the above-mentioned conductor paste. A conductive paste is filled in the through holes 3 and 4, and a conductor pattern to be the internal wiring 5 is printed and laminated to obtain a laminated body 8. This laminated body 8 is heated to a temperature of 1600.
Firing is performed under a reducing atmosphere at a temperature of around ℃ to produce a fired body 8. In this state, inside the fired body 8, the internal wiring 5 made of a conductor such as W or Mo and having a thickness of about 12 μm is formed. On the surface of the fired body 8, the conductor of the through hole portion is exposed, and there may be warpage or undulation (FIG. 2 (b)). To remove this warp and swell,
The front and / or back of the fired body is polished and flattened by buffing or the like using an abrasive. Next, the conductor portion of the through hole exposed on the surface may be N
After plating i, Cu, etc., on the entire flattened surface,
Copper plates 6 and 7 having a thickness of 0.3 mm for forming a surface wiring pattern are joined by a direct joining method (FIG. 7C). The plating on the conductor part of the through hole is
This is to enhance the bondability between the conductor such as W and Mo and the copper plate, and it is possible to bond even without plating.
Tough pitch copper or oxygen-free copper having an oxide film formed on its surface is suitable for the copper plate used in the direct bonding method. Direct bonding is performed in a state where the above copper plate is arranged on the surface of the fired body, in an inert gas atmosphere such as nitrogen gas or argon gas,
It may be heated at a temperature of 5 ° C to 1083 ° C. By this heat treatment, the copper plate is bonded to the alumina, which is a fired body, and the conductor in the through hole portion. At the time of joining by heating, some oxygen is required, but since tough pitch copper contains oxygen, it is not necessary to supply oxygen to others. Further, in the case of oxygen-free copper, by forming an oxide film on the surface as described above, oxygen is supplied to the joint portion, so that it is not necessary to supply oxygen other than this. Next, the copper plate directly bonded to the fired body is etched using a photoresist to form a surface wiring pattern. The specific steps of etching are as follows. First, a liquid photoresist is uniformly applied to the surface of a copper plate, and then a pattern mask corresponding to the wiring pattern is placed on the photoresist application surface and exposure is performed. By developing this, the resist is left only on the wiring pattern portion. In this state, for example, the non-wiring pattern portion is dissolved and removed with a ferric chloride solution. After that, the resist remaining on the wiring pattern portion is removed using a stripping solution. The surface wiring patterns 9 and 10 thus formed have through holes 3 and 4, respectively.
It is electrically connected to the internal wiring 5 by the inner conductor ((d) of the same figure). (Embodiment 2) FIG. 2 is a diagram showing another manufacturing process of the present invention. In the same process as in the example, a fired body 8 having internal wirings and conductors of through holes connected to the internal wirings and having its surface planarized by polishing is obtained ((a) and (b) in the same figure). Next, a thickness of 0.3 which was previously processed into the shape of the surface wiring pattern
A mm copper plate is bonded to the surface of the fired body 8 by the direct bonding method. The conditions of the copper plate and the direct joining were the same as those in Example 1.
Is the same as in. The surface wiring patterns 9 and 10 thus formed are electrically connected to the internal wiring 5 by the conductors in the through holes 3 and 4 (FIG. 7C). The surface wiring pattern obtained in Example 1 or 2 may be Ni-plated with a thickness of about 3 μm and further Au-plated with a thickness of about 1.5 μm, if necessary. The Au plating as the upper layer plating is for improving the bonding property when performing the bonding wiring with the element, and the Ni plating as the plating lower layer is for increasing the adhesion strength between the copper and the Au plating. .
In the above embodiment, an example in which two green sheets are stacked is shown, but the number of stacked green sheets is not particularly limited. Further, the internal wiring may include a capacitive element, a resistive element, or the like. The ceramic circuit board obtained by the method of the present invention,
Since the copper plate is joined after the surface of the fired body is flattened, the adhesion between the fired body and the copper plate is good, and the non-bonded portion (void) is present in the joint.
Does not occur. Further, it is possible to obtain a ceramic circuit board having a multilayer structure including high-density internal wiring and surface wiring made of a copper plate connected through through holes. Therefore, this circuit board has the following features. First of all, since the surface is flat and the dimensional accuracy of the surface wiring is extremely good, it can be applied to applications where dimensional accuracy is required, such as application to IC mounting substrates by flip chip method. . Second, since the surface wiring having a thickness larger than that of the surface wiring formed by the thick film method or the like can be formed, the surface wiring has a lower conduction resistance than the internal wiring. Therefore, it can be used as a high frequency or high power substrate. By the way, the surface wiring having a thickness of 18 to 35 μm is effective when used at a current of 5 mA or less and a frequency of 1 to 4 GHz, whereas the surface wiring having a thickness of 0.3 mm (Example of the present invention) is , A circuit through which a current of up to 25 A flows can be configured. Similarly, the surface wiring having a thickness of 0.5 mm or more can be applied to a circuit in which a current of 30 A or more flows. On the other hand, the internal wiring is formed by depositing a wiring pattern on a green sheet by a printing method, stacking a plurality of sheets, and then firing them. Suitable for wiring. Therefore, it is possible to obtain a circuit board in which the surface wiring for large current and the internal wiring for small current are combined.
A compact circuit board can be obtained. In addition, since the surface wiring obtained by the method of the present invention is formed of copper, it has characteristics that it has better electric characteristics than aluminum and the like and is cheaper than gold and silver. Further, there is also an advantage that mounting such as soldering and bonding can be performed without surface treatment. According to the method of the present invention, it is possible to obtain a ceramic circuit board having a multilayer structure including internal wiring formed by a printing method and surface wiring made of a flat copper plate having a high dimensional accuracy. Therefore, this circuit board can be utilized for applications requiring dimensional accuracy, such as application to a flip-chip type IC mounting board. Further, since the conduction resistance of the surface wiring is low, it can be used as a substrate for high frequency or large power, and a circuit board in combination with high-density internal wiring for small current can be obtained. A compact circuit board can be obtained even for large currents. In addition to this, the surface wiring obtained by the method of the present invention is
Since it is made of copper, it has the advantages of good electrical characteristics and low cost.

【図面の簡単な説明】 第1図は、本発明の方法によってセラミック回路基板を
製造する場合の工程を示す断面図である。第2図は、本
発明の方法によってセラミック回路基板を製造する場合
の他の工程を示す断面図である。 記号の説明 1、2:セラミックグリーンシート、 3、4:スル
ーホール 5:内部配線、 6、7:銅
板、8:積層体、 9、1
0:表面配線
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional view showing a process of manufacturing a ceramic circuit board by the method of the present invention. FIG. 2 is a cross-sectional view showing another process for manufacturing a ceramic circuit board by the method of the present invention. Explanation of symbols 1, 2: Ceramic green sheet, 3, 4: Through hole 5: Internal wiring, 6, 7: Copper plate, 8: Laminated body, 9, 1
0: Surface wiring

Claims (1)

【特許請求の範囲】 (1)導体ペーストからなる内部配線用パターンを備え
たセラミックグリーンシートを積層し、得られたセラミ
ックグリーンシート積層体を焼成して、内部配線を有す
る焼成体を形成させた後、焼成体の表面に表面配線を形
成させるセラミック回路基板の製造方法において、前記
焼成体の表面および/または裏面を研磨して平坦化した
後、前記焼成体の平坦化面に、直接接合法によって銅板
を接合することにより、前記表面配線を形成することを
特徴とするセラミック回路基板の製造方法。 (2)直接接合法によって接合された上記銅板に、エッ
チングを施すことによって表面配線を形成することを特
徴とする請求項1記載のセラミック回路基板の製造方
法。 (3)直接接合法によって接合される上記銅板に、予め
表面配線パターンが形成されていることを特徴とする請
求項1記載のセラミック回路基板の製造方法。
(1) A ceramic green sheet having a pattern for internal wiring made of a conductor paste is laminated, and the obtained ceramic green sheet laminate is fired to form a fired body having internal wiring. After that, in a method for manufacturing a ceramic circuit board in which surface wiring is formed on the surface of the fired body, the front surface and / or the back surface of the fired body is polished and flattened, and then a direct bonding method is applied to the flattened surface of the fired body. A method of manufacturing a ceramic circuit board, wherein the surface wiring is formed by joining a copper plate with each other. (2) The method of manufacturing a ceramic circuit board according to claim 1, wherein the copper wiring plates joined by the direct joining method are subjected to etching to form surface wiring. (3) The method of manufacturing a ceramic circuit board according to claim 1, wherein a surface wiring pattern is formed in advance on the copper plate to be bonded by the direct bonding method.
JP2877394A 1994-01-14 1994-01-14 Ceramic circuit board manufacturing method Expired - Lifetime JPH0763109B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2877394A JPH0763109B2 (en) 1994-01-14 1994-01-14 Ceramic circuit board manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2877394A JPH0763109B2 (en) 1994-01-14 1994-01-14 Ceramic circuit board manufacturing method

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP26857384A Division JPS61147597A (en) 1984-12-21 1984-12-21 Ceramic circuit board and manufacture thereof

Publications (2)

Publication Number Publication Date
JPH0758456A JPH0758456A (en) 1995-03-03
JPH0763109B2 true JPH0763109B2 (en) 1995-07-05

Family

ID=12257733

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2877394A Expired - Lifetime JPH0763109B2 (en) 1994-01-14 1994-01-14 Ceramic circuit board manufacturing method

Country Status (1)

Country Link
JP (1) JPH0763109B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008034828A (en) * 2006-06-30 2008-02-14 Ngk Spark Plug Co Ltd Multilayer ceramic substrate used for integrated circuit (ic) inspection jig device, and manufacturing method of multilayer ceramic substrate

Also Published As

Publication number Publication date
JPH0758456A (en) 1995-03-03

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