JP3783493B2 - Multilayer ceramic substrate and power module substrate using the same - Google Patents

Multilayer ceramic substrate and power module substrate using the same Download PDF

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JP3783493B2
JP3783493B2 JP31382599A JP31382599A JP3783493B2 JP 3783493 B2 JP3783493 B2 JP 3783493B2 JP 31382599 A JP31382599 A JP 31382599A JP 31382599 A JP31382599 A JP 31382599A JP 3783493 B2 JP3783493 B2 JP 3783493B2
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ceramic substrate
bonded
foil
foils
multilayer ceramic
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JP2001135789A (en
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敏之 長瀬
義幸 長友
和明 久保
正一 島村
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Mitsubishi Materials Corp
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Mitsubishi Materials Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched

Abstract

PROBLEM TO BE SOLVED: To improve mounting density of a semiconductor device and effectively conduct heat. SOLUTION: In a stacked ceramic substrate 10, two or more ceramic substrates 11, 12, 13, where an Al foil is adhered to upper and lower surfaces thereof respectively are stacked and Al foils 11b, 12a, 12b, 13a in surface contact part of a ceramic substrate, are brazed to each other. Purity of Al in an Al foil 13b of an uppermost layer and an Al foil 11a of a lowermost layer is 99.900 to 99.999 wt.%, respectively, and thickness thereof is 0.1 to 1.0 mm, respectively, and Al purity of the Al foils 11b, 12a, 12b, 13a adhered to an upper surface and a lower surface of a ceramic substrate excepting an uppermost layer and the lowermost layer is 99.00 to 99.99 wt.%, respectively, and the thickness thereof is 0.1 to 0.7 mm, respectively. The ceramic substrate is constituted of one among AlN, Al2O3 and ASi3N4. The brazed Al foil forms a proscribed circuit pattern.

Description

【０００１】
【発明の属する技術分野】
本発明は、複数の半導体素子が搭載されるセラミック基板に関する。更に詳しくは、２以上のセラミック基板を積重ねて積層した積層セラミック基板及びこの積層セラミック基板をヒートシンクに積層接着したパワーモジュール用基板に関するものである。
【０００２】
【従来の技術】
図３に示すように、従来複数の半導体素子３ａ，３ｂを搭載するセラミック基板１として、ＡｌＮからなるものが知られている。このセラミック基板１の上面及び下面にはＣｕ箔がそれぞれ接着され、半導体素子３ａ，３ｂを搭載する上面のＣｕ箔をエッチング加工することによりそのセラミック基板１の上面には複数種類の導体２ａ，２ｂ，２ｃからなる所定の回路パターン２が形成される。半導体素子３ａ，３ｂの搭載は、この回路パターン２にはんだ付することにより行われ、半導体素子３ａ，３ｂの電極部はワイヤ４又は平板によりそれらの回路パターン２に接続される。
【０００３】
一方、発熱量が比較的多い半導体素子３ａ，３ｂを搭載するパワーモジュール用基板では、このセラミック基板１を図示しないヒートシンクに積層したものが一般的である。ヒートシンクは通常銅により形成され、表面にはニッケルメッキが施される。セラミック基板１のヒートシンクへの積層はセラミック基板下面に接着されたＣｕ箔をヒートシンクにはんだ付けすることにより行われる。このようにヒートシンクにセラミック基板を積層接着したパワーモジュール用基板では、半導体素子が発した熱が回路パターン２、セラミック基板１、Ｃｕ箔、はんだ及び図示しないヒートシンクを介して外部に放散されるようになっている。
【０００４】
【発明が解決しようとする課題】
しかし、上面に複数の導体２ａ，２ｂ，２ｃからなる所定の回路パターン２を形成した上記従来のセラミック基板１では、半導体素子３ａ，３ｂの実装密度を向上することに限界がある不具合がある。図３を用いて具体的に説明すると、図３における回路パターン２は第１導体２ａ、第２導体２ｂ及び第３導体２ｃからなり、二対の第１半導体素子３ａ，３ａは第１導体２ａに接着されその電極部はワイヤ４を介して第２導体２ｂに接続される。また、二対の第２半導体素子３ｂ，３ｂは第２導体２ｂに接着されその電極部はワイヤ４を介して第３導体２ｃに接続される。このような場合において実装密度を向上させるためにはそれぞれの導体２ａ，２ｂ，２ｃ自体の幅及びその導体間の間隔を狭める必要があるが、それらを狭めることには導体２ａ，２ｂ，２ｃの抵抗を高めるとともに、導体間における絶縁特性を劣化させることにもなり、それらを狭めることには限界があった。
【０００５】
また、このようなセラミック基板の下面に接着されたＣｕ箔をヒートシンクにはんだ付けすることにより積層接着した従来のパワーモジュール用基板では、はんだの熱伝導率が比較的低いため、半導体素子３ａ，３ｂが発した熱を有効にヒートシンクに伝導して放散できない不具合もある。
本発明の目的は、半導体素子の実装密度を向上し得る積層セラミック基板を提供することにある。
本発明の別の目的は、熱を有効に伝導して放散し得るパワーモジュール用基板を提供することにある。
【０００６】
【課題を解決するための手段】
請求項１に係る発明は、図１に示すように、上面及び下面にＡｌ箔１１ａ，１１ｂ，１２ａ，１２ｂ，１３ａ，１３ｂがそれぞれ接着された２以上のセラミック基板１１，１２，１３が積重ねられ、セラミック基板１１，１２，１３の面接触する部分におけるＡｌ箔１１ｂ，１２ａ，１２ｂ，１３ａが互いにろう付けされた積層セラミック基板１０である。
その特徴ある点は、最上層のセラミック基板１３上面に接着されたＡｌ箔１３ｂ及び最下層のセラミック基板１１下面に接着されたＡｌ箔１１ａのＡｌ純度がそれぞれ最上層及び最下層以外のセラミック基板の上面及び下面に接着されたＡｌ箔１１ｂ，１２ａ，１２ｂ，１３ａのＡｌ純度より高く、最最上層のセラミック基板１３上面に接着されたＡｌ箔１３ｂ及び最下層のセラミック基板１１下面に接着されたＡｌ箔１１ａの厚さを最上層及び最下層以外のセラミック基板の上面及び下面に接着されたＡｌ箔１１ｂ，１２ａ，１２ｂ，１３ａの厚さで除した値が０．８以上３以下であるところにある。
この請求項１に係る積層セラミック基板１０では、導体として機能するＡｌ箔１１ｂ，１２ｂ，１３ｂがそれぞれ異なるセラミック基板１１，１２，１３に形成されて交差することが許容される。このため、交差する導体からなる回路パターンの形成を可能にし、その回路パターンの設計の自由度が向上し、半導体素子の実装密度を高めることができる。
【０００８】
また、この積層セラミック基板１０では、Ａｌ箔は高純度であるほど塑性変形しやすいため、最上層のセラミック基板１３上面に接着されたＡｌ箔１３ｂ及び最下層のセラミック基板１１下面に接着されたＡｌ箔１１ａのＡｌ純度をそれら以外のＡｌ箔１１ｂ，１２ａ，１２ｂ，１３ａのＡｌ純度より高くすることにより、最上層及び最下層のＡｌ箔１３ｂ，１１ａの厚さがそれら以外のＡｌ箔１１ｂ，１２ａ，１２ｂ，１３ａの厚さより大きくても、作製された積層セラミック基板１０のセラミック基板１１，１２，１３間におけるＡｌ箔の厚さを均一にすることができる。また、最上層及び最下層のＡｌ箔１３ｂ，１１ａの厚さをそれら以外のＡｌ箔１１ｂ，１２ａ，１２ｂ，１３ａの厚さで除した値が０．８以上３以下であることにより、接合前のセラミック基板１１，１２，１３の反りを低減し、積層セラミック基板１０の反りを有効に防止する。
【０００９】
請求項２に係る発明は、請求項１に係る発明であって、最上層のセラミック基板１３上面に接着されたＡｌ箔１３ｂ及び最下層のセラミック基板１１下面に接着されたＡｌ箔１１ａのＡｌ純度がそれぞれ９９．９００〜９９．９９９重量％であってかつ厚さがそれぞれ０．１〜１．０ｍｍであり、最上層及び最下層以外のセラミック基板の上面及び下面に接着されたＡｌ箔１１ｂ，１２ａ，１２ｂ，１３ａのＡｌ純度がそれぞれ９９．００〜９９．９９重量％であってかつ厚さがそれぞれ０．１〜０．７ｍｍである積層セラミック基板である。
【００１０】
この請求項２に係る積層セラミック基板１０では、Ａｌ箔１１ａ，１１ｂ，１２ａ，１２ｂ，１３ａ，１３ｂのＡｌ純度及び厚さを規定することにより、積層セラミック基板１０の作成を容易にしかつ作成された積層セラミック基板１０の信頼性を向上させる。Ａｌ箔１１ａ，１１ｂ，１２ａ，１２ｂ，１３ａ，１３ｂの厚さが０．１ｍｍ未満であると電流による発熱が大きく、数十アンペア以上の電流値が必要なパワーモジュール用基板に使用することができない。最上層のセラミック基板１３上面に接着されたＡｌ箔１３ｂ及び最下層のセラミック基板１１下面に接着されたＡｌ箔１１ａの厚さが１．０ｍｍを越え、又は最上層及び最下層以外のセラミック基板の上面及び下面に接着されたＡｌ箔１１ｂ，１２ａ，１２ｂ，１３ａの厚さが０．７ｍｍを越えると、温度サイクルによりセラミック基板１１，１２，１３が割れたり、積層セラミック基板１０の接合界面に剥離が生じるおそれがある。
【００１１】
請求項３に係る発明は、請求項１又は２に係る発明であって、セラミック基板１１，１２，１３がそれぞれＡｌＮ、Ａｌ2Ｏ3又はＳｉ3Ｎ4のいずれかからなる積層セラミック基板である。
この請求項３に係る積層セラミック基板では、ＡｌＮ、Ａｌ2Ｏ3又はＳｉ3Ｎ4からなるセラミック基板１１，１２，１３を積層することにより、積層セラミック基板１０の熱伝導率、耐熱性及び強度等を向上させるとともに、積層セラミック基板１０の熱膨張率を半導体素子の熱膨張率に整合させることができる。
請求項４に係る発明は、請求項１ないし３いずれか１項に係る発明であって、ろう付けされたＡｌ箔１１ｂ，１２ａ，１２ｂ，１３ａが所定の回路パターンを形成する積層セラミック基板である。
【００１２】
この請求項４に係る積層セラミック基板では、ろう付けされたＡｌ箔１１ｂ，１２ａ，１２ｂ，１３ａにより形成される回路パターンの自由度が更に向上し、半導体素子の実装密度を更に高めることができる。
請求項５に係る発明は、請求項１ないし４いずれか１項に記載の積層セラミック基板がろう材によりヒートシンクに積層接着されたパワーモジュール用基板である。
ろう材は熱伝導率がはんだに比較して高いため、この請求項５に係るパワーモジュール用基板では、発熱量が比較的多い半導体素子を積層セラミック基板１０に搭載しても、その熱は半導体素子の下面から積層セラミック基板１０及び図示しないヒートシンクに有効に伝導され、従来に比較して半導体素子が発した熱を外部に有効に放散することができる。
【００１３】
【発明の実施の形態】
次に本発明の実施の形態を図面に基づいて詳しく説明する。
図１及び図２に示すように、本発明の積層セラミック基板１０は、第１，第２及び第３セラミック基板１１，１２，１３を積層することにより作られる。セラミック基板１１，１２，１３はそれぞれＡｌＮ、Ａｌ2Ｏ3又はＳｉ3Ｎ4のいずれかからなり、第１セラミック基板１１を最下層とし、第３セラミック基板１３を最上層とし、第２セラミック基板１２が中間層になるように積層される。最下層の第１セラミック基板１１は比較的幅の広い方形の基板であって、中間層である第２セラミック基板１２は長さが第１セラミック基板１１と同一であって、幅が第１セラミック基板１１の幅より小さく形成される。最上層である第３セラミック基板１３は長さ及び幅の双方が第２セラミック基板１２の長さ及び幅より小さく形成され、この実施の形態では２枚用意される。それぞれのセラミック基板１１，１２，１３の上面及び下面にはＡｌ箔１１ａ，１１ｂ，１２ａ，１２ｂ，１３ａ，１３ｂがそれぞれ接着される。なお、セラミック基板１１，１２，１３へのＡｌ箔１１ａ，１１ｂ，１２ａ，１２ｂ，１３ａ，１３ｂの接着は図示しないろう材を介して積層接着される。
【００１４】
最上層である第３セラミック基板１３の上面に接着されたＡｌ箔１３ｂ及び最下層である第１セラミック基板１１の下面に接着されたＡｌ箔１１ａは、そのＡｌ純度がそれぞれ９９．９００〜９９．９９９重量％であって、厚さはそれぞれ０．１〜１．０ｍｍのものが使用される。このＡｌ純度の特に好ましい値はそれぞれ９９．９８０〜９９．９９８重量％であって、厚さの好ましい値はそれぞれ０．２〜０．５ｍｍである。このため、これらＡｌ箔１３ｂ，１１ａの融点は６６０℃になる。
一方、第３セラミック基板１３の下面に接着されたＡｌ箔１３ａ、第１セラミック基板１１の上面に接着されたＡｌ箔１１ｂ及び第２セラミック基板１２の上下面に接着されたＡｌ箔１２ａ，１２ｂは、そのＡｌ純度がそれぞれ９９．００〜９９．９９重量％であって、厚さがそれぞれ０．１〜０．７ｍｍのものが使用される。そのＡｌ純度の特に好ましい値はそれぞれ９９．９０〜９９．９９重量％であって、厚さの好ましい値はそれぞれ０．１〜０．４ｍｍである。このため、これらＡｌ箔１３ａ，１１ｂ，１２ａ，１２ｂの融点は６６０℃になる。
【００１５】
最上層である第３セラミック基板１３の上面に接着されたＡｌ箔１３ｂ及び最下層である第１セラミック基板１１の下面に接着されたＡｌ箔１１ａのＡｌ純度がそれぞれ９９．９００重量％未満であるか、又は第３セラミック基板１３の下面に接着されたＡｌ箔１３ａ、第１セラミック基板１１の上面に接着されたＡｌ箔１１ｂ及び第２セラミック基板１２の上下面に接着されたＡｌ箔１２ａ，１２ｂのＡｌ純度がそれぞれ９９．００重量％未満である場合には、それらセラミック基板１１，１２，１３と積層接着されたＡｌ箔１１ａ，１１ｂ，１２ａ，１２ｂ，１３ａ，１３ｂのそれぞれの接合界面に剥離が生じるおそれがある。
【００１６】
また、最上層である第３セラミック基板１３の上面に接着されたＡｌ箔１３ｂ及び最下層である第１セラミック基板１１の下面に接着されたＡｌ箔１１ａの厚さが０．１ｍｍ未満である場合、又は第３セラミック基板１３の下面に接着されたＡｌ箔１３ａ、第１セラミック基板１１の上面に接着されたＡｌ箔１１ｂ及び第２セラミック基板１２の上下面に接着されたＡｌ箔１２ａ，１２ｂの厚さが０．１ｍｍ未満である場合には、それらのＡｌ箔１３ａ，１３ｂ，１１ａ，１１ｂ，１２ａ，１２ｂにおける電流による発熱が大きくなり、この積層セラミック基板１０を数十アンペア以上の電流値が必要なパワーモジュール用基板に使用することができない不具合がある。
【００１７】
一方、最上層のセラミック基板１３及び最下層のセラミック基板１１に接着されたＡｌ箔１３ｂ，１１ａの厚さが１．０ｍｍを越えるか、又はそれら以外のＡｌ箔１３ａ，１１ｂ，１２ａ，１２ｂの厚さが０．７ｍｍを越えると、温度サイクルによりセラミック基板１１，１２，１３が割れたり、積層セラミック基板１０の接合界面若しくはセラミック基板１１，１２，１３とそれらに積層接着されたＡｌ箔１１ａ，１１ｂ，１２ａ，１２ｂ，１３ａ，１３ｂのそれぞれの接合界面に剥離が生じるおそれがある。
【００１８】
また、最上層のセラミック基板１３上面に接着されたＡｌ箔１３ｂ及び最下層のセラミック基板１１下面に接着されたＡｌ箔１１ａのＡｌ純度は、それぞれ最上層及び最下層以外のセラミック基板の上面及び下面に接着されたＡｌ箔１１ｂ，１２ａ，１２ｂ，１３ａのＡｌ純度より高いものが使用され、最上層のセラミック基板１３上面に接着されたＡｌ箔１３ｂ及び最下層のセラミック基板１１下面に接着されたＡｌ箔１１ａの厚さを最上層及び最下層以外のセラミック基板の上面及び下面に接着されたＡｌ箔１１ｂ，１２ａ，１２ｂ，１３ａの厚さで除した値が０．８以上３以下、好ましくは１以上２以下になるように構成される。この値が０．８以上３以下であることにより、接合前のセラミック基板１１，１２，１３の反りを低減することができる。この範囲以外では基板１１，１２，１３の反り量は大きく、積層時に各基板を接合することが困難になる。
【００１９】
それぞれのセラミック基板１１，１２，１３の面接触する部分におけるＡｌ箔は互いにろう付けされる。ろう材は第３セラミック基板１３の下面に接着されたＡｌ箔１３ａ、第１セラミック基板１１の上面に接着されたＡｌ箔１１ｂ及び第２セラミック基板の上下面に接着されたＡｌ箔１２ａ，１２ｂより融点が低いＡｌ−Ｓｉ系の第１ろう材が使用される。即ち、第１ろう材は８５〜９５重量％のＡｌと５〜１５重量％のＳｉを含み、この第１ろう材１６の溶解温度範囲は５７７〜６２０℃である。セラミック基板１１，１２，１３の積層接着は、セラミック基板１１，１２，１３の面接触する部分におけるそれぞれのＡｌ箔１３ａ，１１ｂ，１２ａ，１２ｂの間にこの第１ろう材の箔を挟んだ状態でこれらに荷重０．０５〜２．００ｋｇｆ／ｃｍ2を加え、真空中で５８０〜６５０℃に加熱することにより行われる。
【００２０】
この積層セラミック基板１０には複数の半導体素子１４が搭載される。図２に詳しく示すように、二対の第１半導体素子１４ａ，１４ａは第２セラミック基板１２の上面に接着されたＡｌ箔１２ｂに接着され、その電極部はワイヤ１６を介して第３セラミック基板１３の上面に接着されたＡｌ箔１３ｂに接続される。また、二対の第２半導体素子１４ｂ，１４ｂは第３セラミック基板１３の上面に接着されたＡｌ箔１３ｂに接着され、その電極部はワイヤ１６を介して第１セラミック基板１１の上面に接着されたＡｌ箔１１ｂに接続される。ここで、第１及び第２半導体素子１４ａ，１４ａ，１４ｂ，１４ｂ及びそれらの電極部は２００〜４００℃ではんだによりそれぞれのＡｌ箔１３ｂ，１２ｂ，１１ｂに接着される。
【００２１】
このように構成された積層セラミック基板１０では、導体として機能するＡｌ箔１１ｂ，１２ｂ，１３ｂがそれぞれのセラミック基板１１，１２，１３に形成されるため、回路パターンを同一面に形成した図３に示す従来のセラミック基板に比較して半導体素子１４ａ，１４ｂの実装密度を高めることができる。即ち、それぞれのセラミック基板１１，１２，１３の導体として機能するＡｌ箔１１ｂ，１２ｂ，１３ｂは互いに異なる層に形成されるため、そのＡｌ箔１１ｂ，１２ｂ，１３ｂは交差する。この点で導体を交差させることができない図３に示す従来のセラミック基板と相違し、本発明の積層セラミック基板１０では、そのＡｌ箔１１ｂ，１２ｂ，１３ｂからなる回路パターンの自由度が向上し、従来より半導体素子１４ａ，１４ｂの実装密度を高めることができる。具体的に図３では、第２半導体素子３ｂ，３ｂの端子を接続するために必要とされた第３導体における突出部２ｄが図２における本発明では不要になり、図２における積層セラミック基板１０は図３に示すセラミック基板１より小型になる。
【００２２】
また、発熱量が比較的多い半導体素子１４ａ，１４ｂを搭載する場合には、この半導体素子１４ａ，１４ｂを搭載する積層セラミック基板１０を、熱を放散するための図示しないヒートシンクに予め積層する。この積層セラミック基板１０のヒートシンクへの接着は、積層セラミック基板１０が第１ろう材により既に積層されている関係上、その第１ろう材より溶融温度範囲が低い組成を有する第２ろう材により行われる。このように、積層セラミック基板１０をろう材によりヒートシンクに積層接着したパワーモジュール用基板では、第２ろう材の熱伝導率は、はんだの熱伝導率に比較して高いため、その後に搭載された半導体素子１４ａ，１４ｂが発した熱は、半導体素子１３の下面から積層セラミック基板１０及び図示しないヒートシンクを介して外部に有効に放散される。
【００２３】
なお、上述した実施の形態では第１、第２及び第３セラミック基板１１，１２，１３からなる３層の積層セラミック基板１０を説明したが、積層セラミック基板は、２枚のセラミック基板又は４枚のセラミック基板若しくは５枚のセラミック基板を積み重ねて２層又は４層若しくは５層からなるものであっても良い。
また、上述した実施の形態では、特にそれぞれのＡｌ箔１１ａ，１１ｂ，１２ａ，１２ｂ，１３ａ，１３ｂに回路パターンを形成しなかったが、更に複数種類の半導体素子を搭載させる場合には、ろう付けされたＡｌ箔１１ｂ，１２ａ，１２ｂ，１３ａに所定の回路パターンを形成することが好ましい。回路パターンはそれぞれのＡｌ箔をエッチングすることにより作成可能であって、エッチングはＡｌ箔にレジスト膜でマスキングを行い、この状態でセラミック基板をエッチング液に浸漬してマスキングされていない部分におけるＡｌ箔をエッチング除去することにより行われる。その後レジスト膜を除去することによりそのレジスト膜により覆われていた部分が残存して所定の回路パターンが形成される。このようにろう付けされたＡｌ箔１１ｂ，１２ａ，１２ｂ，１３ａに所定の回路パターンを形成すれば、回路パターンの自由度が更に向上し、半導体素子の実装密度を更に高めることができる。
【００２４】
【発明の効果】
以上述べたように、本発明によれば、上面及び下面にＡｌ箔がそれぞれ接着された２以上のセラミック基板を積重ね、セラミック基板の面接触する部分におけるＡｌ箔を互いにろう付けするので、導体として機能するＡｌ箔をそれぞれ異なるセラミック基板に形成することができ、交差する導体からなる回路パターンの形成を可能にし、その回路パターンの設計の自由度を向上させて半導体素子の実装密度を高めることができる。この場合、所定の要件を満たすＡｌ箔を使用することにより、積層セラミック基板の作成を容易にし、かつ作成された積層セラミック基板のセラミック基板間におけるＡｌ箔の厚さを均一にて積層セラミック基板のそりを有効に防止することができる。
【００２５】
また、ＡｌＮ、Ａｌ2Ｏ3又はＳｉ3Ｎ4からなるセラミック基板を積層すれば、積層セラミック基板の熱伝導率、耐熱性及び強度等を向上させるとともに、積層セラミック基板の熱膨張率を半導体素子の熱膨張率に整合させることができ、ろう付けされたＡｌ箔に回路パターンを形成すれば、その回路パターンの自由度は更に向上し、半導体素子の実装密度を更に高めることができる。
更に、積層セラミック基板の最下面にはＡｌ箔が接着されるので、この積層セラミック基板にヒートシンクを接着するには、熱伝導率がはんだに比較して高いろう材により行われる。このため、この積層セラミック基板をヒートシンクに積層したパワーモジュール用基板にあっては、半導体素子が発する熱を従来より外部に有効に放散することができる。
【図面の簡単な説明】
【図１】本発明の積層セラミック基板を示す図２のＡ−Ａ線断面図。
【図２】半導体素子が搭載された積層セラミック基板の斜視図。
【図３】従来例を示す図２に対応する斜視図。
【符号の説明】
１０ 積層セラミック基板
１１，１２，１３ セラミック基板
１１ａ，１１ｂ，１２ａ，１２ｂ，１３ａ，１３ｂ Ａｌ箔[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a ceramic substrate on which a plurality of semiconductor elements are mounted. More specifically, the present invention relates to a laminated ceramic substrate in which two or more ceramic substrates are stacked and laminated, and a power module substrate in which the laminated ceramic substrates are laminated and bonded to a heat sink.
[0002]
[Prior art]
As shown in FIG. 3, a conventional ceramic substrate 1 on which a plurality of semiconductor elements 3a and 3b are mounted is made of AlN. Cu foils are bonded to the upper and lower surfaces of the ceramic substrate 1, respectively, and a plurality of types of conductors 2a and 2b are formed on the upper surface of the ceramic substrate 1 by etching the upper Cu foil on which the semiconductor elements 3a and 3b are mounted. , 2c, a predetermined circuit pattern 2 is formed. The semiconductor elements 3a and 3b are mounted by soldering to the circuit pattern 2, and the electrode portions of the semiconductor elements 3a and 3b are connected to the circuit pattern 2 by wires 4 or flat plates.
[0003]
On the other hand, in a power module substrate on which semiconductor elements 3a and 3b that generate a relatively large amount of heat are mounted, this ceramic substrate 1 is generally laminated on a heat sink (not shown). The heat sink is usually made of copper, and the surface is plated with nickel. Lamination of the ceramic substrate 1 to the heat sink is performed by soldering a Cu foil bonded to the lower surface of the ceramic substrate to the heat sink. Thus, in the power module substrate in which the ceramic substrate is laminated and bonded to the heat sink, the heat generated by the semiconductor element is dissipated to the outside through the circuit pattern 2, the ceramic substrate 1, Cu foil, solder, and a heat sink (not shown). It has become.
[0004]
[Problems to be solved by the invention]
However, the above-described conventional ceramic substrate 1 on which the predetermined circuit pattern 2 composed of the plurality of conductors 2a, 2b, 2c is formed on the upper surface has a problem that there is a limit in improving the mounting density of the semiconductor elements 3a, 3b. Specifically, referring to FIG. 3, the circuit pattern 2 in FIG. 3 includes a first conductor 2a, a second conductor 2b, and a third conductor 2c, and the two pairs of first semiconductor elements 3a and 3a are the first conductor 2a. The electrode part is connected to the second conductor 2b through the wire 4. The two pairs of second semiconductor elements 3b and 3b are bonded to the second conductor 2b, and the electrode portions thereof are connected to the third conductor 2c through the wires 4. In such a case, in order to improve the mounting density, it is necessary to reduce the width of each conductor 2a, 2b, 2c itself and the interval between the conductors. To reduce them, the conductors 2a, 2b, 2c In addition to increasing the resistance, it also deteriorates the insulation characteristics between the conductors, and there is a limit to narrowing them.
[0005]
Moreover, in the conventional power module substrate in which the Cu foil bonded to the lower surface of the ceramic substrate is laminated and bonded to the heat sink, the thermal conductivity of the solder is relatively low, so that the semiconductor elements 3a and 3b There is also a problem that the heat generated by can not be effectively transferred to the heat sink and dissipated.
An object of the present invention is to provide a multilayer ceramic substrate capable of improving the mounting density of semiconductor elements.
Another object of the present invention is to provide a power module substrate capable of effectively conducting and dissipating heat.
[0006]
[Means for Solving the Problems]
In the invention according to claim 1, as shown in FIG. 1, two or more ceramic substrates 11, 12, 13 each having Al foils 11a, 11b, 12a, 12b, 13a, 13b bonded to the upper and lower surfaces are stacked. A multilayer ceramic substrate 10 in which Al foils 11b, 12a, 12b, and 13a in the surface contact portions of the ceramic substrates 11, 12, and 13 are brazed to each other.
The characteristic feature is that the Al purity of the Al foil 13b bonded to the upper surface of the uppermost ceramic substrate 13 and the Al foil 11a bonded to the lower surface of the lowermost ceramic substrate 11 are different from those of the ceramic substrates other than the uppermost layer and the lowermost layer. Al foils 11b, 12a, 12b, 13a bonded to the upper and lower surfaces of the Al foil 13b bonded to the uppermost surface of the uppermost ceramic substrate 13 and Al bonded to the lower surface of the lowermost ceramic substrate 11 The value obtained by dividing the thickness of the foil 11a by the thickness of the Al foils 11b, 12a, 12b, 13a bonded to the upper and lower surfaces of the ceramic substrate other than the uppermost layer and the lowermost layer is 0.8 or more and 3 or less. is there.
In the multilayer ceramic substrate 10 according to the first aspect, the Al foils 11b, 12b, and 13b that function as conductors are allowed to be formed on different ceramic substrates 11, 12, and 13, respectively, and intersect. For this reason, it is possible to form a circuit pattern composed of intersecting conductors, improve the degree of freedom in designing the circuit pattern, and increase the mounting density of the semiconductor elements.
[0008]
Further, in this multilayer ceramic substrate 10, the higher the purity of the Al foil, the easier the plastic deformation occurs . Therefore , the Al foil 13 b bonded to the upper surface of the uppermost ceramic substrate 13 and the Al foil bonded to the lower surface of the lowermost ceramic substrate 11. By making the Al purity of the foil 11a higher than the Al purity of the other Al foils 11b, 12a, 12b, and 13a, the thicknesses of the uppermost and lowermost Al foils 13b and 11a become the other Al foils 11b and 12a. , 12b, 13a, the thickness of the Al foil between the ceramic substrates 11, 12, 13 of the produced multilayer ceramic substrate 10 can be made uniform. In addition, the value obtained by dividing the thicknesses of the uppermost and lowermost Al foils 13b and 11a by the thicknesses of the other Al foils 11b, 12a, 12b, and 13a is 0.8 or more and 3 or less. The warpage of the ceramic substrates 11, 12, and 13 is reduced, and the warpage of the multilayer ceramic substrate 10 is effectively prevented.
[0009]
The invention according to claim 2 is the invention according to claim 1 , wherein the Al purity of the Al foil 13b bonded to the upper surface of the uppermost ceramic substrate 13 and the Al foil 11a bonded to the lower surface of the lowermost ceramic substrate 11 is obtained. Each of which is 99.900 to 99.999% by weight and has a thickness of 0.1 to 1.0 mm, and is bonded to the upper and lower surfaces of the ceramic substrate other than the uppermost layer and the lowermost layer, 12a, 12b and 13a are multilayer ceramic substrates each having an Al purity of 99.00 to 99.99% by weight and a thickness of 0.1 to 0.7 mm.
[0010]
In the multilayer ceramic substrate 10 according to the claim 2, Al foil 11a, 11b, 12a, 12b, 13a, by defining Al purity and thickness of 13b, was easily create life-and-death creation of multilayer ceramic substrate 10 The reliability of the multilayer ceramic substrate 10 is improved. If the thickness of the Al foils 11a, 11b, 12a, 12b, 13a, and 13b is less than 0.1 mm, the heat generated by the current is large and cannot be used for a power module substrate that requires a current value of several tens of amperes or more. . The thickness of the Al foil 13b bonded to the upper surface of the uppermost ceramic substrate 13 and the Al foil 11a bonded to the lower surface of the lowermost ceramic substrate 11 exceeds 1.0 mm, or the thickness of the ceramic substrate other than the uppermost layer and the lowermost layer When the thickness of the Al foils 11b, 12a, 12b, and 13a bonded to the upper surface and the lower surface exceeds 0.7 mm, the ceramic substrates 11, 12, and 13 are cracked due to the temperature cycle or peeled off at the bonding interface of the multilayer ceramic substrate 10. May occur.
[0011]
The invention according to claim 3 is the invention according to claim 1 or 2 , wherein the ceramic substrates 11, 12, and 13 are each a multilayer ceramic substrate made of any one of AlN, Al 2 O 3, and Si 3 N 4. .
In the multilayer ceramic substrate according to claim 3 , the thermal conductivity, heat resistance and strength of the multilayer ceramic substrate 10 are obtained by laminating the ceramic substrates 11, 12, and 13 made of AlN, Al 2 O 3 or Si 3 N 4. The thermal expansion coefficient of the multilayer ceramic substrate 10 can be matched with the thermal expansion coefficient of the semiconductor element.
The invention according to claim 4 is the multilayer ceramic substrate according to any one of claims 1 to 3 , wherein the brazed Al foils 11b, 12a, 12b, and 13a form a predetermined circuit pattern. .
[0012]
In the multilayer ceramic substrate according to the fourth aspect , the degree of freedom of the circuit pattern formed by the brazed Al foils 11b, 12a, 12b, and 13a is further improved, and the mounting density of the semiconductor elements can be further increased.
The invention according to claim 5 is a power module substrate in which the multilayer ceramic substrate according to any one of claims 1 to 4 is laminated and bonded to a heat sink by a brazing material.
Since the brazing material has a higher thermal conductivity than that of the solder, even if a semiconductor element having a relatively large calorific value is mounted on the multilayer ceramic substrate 10 in the power module substrate according to claim 5 , the heat is generated by the semiconductor. Effectively conducted from the lower surface of the element to the multilayer ceramic substrate 10 and a heat sink (not shown), heat generated by the semiconductor element can be effectively dissipated to the outside as compared with the conventional case.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
Next, embodiments of the present invention will be described in detail with reference to the drawings.
As shown in FIGS. 1 and 2, the multilayer ceramic substrate 10 of the present invention is made by laminating first, second and third ceramic substrates 11, 12 and 13. The ceramic substrates 11, 12, and 13 are each made of any one of AlN, Al 2 O 3 or Si 3 N 4 , the first ceramic substrate 11 is the bottom layer, the third ceramic substrate 13 is the top layer, and the second ceramic substrate. 12 are laminated so as to be an intermediate layer. The lowermost first ceramic substrate 11 is a rectangular substrate having a relatively wide width, and the second ceramic substrate 12 as an intermediate layer has the same length as the first ceramic substrate 11 and the width is the first ceramic substrate. It is formed smaller than the width of the substrate 11. The third ceramic substrate 13 which is the uppermost layer is formed so that both the length and width are smaller than the length and width of the second ceramic substrate 12, and two sheets are prepared in this embodiment. Al foils 11a, 11b, 12a, 12b, 13a, and 13b are bonded to the upper and lower surfaces of the ceramic substrates 11, 12, and 13, respectively. The Al foils 11a, 11b, 12a, 12b, 13a, and 13b are bonded to the ceramic substrates 11, 12, and 13 through a brazing material (not shown).
[0014]
The Al foil 13b bonded to the upper surface of the third ceramic substrate 13 as the uppermost layer and the Al foil 11a bonded to the lower surface of the first ceramic substrate 11 as the lowermost layer have an Al purity of 99.900 to 99.99, respectively. 999% by weight and each having a thickness of 0.1 to 1.0 mm are used. Particularly preferable values of the Al purity are 99.980 to 99.998% by weight, respectively, and preferable values of the thickness are 0.2 to 0.5 mm, respectively. For this reason, melting | fusing point of these Al foils 13b and 11a will be 660 degreeC.
On the other hand, the Al foil 13a bonded to the lower surface of the third ceramic substrate 13, the Al foil 11b bonded to the upper surface of the first ceramic substrate 11, and the Al foils 12a and 12b bonded to the upper and lower surfaces of the second ceramic substrate 12 are The Al purity is 99.00 to 99.99% by weight and the thickness is 0.1 to 0.7 mm. Particularly preferable values of the Al purity are 99.90 to 99.99% by weight, respectively, and preferable values of the thickness are 0.1 to 0.4 mm, respectively. For this reason, melting | fusing point of these Al foil 13a, 11b, 12a, 12b will be 660 degreeC.
[0015]
The Al purity of the Al foil 13b bonded to the upper surface of the third ceramic substrate 13 as the uppermost layer and the Al foil 11a bonded to the lower surface of the first ceramic substrate 11 as the lowermost layer is less than 99.900% by weight, respectively. Or Al foil 13a bonded to the lower surface of the third ceramic substrate 13, Al foil 11b bonded to the upper surface of the first ceramic substrate 11, and Al foils 12a and 12b bonded to the upper and lower surfaces of the second ceramic substrate 12. When the Al purity of each is less than 99.00% by weight, it peels off at the bonding interface of the Al foils 11a, 11b, 12a, 12b, 13a, and 13b laminated and bonded to the ceramic substrates 11, 12, and 13, respectively. May occur.
[0016]
When the thickness of the Al foil 13b bonded to the upper surface of the third ceramic substrate 13 as the uppermost layer and the thickness of the Al foil 11a bonded to the lower surface of the first ceramic substrate 11 as the lowermost layer is less than 0.1 mm Or the Al foil 13a bonded to the lower surface of the third ceramic substrate 13, the Al foil 11b bonded to the upper surface of the first ceramic substrate 11, and the Al foils 12a and 12b bonded to the upper and lower surfaces of the second ceramic substrate 12. When the thickness is less than 0.1 mm, heat generation due to current in the Al foils 13a, 13b, 11a, 11b, 12a, and 12b increases, and the multilayer ceramic substrate 10 has a current value of several tens of amperes or more. There is a problem that it cannot be used for necessary power module substrates.
[0017]
On the other hand, the thickness of the Al foils 13b, 11a bonded to the uppermost ceramic substrate 13 and the lowermost ceramic substrate 11 exceeds 1.0 mm, or the thicknesses of the other Al foils 13a, 11b, 12a, 12b. If the thickness exceeds 0.7 mm, the ceramic substrates 11, 12, and 13 are cracked due to the temperature cycle, or the bonded interface of the laminated ceramic substrate 10 or the Al foils 11 a and 11 b that are laminated and bonded to the ceramic substrates 11, 12, and 13. , 12a, 12b, 13a, and 13b, there is a possibility that peeling occurs at each bonding interface.
[0018]
Further, the Al purity of the Al foil 13b bonded to the upper surface of the uppermost ceramic substrate 13 and the Al foil 11a bonded to the lower surface of the lowermost ceramic substrate 11 is the upper surface and lower surface of the ceramic substrate other than the uppermost layer and the lowermost layer, respectively. Al foils 11b, 12a, 12b, and 13a that are bonded to the upper surface of the ceramic substrate 13 are used. The Al foil 13b that is bonded to the upper surface of the uppermost ceramic substrate 13 and the lower surface of the ceramic substrate 11 that is bonded to the lower surface are used. The value obtained by dividing the thickness of the foil 11a by the thickness of the Al foils 11b, 12a, 12b, and 13a bonded to the upper and lower surfaces of the ceramic substrate other than the uppermost layer and the lowermost layer is 0.8 to 3, preferably 1. It is configured to be 2 or less. When this value is 0.8 or more and 3 or less, warpage of the ceramic substrates 11, 12 and 13 before joining can be reduced. Outside this range, the amount of warpage of the substrates 11, 12, and 13 is large, and it becomes difficult to bond the substrates during lamination.
[0019]
The Al foils in the surface contact portions of the respective ceramic substrates 11, 12, 13 are brazed together. The brazing material is composed of an Al foil 13a bonded to the lower surface of the third ceramic substrate 13, an Al foil 11b bonded to the upper surface of the first ceramic substrate 11, and Al foils 12a and 12b bonded to the upper and lower surfaces of the second ceramic substrate 11. An Al—Si based first brazing material having a low melting point is used. That is, the first brazing material contains 85 to 95 wt% Al and 5 to 15 wt% Si, and the melting temperature range of the first brazing material 16 is 577 to 620 ° C. The laminated adhesion of the ceramic substrates 11, 12, 13 is a state in which the foil of the first brazing material is sandwiched between the respective Al foils 13 a, 11 b, 12 a, 12 b in the surface contact portions of the ceramic substrates 11, 12, 13. And a load of 0.05 to 2.00 kgf / cm 2 is added to these and heated to 580 to 650 ° C. in a vacuum.
[0020]
A plurality of semiconductor elements 14 are mounted on the multilayer ceramic substrate 10. As shown in detail in FIG. 2, the two pairs of first semiconductor elements 14 a and 14 a are bonded to an Al foil 12 b bonded to the upper surface of the second ceramic substrate 12, and the electrode portions thereof are connected to the third ceramic substrate via wires 16. 13 is connected to an Al foil 13b bonded to the upper surface of the A13. The two pairs of second semiconductor elements 14 b and 14 b are bonded to an Al foil 13 b bonded to the upper surface of the third ceramic substrate 13, and their electrode portions are bonded to the upper surface of the first ceramic substrate 11 via wires 16. Connected to the Al foil 11b. Here, the first and second semiconductor elements 14a, 14a, 14b, and 14b and their electrode portions are bonded to the respective Al foils 13b, 12b, and 11b with solder at 200 to 400 ° C.
[0021]
In the multilayer ceramic substrate 10 configured in this way, since the Al foils 11b, 12b, and 13b functioning as conductors are formed on the ceramic substrates 11, 12, and 13, respectively, the circuit pattern is formed on the same surface in FIG. The mounting density of the semiconductor elements 14a and 14b can be increased as compared with the conventional ceramic substrate shown. That is, since the Al foils 11b, 12b, and 13b that function as conductors of the ceramic substrates 11, 12, and 13 are formed in different layers, the Al foils 11b, 12b, and 13b intersect each other. In this respect, unlike the conventional ceramic substrate shown in FIG. 3 where the conductors cannot be crossed, in the multilayer ceramic substrate 10 of the present invention, the degree of freedom of the circuit pattern composed of the Al foils 11b, 12b, 13b is improved. Conventionally, the mounting density of the semiconductor elements 14a and 14b can be increased. Specifically, in FIG. 3, the protruding portion 2d in the third conductor required to connect the terminals of the second semiconductor elements 3b, 3b is not necessary in the present invention in FIG. 2, and the multilayer ceramic substrate 10 in FIG. Is smaller than the ceramic substrate 1 shown in FIG.
[0022]
When semiconductor elements 14a and 14b that generate a relatively large amount of heat are mounted, the multilayer ceramic substrate 10 on which the semiconductor elements 14a and 14b are mounted is previously stacked on a heat sink (not shown) for dissipating heat. The multilayer ceramic substrate 10 is bonded to the heat sink by a second brazing material having a composition whose melting temperature range is lower than that of the first brazing material because the multilayer ceramic substrate 10 is already laminated by the first brazing material. Is called. As described above, in the power module substrate in which the laminated ceramic substrate 10 is laminated and bonded to the heat sink with the brazing material, the thermal conductivity of the second brazing material is higher than the thermal conductivity of the solder. The heat generated by the semiconductor elements 14a and 14b is effectively dissipated from the lower surface of the semiconductor element 13 to the outside through the multilayer ceramic substrate 10 and a heat sink (not shown).
[0023]
In the above-described embodiment, the three-layered multilayer ceramic substrate 10 including the first, second, and third ceramic substrates 11, 12, and 13 has been described. However, the multilayer ceramic substrate may include two ceramic substrates or four ceramic substrates. These ceramic substrates or five ceramic substrates may be stacked to form two layers, four layers, or five layers.
In the above-described embodiment, the circuit pattern is not formed on each of the Al foils 11a, 11b, 12a, 12b, 13a, and 13b. However, when more types of semiconductor elements are mounted, brazing is performed. It is preferable to form a predetermined circuit pattern on the Al foils 11b, 12a, 12b, and 13a. The circuit pattern can be created by etching each Al foil, and the etching is performed by masking the Al foil with a resist film, and in this state, the ceramic substrate is immersed in an etching solution and the Al foil in the unmasked portion. Is removed by etching. Thereafter, by removing the resist film, a portion covered with the resist film remains and a predetermined circuit pattern is formed. If a predetermined circuit pattern is formed on the Al foils 11b, 12a, 12b, and 13a brazed in this way, the degree of freedom of the circuit pattern is further improved, and the mounting density of the semiconductor elements can be further increased.
[0024]
【The invention's effect】
As described above, according to the present invention, two or more ceramic substrates each having an Al foil bonded to the upper surface and the lower surface are stacked, and the Al foils in the surface contact portions of the ceramic substrate are brazed to each other. Functional Al foils can be formed on different ceramic substrates, enabling the formation of circuit patterns consisting of intersecting conductors, improving the design freedom of the circuit patterns and increasing the mounting density of semiconductor elements it can. In this case, the use of Al foil satisfying the predetermined requirements facilitates the production of the multilayer ceramic substrate, and the thickness of the Al foil between the ceramic substrates of the produced multilayer ceramic substrate is uniform. Sled can be effectively prevented.
[0025]
Further, if a ceramic substrate made of AlN, Al 2 O 3 or Si 3 N 4 is laminated, the thermal conductivity, heat resistance, strength, etc. of the laminated ceramic substrate are improved, and the coefficient of thermal expansion of the laminated ceramic substrate is increased to a semiconductor element. If the circuit pattern is formed on the brazed Al foil, the degree of freedom of the circuit pattern can be further improved, and the mounting density of the semiconductor elements can be further increased.
Further, since the Al foil is bonded to the lowermost surface of the multilayer ceramic substrate, the heat sink is bonded to the multilayer ceramic substrate with a brazing material having a higher thermal conductivity than that of the solder. For this reason, in the power module substrate in which the multilayer ceramic substrate is laminated on the heat sink, the heat generated by the semiconductor element can be more effectively dissipated to the outside than in the past.
[Brief description of the drawings]
1 is a cross-sectional view taken along line AA of FIG. 2 showing a multilayer ceramic substrate of the present invention.
FIG. 2 is a perspective view of a multilayer ceramic substrate on which a semiconductor element is mounted.
FIG. 3 is a perspective view corresponding to FIG. 2 showing a conventional example.
[Explanation of symbols]
10 multilayer ceramic substrates 11, 12, 13 ceramic substrates 11a, 11b, 12a, 12b, 13a, 13b Al foil

Claims (5)

上面及び下面にＡｌ箔(11a,11b,12a,12b,13a,13b)がそれぞれ接着された２以上のセラミック基板(11,12,13)が積重ねられ、前記セラミック基板(11,12,13)の面接触する部分における前記Ａｌ箔(11b,12a,12b,13a)が互いにろう付けされた積層セラミック基板であって、
最上層のセラミック基板 (13) 上面に接着されたＡｌ箔 (13b) 及び最下層のセラミック基板 (11) 下面に接着されたＡｌ箔 (11a) のＡｌ純度がそれぞれ前記最上層及び最下層以外のセラミック基板の上面及び下面に接着されたＡｌ箔 (11b,12a,12b,13a) のＡｌ純度より高く、
前記最最上層のセラミック基板 (13) 上面に接着されたＡｌ箔 (13b) 及び最下層のセラミック基板 (11) 下面に接着されたＡｌ箔 (11a) の厚さを前記最上層及び最下層以外のセラミック基板の上面及び下面に接着されたＡｌ箔 (11b,12a,12b,13a) の厚さで除した値が０．８以上３以下である
ことを特徴とする積層セラミック基板。Two or more ceramic substrates (11, 12, 13) each having an Al foil (11a, 11b, 12a, 12b, 13a, 13b) bonded to the upper and lower surfaces are stacked, and the ceramic substrates (11, 12, 13) are stacked. A multilayer ceramic substrate in which the Al foils (11b, 12a, 12b, 13a) in the surface-contacting portion are brazed together ,
The Al purity of the Al foil (13b) bonded to the upper surface of the uppermost ceramic substrate (13) and the Al foil (11a) bonded to the lower surface of the lowermost ceramic substrate (11) are other than the uppermost layer and the lowermost layer, respectively. Higher than the Al purity of the Al foil (11b, 12a, 12b, 13a) bonded to the upper and lower surfaces of the ceramic substrate ,
The thickness of the Al foil (13b) bonded to the upper surface of the uppermost ceramic substrate (13) and the thickness of the Al foil (11a) bonded to the lower surface of the lowermost ceramic substrate (11) is other than the uppermost layer and the lowermost layer. The value divided by the thickness of the Al foil (11b, 12a, 12b, 13a) bonded to the upper and lower surfaces of the ceramic substrate is 0.8 or more and 3 or less
A multilayer ceramic substrate characterized by the above . 最上層のセラミック基板(13)上面に接着されたＡｌ箔(13b)及び最下層のセラミック基板(11)下面に接着されたＡｌ箔(11a)のＡｌ純度がそれぞれ９９．９００〜９９．９９９重量％であってかつ厚さがそれぞれ０．１〜１．０ｍｍであり、
前記最上層及び最下層以外のセラミック基板の上面及び下面に接着されたＡｌ箔(11b,12a,12b,13a)のＡｌ純度がそれぞれ９９．００〜９９．９９重量％であってかつ厚さがそれぞれ０．１〜０．７ｍｍである請求項１記載の積層セラミック基板。The Al purity of the Al foil (13b) bonded to the upper surface of the uppermost ceramic substrate (13) and the Al foil (11a) bonded to the lower surface of the lowermost ceramic substrate (11) are 99.900 to 99.999 wt. % And each thickness is 0.1 to 1.0 mm,
The Al foils (11b, 12a, 12b, 13a) bonded to the upper and lower surfaces of the ceramic substrate other than the uppermost layer and the lowermost layer each have an Al purity of 99.00 to 99.99% by weight and a thickness of The multilayer ceramic substrate according to claim 1 , wherein each is 0.1 to 0.7 mm. セラミック基板(11,12,13)がそれぞれＡｌＮ、Ａｌ2Ｏ3又はＳｉ3Ｎ4のいずれかからなる請求項１又は２記載の積層セラミック基板。The multilayer ceramic substrate according to claim 1 or 2, wherein the ceramic substrate (11, 12, 13) is made of any one of AlN, Al 2 O 3 and Si 3 N 4 . ろう付けされたＡｌ箔(11b,12a,12b,13a)が所定の回路パターンを形成する請求項１ないし３いずれか１項に記載の積層セラミック基板。The multilayer ceramic substrate according to any one of claims 1 to 3, wherein the brazed Al foil (11b, 12a, 12b, 13a) forms a predetermined circuit pattern. 請求項１ないし４いずれか１項に記載の積層セラミック基板がろう材によりヒートシンクに積層接着されたパワーモジュール用基板。A power module substrate in which the multilayer ceramic substrate according to any one of claims 1 to 4 is laminated and bonded to a heat sink by a brazing material.
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