JP2015002212A - Chip resistor and packaging structure for chip resistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a chip resistor the heat dissipation of which can be improved.SOLUTION: The chip resistor includes: a resistor 2; an insulation layer 6 covering the resistor 2; a first electrode 4 electrically conducted to the resistor 2; and a second electrode 5 which is electrically conducted to the resistor and positioned on the side of a second direction X2 opposite a first direction X1 perpendicular to a thickness direction Z1 of the substrate 1 with respect to the first electrode 4. The first electrode 4 includes a first ground layer 41 in direct contact with the resistor 2, and a first plated layer 43 covering the first ground layer 41. The insulation layer is interposed between the first ground layer 41 and the resistor 2.

Description

  The present invention relates to a chip resistor and a mounting structure of the chip resistor.

  Conventionally, chip resistors used in electronic devices are known. For example, the chip resistor includes two plate-like electrodes and a resistor. The resistor is disposed on the two electrodes. For example, Patent Document 1 discloses a chip resistor.

JP 2007-142148 A

  In the conventional chip resistor, since it is necessary to maintain the strength of the chip resistor itself, the thickness of the plate-like electrode cannot be reduced too much. Therefore, the conventional chip resistor cannot be thinned. Conventionally, improvement in heat dissipation of chip resistors has also been demanded.

  The present invention has been conceived under the above circumstances, and its main object is to provide a chip resistor that can be thinned. The present invention has been conceived under the circumstances described above, and its main object is to provide a chip resistor capable of improving heat dissipation.

  According to a first aspect of the present invention, an insulating substrate, a resistor embedded in the substrate, a first electrode conducting to the resistor, and conducting to the resistor, the first A chip resistor is provided that includes, for one electrode, a second electrode located on a second direction side opposite to a first direction orthogonal to the thickness direction of the substrate.

  Preferably, the substrate has a substrate surface and a substrate main surface facing opposite to each other in the thickness direction of the substrate, and the resistor is formed from the substrate surface toward the substrate main surface. I am enthusiastic.

  Preferably, the entire resistor overlaps the substrate in the thickness direction of the substrate.

  Preferably, the substrate is in direct contact with the resistor.

  Preferably, the substrate includes a resin part and a glass fiber part located in the resin part, and the resistor is in direct contact with the glass fiber part.

  Preferably, the resin part is made of an epoxy resin.

  Preferably, the resin portion constitutes the substrate surface and the substrate main surface.

  Preferably, the maximum thickness of the substrate is 60 to 300 μm.

  Preferably, the substrate has a substrate side surface facing the first direction, the resistor has a resistor side surface facing the first direction, and the substrate side surface and the resistor side surface are It ’s just the same.

  Preferably, the side surface of the substrate is directly covered with the first electrode.

  Preferably, the resistor has a resistor surface and a resistor main surface facing opposite sides, and the resistor main surface is in direct contact with the substrate.

  Preferably, the resistor surface is flush with the substrate surface.

  Preferably, the thickness of the resistor is 50 to 200 μm.

  Preferably, an insulating layer covering the resistor is further provided.

  Preferably, the insulating layer has an insulating layer surface and an insulating layer main surface facing each other in the thickness direction of the substrate, and the insulating layer main surface is in direct contact with the substrate and the resistor. Yes.

  Preferably, the insulating layer has a portion interposed between the resistor and the first electrode and a portion interposed between the resistor and the second electrode.

  Preferably, the first electrode and the second electrode are formed on the surface of the insulating layer.

  Preferably, part of the surface of the insulating layer is exposed from the first electrode and the second electrode.

  Preferably, the insulating layer has a thermal conductivity of 1.0 W / (m · K) to 5.0 W / (m · K).

  Preferably, the insulating layer has an insulating layer end surface, the substrate has a substrate end surface, and the substrate end surface and the insulating layer end surface are both in the thickness direction of the substrate and the first direction. Are in a third direction orthogonal to each other and are flush with each other.

  Preferably, the first electrode includes a plating layer formed by plating.

  Preferably, the plating layer has a Cu layer and a Sn layer, and the Cu layer is interposed between the Sn layer and the resistor.

  Preferably, the plating layer has a Ni layer, and the Ni layer is interposed between the Cu layer and the Sn layer.

  Preferably, the first electrode includes a base layer that is in direct contact with the resistor, and the base layer is interposed between the plating layer and the resistor.

  Preferably, the base layer has a portion that overlaps the resistor in the thickness direction of the substrate and is spaced from the resistor in the thickness direction.

  Preferably, the base layer has a thickness of 100 to 500 nm.

  Preferably, the underlayer is formed by PVD, CVD, or printing.

  Preferably, the foundation layer is formed by sputtering.

  Preferably, the underlayer is made of Ni—Cr.

  Preferably, the resistor has a serpentine shape.

  Preferably, the resistor is made of manganin, geranin, a Ni—Cr alloy, a Cu—Ni alloy, or a Fe—Cr alloy.

  According to the second aspect of the present invention, a resistor, an insulating layer covering the resistor, a first electrode connected to the resistor, and a resistor connected to the resistor, On the other hand, a second electrode located on the second direction opposite to the first direction, and the first electrode comprises a base layer that is in direct contact with the resistor and a plating layer that covers the base layer. A chip resistor is provided, wherein the insulating layer is interposed between the base layer and the resistor.

  Preferably, the base layer is interposed between the plating layer and the insulating layer.

  Preferably, the dimension of the foundation layer in the first direction is not less than one quarter of the dimension of the resistor in the first direction.

  Preferably, the dimension of the foundation layer in the first direction is not less than one third of the dimension of the resistor in the first direction.

  Preferably, the dimension of the foundation layer in the first direction is 600 to 3200 μm.

  Preferably, the thickness of the base layer is thinner than the thickness of the resistor.

  Preferably, the base layer has a thickness of 100 to 500 nm.

  Preferably, the underlayer is formed by PVD, CVD, or printing.

  Preferably, the foundation layer is formed by sputtering.

  Preferably, the underlayer is made of Ni—Cr.

  Preferably, the plating layer is in direct contact with the insulating layer.

  Preferably, the plating layer is in direct contact with a portion of the insulating layer located on the second direction side with respect to the base layer.

  Preferably, the plating layer has a Cu layer and a Sn layer, and the Cu layer is interposed between the Sn layer and the resistor.

  Preferably, the plating layer has a Ni layer, and the Ni layer is interposed between the Cu layer and the Sn layer.

  Preferably, the resistor has a first resistor side face facing the first direction, the base layer has a first base layer side face facing the first direction, and the first resistor side face is The first underlayer is flush with the side surface.

  Preferably, the first resistor side surface and the first underlayer side surface are covered with the plating layer.

  Preferably, the resistor has a resistor surface and a resistor main surface facing opposite sides, and the resistor surface is in direct contact with the insulating layer.

  Preferably, the insulating layer has an insulating layer surface and an insulating layer main surface facing opposite to each other, and the insulating layer surface is in direct contact with the base layer.

  Preferably, the insulating layer has a portion interposed between the resistor and the first electrode and a portion interposed between the resistor and the second electrode.

  Preferably, the first electrode and the second electrode are formed on the surface of the insulating layer.

  Preferably, part of the surface of the insulating layer is exposed from the first electrode and the second electrode.

  Preferably, the insulating layer has a thermal conductivity of 1.0 W / (m · K) to 5.0 W / (m · K).

  Preferably, the apparatus further includes a substrate on which the resistor is disposed.

  Preferably, the substrate is made of an insulating material.

  Preferably, the substrate has a substrate end surface, the insulating layer has an insulating layer end surface, and both the substrate end surface and the insulating layer end surface are either in the thickness direction of the substrate or in the first direction. Are in a third direction orthogonal to each other and are flush with each other.

  Preferably, the substrate has a substrate surface and a substrate main surface facing opposite sides, the resistor is disposed on the substrate surface side, and the substrate main surface is exposed.

  Preferably, the thermal conductivity of the material constituting the insulating layer is larger than the thermal conductivity of the material constituting the substrate.

  Preferably, a bonding layer interposed between the substrate and the resistor is further provided.

  Preferably, the bonding layer is made of an epoxy-based material.

  Preferably, the resistor has a serpentine shape.

  Preferably, the resistor is made of manganin, geranin, a Ni—Cr alloy, a Cu—Ni alloy, or a Fe—Cr alloy.

  According to a third aspect of the present invention, a chip resistor provided by the first or second aspect of the present invention, a mounting substrate on which the chip resistor is mounted, the mounting substrate, and the chip resistor A chip resistor mounting structure is provided, comprising a conductive joint interposed between the chip resistor and the chip.

  Other features and advantages of the present invention will become more apparent from the detailed description given below with reference to the accompanying drawings.

It is sectional drawing of the mounting structure of the chip resistor concerning 1st Embodiment of this invention. FIG. 2 is an arrow view (partially see through) of the chip resistor along the line II-II in FIG. 1. FIG. 3 is a cross-sectional view of the chip resistor along the line III-III in FIGS. 1 and 2. It is sectional drawing of the chip resistor which follows the IV-IV line of FIG. 1, FIG. FIG. 3 is a diagram (partially see through) in which the first plating layer and the second plating layer are omitted from FIG. 2. FIG. 2 is a right side view (partially see through) of the chip resistor shown in FIG. 1. FIG. 2 is a left side view (partially see through) of the chip resistor shown in FIG. 1. It is a front view of the chip resistor shown in FIG. FIG. 2 is a rear view of the chip resistor illustrated in FIG. 1. It is a top view which shows one process in the manufacturing method of the chip resistor shown in FIG. It is sectional drawing which follows the XI-XI line of FIG. It is a reverse view which shows the 1 process following FIG. It is sectional drawing which follows the XIII-XIII line | wire of FIG. FIG. 13 is a back view showing one process following FIG. 12. It is sectional drawing which follows the XV-XV line | wire of FIG. FIG. 15 is a back view showing one process following FIG. 14. It is sectional drawing which follows the XVII-XVII line of FIG. It is sectional drawing which shows the 1st modification of 1st Embodiment of this invention. It is sectional drawing which shows the 2nd modification of 1st Embodiment of this invention. It is sectional drawing of the mounting structure of the chip resistor concerning 2nd Embodiment of this invention. FIG. 21 is an arrow view (partially see through) of the chip resistor along the line XXI-XXI in FIG. 20. It is sectional drawing of the chip resistor which follows the XXII-XXII line | wire of FIG. 20, FIG. It is sectional drawing of the chip resistor which follows the XXIII-XXIII line | wire of FIG. 20, FIG. FIG. 22 is a diagram (partially see through) in which the first plating layer and the second plating layer are omitted from FIG. 21. FIG. 21 is a right side view (partially see through) of the chip resistor shown in FIG. 20. FIG. 21 is a left side view (partially see through) of the chip resistor shown in FIG. 20. FIG. 21 is a front view of the chip resistor illustrated in FIG. 20. FIG. 21 is a rear view of the chip resistor illustrated in FIG. 20. It is sectional drawing which shows 1 process in the manufacturing method of the chip resistor shown in FIG. FIG. 30 is a plan view showing a step subsequent to FIG. 29. It is sectional drawing which follows the XXXI-XXXI line | wire of FIG. FIG. 31 is a back view showing one process following on from FIG. 30. It is sectional drawing which follows the XXXIII-XXXIII line | wire of FIG. FIG. 33 is a back view showing one process following on from FIG. 32. It is sectional drawing which follows the XXXV-XXXV line | wire of FIG. FIG. 35 is a rear view showing one process following FIG. 34. It is sectional drawing which follows the XXXVII-XXXVII line | wire of FIG. It is sectional drawing which shows the 1st modification of 2nd Embodiment of this invention. It is sectional drawing which shows the 2nd modification of 2nd Embodiment of this invention.

  Hereinafter, embodiments of the present invention will be specifically described with reference to the drawings.

<First Embodiment>
1st Embodiment of this invention is described using FIGS.

  FIG. 1 is a cross-sectional view of the mounting structure of the chip resistor according to the first embodiment of the present invention.

  A chip resistor mounting structure 891 shown in the figure includes a chip resistor 100, a mounting substrate 893, and a conductive joint 895.

  The mounting board 893 is, for example, a printed wiring board. The mounting substrate 893 includes, for example, an insulating substrate and a pattern electrode (not shown) formed on the insulating substrate. The insulating substrate is, for example, a glass epoxy resin substrate. The chip resistor 100 is mounted on the mounting substrate 893. A conductive junction 895 is interposed between the chip resistor 100 and the mounting substrate 893. The conductive joint portion 895 joins the chip resistor 100 and the mounting substrate 893. The conductive joint portion 895 is made of, for example, solder.

  FIG. 2 is an arrow view (partially see through) of the chip resistor along the line II-II in FIG. FIG. 3 is a cross-sectional view of the chip resistor along the line III-III in FIGS. 1 and 2. FIG. 4 is a cross-sectional view of the chip resistor along the line IV-IV in FIGS. 1 and 2. FIG. 5 is a diagram (partially see through) in which the first plating layer and the second plating layer are omitted from FIG. 6 is a right side view (partially see through) of the chip resistor shown in FIG. FIG. 7 is a left side view (partially see through) of the chip resistor shown in FIG. FIG. 8 is a front view of the chip resistor shown in FIG. FIG. 9 is a rear view of the chip resistor shown in FIG.

  A chip resistor 100 shown in these drawings includes a substrate 1, a resistor 2, a first electrode 4, a second electrode 5, and an insulating layer 6.

The substrate 1 has a plate shape. The substrate 1 is insulative or conductive. When the substrate 1 is insulative, the material constituting the substrate 1 includes, for example, resin or ceramic. When the material constituting the substrate 1 includes a resin, the resin constituting the substrate 1 is, for example, an epoxy resin. When the material constituting the substrate 1 includes a ceramic, examples of such a ceramic include Al ₂ O ₃ , AlN, and SiC. When the board | substrate 1 is electroconductivity, the material which comprises the board | substrate 1 is Cu or Ag, for example. In the present embodiment, the substrate 1 is a glass epoxy resin substrate.

  The substrate 1 has a substrate surface 11, a substrate main surface 12, a first substrate side surface 13, a second substrate side surface 14, a first substrate end surface 15, and a second substrate end surface 16.

  The substrate surface 11, the substrate main surface 12, the first substrate side surface 13, the second substrate side surface 14, the first substrate end surface 15, and the second substrate end surface 16 are all flat. As shown in FIG. 1, the vertical direction in the figure is a thickness direction Z <b> 1 of the substrate 1. Then, as shown in FIG. 2, the right direction in the figure is the first direction X1, the left direction is the second direction X2, the upper direction is the third direction X3, and the lower direction is the fourth direction X4. The maximum thickness of substrate 1 (maximum dimension in thickness direction Z1) is, for example, 60 to 300 μm. The thickness direction Z1 is orthogonal to the first direction X1, the second direction X2, the third direction X3, and the fourth direction X4. The first direction X1 and the second direction X2 are orthogonal to the third direction X3 and the fourth direction X4, respectively.

  The dimension of the chip resistor 100 in the first direction X1 is, for example, 5 to 10 mm, and the dimension of the chip resistor 100 in the third direction X3 is, for example, 2 to 10 mm.

  The substrate surface 11 and the substrate main surface 12 face opposite to each other. The first substrate side surface 13 faces the first direction X1. The second substrate side surface 14 faces the second direction X2. That is, the first substrate side surface 13 and the second substrate side surface 14 face opposite sides. The first substrate end surface 15 faces the third direction X3. The second substrate end surface 16 faces the fourth direction X4. That is, the first substrate end surface 15 and the second substrate end surface 16 face opposite sides.

  As described above, in the present embodiment, the substrate 1 is a glass epoxy resin substrate. Therefore, the substrate 1 includes a glass fiber portion 191 and a resin portion 192.

  The resin portion 192 defines the outer shape of the substrate 1. The resin part 192 is made of, for example, an epoxy resin. The resin portion 192 constitutes the substrate surface 11 and the substrate main surface 12.

  The glass fiber portion 191 is made of glass fiber. Specifically, the glass fiber part 191 is made by stacking glass fiber cloths (cloth). The glass fiber portion 191 constitutes a part of the first substrate side face 13, a part of the second substrate side face 14, a part of the first substrate end face 15, and a part of the second substrate end face 16.

  Unlike this embodiment, the substrate 1 may not be a glass epoxy resin substrate. In this case, the substrate 1 does not include the glass fiber portion 191.

  As shown in FIG. 1, the resistor 2 is disposed on the substrate 1. Specifically, the resistor 2 is disposed on the substrate surface 11 side of the substrate 1. The thickness of the resistor 2 (dimension in the thickness direction Z1 direction) is, for example, 50 to 200 μm. In this embodiment, the resistor 2 has a serpentine shape as viewed in the thickness direction Z1. It is preferable that the resistor 2 has a serpentine shape in that the resistance value of the resistor 2 can be increased. Unlike the present embodiment, the resistor 2 may not be a serpentine shape but may be a strip shape extending in the X1-X2 direction, for example. The resistor 2 is made of a metal resistance material. Examples of such a metal resistance material include manganin, zeranin, Ni—Cr alloy, Cu—Ni alloy, and Fe—Cr alloy.

  As shown in FIGS. 1 and 3, the resistor 2 includes a resistor surface 21, a resistor main surface 22, a first resistor side surface 23, and a second resistor side surface 24. The resistor surface 21, the resistor main surface 22, the first resistor side surface 23, and the second resistor side surface 24 are all flat.

  The resistor surface 21 and the resistor main surface 22 face opposite to each other. The resistor surface 21 faces in the same direction as the substrate surface 11 (that is, the downward direction in FIG. 1). On the other hand, the resistor main surface 22 faces the same direction as the direction of the substrate main surface 12 (that is, the upper direction in FIG. 1). The resistor main surface 22 faces the substrate 1. The first resistor side surface 23 faces the first direction X1. In the present embodiment, the first resistor side surface 23 is flush with the first substrate side surface 13. The second resistor side surface 24 faces the second direction X2. In the present embodiment, the second resistor side surface 24 is flush with the second substrate side surface 14.

  In the present embodiment, the resistor 2 is embedded in the substrate 1. Specifically, the chip resistor 100 has a configuration described below.

  The resistor 2 is recessed from the substrate surface 11 to the substrate 1 from the substrate surface 11 toward the substrate main surface 12. The entire resistor 2 overlaps the substrate 1 in the thickness direction Z1. The resistor 2 is in direct contact with the substrate 1. Further, in the present embodiment in which the substrate 1 is a glass epoxy resin substrate, the resistor 2 is in direct contact with the glass fiber portion 191 in the substrate 1.

  The resistor surface 21 is flush with the substrate surface 11 in the substrate 1. This is suitable for forming an insulating layer 6 described later on the resistor surface 21 and the substrate surface 11. The resistor main surface 22 is in direct contact with the substrate 1. Furthermore, in the present embodiment in which the substrate 1 is a glass epoxy resin substrate, the resistor main surface 22 is in direct contact with the glass fiber portion 191 in the substrate 1.

  Unlike this embodiment, the resistor 2 and the substrate 1 may not be in direct contact with each other. For example, the resistor 2 may be embedded in the substrate 1 with a bonding layer interposed between the resistor 2 and the substrate 1. The resistor 2 may not be in direct contact with the glass fiber portion 191.

  The insulating layer 6 covers the resistor 2. The insulating layer 6 is in direct contact with the resistor 2 and the substrate 1. The insulating layer 6 is in direct contact with the resistor surface 21 in the resistor 2 and the substrate surface 11 in the substrate 1. The insulating layer 6 exposes a portion of the resistor 2 on the first direction X1 side and a portion of the resistor 2 on the second direction X2 side. The insulating layer 6 is made of, for example, a thermosetting material. The dimension of the insulating layer 6 in the third direction X3 is the same as the dimension of the substrate 1 in the third direction X3. The maximum thickness of the insulating layer 6 (maximum dimension in the thickness direction Z1) is, for example, 20 to 60 μm. The insulating layer 6 is made of resin, for example. The insulating layer 6 is preferably made of a material having high thermal conductivity as the material constituting the insulating layer 6 in order to easily dissipate the heat generated in the resistor 2 to the outside of the chip resistor 100. The thermal conductivity of the insulating layer 6 is preferably larger than the thermal conductivity of the material constituting the substrate 1 (in this embodiment, the material constituting the resin portion 192). The thermal conductivity of the insulating layer 6 is preferably 1.0 W / (m · K) to 5.0 W / (m · K), for example.

  The insulating layer 6 includes an insulating layer surface 61, an insulating layer main surface 62, a first insulating layer side surface 63, a second insulating layer side surface 64, a first insulating layer end surface 65, a second insulating layer end surface 66, Have

  The insulating layer surface 61 and the insulating layer main surface 62 face opposite to each other. The insulating layer surface 61 faces the same direction as the direction of the resistor surface 21 (that is, the downward direction in FIG. 1). The first electrode 4 and the second electrode 5 are formed on the insulating layer surface 61. Part of the insulating layer surface 61 (a region sandwiched between the first electrode 4 and the second electrode 5 in the insulating layer surface 61) is exposed from the first electrode 4 and the second electrode 5. The insulating layer main surface 62 faces the same direction as the direction of the resistor main surface 22 (that is, the upper direction in FIG. 1). In the present embodiment, the insulating layer main surface 62 is in direct contact with the resistor 2 and the substrate 1. Specifically, the insulating layer main surface 62 is in direct contact with the resistor surface 21 and the substrate surface 11. The first insulating layer side surface 63 faces the first direction X1. The second insulating layer side surface 64 faces the second direction X2. The first insulating layer end face 65 faces the third direction X3. In the present embodiment, the first insulating layer end face 65 is flush with the first substrate end face 15. The second insulating layer end surface 66 faces the fourth direction X4. The second insulating layer end surface 66 is flush with the second substrate end surface 16.

  The first electrode 4 is electrically connected to the resistor 2. The first electrode 4 is for supplying power from the mounting substrate 893 on which the chip resistor 100 is mounted to the resistor 2. The first electrode 4 is in direct contact with the resistor 2. In the present embodiment, the first electrode 4 is in direct contact with the resistor surface 21 in the resistor 2. In the present embodiment, the first electrode 4 further covers the first resistor side surface 23 of the resistor 2 and the insulating layer 6. In the present embodiment, an insulating layer 6 is interposed between the first electrode 4 and the resistor 2. Further, in the present embodiment, the first electrode 4 does not cover the substrate main surface 12 side. Unlike the present embodiment, the first electrode 4 may cover the substrate main surface 12. As shown in FIG. 1, in the mounting structure 891, the first electrode 4 is in direct contact with the conductive bonding portion 895, and the wiring pattern (not shown) on the mounting substrate 893 is connected via the conductive bonding portion 895. Conducted.

  The first electrode 4 includes a first base layer 41 and a first plating layer 43.

  The first underlayer 41 is in direct contact with the resistor 2. In the present embodiment, the first base layer 41 is formed in order to form the first plating layer 43 on the insulating layer 6 by plating. The first base layer 41 is in direct contact with a portion of the resistor surface 21 exposed from the insulating layer 6. The first base layer 41 overlaps the resistor 2 when viewed in the thickness direction Z1 of the substrate 1. Further, the first base layer 41 has a portion that is separated from the resistor 2 in the thickness direction Z1. An insulating layer 6 is interposed between the first base layer 41 and the resistor 2. The first foundation layer 41 is interposed between the first plating layer 43 and the insulating layer 6. In the present embodiment, it is preferable that the first base layer 41 has a larger dimension in the first direction X1. Preferably, the dimension of the first base layer 41 in the first direction X1 is not less than one quarter of the dimension of the resistor 2 in the first direction X1, and more preferably, the dimension of the resistor 2 in the first direction X1. It is 1/3 or more. The dimension of the first base layer 41 in the first direction X1 is, for example, 600 to 3200 μm. The thickness of the first base layer 41 is thinner than the thickness of the resistor 2. The first underlayer 41 may be formed by PVD (Physical Vapor Deposition), CVD (Chemical Vapor Deposition), or printing. In the present embodiment, the first foundation layer 41 is formed by sputtering of PVD. The thickness of the first base layer 41 is, for example, 100 to 500 nm. The first foundation layer 41 includes, for example, Ni or Cr.

  The first underlayer 41 has a first underlayer side surface 413. The first underlayer side surface 413 faces the first direction X1. In the present embodiment, the first underlayer side surface 413 is flush with the first substrate side surface 13 and the first resistor side surface 23.

  The first plating layer 43 directly covers the first base layer 41. The first plating layer 43 is formed on the resistor 2. The first plating layer 43 is in direct contact with the insulating layer 6. The first plating layer 43 is in direct contact with a portion of the insulating layer 6 that is located on the second direction X2 side with respect to the first base layer 41. In the chip resistor 100 before being mounted on the mounting substrate 893, the first plating layer 43 is exposed to the outside. Therefore, as shown in FIG. 1, in the mounting structure 891, the first plating layer 43 is in direct contact with the conductive bonding portion 895, and the wiring pattern (illustrated) on the mounting substrate 893 is interposed via the conductive bonding portion 895. Abbreviation). In the present embodiment, the first plating layer 43 covers the first resistor side surface 23 of the resistor 2. This is preferable in that a solder fillet can be formed at the conductive joint 895.

  Specifically, in the present embodiment, the first plating layer 43 includes a Cu layer 43a, a Ni layer 43b, and a Sn layer 43c. The Cu layer 43a directly covers the first underlayer 41. The Ni layer 43b directly covers the Cu layer 43a. The Sn layer 43c directly covers the Ni layer 43b. The Sn layer 43c is exposed to the outside. In the mounting structure 891 of the chip resistor 100, the conductive junction 895 (solder in this embodiment) adheres to the Sn layer 43c. The thickness of the Cu layer 43a is, for example, 10 to 50 μm, the thickness of the Ni layer 43b is, for example, 1 to 10 μm, and the thickness of the Sn layer 43c is, for example, 1 to 10 μm. Unlike the present embodiment, the first plating layer 43 may not include the Ni layer 43b.

  The second electrode 5 is located on the second direction X2 side with respect to the first electrode 4. The second electrode 5 is electrically connected to the resistor 2. The second electrode 5 is for supplying power from the mounting substrate 893 on which the chip resistor 100 is mounted to the resistor 2. The second electrode 5 is in direct contact with the resistor 2. In the present embodiment, the second electrode 5 is in direct contact with the resistor surface 21 in the resistor 2. In the present embodiment, the second electrode 5 further covers the second resistor side surface 24 of the resistor 2 and the insulating layer 6. In the present embodiment, an insulating layer 6 is interposed between the second electrode 5 and the resistor 2. Further, in the present embodiment, the second electrode 5 does not cover the substrate main surface 12 side. Unlike the present embodiment, the second electrode 5 may cover the substrate main surface 12. As shown in FIG. 1, in the mounting structure 891, the second electrode 5 is in direct contact with the conductive bonding portion 895, and a wiring pattern (not shown) on the mounting substrate 893 is connected via the conductive bonding portion 895. Conducted.

  The second electrode 5 includes a second base layer 51 and a second plating layer 53.

  The second underlayer 51 is in direct contact with the resistor 2. In the present embodiment, the second underlayer 51 is formed in order to form the second plating layer 53 on the insulating layer 6 by plating. The second underlayer 51 is in direct contact with a portion of the resistor surface 21 exposed from the insulating layer 6. An insulating layer 6 is interposed between the second base layer 51 and the resistor 2. The second foundation layer 51 is interposed between the second plating layer 53 and the insulating layer 6. In the present embodiment, it is preferable that the second underlayer 51 has a larger dimension in the second direction X2. Preferably, the dimension of the second base layer 51 in the second direction X2 is not less than one quarter of the dimension of the resistor 2 in the second direction X2, and more preferably, the dimension of the resistor 2 in the second direction X2. It is 1/3 or more. The dimension of the second base layer 51 in the second direction X2 is, for example, 600 to 3200 μm. The thickness of the second foundation layer 51 is thinner than the thickness of the resistor 2. The second underlayer 51 may be formed by PVD (Physical Vapor Deposition), CVD (Chemical Vapor Deposition), or printing. In the present embodiment, the second underlayer 51 is formed by sputtering of PVD. The thickness of the second foundation layer 51 is, for example, 0.5 to 1.0 nm. The second underlayer 51 includes, for example, Ni or Cr.

  The second underlayer 51 has a second underlayer side surface 514. The second underlayer side surface 514 faces the second direction X2. In the present embodiment, the second underlayer side surface 514 is flush with the second substrate side surface 14 and the second resistor side surface 24.

  The second plating layer 53 directly covers the second base layer 51. The second plating layer 53 is formed on the resistor 2. The second plating layer 53 is in direct contact with the insulating layer 6. The second plating layer 53 is in direct contact with a portion of the insulating layer 6 that is located closer to the first direction X1 than the second base layer 51. In the chip resistor 100 before being mounted on the mounting substrate 893, the second plating layer 53 is exposed to the outside. Therefore, as shown in FIG. 1, in the mounting structure 891, the second plating layer 53 is in direct contact with the conductive bonding portion 895, and the wiring pattern (illustrated) on the mounting substrate 893 is interposed via the conductive bonding portion 895. Abbreviation). In the present embodiment, the second plating layer 53 covers the second resistor side surface 24 of the resistor 2. This is preferable in that a solder fillet can be formed at the conductive joint 895.

  Specifically, in the present embodiment, the second plating layer 53 includes a Cu layer 53a, a Ni layer 53b, and a Sn layer 53c. The Cu layer 53a directly covers the second underlayer 51. The Ni layer 53b directly covers the Cu layer 53a. The Sn layer 53c directly covers the Ni layer 53b. The Sn layer 53c is exposed to the outside. In the mounting structure 891 of the chip resistor 100, the conductive junction 895 (solder in this embodiment) adheres to the Sn layer 53c. The thickness of the Cu layer 53a is, for example, 10 to 50 μm, the thickness of the Ni layer 53b is, for example, 1 to 10 μm, and the thickness of the Sn layer 53c is, for example, 1 to 10 μm. Unlike the present embodiment, the second plating layer 53 may not include the Ni layer 53b.

  Next, a method for manufacturing the chip resistor 100 will be briefly described.

  First, as shown in FIGS. 10 and 11, a collective sheet 850 is prepared. The aggregate sheet 850 includes a substrate sheet 810 and a resistance aggregate 820. In the present embodiment, the aggregate sheet 850 is formed in a state where the resistance aggregate 820 is embedded in the substrate sheet 810. The aggregate sheet 850 is formed using, for example, a vacuum press. In the assembly sheet 850, the resistance assembly 820 is completely fixed to the substrate sheet 810.

  The substrate sheet 810 is the substrate 1 described above. The resistor assembly 820 is the resistor 2 described above. Therefore, in the aggregate sheet 850, the resistance aggregate 820 is in direct contact with the glass fiber portion 191.

  Further, the resistance assembly 820 has a plurality of portions to be the above-described resistor 2. In this embodiment, in order to form the serpentine-like resistor 2, a plurality of serpentine-like portions are previously formed in the resistor assembly 820 by etching or punching dies.

  Next, the resistance value of the resistor 2 in the resistor assembly 820 is adjusted. The resistance value of the resistor 2 is adjusted by, for example, grinding the resistor assembly 820.

  Next, as shown in FIGS. 12 and 13, an insulating film 860 is formed. The insulating film 860 becomes the above-described insulating layer 6. The insulating film 860 is formed in a plurality of strips extending along one direction. The insulating film 860 is formed by printing or coating, for example. A part of the resistance assembly 820 is exposed from the insulating film 860.

  Next, as shown in FIGS. 14 and 15, a conductive material 840 is stacked on the resistance assembly 820. The conductive material 840 becomes the first underlayer 41 or the second underlayer 51 described above. In the step of laminating the conductive material 840, PVD or CVD is used, and PVD used for laminating the conductive material 840 includes, for example, sputtering. In the present embodiment, in the step of laminating the conductive material 840, the conductive material 840 is laminated so as to form a strip shape along the direction in which the insulating film 860 extends. Therefore, part of the insulating film 860 is exposed from the stacked conductive material 840. Note that in order to stack the conductive material 840 so as to have a strip shape, for example, masking may be performed. The conductive material 840 is, for example, Ni or Cr.

  Next, as shown in FIGS. 16 and 17, a plurality of solid pieces 886 are obtained by cutting the resistance assembly 820. In the present embodiment, the aggregate sheet 850 (the resistance aggregate 820 and the substrate sheet 810) is cut together. In order to obtain the solid piece 886, for example, punching or dicing is performed. In this embodiment, punching is performed to obtain the solid piece 886.

  By cutting when obtaining the solid piece 886, the first substrate side surface 13, the second substrate side surface 14, the first substrate end surface 15, the second substrate end surface 16, the first resistor side surface 23, the second resistor side surface 24, A first underlayer side surface 413, a second underlayer side surface 514, a first insulating layer end surface 65, and a second insulating layer end surface 66 are formed. By cutting the substrate sheet 810, the resistance assembly 820, and the like at the same time, the first substrate side surface 13, the first resistor side surface 23, and the first base layer side surface 413 are flush with each other. Similarly, the substrate sheet 810, the resistor assembly 820, and the like are cut at the same time, so that the second substrate side surface 14, the second resistor side surface 24, and the second underlayer side surface 514 are flush with each other. Become. Similarly, by this cutting, the first substrate end face 15 and the first insulating layer end face 65 are flush with each other. Similarly, the second substrate end face 16 and the second insulating layer end face 66 are flush with each other by this cutting.

  Next, on the solid piece 886, the first plating layer 43 (Cu layer 43a, Ni layer 43b, and Sn layer 43c) shown in FIG. 1, and the second plating layer 53 (Cu layer 53a, Ni layer 53b, and Sn layer 53c) is formed. For example, barrel plating is used to form the first plating layer 43 and the second plating layer 53. Through the above steps, the manufacture of the chip resistor 100 is completed.

  Next, the effect of this embodiment is demonstrated.

  In the present embodiment, the resistor 2 is embedded in the substrate 1. According to such a configuration, it is possible to reduce the overall size of the assembly of the substrate 1 and the resistor 2 in the thickness direction Z1 of the substrate 1. Thereby, the chip resistor 100 can be thinned.

  Further, when the chip resistor 100 is manufactured, the assembly sheet 850 in which the resistance assembly 820 is embedded in the substrate sheet 810 can be used. Therefore, in order to manufacture the chip resistor 100, it is only necessary to prepare the assembly sheet 850, and it is possible to reduce the trouble of attaching the resistance assembly 820 to the substrate sheet 810. This contributes to the efficiency of manufacturing the chip resistor 100.

  In the present embodiment, the thermal conductivity of the insulating layer 6 is 1.0 W / (m · K) to 5.0 W / (m · K), which is relatively large. According to such a configuration, it is easy to release the heat generated in the resistor 2 to the outside of the chip resistor 100 via the insulating layer 6. Therefore, it is possible to prevent the chip resistor 100 from being excessively heated.

  In the present embodiment, the first electrode 4 includes a first foundation layer 41 that is in direct contact with the resistor 2 and a first plating layer 43 that covers the first foundation layer 41. The insulating layer 6 is interposed between the first base layer 41 and the resistor 2. According to such a configuration, the first plating layer 43 can be easily formed on the insulating layer 6. Therefore, the area of the first electrode 4 can be increased. If the area of the first electrode 4 can be increased, the heat generated in the resistor 2 can be easily released to the mounting substrate 893 via the first electrode 4. That is, the heat dissipation of the chip resistor 100 can be improved.

  In the present embodiment, the substrate 1 is made of an insulating material. In such a configuration, it is not necessary to use a relatively thick Cu electrode. Therefore, the trouble of processing the Cu electrode can be reduced. This contributes to the efficiency of manufacturing the chip resistor 100.

  In the present embodiment, both the substrate 1 and the mounting substrate 893 are glass epoxy resin substrates. In such a configuration, the thermal expansion coefficients of the substrate 1 and the mounting substrate 893 are almost the same. Therefore, even if the substrate 1 is thermally expanded during use of the chip resistor 100, the mounting substrate 893 is considered to be thermally expanded at the same rate. Therefore, the malfunction (for example, chip resistor 100 breaks) which may arise by the influence of thermal expansion during use of chip resistor 100 can be prevented.

<First Modification of First Embodiment>
A first modification of the first embodiment of the present invention will be described with reference to FIG.

  FIG. 18 is a cross-sectional view showing a first modification of the first embodiment of the present invention.

  The chip resistor 101 shown in the figure is different from the chip resistor 100 in that the first resistor side surface 23 of the resistor 2 and the second resistor side surface 24 of the resistor 2 are covered with the substrate 1. Mainly different. Since the other points are the same as those of the chip resistor 100, description thereof is omitted.

  The chip resistor 101 also has the same effects as described for the chip resistor 100.

<Second Modification of First Embodiment>
A second modification of the first embodiment of the present invention will be described with reference to FIG.

  FIG. 19 is a cross-sectional view showing a second modification of the first embodiment of the present invention.

  In the chip resistor 102 shown in the figure, the first plating layer 43 has a surface flush with the first underlayer side surface 413 of the first underlayer 41, and the second plating layer 53 has The second base layer 51 is mainly different from the chip resistor 100 in that the second base layer 51 has a surface flush with the second base layer side surface 514. Since the other points are the same as those of the chip resistor 100, description thereof is omitted. In order to manufacture the chip resistor 102, a plating layer is formed before the cutting process of the assembly sheet 850 described with reference to FIGS.

  The chip resistor 102 also provides the same operational effects as described for the chip resistor 100.

Second Embodiment
A second embodiment of the present invention will be described with reference to FIGS.

  FIG. 20 is a cross-sectional view of the chip resistor mounting structure according to the second embodiment of the present invention.

  The chip resistor mounting structure 892 shown in the figure includes a chip resistor 200, a mounting substrate 893, and a conductive joint 895.

  Since the description described in the first embodiment can be applied to the mounting substrate 893 and the conductive bonding portion 895, the description is omitted in this embodiment.

  FIG. 21 is an arrow view (partially see through) of the chip resistor along the line XXI-XXI in FIG. 20. FIG. 22 is a cross-sectional view of the chip resistor along the line XXII-XXII of FIGS. FIG. 23 is a cross-sectional view of the chip resistor along the line XXIII-XXIII in FIGS. 20 and 21. FIG. 24 is a diagram (partially see through) in which the first plating layer and the second plating layer are omitted from FIG. 25 is a right side view (partially see through) of the chip resistor shown in FIG. FIG. 26 is a left side view (partially see through) of the chip resistor shown in FIG. FIG. 27 is a front view of the chip resistor shown in FIG. FIG. 28 is a rear view of the chip resistor shown in FIG.

  A chip resistor 200 shown in these drawings includes a substrate 1, a resistor 2, a bonding layer 3, a first electrode 4, a second electrode 5, and an insulating layer 6.

The substrate 1 has a plate shape. The substrate 1 is insulative or conductive. When the substrate 1 is insulative, the material constituting the substrate 1 includes, for example, resin or ceramic. When the material constituting the substrate 1 includes a resin, the resin constituting the substrate 1 is, for example, an epoxy resin. When the material constituting the substrate 1 includes a ceramic, examples of such a ceramic include Al ₂ O ₃ , AlN, and SiC. When the board | substrate 1 is electroconductivity, the material which comprises the board | substrate 1 is Cu or Ag, for example. In the present embodiment, the substrate 1 is a glass epoxy resin substrate.

  The substrate 1 has a substrate surface 11, a substrate main surface 12, a first substrate side surface 13, a second substrate side surface 14, a first substrate end surface 15, and a second substrate end surface 16.

  The substrate surface 11, the substrate main surface 12, the first substrate side surface 13, the second substrate side surface 14, the first substrate end surface 15, and the second substrate end surface 16 are all flat. As shown in FIG. 20, the vertical direction in FIG. Then, as shown in FIG. 21, the right direction in FIG. 21 is the first direction X1, the left direction is the second direction X2, the upper direction is the third direction X3, and the lower direction is the fourth direction X4. The maximum thickness of substrate 1 (maximum dimension in thickness direction Z1) is, for example, 60 to 300 μm. The thickness direction Z1 is orthogonal to the first direction X1, the second direction X2, the third direction X3, and the fourth direction X4. The first direction X1 and the second direction X2 are orthogonal to the third direction X3 and the fourth direction X4, respectively.

  In addition, the dimension in the 1st direction X1 of the chip resistor 200 is 5-10 mm, for example, and the dimension in the 3rd direction X3 of the chip resistor 200 is 2-10 mm, for example.

  The substrate surface 11 and the substrate main surface 12 face opposite to each other. The first substrate side surface 13 faces the first direction X1. The second substrate side surface 14 faces the second direction X2. That is, the first substrate side surface 13 and the second substrate side surface 14 face opposite sides. The first substrate end surface 15 faces the third direction X3. The second substrate end surface 16 faces the fourth direction X4. That is, the first substrate end surface 15 and the second substrate end surface 16 face opposite sides.

  As shown in FIG. 20, the resistor 2 is disposed on the substrate 1. Specifically, the resistor 2 is disposed on the substrate surface 11 side of the substrate 1. The thickness of the resistor 2 (dimension in the thickness direction Z1 direction) is, for example, 50 to 200 μm. In this embodiment, the resistor 2 has a serpentine shape as viewed in the thickness direction Z1. It is preferable that the resistor 2 has a serpentine shape in that the resistance value of the resistor 2 can be increased. Unlike the present embodiment, the resistor 2 may not be a serpentine shape but may be a strip shape extending in the X1-X2 direction, for example. The resistor 2 is made of a metal resistance material. Examples of such a metal resistance material include manganin, zeranin, Ni—Cr alloy, Cu—Ni alloy, and Fe—Cr alloy.

  As shown in FIGS. 21 and 22, the resistor 2 has a resistor surface 21, a resistor main surface 22, a first resistor side surface 23, and a second resistor side surface 24. The resistor surface 21, the resistor main surface 22, the first resistor side surface 23, and the second resistor side surface 24 are all flat.

  The resistor surface 21 and the resistor main surface 22 face opposite to each other. The resistor surface 21 faces the same direction as the substrate surface 11 faces (that is, the downward direction in FIG. 20). On the other hand, the resistor main surface 22 faces the same direction as the direction of the substrate main surface 12 (that is, the upward direction in FIG. 20). The resistor main surface 22 faces the substrate 1. The first resistor side surface 23 faces the first direction X1. In the present embodiment, the first resistor side surface 23 is flush with the first substrate side surface 13. The second resistor side surface 24 faces the second direction X2. In the present embodiment, the second resistor side surface 24 is flush with the second substrate side surface 14.

  The bonding layer 3 is interposed between the substrate 1 and the resistor 2. Specifically, the bonding layer 3 is interposed between the substrate surface 11 in the substrate 1 and the resistor 2. The bonding layer 3 bonds the resistor 2 to the substrate surface 11. The bonding layer 3 is preferably made of an insulating material. An example of such an insulating material is an epoxy-based material. The thickness (dimension in the thickness direction Z1) of the bonding layer 3 is, for example, 30 to 100 μm. As shown in FIGS. 20 and 22, in the present embodiment, the bonding layer 3 covers the entire surface of the substrate 11.

  Unlike the present embodiment, the bonding layer 3 may be formed only on a part of the substrate surface 11. For example, the bonding layer 3 may be formed only in a region of the substrate surface 11 that overlaps the resistor 2.

  As shown in FIGS. 20 and 22, the bonding layer 3 has a bonding layer surface 31 and a bonding layer main surface 32 that face opposite sides. The bonding layer surface 31 faces the same direction as the substrate surface 11 faces (that is, the downward direction in FIG. 20). The bonding layer surface 31 is in direct contact with the resistor 2. The bonding layer main surface 32 is in direct contact with the substrate 1.

  The insulating layer 6 covers the resistor 2. The insulating layer 6 is disposed on the resistor 2 and the substrate 1 via the bonding layer 3. The insulating layer 6 is in direct contact with the resistor surface 21 in the resistor 2. The insulating layer 6 exposes a portion of the resistor 2 on the first direction X1 side and a portion of the resistor 2 on the second direction X2 side. The insulating layer 6 is made of, for example, a thermosetting material. The dimension of the insulating layer 6 in the third direction X3 is the same as the dimension of the substrate 1 in the third direction X3. The maximum thickness of the insulating layer 6 (maximum dimension in the thickness direction Z1) is, for example, 60 to 150 μm. The insulating layer 6 is made of resin, for example. For the insulating layer 6, it is preferable to use a material having a high thermal conductivity as a material constituting the insulating layer 6 in order to easily dissipate heat generated in the resistor 2 to the outside of the chip resistor 200. The thermal conductivity of the insulating layer 6 is preferably larger than the thermal conductivity of the material constituting the substrate 1. The thermal conductivity of the insulating layer 6 is preferably 1.0 W / (m · K) to 5.0 W / (m · K), for example.

  The insulating layer 6 includes an insulating layer surface 61, an insulating layer main surface 62, a first insulating layer side surface 63, a second insulating layer side surface 64, a first insulating layer end surface 65, a second insulating layer end surface 66, Have

  The insulating layer surface 61 and the insulating layer main surface 62 face opposite to each other. The insulating layer surface 61 faces the same direction as the direction of the resistor surface 21 (that is, the downward direction in FIG. 20). The first electrode 4 and the second electrode 5 are formed on the insulating layer surface 61. Part of the insulating layer surface 61 (a region sandwiched between the first electrode 4 and the second electrode 5 in the insulating layer surface 61) is exposed from the first electrode 4 and the second electrode 5. The insulating layer main surface 62 faces the same direction as the direction of the resistor main surface 22 (that is, the upward direction in FIG. 20). In this embodiment, it is in direct contact with the bonding layer 3. Specifically, the insulating layer main surface 62 is in direct contact with the bonding layer surface 31. The first insulating layer side surface 63 faces the first direction X1. The second insulating layer side surface 64 faces the second direction X2. The first insulating layer end face 65 faces the third direction X3. In the present embodiment, the first insulating layer end face 65 is flush with the first substrate end face 15. The second insulating layer end surface 66 faces the fourth direction X4. The second insulating layer end surface 66 is flush with the second substrate end surface 16.

  The first electrode 4 is electrically connected to the resistor 2. The first electrode 4 is for supplying power from the mounting substrate 893 on which the chip resistor 200 is mounted to the resistor 2. The first electrode 4 is in direct contact with the resistor 2. In the present embodiment, the first electrode 4 is in direct contact with the resistor surface 21 in the resistor 2. In the present embodiment, the first electrode 4 further covers the first resistor side surface 23 of the resistor 2 and the insulating layer 6. In the present embodiment, an insulating layer 6 is interposed between the first electrode 4 and the resistor 2. Further, in the present embodiment, the first electrode 4 does not cover the substrate main surface 12 side. Unlike the present embodiment, the first electrode 4 may cover the substrate main surface 12. As shown in FIG. 20, in the mounting structure 892, the first electrode 4 is in direct contact with the conductive bonding portion 895, and the wiring pattern (not shown) on the mounting substrate 893 is connected via the conductive bonding portion 895. Conducted.

  As shown in FIG. 20, the first electrode 4 includes a first foundation layer 41 and a first plating layer 43.

  The first underlayer 41 is in direct contact with the resistor 2. In the present embodiment, the first base layer 41 is formed in order to form the first plating layer 43 on the insulating layer 6 by plating. The first base layer 41 is in direct contact with a portion of the resistor surface 21 exposed from the insulating layer 6. The first base layer 41 overlaps the resistor 2 when viewed in the thickness direction Z1 of the substrate 1. Further, the first base layer 41 has a portion that is separated from the resistor 2 in the thickness direction Z1. An insulating layer 6 is interposed between the first base layer 41 and the resistor 2. The first foundation layer 41 is interposed between the first plating layer 43 and the insulating layer 6. In the present embodiment, it is preferable that the first base layer 41 has a larger dimension in the first direction X1. Preferably, the dimension of the first base layer 41 in the first direction X1 is not less than one quarter of the dimension of the resistor 2 in the first direction X1, and more preferably, the dimension of the resistor 2 in the first direction X1. It is 1/3 or more. The dimension of the first base layer 41 in the first direction X1 is, for example, 600 to 3200 μm. The thickness of the first base layer 41 is thinner than the thickness of the resistor 2. The first underlayer 41 may be formed by PVD (Physical Vapor Deposition), CVD (Chemical Vapor Deposition), or printing. In the present embodiment, the first foundation layer 41 is formed by sputtering of PVD. The thickness of the first base layer 41 is, for example, 0.5 to 1.0 nm. The first foundation layer 41 includes, for example, Ni or Cr.

  The first underlayer 41 has a first underlayer side surface 413. The first underlayer side surface 413 faces the first direction X1. In the present embodiment, the first underlayer side surface 413 is flush with the first substrate side surface 13 and the first resistor side surface 23.

  The first plating layer 43 directly covers the first base layer 41. The first plating layer 43 is formed on the resistor 2. The first plating layer 43 is in direct contact with the insulating layer 6. The first plating layer 43 is in direct contact with a portion of the insulating layer 6 that is located on the second direction X2 side with respect to the first base layer 41. In the chip resistor 200 before being mounted on the mounting substrate 893, the first plating layer 43 is exposed to the outside. Therefore, as shown in FIG. 20, in the mounting structure 892, the first plating layer 43 is in direct contact with the conductive bonding portion 895, and the wiring pattern (illustrated) on the mounting substrate 893 is interposed via the conductive bonding portion 895. Abbreviation). In the present embodiment, the first plating layer 43 covers the first resistor side surface 23 of the resistor 2. This is preferable in that a solder fillet can be formed at the conductive joint 895.

  Specifically, in the present embodiment, the first plating layer 43 includes a Cu layer 43a, a Ni layer 43b, and a Sn layer 43c. The Cu layer 43a directly covers the first underlayer 41. The Ni layer 43b directly covers the Cu layer 43a. The Sn layer 43c directly covers the Ni layer 43b. The Sn layer 43c is exposed to the outside. In the mounting structure 892 of the chip resistor 200, the conductive junction 895 (solder in this embodiment) adheres to the Sn layer 43c. The thickness of the Cu layer 43a is, for example, 10 to 50 μm, the thickness of the Ni layer 43b is, for example, 1 to 10 μm, and the thickness of the Sn layer 43c is, for example, 1 to 10 μm. Unlike the present embodiment, the first plating layer 43 may not include the Ni layer 43b.

  The second electrode 5 is located on the second direction X2 side with respect to the first electrode 4. The second electrode 5 is electrically connected to the resistor 2. The second electrode 5 is for supplying power from the mounting substrate 893 on which the chip resistor 200 is mounted to the resistor 2. The second electrode 5 is in direct contact with the resistor 2. In the present embodiment, the second electrode 5 is in direct contact with the resistor surface 21 in the resistor 2. In the present embodiment, the second electrode 5 further covers the second resistor side surface 24 of the resistor 2 and the insulating layer 6. In the present embodiment, an insulating layer 6 is interposed between the second electrode 5 and the resistor 2. Further, in the present embodiment, the second electrode 5 does not cover the substrate main surface 12 side. Unlike the present embodiment, the second electrode 5 may cover the substrate main surface 12. As shown in FIG. 20, in the mounting structure 892, the second electrode 5 is in direct contact with the conductive bonding portion 895, and the wiring pattern (not shown) on the mounting substrate 893 is connected via the conductive bonding portion 895. Conducted.

  As shown in FIG. 20, the second electrode 5 includes a second foundation layer 51 and a second plating layer 53.

  The second underlayer 51 is in direct contact with the resistor 2. In the present embodiment, the second underlayer 51 is formed in order to form the second plating layer 53 on the insulating layer 6 by plating. The second underlayer 51 is in direct contact with a portion of the resistor surface 21 exposed from the insulating layer 6. An insulating layer 6 is interposed between the second base layer 51 and the resistor 2. The second foundation layer 51 is interposed between the second plating layer 53 and the insulating layer 6. In the present embodiment, it is preferable that the second underlayer 51 has a larger dimension in the second direction X2. Preferably, the dimension of the second base layer 51 in the second direction X2 is not less than one quarter of the dimension of the resistor 2 in the second direction X2, and more preferably, the dimension of the resistor 2 in the second direction X2. It is 1/3 or more. The dimension of the second base layer 51 in the second direction X2 is, for example, 600 to 3200 μm. The thickness of the second foundation layer 51 is thinner than the thickness of the resistor 2. The second underlayer 51 may be formed by PVD (Physical Vapor Deposition), CVD (Chemical Vapor Deposition), or printing. In the present embodiment, the second underlayer 51 is formed by sputtering of PVD. The thickness of the second foundation layer 51 is, for example, 0.5 to 1.0 nm. The second underlayer 51 includes, for example, Ni or Cr.

  The second underlayer 51 has a second underlayer side surface 514. The second underlayer side surface 514 faces the second direction X2. In the present embodiment, the second underlayer side surface 514 is flush with the second substrate side surface 14 and the second resistor side surface 24.

  The second plating layer 53 directly covers the second base layer 51. The second plating layer 53 is formed on the resistor 2. The second plating layer 53 is in direct contact with the insulating layer 6. The second plating layer 53 is in direct contact with a portion of the insulating layer 6 that is located closer to the first direction X1 than the second base layer 51. In the chip resistor 200 before being mounted on the mounting substrate 893, the second plating layer 53 is exposed to the outside. Therefore, as shown in FIG. 20, in the mounting structure 892, the second plating layer 53 is in direct contact with the conductive bonding portion 895, and the wiring pattern (illustrated) on the mounting substrate 893 is interposed via the conductive bonding portion 895. Abbreviation). In the present embodiment, the second plating layer 53 covers the second resistor side surface 24 of the resistor 2. This is preferable in that a solder fillet can be formed at the conductive joint 895.

  Specifically, in the present embodiment, the second plating layer 53 includes a Cu layer 53a, a Ni layer 53b, and a Sn layer 53c. The Cu layer 53a directly covers the second underlayer 51. The Ni layer 53b directly covers the Cu layer 53a. The Sn layer 53c directly covers the Ni layer 53b. The Sn layer 53c is exposed to the outside. In the mounting structure 892 of the chip resistor 200, the conductive junction 895 (solder in this embodiment) adheres to the Sn layer 53c. The thickness of the Cu layer 53a is, for example, 10 to 50 μm, the thickness of the Ni layer 53b is, for example, 1 to 10 μm, and the thickness of the Sn layer 53c is, for example, 1 to 10 μm. Unlike the present embodiment, the second plating layer 53 may not include the Ni layer 53b.

  Next, a method for manufacturing the chip resistor 200 will be briefly described.

First, as shown in FIG. 29, a substrate sheet 810 is prepared. The substrate sheet 810 becomes the substrate 1 described above. The substrate sheet 810 is made of an insulating material. The substrate sheet 810 is made of ceramic or resin. Examples of the ceramic include Al ₂ O ₃ , AlN, and SiC. The substrate sheet 810 has a sheet surface 811 and a sheet back surface 812 that face opposite sides.

  Next, as shown in FIGS. 30 and 31, a bonding material 830 is bonded to the sheet surface 811 of the substrate sheet 810. The bonding material 830 becomes the above-described bonding layer 3. In the present embodiment, the bonding material 830 is a heat conductive adhesive sheet. In the state shown in FIG. 31, the bonding material 830 is temporarily thermocompression bonded to the sheet surface 811 of the substrate sheet 810.

  Next, as shown in FIGS. 30 and 31, the resistance assembly 820 is bonded to the sheet surface 811 with a bonding material 830. In the present embodiment, the resistance assembly 820 is temporarily bonded to the bonding material 830 in the state shown in FIGS. The resistor assembly 820 has a plurality of portions that should become the resistor 2 described above. In this embodiment, a plurality of serpentine-like portions are formed on the resistance assembly 820 by etching or punching dies before the resistance assembly 820 is joined to the sheet surface 811 in order to form the serpentine-like resistor 2. ing. Next, the resistance assembly 820 is subjected to trimming processing (not shown). This is for adjusting the resistance value of the resistor 2. The trimming process is performed using, for example, a laser, sandblast, dicer, grinder, or the like.

  Unlike the present embodiment, in order to join the resistance assembly 820 to the sheet surface 811 of the substrate sheet 810, a liquid adhesive may be used as the joining material 830 without using a sheet-like member.

  Next, as shown in FIGS. 32 and 33, an insulating film 860 is formed. The insulating film 860 becomes the above-described insulating layer 6. The insulating film 860 is formed in a plurality of strips extending along one direction. The insulating film 860 is formed by printing or coating, for example. A part of the resistance assembly 820 is exposed from the insulating film 860.

  Next, as shown in FIGS. 34 and 35, a conductive material 840 is stacked on the resistance assembly 820. The conductive material 840 becomes the first underlayer 41 or the second underlayer 51 described above. In the step of laminating the conductive material 840, PVD or CVD is used, and PVD used for laminating the conductive material 840 includes, for example, sputtering. In the present embodiment, in the step of laminating the conductive material 840, the conductive material 840 is laminated so as to form a strip shape along the direction in which the insulating film 860 extends. Therefore, part of the insulating film 860 is exposed from the stacked conductive material 840. Note that in order to stack the conductive material 840 so as to have a strip shape, for example, masking may be performed. The conductive material 840 is, for example, Ni or Cr.

  Next, as shown in FIGS. 36 and 37, a plurality of solid pieces 886 are obtained by cutting the resistance assembly 820. In this embodiment, the resistance assembly 820 and the substrate sheet 810 are cut together. In order to obtain the solid piece 886, for example, punching or dicing is performed. In this embodiment, punching is performed to obtain the solid piece 886.

  By cutting when obtaining the solid piece 886, the first substrate side surface 13, the second substrate side surface 14, the first substrate end surface 15, the second substrate end surface 16, the first resistor side surface 23, the second resistor side surface 24, A first underlayer side surface 413, a second underlayer side surface 514, a first insulating layer end surface 65, and a second insulating layer end surface 66 are formed. By cutting the substrate sheet 810, the resistance assembly 820, and the like at the same time, the first substrate side surface 13, the first resistor side surface 23, and the first base layer side surface 413 are flush with each other. Similarly, the substrate sheet 810, the resistor assembly 820, and the like are cut at the same time, so that the second substrate side surface 14, the second resistor side surface 24, and the second underlayer side surface 514 are flush with each other. Become. Similarly, by this cutting, the first substrate end face 15 and the first insulating layer end face 65 are flush with each other. Similarly, the second substrate end face 16 and the second insulating layer end face 66 are flush with each other by this cutting.

  Next, on the solid piece 886, the first plating layer 43 (Cu layer 43a, Ni layer 43b, and Sn layer 43c) and the second plating layer 53 (Cu layer 53a, Ni layer 53b, and Sn layer 53c) is formed. For example, barrel plating is used to form the first plating layer 43 and the second plating layer 53. Through the above steps, the manufacture of the chip resistor 200 is completed.

  Next, the effect of this embodiment is demonstrated.

  In the present embodiment, the thermal conductivity of the insulating layer 6 is 1.0 W / (m · K) to 5.0 W / (m · K), which is relatively large. According to such a configuration, it is easy to release the heat generated in the resistor 2 to the outside of the chip resistor 200 via the insulating layer 6. Therefore, it is possible to prevent the chip resistor 200 from becoming excessively high temperature.

  In the present embodiment, the first electrode 4 includes a first foundation layer 41 that is in direct contact with the resistor 2 and a first plating layer 43 that covers the first foundation layer 41. The insulating layer 6 is interposed between the first base layer 41 and the resistor 2. According to such a configuration, the first plating layer 43 can be easily formed on the insulating layer 6. Therefore, the area of the first electrode 4 can be increased. If the area of the first electrode 4 can be increased, the heat generated in the resistor 2 can be easily released to the mounting substrate 893 via the first electrode 4. That is, the heat dissipation of the chip resistor 200 can be improved. Thereby, it can prevent that the chip resistor 200 becomes high temperature too much.

  In the present embodiment, the substrate 1 is made of an insulating material. In such a configuration, it is not necessary to use a relatively thick Cu electrode. Therefore, the trouble of processing the Cu electrode can be reduced. This contributes to efficient manufacturing of the chip resistor 200.

  In the present embodiment, both the substrate 1 and the mounting substrate 893 are glass epoxy resin substrates. In such a configuration, the thermal expansion coefficients of the substrate 1 and the mounting substrate 893 are almost the same. Therefore, even if the substrate 1 is thermally expanded during use of the chip resistor 200, the mounting substrate 893 is considered to thermally expand at the same rate. Therefore, the malfunction (for example, chip resistor 200 breaks) which may arise by the influence of thermal expansion during use of chip resistor 200 can be prevented.

<First Modification of Second Embodiment>
A first modification of the second embodiment of the present invention will be described with reference to FIG.

  FIG. 38 is a cross-sectional view showing a first modification of the second embodiment of the present invention.

  The chip resistor 201 shown in the figure is similar to the chip resistor 200 in that the first resistor side surface 23 of the resistor 2 and the second resistor side surface 24 of the resistor 2 are covered with the substrate 1. Mainly different. Since the other points are the same as those of the chip resistor 200, the description thereof is omitted.

  The chip resistor 201 also provides the same operational effects as described for the chip resistor 200.

<Second Modification of Second Embodiment>
A second modification of the second embodiment of the present invention will be described with reference to FIG.

  FIG. 39 is a cross-sectional view showing a second modification of the second embodiment of the present invention.

  In the chip resistor 202 shown in the figure, the first plating layer 43 has a surface flush with the first underlayer side surface 413 of the first underlayer 41, and the second plating layer 53 has The second base layer 51 is mainly different from the chip resistor 200 in that the second base layer 51 has a surface flush with the second base layer side surface 514. Since the other points are the same as those of the chip resistor 200, the description thereof is omitted. In order to manufacture the chip resistor 202, a plating layer is formed before the cutting process of the substrate 1 sheet 810 and the resistor assembly 820 described with reference to FIGS.

  The chip resistor 202 also provides the same operational effects as described for the chip resistor 200.

  The present invention is not limited to the embodiment described above. The specific configuration of each part of the present invention can be changed in various ways.

DESCRIPTION OF SYMBOLS 1 Substrate 100, 101, 102, 200, 201, 202 Chip resistor 11 Substrate surface 12 Substrate main surface 13 First substrate side surface 14 Second substrate side surface 15 First substrate end surface 16 Second substrate end surface 191 Glass fiber portion 192 Resin portion 2 resistor 21 resistor surface 22 resistor main surface 23 first resistor side surface 24 second resistor side surface 3 bonding layer 31 bonding layer surface 32 bonding layer main surface 4 first electrode 41 first underlayer 413 first underlayer Side surface 43 First plating layer 43a Cu layer 43b Ni layer 43c Sn layer 5 Second electrode 51 Second underlayer 514 Second underlayer side surface 53 Second plating layer 53a Cu layer 53b Ni layer 53c Sn layer 6 Insulating layer 61 Insulating layer Surface 62 Insulating layer main surface 63 First insulating layer side surface 64 Second insulating layer side surface 65 First insulating layer end surface 66 Second insulating layer end surface 810 Substrate sheet 811 Sheet surface 812 Sheet back surface 20 Resistance assembly 830 Bonding material 840 Conductive material 850 Assembly sheet 860 Insulating film 886 Solid pieces 891, 892 Mounting structure 893 Mounting substrate 895 Conductive bonding portion X1 First direction X2 Second direction X3 Third direction X4 Fourth direction Z1 Thickness direction

Claims (32)

A resistor,
An insulating layer covering the resistor;
A first electrode connected to the resistor;
A second electrode that is electrically connected to the resistor and is located on a second direction side opposite to the first direction with respect to the first electrode;
The first electrode includes a base layer that is in direct contact with the resistor, and a plating layer that covers the base layer,
The insulating layer is a chip resistor interposed between the base layer and the resistor.   The chip resistor according to claim 1, wherein the base layer is interposed between the plating layer and the insulating layer.   3. The chip resistor according to claim 1, wherein a dimension of the base layer in the first direction is not less than one quarter of a dimension of the resistor in the first direction.   3. The chip resistor according to claim 1, wherein a dimension of the base layer in the first direction is one third or more of a dimension of the resistor in the first direction.   The chip resistor according to claim 1, wherein a dimension of the base layer in the first direction is 600 to 3200 μm.   The chip resistor according to claim 1, wherein a thickness of the base layer is thinner than a thickness of the resistor.   The chip resistor according to claim 1, wherein a thickness of the underlayer is 0.5 to 1.0 nm.   The chip resistor according to claim 1, wherein the underlayer is formed by PVD, CVD, or printing.   The chip resistor according to claim 1, wherein the underlayer is formed by sputtering.   The chip resistor according to claim 1, wherein the underlayer is made of Ni—Cr.   The chip resistor according to claim 1, wherein the plating layer is in direct contact with the insulating layer.   12. The chip resistor according to claim 1, wherein the plating layer is in direct contact with a portion of the insulating layer that is located on the second direction side with respect to the base layer. The plating layer has a Cu layer and a Sn layer,
The chip resistor according to claim 1, wherein the Cu layer is interposed between the Sn layer and the resistor. The plating layer has a Ni layer,
The chip resistor according to claim 13, wherein the Ni layer is interposed between the Cu layer and the Sn layer. The resistor has a first resistor side surface facing the first direction,
The underlayer has a first underlayer side surface facing the first direction,
The chip resistor according to claim 1, wherein the first resistor side surface is flush with the first underlayer side surface.   The chip resistor according to claim 15, wherein the first resistor side surface and the first underlayer side surface are covered with the plating layer. The resistor has a resistor surface and a resistor main surface facing opposite sides,
The chip resistor according to claim 1, wherein the resistor surface is in direct contact with the insulating layer. The insulating layer has an insulating layer surface and an insulating layer main surface facing opposite sides,
The chip resistor according to claim 1, wherein the surface of the insulating layer is in direct contact with the base layer.   The said insulating layer has either the site | part interposed between the said resistor and the said 1st electrode, and the site | part interposed between the said resistor and the said 2nd electrode. Chip resistor according to.   The chip resistor according to claim 18, wherein the first electrode and the second electrode are formed on a surface of the insulating layer.   The chip resistor according to claim 20, wherein a part of the surface of the insulating layer is exposed from the first electrode and the second electrode.   The chip resistor according to any one of claims 1 to 21, wherein the thermal conductivity of the insulating layer is 1.0 W / (m · K) to 5.0 W / (m · K).   The chip resistor according to claim 1, further comprising a substrate on which the resistor is disposed.   The chip resistor according to claim 23, wherein the substrate is made of an insulating material. The substrate has a substrate end surface;
The insulating layer has an insulating layer end face;
The substrate end surface and the insulating layer end surface both face a third direction orthogonal to both the thickness direction of the substrate and the first direction, and are flush with each other. Or the chip resistor of Claim 24. The substrate has a substrate surface and a substrate main surface facing away from each other;
The resistor is arranged on the substrate surface side,
26. The chip resistor according to claim 23, wherein the substrate main surface is exposed.   27. The chip resistor according to claim 23, wherein the material constituting the insulating layer has a thermal conductivity greater than that of the material constituting the substrate.   The chip resistor according to claim 23, further comprising a bonding layer interposed between the substrate and the resistor.   The chip resistor according to claim 28, wherein the bonding layer is made of an epoxy-based material.   30. The chip resistor according to claim 1, wherein the resistor has a serpentine shape.   The chip resistor according to any one of claims 1 to 30, wherein the resistor is made of manganin, geranin, a Ni-Cr alloy, a Cu-Ni alloy, or a Fe-Cr alloy. A chip resistor according to any one of claims 1 to 31,
A mounting substrate on which the chip resistor is mounted;
A chip resistor mounting structure comprising: a conductive joint interposed between the mounting substrate and the chip resistor.

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