JP3872401B2 - Wiring board - Google Patents

Wiring board Download PDF

Info

Publication number
JP3872401B2
JP3872401B2 JP2002242201A JP2002242201A JP3872401B2 JP 3872401 B2 JP3872401 B2 JP 3872401B2 JP 2002242201 A JP2002242201 A JP 2002242201A JP 2002242201 A JP2002242201 A JP 2002242201A JP 3872401 B2 JP3872401 B2 JP 3872401B2
Authority
JP
Japan
Prior art keywords
connection pad
melting point
low melting
brazing material
wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2002242201A
Other languages
Japanese (ja)
Other versions
JP2004087518A (en
Inventor
拓 松寺
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP2002242201A priority Critical patent/JP3872401B2/en
Publication of JP2004087518A publication Critical patent/JP2004087518A/en
Application granted granted Critical
Publication of JP3872401B2 publication Critical patent/JP3872401B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]

Landscapes

  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Description

【０００１】
【発明の属する技術分野】
本発明は半導体素子やコンデンサ、抵抗器等の電子部品が搭載される配線基板に関するものである。
【０００２】
【従来の技術】
従来、電子部品、例えば、半導体素子が搭載される配線基板は、酸化アルミニウム質焼結体やガラスセラミック焼結体等の電気絶縁材料から成り、その表面に半導体素子が搭載される搭載部を有する絶縁基体と、該絶縁基体の半導体素子搭載部またはその周辺から下面にかけて導出されている、例えば、タングステンやモリブデン等の高融点金属粉末から成る複数個の配線導体と、絶縁基体の下面に形成され、前記配線導体と電気的に接続されている複数個の接続パッドとから構成されており、絶縁基体の搭載部に半導体素子をガラス、樹脂、ロウ材等から成る接着材を介して接着固定させるとともに半導体素子の各電極をボンディングワイヤ等の電気的接続手段を介して配線導体に電気的に接続し、しかる後、必要に応じて前記半導体素子を蓋体や封止樹脂で気密封止させることによって半導体装置となる。
【０００３】
かかる半導体装置は、外部電気回路基板上に、該外部電気回路基板の回路配線と絶縁基体下面の接続パッドとが、間に錫−鉛半田等の低融点ロウ材を挟んで対向するよう載置させ、しかる後、前記低融点ロウ材を約２００℃〜３００℃の温度で加熱溶融させ、外部電気回路基板の回路配線と絶縁基体下面の接続パッドとを接合させることによって外部電気回路基板上に実装され、同時に配線基板に搭載されている半導体素子の各電極も配線導体および低融点ロウ材を介して外部電気回路基板に電気的に接続される。
【０００４】
【発明が解決しようとする課題】
しかしながら、上記従来の半導体素子が搭載される配線基板は絶縁基体が酸化アルミニウム質焼結体等のセラミックス材料で形成されており、その熱膨張係数が約４×１０-6／℃〜１０×１０-6／℃であるのに対し、外部電気回路基板は一般にガラスエポキシ樹脂等の樹脂材で形成されており、その熱膨張係数が３０×１０-6／℃〜５０×１０-6／℃であり大きく相違すること、接続パッドは一般に円形状もしくは楕円形状をなしており、接続パッドと低融点ロウ材との接合面の外縁部も同様の円形状、楕円形状等の線状をなしていること等から外部電気回路基板上に半導体装置を実装した後、半導体素子の作動時に発する熱が配線基板の絶縁基体と外部電気回路基板に繰り返し作用すると、両者間に両者の熱膨張係数の差に起因して水平方向に大きな熱応力が繰り返し生じるとともにこの熱応力が接続パッドの外周縁に沿って線状に集中し、その結果、接続パッドと外部電気回路基板とを接合する低融点ロウ材の前記接続パッドとの界面付近の外縁部に亀裂が生じるとともにこれが前記界面に沿って進行し、最終的には低融点ロウ材に破断が発生し、半導体素子と外部電気回路との電気的接続が短期間で破れてしまうという問題があった。
【０００５】
特に、低融点ロウ材として、従来の錫−鉛半田に代わり、錫−銀−ビスマス系等の鉛非含有半田が用いられるようになると、このような鉛非含有半田は、ビスマス等の成分の偏析により接続パッドに対する接合強度が低くなりやすいため、低融点ロウ材の破断の発生がより顕著なものとなってしまう。
【０００６】
本発明は、従来の配線基板における上記問題点に鑑み案出されたもので、その目的は、絶縁基体の接続パッドと外部電気回路基板の回路配線とを接合する低融点ロウ材に破断が発生するのを有効に防止し、半導体素子等の電子部品の各電極を外部電気回路に長期間にわたり確実、強固に電気的接続することができる長期信頼性に優れた配線基板を提供することにある。
【０００７】
【課題を解決するための手段】
本発明は、電気絶縁材料から成り、表面に電子部品が搭載される搭載部を有する絶縁基体と、該絶縁基体の下面に形成されている多数の接続パッドと、前記絶縁基体の前記搭載部から前記接続パッドにかけて導出されている複数個の配線導体とから成る配線基板であって、前記各接続パッドは外周縁部分のみがメッシュ状であることを特徴とするものである。
【０００８】
本発明の配線基板によれば、接続パッドの外周縁部分のみをメッシュ状としたことから、接続パッドと低融点ロウ材との接合面の外縁部を入り組んだ形状とすることができ、外部電気回路基板上に実装した後、配線基板の絶縁基体と外部電気回路基板に熱が繰り返し作用し、両者間に両者の熱膨張係数の差に起因して水平方向に大きな熱応力が繰り返し生じたとしても、この熱応力はメッシュ状とされた接続パッドの外周縁に沿って分散されるため集中することはなく、同時に、メッシュ部分の側面部分で、接続パッドと低融点ロウ材との接合面は、熱応力が作用する方向に対してほぼ直角方向となって熱応力に対する耐性が大きくなり、その結果、接続パッドと外部電気回路基板とを接合する低融点ロウ材の接続パッドとの界面付近の外縁部に亀裂が生じることはほとんどなく、低融点ロウ材として鉛フリー半田を使用したとしても、低融点ロウ材に短期間で破断が生じることはなく、これによって接続パッドと外部電気回路基板の回路配線とを確実、強固に電気的接続することができるとともに電子部品の各電極と外部電気回路との接続を長期信頼性に優れたものとなすことが可能となる。
【０００９】
【発明の実施の形態】
次に本発明を添付の図面を基にして詳細に説明する。
【００１０】
図１及び図2は、本発明の配線基板を半導体素子収納用パッケージに適用した場合の一実施例を示す断面図及び底面図であり、１は絶縁基体、２は配線導体である。この絶縁基体１と配線導体２とで半導体素子３を搭載する配線基板４が構成される。
【００１１】
前記絶縁基体１は、酸化アルミニウム質焼結体、窒化アルミニウム質焼結体、ムライト質焼結体、炭化珪素質焼結体、ガラスセラミック焼結体等の電気絶縁材料から成り、その上面に半導体素子３が搭載収容される凹状の収納部１ａを有し、該収納部１ａ底面には半導体素子３がガラスや樹脂、ロウ材等の接着材を介して接着固定される。
【００１２】
前記絶縁基体１は、例えば、酸化アルミニウム質焼結体から成る場合、酸化アルミニウム、酸化珪素、酸化カルシウム、酸化マグネシウム等の原料粉末に適当な有機バインダー、溶剤を添加混合して泥漿状のセラミックスラリーとなすとともに該セラミックスラリーを従来周知のドクターブレード法やカレンダーロール法等のシート成型技術を採用してシート状のセラミックグリーンシート（セラミック生シート）を得、しかる後、前記セラミックグリーンシートを切断加工や打ち抜き加工により適当な形状とするとともにこれを複数枚積層し、最後に前記積層されたセラミックグリーンシートを還元雰囲気中、約１６００℃の温度で焼成することによって製作される。
【００１３】
また前記絶縁基体１は、その収納部１ａ周辺から下面にかけて多数の配線導体２が被着形成されており、該配線導体２の収納部１ａ周辺部位には半導体素子３の各電極がボンディングワイヤ５を介して電気的に接続され、また絶縁基体１下面に導出された部位には配線導体２と電気的に接続する複数の接続パッド６が形成されている。
【００１４】
前記配線導体２および接続パッド６は、半導体素子３の電極を外部電気回路に接続する作用をなし、例えば、タングステン、モリブデン、マンガン等の高融点金属粉末から成り、タングステン等の高融点金属粉末に適当な有機バインダーや溶剤を添加混合して得た金属ペーストを絶縁基体１となるセラミックグリーンシートに予め従来周知のスクリーン印刷法により所定パターンに印刷塗布しておくことによって、絶縁基体１の収納部１ａ周辺から下面にかけて被着形成される。
【００１５】
また前記接続パッド６は、配線基板４を外部電気回路基板に実装する外部端子として作用し、低融点ロウ材を介して外部電気回路基板の回路配線に接合され、これにより半導体素子３の電極が外部電気回路基板の回路配線と電気的に接続される。
【００１６】
本発明においては、図３に示すように、前記接続パッド６の外周縁部分６ａのみをメッシュ状としておくことが重要である。
【００１７】
このように接続パッド６の外周縁部分６ａのみをメッシュ状としておくと、接続パッド６と低融点ロウ材との接合面の外縁部を入り組んだ形状とすることができ、外部電気回路基板上に半導体装置を実装した後、半導体素子３の作動時に発する熱が配線基板４の絶縁基体１と外部電気回路基板に繰り返し作用し、両者間に両者の熱膨張係数の差に起因して水平方向に大きな熱応力が繰り返し生じたとしても、この熱応力はメッシュ状とされた接続パッド６の外周縁に沿って分散されるため集中することはなく、低融点ロウ材として鉛フリー半田を使用したとしても、低融点ロウ材の接続パッド６との界面付近の外縁部から亀裂が生じることを効果的に防止することができる。
【００１８】
また同時に、接続パッド６の外周縁部分６ａのみをメッシュ状としておくと、このメッシュ状の部分、例えば網目状のパターンの側面で、接続パッド６と低融点ロウ材との接合面を、熱応力が作用する方向に対してほぼ直角方向とすることができ、熱応力によって低融点ロウ材の接合面に亀裂が発生することを効果的に防止することができる。
【００１９】
その結果、低融点ロウ材に短期間で破断が生じることはなく、これによって接続パッド６と外部電気回路基板の回路配線とを確実、強固に電気的接続することができるとともに半導体素子３の外部電気回路への接続を長期信頼性に優れたものとなすことが可能となる。
【００２０】
前記接続パッド６の外周縁部分６ａのみをメッシュ状にする方法としては、タングステンやモリブテン等の高融点金属粉末に適当な有機バインダーや溶剤を添加混合して得た金属ペーストをスクリーン印刷法等により所定パターンに印刷して接続パッド６を形成する際、スクリーンマスクの接続パッド６の外周縁部分６ａのみに対応する領域をメッシュ状としておくことによって、或いは、絶縁基体１の下面で接続パッド６の外周縁部分６ａのみが形成される領域に予め多数の窪み部を配列形成しておくことによって形成される。
【００２１】
なお、図４に示すように、前記接続パッド６の外周縁部分の各メッシュ６ｂの幅Ａは、２０μｍ未満では、接続パッド６の外縁に沿って集中しようとする熱応力を分散させる効果が不十分となるおそれがあり、特に半導体素子３の発熱量が増大したようなときや、ビスマス含有量の多い鉛フリー半田を低融点ロウ材として用いたようなときに、接続パッド６と低融点ロウ材との接合の信頼性が劣化する傾向がある。また、接続パッド６の外周縁部分の各メッシュ６ｂの幅Ａが１００μｍを超えると、かえって、各メッシュ６ｂの先端（外縁）部分に大きな熱応力が集中し、この個々のメッシュ６ｂの先端（外縁）部分から低融点ロウ材に亀裂が生じ、低融点ロウ材が短期間で破断するおそれがある。したがって、前記接続パッド外周縁部分６ａの各メッシュ６ｂの幅Ａは２０〜１００μｍとしておくことが好ましい。
【００２２】
また、前記接続パッド６のメッシュ状とされた外周縁部分６ａの幅は、接続パッド６の半径に対して４０％を超えると、接続パッド６の絶縁基体１に対する被着強度が低下し、配線基板としての長期信頼性が低下するおそれがある。したがって、接続パッド６のメッシュ状とされた外周縁部分６ａの幅は、接続パッド６の半径に対して４０％以下としておくことが好ましい。
【００２３】
更に前記各メッシュ６ｂは、その上下端の角部分を円弧状に面取りしておくことが好ましく、メッシュ６ｂの間隙部内にエアーを巻き込むことなく低融点ロウ材を充填させることがより一層容易・確実となるとともに、角部と接する部分で低融点ロウ材に熱応力が集中して短期間で亀裂が発生することを効果的に防止することができる。したがって、前記各メッシュ６ｂは、その上下端の角部分を円弧状に面取りしておくことが好ましい。
【００２４】
また更に前記配線導体２および接続パッド６は、またその露出する領域に、ニッケル、銅、金等の低融点ロウ材に対する濡れ性およびボンディング性に優れた金属からなるめっき層を、例えばニッケルまたは銅を約１μｍ〜１０μｍ、金を０．０５μｍ〜５μｍの厚さで順次、被着させておくと、配線導体２および接続パッド６の酸化腐食を効果的に防ぐことができるとともに、接続パッド６に対し低融点ロウ材やボンディングワイヤ５を強固に接合、接続させることができる。従って、前記配線導体２および接続パッド６はその表面にニッケル、銅、金等のめっき層を約１μｍ〜１５μｍの厚さで被着させておくことが好ましい。
【００２５】
かくして本発明の配線基板によれば、絶縁基体１の凹状の収納部１ａ底面に半導体素子３をガラスや樹脂、ロウ材等の接着剤を介して接着固定するとともにこの半導体素子３の各電極を配線導体２にボンディングワイヤ５を介して電気的に接続し、しかる後、絶縁基体１の上面に金属やセラミックスから成る蓋体７をガラスや樹脂、ロウ材等の封止材を介して接合させ、絶縁基体１と蓋体７とから成る容器内部に半導体素子３を気密に収容することによって製品としての半導体装置が完成する。
【００２６】
なお、本発明の配線基板は上述の実施の形態に限定されるものではなく、本発明の要旨を逸脱しない範囲であれば種々の変更は可能であり、例えば、上記の実施例では本発明の配線基板を半導体素子収納用パッケージに用いた例について説明したが、これを混成集積回路基板等に用いてもよい。
【００２７】
【発明の効果】
本発明の配線基板によれば、接続パッドの外周縁部分のみをメッシュ状としたことから、接続パッドと低融点ロウ材との接合面の外縁部を入り組んだ形状とすることができ、外部電気回路基板上に実装した後、配線基板の絶縁基体と外部電気回路基板に熱が繰り返し作用し、両者間に両者の熱膨張係数の差に起因して水平方向に大きな熱応力が繰り返し生じたとしても、この熱応力はメッシュ状とされた接続パッドの外周縁に沿って分散されるため集中することはなく、同時に、メッシュ部分の側面部分で、接続パッドと低融点ロウ材との接合面は、熱応力が作用する方向に対してほぼ直角方向となって熱応力に対する耐性が大きくなり、その結果、接続パッドと外部電気回路基板とを接合する低融点ロウ材の接続パッドとの界面付近の外縁部に亀裂が生じることはほとんどなく、低融点ロウ材として鉛フリー半田を使用したとしても、低融点ロウ材に短期間で破断が生じることはなく、これによって接続パッドと外部電気回路基板の回路配線とを確実、強固に電気的接続することができるとともに電子部品の各電極と外部電気回路との接続を長期信頼性に優れたものとなすことが可能となる。
【図面の簡単な説明】
【図１】本発明の配線基板の一実施例を示す断面図である。
【図２】図１に示す配線基板の底面図である。
【図３】図１に示す配線基板の要部拡大下面図である。
【図４】図３の部分拡大図である。
【符号の説明】
１・・・・絶縁基体
１ａ・・・収納部
２・・・・配線導体
３・・・・半導体素子
４・・・・配線基板
５・・・・ボンディングワイヤ
６・・・・接続パッド
６ａ・・・接続パッドの外周縁部分
６ｂ・・・各メッシュ
７・・・・蓋体
Ａ・・・・各メッシュの幅[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a wiring board on which electronic components such as a semiconductor element, a capacitor, and a resistor are mounted.
[0002]
[Prior art]
Conventionally, an electronic component, for example, a wiring board on which a semiconductor element is mounted is made of an electrically insulating material such as an aluminum oxide sintered body or a glass ceramic sintered body, and has a mounting portion on which the semiconductor element is mounted. An insulating base, a plurality of wiring conductors made of refractory metal powder such as tungsten and molybdenum, which are led out from the semiconductor element mounting portion of the insulating base or its periphery to the lower surface, and formed on the lower surface of the insulating base. And a plurality of connection pads electrically connected to the wiring conductor, and the semiconductor element is bonded and fixed to the mounting portion of the insulating base via an adhesive made of glass, resin, brazing material, or the like. In addition, each electrode of the semiconductor element is electrically connected to the wiring conductor via an electrical connection means such as a bonding wire, and then, if necessary, the semiconductor element A semiconductor device by causing hermetically sealed with a lid and a sealing resin.
[0003]
Such a semiconductor device is placed on an external electric circuit board such that the circuit wiring of the external electric circuit board and the connection pads on the lower surface of the insulating base are opposed to each other with a low melting point solder such as tin-lead solder interposed therebetween. After that, the low melting point brazing material is heated and melted at a temperature of about 200 ° C. to 300 ° C., and the circuit wiring of the external electric circuit board and the connection pads on the lower surface of the insulating base are bonded to each other on the external electric circuit board. Each electrode of the semiconductor element mounted and simultaneously mounted on the wiring board is also electrically connected to the external electric circuit board via the wiring conductor and the low melting point brazing material.
[0004]
[Problems to be solved by the invention]
However, the wiring substrate on which the conventional semiconductor element is mounted has an insulating base made of a ceramic material such as an aluminum oxide sintered body, and has a thermal expansion coefficient of about 4 × 10 −6 / ° C. to 10 × 10. The external electric circuit board is generally formed of a resin material such as a glass epoxy resin, and its thermal expansion coefficient is 30 × 10 −6 / ° C. to 50 × 10 −6 / ° C. The connection pad is generally circular or elliptical, and the outer edge of the joint surface between the connection pad and the low melting point brazing material has a similar circular or elliptical line shape. Therefore, after mounting a semiconductor device on an external electric circuit board, if the heat generated during the operation of the semiconductor element repeatedly acts on the insulating substrate of the wiring board and the external electric circuit board, the difference in thermal expansion coefficient between the two will be caused. Due to horizontal In addition, a large thermal stress is repeatedly generated in the substrate, and the thermal stress is concentrated linearly along the outer peripheral edge of the connection pad. As a result, the low melting point brazing material connecting the connection pad and the external electric circuit board is connected to the connection pad. Cracks occur at the outer edge near the interface and this progresses along the interface, eventually causing a breakage in the low melting point brazing material and breaking the electrical connection between the semiconductor element and the external electric circuit in a short period of time. There was a problem that.
[0005]
In particular, when lead-free solder such as tin-silver-bismuth is used instead of the conventional tin-lead solder as the low melting point brazing material, such lead-free solder is composed of bismuth and the like. Since the bonding strength to the connection pad tends to be lowered due to segregation, the occurrence of breakage of the low melting point brazing material becomes more remarkable.
[0006]
The present invention has been devised in view of the above-mentioned problems in the conventional wiring board, and its purpose is to break the low melting point brazing material that joins the connection pad of the insulating base and the circuit wiring of the external electric circuit board. It is an object of the present invention to provide a wiring board excellent in long-term reliability that can effectively prevent electrical connection and can reliably and firmly electrically connect each electrode of an electronic component such as a semiconductor element to an external electric circuit for a long period of time. .
[0007]
[Means for Solving the Problems]
The present invention comprises an insulating base made of an electrically insulating material and having a mounting portion on which an electronic component is mounted, a large number of connection pads formed on the lower surface of the insulating base, and the mounting portion of the insulating base. A wiring board comprising a plurality of wiring conductors led out over the connection pads, wherein each connection pad has a mesh shape only at the outer peripheral edge.
[0008]
According to the wiring board of the present invention, since only the outer peripheral edge portion of the connection pad is made into a mesh shape, the outer edge portion of the joint surface between the connection pad and the low melting point brazing material can be formed in an intricate shape. After mounting on the circuit board, heat repeatedly acts on the insulating substrate of the wiring board and the external electric circuit board, and a large thermal stress is repeatedly generated in the horizontal direction due to the difference in thermal expansion coefficient between the two. However, since this thermal stress is distributed along the outer peripheral edge of the mesh-like connection pad , it does not concentrate, and at the same time, the joint surface between the connection pad and the low melting point brazing material is on the side surface of the mesh part. As a result, the resistance to the thermal stress increases substantially at a right angle to the direction in which the thermal stress acts, and as a result, near the interface between the connection pad and the connection pad of the low melting point brazing material that joins the external electric circuit board. Outer edge Even if lead-free solder is used as the low melting point soldering material, the low melting point soldering material will not break in a short period of time. Can be reliably and firmly electrically connected, and the connection between each electrode of the electronic component and the external electric circuit can be made excellent in long-term reliability.
[0009]
DETAILED DESCRIPTION OF THE INVENTION
The present invention will now be described in detail with reference to the accompanying drawings.
[0010]
1 and 2 are a cross-sectional view and a bottom view showing an embodiment in which the wiring board of the present invention is applied to a package for housing a semiconductor element, wherein 1 is an insulating substrate, and 2 is a wiring conductor. The insulating substrate 1 and the wiring conductor 2 constitute a wiring board 4 on which the semiconductor element 3 is mounted.
[0011]
The insulating substrate 1 is made of an electrically insulating material such as an aluminum oxide sintered body, an aluminum nitride sintered body, a mullite sintered body, a silicon carbide sintered body, a glass ceramic sintered body, and a semiconductor on its upper surface. It has a concave storage portion 1a on which the element 3 is mounted and received, and the semiconductor element 3 is bonded and fixed to the bottom surface of the storage portion 1a via an adhesive such as glass, resin, or brazing material.
[0012]
For example, when the insulating substrate 1 is made of an aluminum oxide sintered body, a suitable organic binder and solvent are added to and mixed with raw material powders such as aluminum oxide, silicon oxide, calcium oxide, magnesium oxide, etc., and a slurry-like ceramic slurry is obtained. At the same time, the ceramic slurry is formed into a sheet-like ceramic green sheet (ceramic green sheet) by using a sheet molding technique such as a doctor blade method or a calender roll method, and then the ceramic green sheet is cut. It is manufactured by forming a suitable shape by punching or by stacking a plurality of sheets, and finally firing the laminated ceramic green sheets at a temperature of about 1600 ° C. in a reducing atmosphere.
[0013]
The insulating base 1 has a large number of wiring conductors 2 formed from the periphery of the housing portion 1a to the lower surface, and each electrode of the semiconductor element 3 is bonded to the bonding wire 5 around the housing portion 1a of the wiring conductor 2. A plurality of connection pads 6 that are electrically connected to each other and are electrically connected to the wiring conductor 2 are formed at a portion led out to the lower surface of the insulating base 1.
[0014]
The wiring conductor 2 and the connection pad 6 serve to connect the electrode of the semiconductor element 3 to an external electric circuit. For example, the wiring conductor 2 and the connection pad 6 are made of a refractory metal powder such as tungsten, molybdenum, or manganese. A metal paste obtained by adding and mixing an appropriate organic binder or solvent is preliminarily printed and applied in a predetermined pattern on a ceramic green sheet serving as the insulating substrate 1 by a well-known screen printing method. 1a is deposited from the periphery to the lower surface.
[0015]
The connection pad 6 acts as an external terminal for mounting the wiring board 4 on the external electric circuit board, and is joined to the circuit wiring of the external electric circuit board through a low melting point brazing material, whereby the electrodes of the semiconductor element 3 are connected. It is electrically connected to the circuit wiring of the external electric circuit board.
[0016]
In the present invention, as shown in FIG. 3, it is important that only the outer peripheral edge portion 6a of the connecting Pas head 6 keep the meshed.
[0017]
With such only the outer peripheral edge portion 6a of the connecting Pas head 6 keep the mesh-like, can be the connection pads 6 and intricate shape an outer edge of the joint surface of the low melting brazing material, an external electric circuit After mounting the semiconductor device on the substrate, the heat generated during the operation of the semiconductor element 3 repeatedly acts on the insulating base 1 of the wiring substrate 4 and the external electric circuit substrate, resulting from the difference in thermal expansion coefficient between them. Even if a large thermal stress is repeatedly generated in the horizontal direction, the thermal stress is dispersed along the outer peripheral edge of the mesh-like connection pad 6 and thus does not concentrate. Lead-free solder is used as a low melting point brazing material. Even if it is used, it is possible to effectively prevent cracks from occurring at the outer edge near the interface with the connection pad 6 of the low melting point brazing material.
[0018]
At the same time, when only the outer peripheral edge portion 6a of the connection pad 6 is made into a mesh shape, the joint surface between the connection pad 6 and the low melting point brazing material is thermally stressed on the side surface of the mesh-shaped portion, for example, a mesh pattern. Therefore, it is possible to effectively prevent cracks from occurring on the joint surface of the low melting point brazing material due to thermal stress.
[0019]
As a result, the low melting point brazing material does not break in a short period of time, and thereby the connection pad 6 and the circuit wiring of the external electric circuit board can be reliably and firmly electrically connected, and the outside of the semiconductor element 3 Connection to an electric circuit can be made excellent in long-term reliability.
[0020]
The contact as a way to continue Pas head 6 the outer peripheral edge portion 6a only a mesh, a high melting point metal powder in a suitable organic binder and solvent metal paste obtained by adding and mixing, such as tungsten or molybdenum screen printing when forming the connection path head 6 to print a predetermined pattern by law or the like, by an area corresponding only to the outer peripheral edge component 6a of the connection Pas head 6 of the screen mask keep the mesh-like, or, is formed by advance multiple recess array formed in a region where only the outer peripheral edge portion 6a of the connecting Pas head 6 on the lower surface of the insulating base 1 is formed.
[0021]
As shown in FIG. 4, if the width A of each mesh 6b at the outer peripheral edge of the connection pad 6 is less than 20 μm, the effect of dispersing thermal stress that tends to concentrate along the outer edge of the connection pad 6 is ineffective. In particular, when the heat generation amount of the semiconductor element 3 is increased, or when lead-free solder having a high bismuth content is used as the low melting point soldering material, the connection pad 6 and the low melting point soldering are used. There is a tendency that the reliability of bonding with the material deteriorates. If the width A of each mesh 6b at the outer peripheral edge portion of the connection pad 6 exceeds 100 μm, a large thermal stress is concentrated on the tip (outer edge) portion of each mesh 6b, and the tip (outer edge) of each mesh 6b is concentrated. ) Cracks occur in the low melting point brazing material from the portion, and the low melting point brazing material may break in a short period of time. Accordingly, the width A of each mesh 6b of the connection pad outer peripheral edge portion 6a is preferably set to 20 to 100 μm.
[0022]
Further, when the width of the outer peripheral edge portion 6a in the mesh shape of the connection pad 6 exceeds 40% with respect to the radius of the connection pad 6, the adhesion strength of the connection pad 6 to the insulating substrate 1 is reduced, and the wiring Long-term reliability as a substrate may be reduced. Therefore, it is preferable that the width of the outer peripheral edge portion 6 a in the mesh shape of the connection pad 6 is 40% or less with respect to the radius of the connection pad 6.
[0023]
Further, it is preferable that the upper and lower corners of each mesh 6b are chamfered in an arc shape, and it is easier and more reliable to fill the low melting point brazing material without entraining air in the gaps of the mesh 6b. In addition, it is possible to effectively prevent the thermal stress from concentrating on the low melting point brazing material at the portion in contact with the corner and cracking in a short period of time. Therefore, it is preferable that the upper and lower corners of each mesh 6b are chamfered in an arc shape.
[0024]
Furthermore, the wiring conductor 2 and the connection pad 6 are further provided with a plating layer made of a metal excellent in wettability and bonding property to a low melting point brazing material such as nickel, copper, gold, etc., for example, nickel or copper. Is deposited in a thickness of about 1 μm to 10 μm and gold is sequentially deposited to a thickness of 0.05 μm to 5 μm, so that the oxidative corrosion of the wiring conductor 2 and the connection pad 6 can be effectively prevented, and the connection pad 6 On the other hand, the low melting point brazing material and the bonding wire 5 can be firmly joined and connected. Therefore, it is preferable that a plating layer of nickel, copper, gold or the like is deposited on the surface of the wiring conductor 2 and the connection pad 6 with a thickness of about 1 μm to 15 μm.
[0025]
Thus, according to the wiring board of the present invention, the semiconductor element 3 is bonded and fixed to the bottom surface of the concave housing portion 1a of the insulating base 1 via an adhesive such as glass, resin, or brazing material, and each electrode of the semiconductor element 3 is fixed. Electrically connected to the wiring conductor 2 via bonding wires 5, and then a lid 7 made of metal or ceramics is joined to the upper surface of the insulating substrate 1 via a sealing material such as glass, resin or brazing material. A semiconductor device as a product is completed by airtightly housing the semiconductor element 3 in a container composed of the insulating base 1 and the lid 7.
[0026]
The wiring board of the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the gist of the present invention. Although the example in which the wiring board is used for the package for housing semiconductor elements has been described, this may be used for a hybrid integrated circuit board or the like.
[0027]
【The invention's effect】
According to the wiring board of the present invention, since only the outer peripheral edge portion of the connection pad has a mesh shape, the outer edge portion of the joint surface between the connection pad and the low melting point brazing material can be complicated, After mounting on the circuit board, heat repeatedly acts on the insulating substrate of the wiring board and the external electric circuit board, and a large thermal stress is repeatedly generated in the horizontal direction due to the difference in thermal expansion coefficient between the two. However, since this thermal stress is distributed along the outer peripheral edge of the mesh-like connection pad , it does not concentrate, and at the same time, the joint surface between the connection pad and the low melting point brazing material is on the side surface of the mesh part. As a result, the resistance to the thermal stress increases substantially at a right angle to the direction in which the thermal stress acts, and as a result, near the interface between the connection pad and the connection pad of the low melting point brazing material that joins the external electric circuit board. Outer edge Even if lead-free solder is used as the low melting point soldering material, the low melting point soldering material will not break in a short period of time. Can be reliably and firmly electrically connected, and the connection between each electrode of the electronic component and the external electric circuit can be made excellent in long-term reliability.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing an embodiment of a wiring board according to the present invention.
2 is a bottom view of the wiring board shown in FIG. 1. FIG.
FIG. 3 is an enlarged bottom view of the main part of the wiring board shown in FIG. 1;
4 is a partially enlarged view of FIG. 3;
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Insulation base | substrate 1a ... Storage part 2 ... Wiring conductor 3 ... Semiconductor element 4 ... Wiring board 5 ... Bonding wire 6 ... Connection pad 6a ... .... Outer peripheral edge portion 6b of connection pad ... each mesh 7 ... lid body A ... width of each mesh

Claims (1)

電気絶縁材料から成り、表面に電子部品が搭載される搭載部を有する絶縁基体と、該絶縁基体の下面に形成されている多数の接続パッドと、前記絶縁基体の前記搭載部から前記接続パッドにかけて導出されている複数個の配線導体とから成る配線基板であって、前記各接続パッドは外周縁部分のみがメッシュ状であることを特徴とする配線基板。An insulating base made of an electrically insulating material and having a mounting portion on which an electronic component is mounted, a number of connection pads formed on the lower surface of the insulating base, and from the mounting portion of the insulating base to the connection pad A wiring board comprising a plurality of derived wiring conductors, wherein each connection pad has a mesh shape only at an outer peripheral edge portion.
JP2002242201A 2002-08-22 2002-08-22 Wiring board Expired - Fee Related JP3872401B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2002242201A JP3872401B2 (en) 2002-08-22 2002-08-22 Wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002242201A JP3872401B2 (en) 2002-08-22 2002-08-22 Wiring board

Publications (2)

Publication Number Publication Date
JP2004087518A JP2004087518A (en) 2004-03-18
JP3872401B2 true JP3872401B2 (en) 2007-01-24

Family

ID=32051355

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002242201A Expired - Fee Related JP3872401B2 (en) 2002-08-22 2002-08-22 Wiring board

Country Status (1)

Country Link
JP (1) JP3872401B2 (en)

Also Published As

Publication number Publication date
JP2004087518A (en) 2004-03-18

Similar Documents

Publication Publication Date Title
JP3872401B2 (en) Wiring board
JP3838940B2 (en) Wiring board
JP3556567B2 (en) Electronic component storage package
JP3850341B2 (en) Wiring board
JP3784345B2 (en) Wiring board
JP2003179175A (en) Wiring board
JP3935054B2 (en) Wiring board
JP2004288661A (en) Wiring board
JP3532049B2 (en) Connection structure between semiconductor device and circuit board
JP3393784B2 (en) Electronic component storage package
JP3847216B2 (en) Wiring board
JP2003158220A (en) Circuit board
JP3872399B2 (en) Wiring board
JP2004200416A (en) Wiring board
JP3780503B2 (en) Wiring board
JP2000277872A (en) Wiring board
JP4409383B2 (en) Wiring board
JP2001237344A (en) Wiring board
JP2004179175A (en) Wiring board
JP2003243553A (en) Wiring board
JP2003218489A (en) Wiring board
JP2001127187A (en) Wiring board
JP2002164456A (en) Electronic part storing package
JP2003068920A (en) Wiring board
JP2004288736A (en) Wiring board

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20050216

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20050822

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20060711

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20060905

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20061003

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20061019

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20101027

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20101027

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20111027

Year of fee payment: 5

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20121027

Year of fee payment: 6

LAPS Cancellation because of no payment of annual fees