JPH06244244A - Substrate for semiconductor device mounting - Google Patents
Substrate for semiconductor device mountingInfo
- Publication number
- JPH06244244A JPH06244244A JP5288393A JP5288393A JPH06244244A JP H06244244 A JPH06244244 A JP H06244244A JP 5288393 A JP5288393 A JP 5288393A JP 5288393 A JP5288393 A JP 5288393A JP H06244244 A JPH06244244 A JP H06244244A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- semiconductor device
- mounting
- flip
- active area
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 94
- 239000004065 semiconductor Substances 0.000 title claims abstract description 51
- 238000000034 method Methods 0.000 claims description 43
- 238000004519 manufacturing process Methods 0.000 claims description 17
- 239000011347 resin Substances 0.000 claims description 8
- 229920005989 resin Polymers 0.000 claims description 8
- 239000000919 ceramic Substances 0.000 claims description 6
- 238000003825 pressing Methods 0.000 claims description 6
- 238000005476 soldering Methods 0.000 claims description 2
- 230000017525 heat dissipation Effects 0.000 abstract description 12
- 230000000694 effects Effects 0.000 abstract description 6
- 238000007796 conventional method Methods 0.000 abstract description 2
- 229910000679 solder Inorganic materials 0.000 description 13
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical group [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 239000011230 binding agent Substances 0.000 description 2
- 238000010304 firing Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 239000000155 melt Substances 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 238000007650 screen-printing Methods 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- 239000005388 borosilicate glass Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000004070 electrodeposition Methods 0.000 description 1
- 230000008030 elimination Effects 0.000 description 1
- 238000003379 elimination reaction Methods 0.000 description 1
- 201000003373 familial cold autoinflammatory syndrome 3 Diseases 0.000 description 1
- 239000011888 foil Substances 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 239000010410 layer Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 239000002002 slurry Substances 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体装置の熱放散性
が良好な半導体装置実装用基板に係り、特に従来の放熱
不良なフリップチップ実装による半導体装置の動作時の
熱を基板側へ効率良く放熱することができる半導体装置
実装用基板及びその製造方法に関し、さらには、該基板
に半導体装置を実装する方法及び半導体装置を実装した
基板に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device mounting substrate in which the heat dissipation of the semiconductor device is good, and in particular, the heat generated during the operation of the conventional semiconductor device due to flip chip mounting in which heat dissipation is poor is efficiently transmitted to the substrate side. The present invention relates to a semiconductor device mounting substrate capable of radiating heat well and a method of manufacturing the same, and more particularly to a method of mounting a semiconductor device on the substrate and a substrate on which the semiconductor device is mounted.
【０００２】[0002]
【従来の技術】半導体装置（以下、ＩＣと略称する。）
をパッケ−ジングしないで基板に実装する所謂ベアチッ
プ実装には、実装されるＩＣの基板に対する向きによっ
て大別し、従来より次の(1)及び(2)の方式が知られてい
る。 (1) フェイスアップ（ＩＣと基板が同方向）方式。 (2) フェイスダウン（ＩＣと基板が逆方向）方式。2. Description of the Related Art A semiconductor device (hereinafter abbreviated as IC).
The so-called bare chip mounting, in which the ICs are mounted on the substrate without packaging, is roughly classified according to the orientation of the mounted IC with respect to the substrate, and conventionally the following methods (1) and (2) are known. (1) Face-up method (IC and substrate are in the same direction). (2) Face-down method (IC and substrate are in the opposite direction).
【０００３】上記(1)のフェイスアップ方式では、ワイ
ヤ−ボンディングでＩＣのパッドと基板の電極とが結ば
れており、そして、ＩＣの動作時における熱はＩＣの裏
面から（及びワイヤ−を伝わって）基板へ逃げる構造か
らなっている。これに対して、上記(2)のフェイスダウ
ン方式では、はんだ、導電ペ−スト等でＩＣのパッド
（バンプ）と基板の電極とが結ばれており（フリップチ
ップ実装）、そして、ＩＣの動作時における熱はパッド
から上記はんだ、導電ペ−スト等を伝わって基板へ逃げ
るだけである。In the face-up method of the above (1), the pad of the IC and the electrode of the substrate are connected by wire bonding, and the heat during the operation of the IC is transmitted from the back surface of the IC (and transmitted through the wire). It has a structure that escapes to the substrate. On the other hand, in the face-down method of (2) above, the pads (bumps) of the IC are connected to the electrodes of the substrate by solder, conductive paste, etc. (flip chip mounting), and the operation of the IC The heat at that time only escapes from the pad to the substrate through the solder, the conductive paste and the like.
【０００４】[0004]
【発明が解決しようとする課題】前記(2)のフェイスダ
ウン方式のフリップチップ実装は、実装面積を最小にさ
せることができるので高密度実装にとって要求が多いけ
れども、ＩＣ動作時の熱は、外部に放熱フィンを付設
し、これによって逃す以外に有効な放熱手段はなかっ
た。The face-down type flip-chip mounting of (2) described above can minimize the mounting area, and is therefore often required for high-density mounting. There was no effective heat dissipation means other than that with a heat dissipation fin attached.
【０００５】このようにフリップチップ実装では、ＩＣ
動作時の発熱をパッド−電極間以外からは殆ど逃がすこ
とができず、外部に放熱フィンを付設する以外に有効な
放熱手段はなかった。これは、ＩＣがパッド−電極間以
外は基板から浮いていることによるものである。As described above, in the flip chip mounting, the IC
Almost no heat generated during the operation can be released except between the pad and the electrode, and there is no effective heat radiating means other than attaching a heat radiating fin to the outside. This is because the IC is floating from the substrate except between the pad and the electrode.
【０００６】フリップチップ実装においては、通常のは
んだを用いる場合も導電性ペ−ストを用いる場合もＩＣ
側に形成するバンプによりＩＣ表面と基板表面との間に
隙間が生じる。この隙間を小さくすることを意図して、
はんだの場合例えばボンディング時に基板に押しつけ
る、導電ペ−ストの場合バンプを無くする、等の手段を
施すと、電極間のショ−トが起こったり、強度が不足し
たりなど不具合が生じる。従って、接続において隙間を
なくすことはできない。一方、隙間があるとＩＣ動作時
の放熱効率が低下する欠点を有している。In flip-chip mounting, an IC is used regardless of whether normal solder is used or a conductive paste is used.
The bumps formed on the side form a gap between the IC surface and the substrate surface. With the intention of reducing this gap,
In the case of soldering, for example, when a means such as pressing against a substrate during bonding, or elimination of bumps in the case of a conductive paste is applied, short-circuits between electrodes occur, or strength is insufficient, and other problems occur. Therefore, the gap cannot be eliminated in the connection. On the other hand, if there is a gap, there is a drawback that the heat radiation efficiency at the time of IC operation decreases.
【０００７】本発明は、上記不具合並びに欠点を解消す
る半導体装置実装用基板に係る技術を提供することを目
的とし、詳細には、放熱不良なフリップチップ実装によ
るＩＣ動作時の熱を基板側へ効率良く逃がすことができ
る半導体装置実装用基板及びその製造方法を提供するこ
とを目的とする。また、本発明は、上記基板に半導体装
置を実装してなる半導体装置実装基板及び半導体装置を
基板に実装する方法を提供することを目的とする。It is an object of the present invention to provide a technique relating to a semiconductor device mounting substrate that solves the above-mentioned problems and drawbacks. More specifically, heat generated during IC operation due to flip chip mounting with poor heat dissipation is transferred to the substrate side. An object of the present invention is to provide a semiconductor device mounting substrate that can be efficiently released and a method for manufacturing the same. Another object of the present invention is to provide a semiconductor device mounting board in which a semiconductor device is mounted on the board and a method for mounting the semiconductor device on the board.
【０００８】[0008]
【課題を解決するための手段】本発明の半導体装置実装
用基板は、「半導体装置をフリップチップ実装するため
の基板であって、該基板の半導体装置がフェイスダウン
で実装される部分の該半導体装置のアクティブエリアに
対向する部分を他より凸状に形成して成ることを特徴と
する半導体装置実装用基板。」を要旨とする。即ち、本
発明の半導体装置実装用基板は、接続に関係しないで且
つＩＣ内で発熱する部位であるＩＣのアクティブエリア
のみ基板に接触させるために、基板のＩＣがフリップチ
ップで実装される部分のＩＣのアクティブエリアに対向
する部分を他の部分より高くした凸部構造とすることを
特徴とし、これにより上記目的とするＩＣ動作時の熱を
基板側へ効率良く逃がすことができる半導体装置実装用
基板を提供するものである。A semiconductor device mounting substrate according to the present invention is a "substrate for flip-chip mounting a semiconductor device, in which the semiconductor device is mounted face down on the semiconductor device. The semiconductor device mounting substrate is characterized in that the portion facing the active area of the device is formed to be more convex than the others. " In other words, the semiconductor device mounting substrate of the present invention has a portion where the IC of the substrate is mounted by flip-chip in order to bring the substrate into contact only with the active area of the IC, which is a portion that generates heat in the IC regardless of connection. For mounting a semiconductor device, which is characterized in that a convex portion structure in which a portion facing the active area of the IC is made higher than other portions, and thereby heat during the intended IC operation can be efficiently released to the substrate side A substrate is provided.
【０００９】また、本発明の上記基板を製造する方法と
しては、「半導体装置実装用基板としてセラミック基板
を用い、該基板の凸部をグリ−ンシ−ト多層工程のプレ
ス時に金型により形成することを特徴とする半導体装置
実装用基板の製造方法。」及び「上記セラミック基板を
低温焼成セラミック多層基板とし、該基板の凸部をプレ
ス時に金型により形成することを特徴とする半導体装置
実装用基板の製造方法。」を要旨とする。As a method for manufacturing the above-mentioned substrate of the present invention, "a ceramic substrate is used as a substrate for mounting a semiconductor device, and the convex portions of the substrate are formed by a mold during pressing in the green sheet multilayer process. A method for manufacturing a substrate for mounting a semiconductor device, characterized in that the ceramic substrate is a low temperature fired ceramic multilayer substrate, and convex portions of the substrate are formed by a die during pressing. Substrate manufacturing method. "
【００１０】更に、上記基板に半導体装置を実装してな
る半導体装置実装基板に関する本発明は、「半導体装置
のアクティブエリアが前記基板の凸部に接触するように
実装して成ることを特徴とする半導体装置実装基板。」
及び「ＩＣのアクティブエリアと前記基板の凸部の間に
熱伝導性樹脂を挿入して成ることを特徴とする半導体装
置実装基板。」を要旨とし、ＩＣ動作時の放熱効率を向
上させたＩＣ実装構造体を提供するものである。Further, the present invention relates to a semiconductor device mounting board in which a semiconductor device is mounted on the above-mentioned substrate, "a semiconductor device is mounted so that an active area of the semiconductor device contacts a convex portion of the substrate. Semiconductor device mounting board. "
And a semiconductor device mounting board characterized in that a heat conductive resin is inserted between the active area of the IC and the convex portion of the board. The IC has improved heat dissipation efficiency during IC operation. It provides a mounting structure.
【００１１】また、上記半導体装置実装基板におけるＩ
Ｃの実装方法として、本発明は、「はんだ又は導電性ペ
−ストによりフリップチップ実装を行うことを特徴とす
る半導体装置の実装方法。」及び「ＩＣを実装時に固着
するまで裏面から圧力をかけ続けることを特徴とする半
導体装置の実装方法。」を要旨とし、このように裏面か
ら圧力をかけ、ＩＣのアクティブエリアと基板の凸部と
が接触するよう押し続けて固着するＩＣの実装方法であ
る。I in the semiconductor device mounting board
As a mounting method of C, the present invention "mounting method of semiconductor device characterized by performing flip-chip mounting by solder or conductive paste." And "pressure is applied from the back surface until the IC is fixed during mounting. The method for mounting a semiconductor device is characterized by continuing. ”And a method for mounting an IC in which pressure is applied from the rear surface and the active area of the IC and the convex portion of the substrate are continuously pressed and fixed as described above. is there.
【００１２】[0012]
【実施例】以下本発明の実施例（基板の製造例、ＩＣ実
装例）を挙げ、本発明をより詳細に説明する。EXAMPLES The present invention will be described in more detail with reference to the examples of the present invention (examples of manufacturing a substrate and examples of mounting an IC).
【００１３】（実施例１） (1) 基板の製造例 図１は、本発明の一実施例である基板の製造工程フロ−
図であり、この図１を参照して、基板の製造例について
説明する。基板材料としてアルミナとホウ珪酸鉛系ガラ
スを用い、各々50／50ｗｔ比とした配合物に樹脂（バイ
ンダ−）と溶剤を加えて混合し、スラリ−化した。これ
をドクタ−プレイド法により塗工し、乾燥後シ−ト化し
た。Example 1 (1) Manufacturing Example of Substrate FIG. 1 is a flow chart of a manufacturing process of a substrate which is an example of the present invention.
It is a figure, and an example of manufacture of a substrate is explained with reference to this Drawing 1. Alumina and lead borosilicate glass were used as the substrate material, and a resin (binder) and a solvent were added to the compounded mixture at a ratio of 50/50 wt% and mixed to form a slurry. This was applied by the doctor-plaid method, dried and formed into a sheet.
【００１４】このグリ−ンシ−トに層間接続用の孔開け
を行い、スクリ−ン印刷法にて孔内にＡｇペ−ストを充
填した。この時、同時に最外層のシ−トでＩＣをフリッ
プチップ実装するための電極の位置（基板の焼成収縮率
が12％のため1.14倍した）に電極兼用の孔開けを行い、
スクリ−ン印刷法にて孔内にＡｇ−Ｐｄペ−ストを充填
した。A hole for interlayer connection was formed in this green sheet, and Ag paste was filled in the hole by a screen printing method. At the same time, at the same time, the outermost sheet is used to form a hole that also serves as an electrode at the electrode position for flip-chip mounting the IC (1.14 times as the firing shrinkage of the substrate is 12%).
The holes were filled with Ag-Pd paste by the screen printing method.
【００１５】次に、内層配線用Ａｇペ−ストを用い、印
刷法にて配線を形成し、続いて積層した後、290Ｋｇ／
ｃｍ2で10分間プレスした。この時、プレス型の一部が
凹になったもの若しくは同様のスペ−サを凹部がＩＣを
実装する位置のＩＣのアクティブエリアに相当する部分
と一致するよう合わせてから行った。凹部の深さは80μ
ｍとした。Next, using an Ag paste for inner layer wiring, wiring was formed by a printing method, and subsequently laminated, and then 290 Kg /
Pressed at cm 2 for 10 minutes. At this time, a press die in which a part thereof is concave or a similar spacer is aligned with the concave portion so as to correspond to a portion corresponding to an active area of the IC at a position where the IC is mounted. The depth of the recess is 80μ
m.
【００１６】その後400℃で120分間脱バインダ−し（樹
脂をＯ2で灰化して取り除く）、850℃で10分間焼成し
た。（図１は、上記製造工程のフロ−図である。）この
ようにして基板上のＩＣを実装する位置のＩＣのアクテ
ィブエリアに相当する部分が他より70μｍ凸部を有する
基板が得られた。Thereafter, the binder was removed at 400 ° C. for 120 minutes (resin was removed by ashing with O 2 ), followed by firing at 850 ° C. for 10 minutes. (FIG. 1 is a flow chart of the above manufacturing process.) In this manner, a substrate was obtained in which the portion corresponding to the active area of the IC on the substrate where the IC was mounted had a convex portion of 70 μm more than others. .
【００１７】(2) ＩＣ実装例 図２は、本発明の一実施例であるＩＣ実装工程Ａ〜Ｃの
工程順断面模式図であり、図３は、同ＩＣ実装工程フロ
−図である。この図２及び図３（主として図２）を参照
してＩＣ実装例を説明する。(2) IC Mounting Example FIG. 2 is a schematic cross-sectional view in order of the steps of IC mounting steps A to C which are one embodiment of the present invention, and FIG. 3 is a flow chart of the same IC mounting step. An IC mounting example will be described with reference to FIGS. 2 and 3 (mainly FIG. 2).
【００１８】まず、図２の工程Ａに示すように、凸部１
を持つ基板２（この基板２として、前記した方法によっ
て得られた凸部を有する基板を用いた。）を150℃に加
熱し、一方、通常の工程（例えば社団法人電子情報通信
学会編「ＬＳＩ技術」）で90μｍの高さのはんだバンプ
３を形成したＩＣ４をフエイスダウンで上記基板２の電
極５と位置合せした。次に、同工程Ｂに示すように、Ｉ
Ｃ４のはんだバンプ３と基板２の電極５とを接触させた
後、同工程Ｃに示すように、ＩＣ４の裏面からヒ−タ−
ツ−ル（図示せず）で5Ｋｇ／ｃｍ2で押圧し、このヒ−
タ−ツ−ルを250℃に加熱した後、ヒ−タ−ツ−ルの加
圧を80ｇ／ｃｍ2に下げ、はんだが溶けてからヒ−タ−
ツ−ルを冷却し、はんだが固化してからヒ−タ−ツ−ル
を離した。First, as shown in step A of FIG.
Substrate 2 (having a convex portion obtained by the above-described method was used as the substrate 2) having a temperature of 150 ° C., while a normal process (eg, “LSI The IC 4 on which the solder bump 3 having a height of 90 μm is formed by the technique ”is aligned with the electrode 5 of the substrate 2 by face down. Next, as shown in the same step B, I
After the solder bumps 3 of C4 and the electrodes 5 of the substrate 2 are brought into contact with each other, as shown in the same step C, the heater is transferred from the back surface of the IC 4 to the heater.
Press the tool (not shown) at 5 Kg / cm 2 and press
After heating the tool to 250 ° C, reduce the pressure applied to the tool to 80g / cm 2 and wait until the solder melts.
The tool was cooled and the heater tool was released after the solder solidified.
【００１９】これによりＩＣ４のアクティブエリアが基
板２に接触したフリップチップ実装が得られた（図２工
程Ｃ参照）。なお、図３は、上記ＩＣ実装工程のフロ−
図である。従来法によってフリップチップ実装したＩＣ
が、動作時においてＩＣ裏面温度が約70℃であったもの
が、実施例１によるフリップチップ実装したＩＣでは、
その裏面温度が約55℃まで下がっていた。この事実から
みて、この実施例１では充分な放熱効果が得られること
が認められた。As a result, flip chip mounting was obtained in which the active area of the IC 4 was in contact with the substrate 2 (see step C in FIG. 2). 3 is a flow chart of the IC mounting process.
It is a figure. IC flip-chip mounted by the conventional method
However, when the backside temperature of the IC was about 70 ° C. during operation, in the IC mounted with the flip chip according to Example 1,
Its backside temperature had dropped to about 55 ° C. From this fact, it was confirmed that in Example 1, a sufficient heat dissipation effect was obtained.
【００２０】（実施例２） (1) 基板の製造例 実施例２で使用する基板（次のＩＣ実装例で用いる凸部
を有する基板）は、前記実施例１のそれと同一方法で製
造した。Example 2 (1) Manufacturing Example of Substrate A substrate used in Example 2 (a substrate having a convex portion used in the next IC mounting example) was manufactured by the same method as that of Example 1 described above.
【００２１】(2) ＩＣ実装例 図４は、本発明の他の実施例であるＩＣ実装工程順断面
模式図であり、図５は同ＩＣ実装工程フロ−図である。
まず、図４の工程Ａに示すように、基板２の凸部１上に
熱伝導性の良好な樹脂６（例えば日本エイブルステック
社製：エイブルボンド84-3）を塗布した。(2) Example of IC mounting FIG. 4 is a schematic cross-sectional view of an IC mounting process according to another embodiment of the present invention, and FIG. 5 is a flowchart of the same IC mounting process.
First, as shown in Step A of FIG. 4, a resin 6 having a good thermal conductivity (for example, Able Bond 84-3 manufactured by Japan Able Stick Co., Ltd.) was applied onto the convex portion 1 of the substrate 2.
【００２２】次に、同工程Ｂに示すように、基板２を15
0℃に加熱し、以下実施例１と同様90μｍの高さのはん
だバンプ３を形成したＩＣ４をフエイスダウンで上記基
板２の電極５と位置合せした。続いて、同工程Ｃに示す
ように、ＩＣ４のはんだバンプ３と基板２の電極５とを
接触させた後、同工程Ｄに示すように、ＩＣ４の裏面か
らヒ−タ−ツ−ル（図示せず）で5Ｋｇ／ｃｍ2で押圧
し、ヒ−タ−ツ−ルを250℃に加熱した後、ヒ−タ−ツ
−ルの加圧を80ｇ／ｃｍ2に下げ、はんだが溶解してか
らヒ−タ−ツ−ルを冷却し、はんだが固化してからヒ−
タ−ツ−ルを離した。Next, as shown in the same step B, the substrate 2 is removed by 15
After heating to 0 ° C., the IC 4 on which the solder bump 3 having a height of 90 μm was formed was aligned with the electrode 5 of the substrate 2 by face down as in the case of Example 1. Then, as shown in the same step C, after the solder bumps 3 of the IC 4 and the electrodes 5 of the substrate 2 are brought into contact with each other, as shown in the same step D, a heater tool (Fig. After pressing the heater tool to 250 ° C. with a pressure of 5 kg / cm 2 ( not shown), the pressure of the heater tool is lowered to 80 g / cm 2 and the solder melts. To cool the heater tool and allow the solder to solidify before the heat
The tool was released.
【００２３】その後、樹脂６を硬化させるために125℃
で2時間加熱した。これによりアクティブエリアが基板
２に接触したフリップチップ実装が得られた（図４工程
Ｄ参照）。この実施例２においても前記実施例１と同様
十分な放熱効果が得られた。Thereafter, in order to cure the resin 6, 125 ° C.
Heated for 2 hours. As a result, flip chip mounting in which the active area was in contact with the substrate 2 was obtained (see step D in FIG. 4). In this second embodiment, a sufficient heat dissipation effect was obtained as in the first embodiment.
【００２４】（実施例３） (1) 基板の製造例 実施例３で使用する基板（次のＩＣ実装例で用いる凸部
を有する基板）は、前記実施例１のそれと同一方法で製
造した。Example 3 (1) Manufacturing Example of Substrate A substrate used in Example 3 (a substrate having a convex portion used in the next IC mounting example) was manufactured by the same method as that of Example 1 described above.
【００２５】(2) ＩＣ実装例 図６は、本発明のその他の実施例であるＩＣ実装工程順
断面模式図であり、図７は、同ＩＣ実装工程フロ−図で
ある。(2) Example of IC mounting FIG. 6 is a schematic cross-sectional view of an IC mounting process according to another embodiment of the present invention, and FIG. 7 is a flowchart of the same IC mounting process.
【００２６】ISHM（MINNEAPOLIS）PROCEEDINGS（1987）
のp.p.635〜640と同様の方法で、銅コア金バンプ７を形
成したＩＣ4aのバンプ上に、銀−パラデュ−ムペ−スト
８（福田金属箔粉工業製：RM-300）を転写し、位置合せ
をした（図６工程Ａ）。次に、同工程Ｂに示すように、
銅コア金バンプ７と基板２の電極５とを銀−パラデュ−
ムペ−スト８を介して接触させた。ISHM (MINNEAPOLIS) PROCEEDINGS (1987)
In the same manner as pp635 to 640, the silver-paradium paste 8 (RM-300 manufactured by Fukuda Metal Foil & Powder Co., Ltd.) is transferred onto the bumps of the IC 4a on which the copper core gold bumps 7 are formed, and the alignment is performed. Was performed (step A in FIG. 6). Next, as shown in the same step B,
The copper core gold bump 7 and the electrode 5 of the substrate 2 are silver-plated.
Contact was made via Mupaste 8.
【００２７】続いて、同工程Ｃに示すように、ＩＣ4aの
裏面から100ｇ／ｃｍ2で加圧し、そのまま150℃で30分
間加熱し、室温程度まで冷却した後除圧した。これによ
りアクティブエリアが基板２に接触したフリップチップ
実装が得られた（図６工程Ｃ参照）。この実施例３にお
いても前記実施例１と同様充分な放熱効果が得られた。
なお、この実施例３では、前記実施例２と同様凸部１と
ＩＣ4aとの間に熱伝導性のよい樹脂６（図４工程Ａ参
照）を入れることも可能であり、これによってより安定
した放熱効果が得られる。Subsequently, as shown in the same step C, pressure was applied from the back surface of the IC 4a at 100 g / cm 2 , and the mixture was heated at 150 ° C. for 30 minutes, cooled to room temperature, and then depressurized. As a result, flip chip mounting in which the active area was in contact with the substrate 2 was obtained (see step C in FIG. 6). In this third embodiment, a sufficient heat dissipation effect was obtained as in the first embodiment.
In the third embodiment, as in the second embodiment, it is also possible to insert a resin 6 having good thermal conductivity (see step A in FIG. 4) between the convex portion 1 and the IC 4a, which makes it more stable. A heat dissipation effect can be obtained.
【００２８】[0028]
【発明の効果】本発明は、以上詳記したとおり、半導体
装置がフェイスダウンで実装される部分の該半導体装置
のアクティブエリアに対向する部分を他より凸状に形成
して成ることを特徴とするものであり、これにより従来
の放熱性不良なフリップチップ実装によるＩＣの動作時
の熱を基板側へ効率良く逃がすことができるという顕著
な効果が生じる。As described in detail above, the present invention is characterized in that a portion of a semiconductor device mounted facedown is opposed to the active area of the semiconductor device in a convex shape. This brings about a remarkable effect that the heat during the operation of the IC due to the conventional flip-chip mounting with poor heat dissipation can be efficiently released to the substrate side.
【図１】本発明の一実施例である基板の製造工程フロ−
図。FIG. 1 is a flow chart of a substrate manufacturing process according to an embodiment of the present invention.
Fig.
【図２】本発明の一実施例であるＩＣ実装工程順断面模
式図。FIG. 2 is a schematic cross-sectional view of an IC mounting process in order according to an embodiment of the present invention.
【図３】本発明の一実施例であるＩＣ実装工程フロ−
図。FIG. 3 is a flowchart showing an IC mounting process according to an embodiment of the present invention.
Fig.
【図４】本発明の他の実施例であるＩＣ実装工程順断面
模式図。FIG. 4 is a schematic cross-sectional view in order of an IC mounting process which is another embodiment of the present invention.
【図５】本発明の他の実施例であるＩＣ実装工程フロ−
図。FIG. 5 is an IC mounting process flow chart of another embodiment of the present invention.
Fig.
【図６】本発明のその他の実施例であるＩＣ実装工程順
断面模式図。FIG. 6 is a schematic cross-sectional view of an IC mounting process according to another embodiment of the present invention.
【図７】本発明のその他の実施例であるＩＣ実装工程フ
ロ−図。FIG. 7 is a flowchart of an IC mounting process which is another embodiment of the present invention.
１ 凸部 ２ 基板 ３ はんだバンプ ４ ＩＣ ４ａ ＩＣ ５ 電極 ６ 樹脂 ７ 銅コア金バンプ ８ 銀−パラデュ−ムペ−スト DESCRIPTION OF SYMBOLS 1 convex part 2 substrate 3 solder bump 4 IC 4a IC 5 electrode 6 resin 7 copper core gold bump 8 silver-paradium paste
Claims (8)
めの基板であって、該基板の半導体装置がフェイスダウ
ンで実装される部分の該半導体装置のアクティブエリア
に対向する部分を他より凸状に形成して成ることを特徴
とする半導体装置実装用基板。1. A substrate for flip-chip mounting a semiconductor device, wherein a portion of the substrate where the semiconductor device is mounted facedown is formed to be more convex than other portions facing the active area of the semiconductor device. A substrate for mounting a semiconductor device, comprising:
装置のアクティブエリアが基板の凸部に接触するように
実装して成ることを特徴とする半導体装置実装基板。2. The substrate according to claim 1, wherein the semiconductor device mounting substrate is mounted so that an active area of the semiconductor device is in contact with a convex portion of the substrate.
おいて、半導体装置のアクティブエリアと基板の凸部と
の間に熱伝導性樹脂を挿入して成ることを特徴とする半
導体装置実装基板。3. The semiconductor device mounting board according to claim 2, wherein a thermally conductive resin is inserted between the active area of the semiconductor device and the convex portion of the substrate.
置実装基板における半導体装置の実装方法として、はん
だによりフリップチップ実装を行うことを特徴とする半
導体装置の実装方法。4. A method of mounting a semiconductor device on the semiconductor device mounting board according to claim 2, wherein flip-chip mounting is performed by soldering.
置実装基板における半導体装置の実装方法として、導電
性ペ−ストよりフリップチップ実装を行うことを特徴と
する半導体装置の実装方法。5. A method for mounting a semiconductor device on the semiconductor device mounting substrate according to claim 2, wherein flip chip mounting is performed from a conductive paste.
置の実装方法において、半導体装置を実装時に固着する
まで裏面から圧力をかけ続けることを特徴とする半導体
装置の実装方法。6. The method of mounting a semiconductor device according to claim 4, wherein pressure is continuously applied from the back surface until the semiconductor device is fixed during mounting.
の半導体装置実装用基板の製造方法において、該基板と
してセラミック基板を用い、この基板の凸部をグリ−ン
シ−ト多層工程のプレス時に金型により形成することを
特徴とする半導体装置実装用基板の製造方法。7. The method for manufacturing a semiconductor device mounting substrate according to claim 1, 2, 3, 4, 5 or 6, wherein a ceramic substrate is used as the substrate, and the convex portion of the substrate is ground sheet. A method of manufacturing a substrate for mounting a semiconductor device, which is characterized in that it is formed by a mold during pressing in a multi-layer process.
の製造方法において、セラミック基板を低温焼成セラミ
ック多層基板とし、該基板の凸部をプレス時に金型によ
り形成することを特徴とする半導体装置実装用基板の製
造方法。8. The method for manufacturing a substrate for mounting a semiconductor device according to claim 7, wherein the ceramic substrate is a low temperature fired ceramic multilayer substrate, and the convex portions of the substrate are formed by a die during pressing. Method for manufacturing device mounting substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP05288393A JP3271631B2 (en) | 1993-02-18 | 1993-02-18 | Substrate for mounting semiconductor devices |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP05288393A JP3271631B2 (en) | 1993-02-18 | 1993-02-18 | Substrate for mounting semiconductor devices |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH06244244A true JPH06244244A (en) | 1994-09-02 |
| JP3271631B2 JP3271631B2 (en) | 2002-04-02 |
Family
ID=12927284
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP05288393A Expired - Fee Related JP3271631B2 (en) | 1993-02-18 | 1993-02-18 | Substrate for mounting semiconductor devices |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3271631B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008517459A (en) * | 2004-10-14 | 2008-05-22 | アギア システムズ インコーポレーテッド | Printed circuit board assembly with improved thermal energy dissipation |
| JP2011135083A (en) * | 2009-12-23 | 2011-07-07 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | Method for assembling at least one chip with wire element, electronic chip with deformable connection element,fabrication method of a plurality of chips, and assembly of at least one chip with wired element |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR3083643B1 (en) * | 2018-07-04 | 2023-01-13 | Commissariat Energie Atomique | METHOD FOR MAKING AN ELECTRONIC DEVICE |
-
1993
- 1993-02-18 JP JP05288393A patent/JP3271631B2/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008517459A (en) * | 2004-10-14 | 2008-05-22 | アギア システムズ インコーポレーテッド | Printed circuit board assembly with improved thermal energy dissipation |
| JP2011135083A (en) * | 2009-12-23 | 2011-07-07 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | Method for assembling at least one chip with wire element, electronic chip with deformable connection element,fabrication method of a plurality of chips, and assembly of at least one chip with wired element |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3271631B2 (en) | 2002-04-02 |
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