JPH09260529A - Substrate for semiconductor device, and semiconductor device - Google Patents
Substrate for semiconductor device, and semiconductor deviceInfo
- Publication number
- JPH09260529A JPH09260529A JP6637496A JP6637496A JPH09260529A JP H09260529 A JPH09260529 A JP H09260529A JP 6637496 A JP6637496 A JP 6637496A JP 6637496 A JP6637496 A JP 6637496A JP H09260529 A JPH09260529 A JP H09260529A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- ceramic substrate
- substrate
- external connection
- solder
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
Abstract
Description
【発明の詳細な説明】Detailed Description of the Invention
【０００１】[0001]
【発明の属する技術分野】本発明は半導体装置用基板及
び半導体装置に関し、更に詳細にはセラミック基板の一
面に半導体素子が搭載されると共に、外部接続用バンプ
が前記セラミック基板の他面から突出するように形成さ
れる半導体装置用基板、及びセラミック基板の一面に半
導体素子が搭載され、且つ外部接続用バンプが、前記セ
ラミック基板の他面から突出して形成された半導体装置
に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device substrate and a semiconductor device. More specifically, a semiconductor element is mounted on one surface of a ceramic substrate, and external connection bumps project from the other surface of the ceramic substrate. The semiconductor device substrate thus formed, and the semiconductor device in which the semiconductor element is mounted on one surface of the ceramic substrate, and the external connection bumps are formed to project from the other surface of the ceramic substrate.
【０００２】[0002]
【従来の技術】半導体装置には、図１３に示すセラミッ
ク基板１００が汎用されている。このセラミック基板１
００には、一面に導体パターン１０２、１０２・・が形
成されていると共に、他面に形成されたパッド１０４、
１０４・・に、はんだ等の金属ろう材から成る外部接続
用バンプ１０６、１０６・・が形成されている。この導
体パターン１０２、１０２・・と外部接続用バンプ１０
６、１０６・・とは、セラミック基板１００を貫通する
ビア１０８、１０８・・によって電気的に接続されてい
る。かかるセラミック基板１００は、通常、セラミック
粉末にバインダー等を混合して所定形状に成形したグリ
ーンシートを焼成して形成する。その際に、導体パター
ン１０２、パッド１０４、及びビア１０８は、グリーン
シートの一面にスクリーン印刷等によって所定パターン
に塗布し且つビア用穴部に充填したタングステン等の金
属が含有されたメタライズ用ペーストを、グリーンシー
トと共に同時焼成して形成できる。或いは、焼成した得
たセラミック基板にスクリーン印刷等によって所定パタ
ーンに塗布し且つセラミック基板に形成されたビア用穴
部に充填したメタライズ用ペーストを焼成して導体パタ
ーン１０２やビア１０８等を形成できる。次いで、導体
パターン１０２、１０２・・が形成されたセラミック基
板１００の一面に半導体素子を搭載し、更にキャップや
樹脂で封止した後、セラミック基板１００の他面に形成
したパッド１０４、１０４・・に載置したはんだボール
をリフローして外部接続用バンプ１０６、１０６・・を
形成する。2. Description of the Related Art A ceramic substrate 100 shown in FIG. 13 is generally used for a semiconductor device. This ceramic substrate 1
00 has conductor patterns 102, 102, ... Formed on one surface and pads 104 formed on the other surface,
External connection bumps 106, 106 made of a metal brazing material such as solder are formed at 104. .. and the bumps 10 for external connection
6 are electrically connected to each other by vias 108, 108 penetrating the ceramic substrate 100. Such a ceramic substrate 100 is usually formed by mixing a ceramic powder with a binder or the like and firing a green sheet formed into a predetermined shape. At that time, the conductor pattern 102, the pad 104, and the via 108 are the metallizing paste containing a metal such as tungsten, which is applied in a predetermined pattern on one surface of the green sheet by screen printing or the like and filled in the via hole. It can be formed by co-firing with a green sheet. Alternatively, the conductor pattern 102, the vias 108, etc. can be formed by firing a metallizing paste applied to a predetermined pattern on the fired ceramic substrate by screen printing or the like and filling the via holes formed in the ceramic substrate. Next, after mounting a semiconductor element on one surface of the ceramic substrate 100 on which the conductor patterns 102, 102 ... Are formed, and further sealing with a cap or resin, the pads 104, 104 ... Formed on the other surface of the ceramic substrate 100. The solder balls placed on the substrate are reflowed to form the external connection bumps 106, 106, ....
【０００３】[0003]
【発明が解決しようとする課題】この様にして得られた
セラミック基板１００は、プラスチック基板に比較して
反りが少なく且つ容易にワイヤボンドが可能であるた
め、半導体装置用基板として好適に使用される。しか
し、セラミック基板１００の成形工程は、プラスチック
基板の成形工程に比較して工程数が多い。更に、メタラ
イズ用ペーストを焼成して導体パターン１０２等を形成
するメタライズ工程において、得られた導体パターン１
０２やビア１０８の電気的特性等の関係からメタライズ
用ペースト中に含有されているバインダー成分を完全に
なくす必要があり、焼成時間の短縮が困難である。この
ため、セラミック基板１００の製造コストの低減も困難
である。また、セラミック基板１００を用いた半導体装
置は、セラミック基板１００との熱膨張率差を有するプ
ラスチック製の実装基板に実装される場合が多い。かか
る両基板の熱膨張率差に起因する応力は、セラミック基
板１００に形成されたパッド１０４と外部接続用バンプ
１０６との境界近傍に集中し、クラックが発生すること
がある。The ceramic substrate 100 thus obtained has less warpage as compared with a plastic substrate and can be easily wire-bonded, and thus is suitably used as a substrate for a semiconductor device. It However, the molding process of the ceramic substrate 100 has more steps than the molding process of the plastic substrate. Further, the conductor pattern 1 obtained in the metallizing step of firing the metallizing paste to form the conductor pattern 102 and the like.
It is necessary to completely eliminate the binder component contained in the metallizing paste because of the electrical characteristics of the No. 02 and the via 108, and it is difficult to shorten the firing time. Therefore, it is difficult to reduce the manufacturing cost of the ceramic substrate 100. Further, a semiconductor device using the ceramic substrate 100 is often mounted on a plastic mounting substrate having a coefficient of thermal expansion different from that of the ceramic substrate 100. The stress resulting from the difference in the coefficient of thermal expansion between the two substrates may be concentrated near the boundary between the pad 104 formed on the ceramic substrate 100 and the external connection bump 106, and a crack may occur.
【０００４】そこで、本発明の課題は、反りが少なく且
つワイヤボンドが可能であるセラミック基板の特性を生
かしつつ、プラスチック製の実装基板に実装されても外
部接続用バンプ等にクラックの発生を防止でき、且つ製
造コストの低減も図り得る半導体装置用基板及び半導体
装置を提供することにある。Therefore, an object of the present invention is to prevent the occurrence of cracks in external connection bumps or the like even when mounted on a plastic mounting substrate while making the most of the characteristics of a ceramic substrate that has a small amount of warp and enables wire bonding. An object of the present invention is to provide a substrate for a semiconductor device and a semiconductor device that can be manufactured and can reduce the manufacturing cost.
【０００５】[0005]
【課題を解決するための手段】本発明者等は、前記課題
を解決すためには、セラミック基板に導体パターンをメ
タライズすることなく形成でき、且つ半導体装置をプラ
スチック製の実装基板に実装した際に、セラミック基板
とプラスチック実装基板との熱膨張率差に起因して発生
する応力に対抗し得る外部接続用バンプを形成すること
が有効であると考え検討した。その結果、セラミック基
板の一面に接着層を介して接着された銅等の金属箔から
導体パターンを形成すると共に、導体パターンを底面と
しセラミック基板を貫通して他面に開口するビア用穴部
を形成し、このビア用穴部にはんだ等の金属ろう材を充
填して形成したビアと、ビア用穴部の開口部に形成した
はんだ等の金属ろう材から成る外部接続用バンプとを一
体化することによって、導体パターン等をメタライズで
形成することを要せず、且つ半導体装置をプラスチック
製の実装基板に実装しても、外部接続用バンプがセラミ
ック基板とプラスチック実装基板との熱膨張率差に起因
して発生する応力に充分に対抗し得ることを知り、本発
明に到達した。In order to solve the above-mentioned problems, the present inventors have found that when a conductor pattern can be formed on a ceramic substrate without metallizing, and a semiconductor device is mounted on a plastic mounting substrate. In addition, it was considered effective to form bumps for external connection that can withstand the stress caused by the difference in coefficient of thermal expansion between the ceramic substrate and the plastic mounting substrate. As a result, a conductor pattern is formed from a metal foil such as copper that is adhered to one surface of the ceramic substrate via an adhesive layer, and a via hole that penetrates the ceramic substrate to the other surface is formed with the conductor pattern as the bottom surface. A via formed by filling the via hole with a metal brazing material such as solder and the external connection bump formed of a metal brazing material such as solder formed in the opening of the via hole are integrated. By doing so, it is not necessary to form a conductor pattern by metallization, and even if the semiconductor device is mounted on a plastic mounting board, the bumps for external connection have a difference in coefficient of thermal expansion between the ceramic board and the plastic mounting board. The inventors have reached the present invention knowing that they can sufficiently counter the stress generated due to.
【０００６】すなわち、本発明は、セラミック基板の一
面に半導体素子が搭載されると共に、外部接続用バンプ
が前記セラミック基板の他面から突出するように形成さ
れる半導体装置用基板において、該半導体素子が搭載さ
れるセラミック基板の一面に、導体パターンが形成され
る銅箔等の金属箔が接着層を介して接着され、且つ前記
金属箔を底面としセラミック基板を貫通して他面に開口
されている穴部が形成されていると共に、前記穴部が、
セラミック基板の一面に前記金属箔から形成される導体
パターンと、前記穴部の開口部に形成されるはんだ等の
金属ろう材から成る外部接続用バンプとを電気的に接続
するように、はんだ等の金属ろう材が充填されて外部接
続用バンプと一体化されるビアを形成する、ビア用穴部
であることを特徴とする半導体装置用基板にある。ま
た、本発明は、セラミック基板の一面に半導体素子が搭
載され、且つ前記セラミック基板の他面に外部接続用バ
ンプが突出して形成された半導体装置において、該半導
体素子が搭載されるセラミック基板の一面に接着層を介
して接着された銅箔等の金属箔から成る導体パターンが
形成されていると共に、前記導体パターンを底面とし前
記セラミック基板を貫通して他面に開口されたビア用穴
部に、はんだ等の金属ろう材が充填されて形成されたビ
アと、前記ビア用穴部の開口部に形成されたはんだ等の
金属ろう材から成る外部接続用バンプとが一体に形成さ
れていることを特徴とする半導体装置にある。That is, the present invention provides a semiconductor device substrate in which a semiconductor element is mounted on one surface of a ceramic substrate, and external connection bumps are formed so as to project from the other surface of the ceramic substrate. A metal foil such as a copper foil on which a conductor pattern is formed is adhered to one surface of a ceramic substrate on which is mounted via an adhesive layer, and the metal foil is used as a bottom surface to penetrate the ceramic substrate and be opened to the other surface. A hole part is formed, and the hole part is
Solder or the like so as to electrically connect the conductor pattern formed of the metal foil on one surface of the ceramic substrate and the external connection bump formed of the metal brazing material such as solder formed in the opening of the hole. The semiconductor device substrate, which is a via hole for forming a via that is filled with the metal brazing material and is integrated with the external connection bump. Further, the present invention provides a semiconductor device in which a semiconductor element is mounted on one surface of a ceramic substrate, and external connection bumps are formed on the other surface of the ceramic substrate so as to project on one surface of the ceramic substrate. A conductor pattern made of a metal foil such as a copper foil adhered via an adhesive layer to is formed on a via hole formed in the other surface through the ceramic substrate with the conductor pattern serving as a bottom surface. A via formed by being filled with a metal brazing material such as solder, and an external connection bump formed of a metal brazing material such as solder formed in the opening of the via hole are integrally formed. In a semiconductor device.
【０００７】かかる本発明に係る半導体装置用基板にお
いて、セラミック基板の一面に接着された銅箔等の金属
箔を導体パターンに形成しておくこと、及び／又は外部
接続用バンプを形成するはんだ等の金属ろう材をビア用
穴部に充填しておくことが、本発明に係る半導体装置を
製造する上で好ましい。また、本発明に係る半導体装置
において、外部接続用バンプを、セラミック基板面に対
して垂直方向に延ばした楕円球状とすることにより、略
円球状の外部接続用バンプが形成された半導体装置と比
較して、半導体装置を実装基板に実装したとき、半導体
装置と実装基板との基板間の間隔を大にでき、セラミッ
ク基板とプラスチック実装基板との熱膨張率差に起因し
て発生する外部接続用バンプに対する応力集中を緩和で
きる。更に、セラミック基板に開口されたビア用穴部の
開口部近傍の基板面に、ソルダレジスト等の有機物から
成る絶縁層を形成することによっても、セラミック基板
とプラスチック実装基板との熱膨張率差に起因して発生
する外部接続用バンプに対する応力集中を可及的に緩和
できる。この様な、半導体装置において、外部接続用バ
ンプを高くし且つ半導体装置を実装基板に実装したと
き、半導体装置と実装基板との基板面間に所定間隔を確
実に確保すべく、外部接続用バンプ及びビア形成用穴部
の中心軸に沿って、針状部材を挿入することが好まし
い。In such a semiconductor device substrate according to the present invention, a metal foil such as a copper foil adhered to one surface of a ceramic substrate is formed on a conductor pattern, and / or solder for forming bumps for external connection is formed. In order to manufacture the semiconductor device according to the present invention, it is preferable to fill the via hole with the metal brazing material. Further, in the semiconductor device according to the present invention, the external connection bumps have an elliptic spherical shape extending in a direction perpendicular to the surface of the ceramic substrate, so that a substantially spherical external connection bump is formed. When the semiconductor device is mounted on a mounting board, the distance between the semiconductor device and the mounting board can be increased, and the external connection is caused by the difference in the coefficient of thermal expansion between the ceramic board and the plastic mounting board. Stress concentration on the bumps can be relaxed. Further, by forming an insulating layer made of an organic material such as solder resist on the substrate surface near the opening of the via hole opened in the ceramic substrate, the difference in the coefficient of thermal expansion between the ceramic substrate and the plastic mounting substrate can be reduced. It is possible to reduce the stress concentration on the external connection bumps caused as much as possible. In such a semiconductor device, when the bumps for external connection are raised and the semiconductor device is mounted on the mounting board, the bumps for external connection are ensured in order to ensure a predetermined space between the substrate surfaces of the semiconductor device and the mounting board. Further, it is preferable to insert the needle-shaped member along the central axis of the via forming hole.
【０００８】本発明によれば、セラミック基板の一面に
接着層を介して接着された銅箔等の金属箔から導体パタ
ーンを形成することによって、メタライズにより導体パ
ターンを形成する工程を省略でき、且つメタライズによ
って形成された導体パターンに比較して導体パターンの
インダクタンス等の電気特性も向上できる。また、セラ
ミック基板の基板面から突出して形成された外部接続用
バンプは、導体パターンを底面としセラミック基板を貫
通して他面に開口されたビア用穴部に、はんだ等の金属
ろう材が充填されて形成されたビアと、ビア用穴部の開
口部に形成されたはんだ等の金属ろう材から成る外部接
続用バンプとが一体に形成されている。このため、導体
パターンと外部接続用バンプとを電気的に確実に接続さ
れることは勿論のこと、半導体装置をプラスチック製の
実装基板に実装したとき、セラミック基板とプラスチッ
ク実装基板との熱膨張率差に起因して発生する応力に対
しても、外部接続用バンプは充分に対抗できる。According to the present invention, the step of forming a conductor pattern by metallization can be omitted by forming the conductor pattern from a metal foil such as a copper foil adhered to one surface of the ceramic substrate via an adhesive layer, and The electrical characteristics such as the inductance of the conductor pattern can be improved as compared with the conductor pattern formed by metallization. Also, the external connection bumps that are formed so as to project from the board surface of the ceramic board are filled with a metal brazing material such as solder in the via holes that are formed on the other surface through the ceramic board with the conductor pattern as the bottom surface. The via thus formed and the external connection bump formed of a metal brazing material such as solder formed in the opening of the via hole are integrally formed. Therefore, the conductor pattern and the bumps for external connection are not only electrically reliably connected, but also when the semiconductor device is mounted on a plastic mounting substrate, the coefficient of thermal expansion between the ceramic substrate and the plastic mounting substrate. The external connection bumps can sufficiently oppose the stress generated due to the difference.
【０００９】[0009]
【発明の実施の形態】本発明を図面を用いて更に詳細に
説明する。図１は、本発明に係る半導体装置用基板の一
例を示す部分断面図である。図１において、セラミック
基板１０の一面に接着層１２を介して銅箔等の金属箔１
４が接着されている。このセラミック基板１０には、金
属箔１４を底面としセラミック基板１０を貫通して他面
に開口するビア用穴部１６、１６・・が形成されてい
る。かかる半導体装置用基板を製造する際には、先ず、
セラミック粉末にバインダー等を混合して所定形状のグ
リーンシートを成形した後、このグリーンシートの厚み
方向に貫通する貫通孔をグリーンシートの所定箇所に穿
設した後、所定温度で焼成することによって、ビア用穴
部を構成する貫通孔が所定箇所に穿設されたセラミック
基板１０を得る。このセラミック基板１０を成形するセ
ラミックとしては、セラミック基板１０に対する要求特
性に合わせてアルミナ、窒化アルミ、ムライト等の任意
なものを採用できる。また、得られたセラミック基板１
０は、メタライズで導体パターン等を形成することを要
しないため、採用したセラミックの種類に適した温度で
焼成でき、場合によっては大気中での焼成が可能であ
る。The present invention will be described in more detail with reference to the drawings. FIG. 1 is a partial cross-sectional view showing an example of a semiconductor device substrate according to the present invention. In FIG. 1, a metal foil 1 such as a copper foil is provided on one surface of a ceramic substrate 10 with an adhesive layer 12 interposed therebetween.
4 are adhered. The ceramic substrate 10 is provided with via holes 16, 16 ... With the metal foil 14 as the bottom face and penetrating the ceramic substrate 10 and opening to the other face. When manufacturing such a semiconductor device substrate, first,
After molding a green sheet having a predetermined shape by mixing a binder and the like with the ceramic powder, after forming through holes penetrating in the thickness direction of the green sheet at predetermined positions of the green sheet, by firing at a predetermined temperature, A ceramic substrate 10 having a through hole forming a via hole at a predetermined position is obtained. As a ceramic for forming the ceramic substrate 10, any material such as alumina, aluminum nitride, or mullite can be adopted according to the required characteristics of the ceramic substrate 10. Moreover, the obtained ceramic substrate 1
Since 0 does not require formation of a conductor pattern or the like by metallization, firing can be performed at a temperature suitable for the type of ceramic employed, and in some cases firing in air is possible.
【００１０】次いで、焼成した得たセラミック基板１０
の一面に、ポリイミド系、エポキシ系、又はＢＴ（ビス
マレイミドトリアジン）等の有機系接着剤から成り且つ
ビア用穴部１６に対応する位置にスルーホールが穿設さ
れたシート体を、セラミック基板１０の一面に載置した
後、シート体から成る接着層１２を介して銅箔等の金属
箔１４を圧着することによって、図１に示す半導体装置
用基板を得ることができる。かかる図１に示す半導体装
置用基板においては、半導体装置を容易に製造すべく、
図２に示す様に、ビア用穴部１６、１６・・にはんだ等
の金属ろう材を充填しておいてもよく、銅箔等の金属箔
１４をフォトリソ法等によって導体パターンに形成して
おいてもよい。尚、この有機系接着剤から成るシート体
に代えて、有機系接着剤をスクリーン印刷等によってセ
ラミック基板１０の一面に塗布して接着層１２を形成し
てもよく、半導体装置用基板の放熱性、耐熱性、耐薬品
性等を向上すべく、接着層１２に無機繊維、窒化アルミ
（AlN ）、酸化ケイ素（SiO2）、ガラス等の無機粉末を
混入してもよい。Then, the ceramic substrate 10 obtained by firing is obtained.
On one surface, a sheet body made of an organic adhesive such as polyimide, epoxy, or BT (bismaleimide triazine) and having through holes formed at positions corresponding to the via holes 16 is provided on the ceramic substrate 10. After being placed on one surface, the semiconductor device substrate shown in FIG. 1 can be obtained by pressure-bonding a metal foil 14 such as a copper foil via the adhesive layer 12 made of a sheet. In the semiconductor device substrate shown in FIG. 1, in order to easily manufacture the semiconductor device,
As shown in FIG. 2, the via holes 16, 16 may be filled with a metal brazing material such as solder, and the metal foil 14 such as a copper foil is formed into a conductor pattern by a photolithography method or the like. You can leave it. Instead of the sheet body made of the organic adhesive, an organic adhesive may be applied to one surface of the ceramic substrate 10 by screen printing or the like to form the adhesive layer 12. In order to improve heat resistance, chemical resistance, and the like, the adhesive layer 12 may be mixed with inorganic powder such as inorganic fibers, aluminum nitride (AlN 3), silicon oxide (SiO 2 ), and glass.
【００１１】図１又は図２に示す半導体装置用基板を用
いた半導体装置では、図３に示す様に、半導体素子が搭
載されるセラミック基板１０の一面に接着層１２を介し
て接着した金属箔１４をフォトリソ法等によって所定パ
ターンの導体パターン２０、２０・・に形成されている
と共に、セラミック基板１０を厚み方向に貫通して導体
パターン２０、２０・・を底面とし且つセラミック基板
１０の他面に開口するビア用穴部１６、１６・・が形成
されている。更に、ビア用穴部１６、１６・・の各々に
はんだ等の金属ろう材が充填されて形成されたビア２
４、２４・・と、ビア用穴部１６、１６・・の各開口部
にセラミック基板１０の基板面から略円球状に突出して
形成された、はんだ等の金属ろう材から成る外部接続用
バンプ２２ａ、２２ａ・・とは、一体化されて導体パタ
ーン２０、２０・・の各々と電気的に接続されている。
この様に、セラミック基板１０を貫通するビア２４と外
部接続用バンプ２２ａとが一体化されているため、半導
体装置をプラスチック製の実装基板に実装したとき、セ
ラミック基板１０とプラスチック実装基板との熱膨張率
差に起因して発生する応力に対し、外部接続用バンプ１
０とビア２４との間に境界面が実質的に存在しないこと
と相俟って、外部接続用バンプ２２ａは充分に対抗でき
る。In the semiconductor device using the semiconductor device substrate shown in FIG. 1 or 2, as shown in FIG. 3, a metal foil adhered to one surface of a ceramic substrate 10 on which a semiconductor element is mounted via an adhesive layer 12. 14 is formed into a predetermined pattern of conductor patterns 20, 20, ... By a photolithography method, etc., and the ceramic substrate 10 is penetrated in the thickness direction to make the conductor patterns 20, 20 ,. Are formed with via holes 16, 16 ... Further, the via 2 formed by filling each of the via holes 16 and 16 with a metal brazing material such as solder.
The external connection bumps made of a metal brazing material such as solder and formed in the openings of the via holes 16 and 16 ... 22a, 22a ... Are integrally connected to each of the conductor patterns 20, 20.
In this way, since the via 24 penetrating the ceramic substrate 10 and the external connection bump 22a are integrated, when the semiconductor device is mounted on a plastic mounting substrate, heat generated between the ceramic substrate 10 and the plastic mounting substrate is reduced. Bump 1 for external connection against the stress generated due to the difference in expansion coefficient
Coupled with the fact that there is substantially no boundary surface between 0 and the via 24, the external connection bump 22a can sufficiently oppose.
【００１２】かかる外部接続用バンプ２２ａ及びビア２
４は、はんだ等の金属ろう材によって形成されているた
め、セラミック基板１０よりも熱伝導率が良好である。
このため、図４に示す様に、銅箔等の金属箔１４から形
成した半導体素子搭載用のダイパッド２６に一端が当接
するビア２４の他端に、はんだ等の金属ろう材によって
形成されたサーマルバンプ２８をビア２４と一体化する
ことによって、搭載した半導体素子３０で発生した熱を
半導体装置外に容易に放散できる。このサーマルバンプ
２８も、セラミック基板１０を貫通するビア２４と一体
化されているため、セラミック基板１０とプラスチック
実装基板との熱膨張率差に起因して発生する応力に対し
て充分に対抗できる。尚、図４に示す半導体装置の場合
には、半導体素子３０は封止樹脂やキャップによって封
止される。The bump 22a for external connection and the via 2
Since No. 4 is formed of a metal brazing material such as solder, it has better thermal conductivity than the ceramic substrate 10.
Therefore, as shown in FIG. 4, a thermal solder formed of a metal brazing material such as solder is attached to the other end of the via 24, one end of which contacts the die pad 26 for mounting a semiconductor element, which is formed of the metal foil 14 such as a copper foil. By integrating the bump 28 with the via 24, the heat generated in the mounted semiconductor element 30 can be easily dissipated to the outside of the semiconductor device. Since the thermal bumps 28 are also integrated with the vias 24 penetrating the ceramic substrate 10, the stress generated due to the difference in coefficient of thermal expansion between the ceramic substrate 10 and the plastic mounting substrate can be sufficiently countered. In the case of the semiconductor device shown in FIG. 4, the semiconductor element 30 is sealed with a sealing resin or a cap.
【００１３】図１〜図４に示す半導体装置用基板又は半
導体装置においては、外部接続用バンプ２２ａが形成さ
れたセラミック基板１０の基板面に、図５に示す様に、
ソルダレジスト等の有機物から成る絶縁層３２が形成さ
れていることが好ましい。この絶縁層３２によって、半
導体装置をプラスチック製の実装基板に実装したとき、
半導体装置を構成するセラミック基板１０とプラスチッ
ク製の実装基板との熱膨張率差に起因して発生する外部
接続用バンプ２２ａに対する応力集中を可及的に緩和で
きる。また、図６に示す様に、外部接続用バンプ２２ｂ
の形状をセラミック基板１０の基板面に対して垂直方向
に延ばされた楕円球状とすることによっても、セラミッ
ク基板１０とプラスチック実装基板との熱膨張率差に起
因して発生する外部接続用バンプ２２ｂに対する応力集
中を緩和できる。楕円形状の外部接続用バンプ２２ｂが
装着された半導体装置をプラスチック製の実装基板に実
装したとき、セラミック基板１０とプラスチック製の実
装基板との基板面間の距離を、図３〜図５に示す略円球
状の外部接続用バンプ２２ａが装着された半導体装置よ
りも大にできるからである。かかる外部接続用バンプ２
２ｂが装着された半導体装置においても、図７に示す様
に、外部接続用バンプ２２ｂが装着されたセラミック基
板１０の基板面にソルダレジスト等の有機物から成る絶
縁層３２を形成することによって、外部接続用バンプ２
２ｂに対する応力集中を更に緩和できる。図６及び図７
に示す楕円球状の外部接続用バンプ２２ｂは、半導体装
置用基板に設けられたビア形成用穴部１６に、はんだ等
の金属ろう材から成る所定長の線材を挿入し、セラミッ
ク基板１０の一面から加熱する異方性加熱を施すことに
よって形成できる。In the semiconductor device substrate or semiconductor device shown in FIGS. 1 to 4, on the substrate surface of the ceramic substrate 10 on which the external connection bumps 22a are formed, as shown in FIG.
It is preferable that the insulating layer 32 made of an organic material such as a solder resist is formed. When the semiconductor device is mounted on a plastic mounting board by this insulating layer 32,
It is possible to reduce as much as possible the stress concentration on the external connection bumps 22a caused by the difference in the coefficient of thermal expansion between the ceramic substrate 10 that constitutes the semiconductor device and the plastic mounting substrate. In addition, as shown in FIG. 6, bumps 22b for external connection are provided.
The external connection bumps caused by the difference in the coefficient of thermal expansion between the ceramic substrate 10 and the plastic mounting substrate can be obtained by making the shape of the ellipse spherical in a direction perpendicular to the substrate surface of the ceramic substrate 10. The stress concentration on 22b can be relaxed. 3 to 5 show the distances between the substrate surfaces of the ceramic substrate 10 and the plastic mounting substrate when the semiconductor device having the elliptical external connection bumps 22b mounted thereon is mounted on the plastic mounting substrate. This is because it can be made larger than the semiconductor device to which the substantially spherical external connection bump 22a is mounted. Such external connection bump 2
Also in the semiconductor device having the 2b mounted thereon, as shown in FIG. 7, by forming an insulating layer 32 made of an organic material such as solder resist on the substrate surface of the ceramic substrate 10 having the external connection bumps 22b mounted thereon, Connection bump 2
The stress concentration on 2b can be further alleviated. 6 and 7
The elliptic spherical external connection bump 22b shown in FIG. 1 is formed by inserting a wire rod of a predetermined length made of a brazing metal such as solder into the via forming hole 16 provided in the semiconductor device substrate, and It can be formed by applying anisotropic heating.
【００１４】図３〜図７に示す外部接続用バンプ２２
ａ、２２ｂは、はんだ等の金属ろう材を一旦溶融して形
成するため、バンプ高さは溶融した金属ろう材の表面張
力に依存しており限界がある。また、半導体装置を実装
基板に実装する際に、外部接続用バンプ２２ａ、２２ｂ
の一部を溶融して実装基板のパッドに溶着する。このた
め、実装基板に実装したとき、半導体装置のセラミック
基板１０と実装基板との基板面間に所定間隔を形成すべ
く、所定高さ以上のバンプを形成する場合には、図８に
示す様に、はんだ等の金属ろう材から成る外部接続用バ
ンプ２２とビア２４との中心軸に沿って所定長さの銅等
の金属から成る針状部材３４を挿入することが好まし
い。かかる針状部材３４が挿入された外部接続用バンプ
２２は、はんだ等の金属ろう材がコーティングされた針
状部材３４を、半導体装置用基板に設けられたビア形成
用穴部１６に挿入し、セラミック基板１０の一面から加
熱する異方性加熱を施すことによって形成できる。この
際に、溶融した金属ろう材がセラミック基板１０の基板
面から突出する針状部材３４に沿って球状部を形成する
ため、溶融した金属ろう材から成る球状部を冷却するこ
とによって外部接続用バンプ２２を形成できる。External connection bumps 22 shown in FIGS.
Since a and 22b are formed by temporarily melting a metal brazing material such as solder, the bump height depends on the surface tension of the molten metal brazing material and has a limit. Also, when mounting the semiconductor device on the mounting substrate, the external connection bumps 22a, 22b are provided.
Is melted and welded to the pads on the mounting board. Therefore, when the bumps having a predetermined height or more are formed so as to form a predetermined space between the substrate surfaces of the ceramic substrate 10 and the mounting substrate of the semiconductor device when mounted on the mounting substrate, as shown in FIG. It is preferable to insert a needle-shaped member 34 made of a metal such as copper and having a predetermined length along the central axis between the external connection bump 22 made of a metal brazing material such as solder and the via 24. The external connection bump 22 having the needle-shaped member 34 inserted therein is obtained by inserting the needle-shaped member 34 coated with a metal brazing material such as solder into the via-forming hole 16 provided in the semiconductor device substrate. It can be formed by performing anisotropic heating in which the ceramic substrate 10 is heated from one surface. At this time, since the molten metal brazing material forms a spherical portion along the needle-shaped member 34 protruding from the substrate surface of the ceramic substrate 10, the spherical portion made of the molten metal brazing material is cooled for external connection. The bumps 22 can be formed.
【００１５】この様に、針状部材３４が挿入された外部
接続用バンプ２２を形成した半導体装置においても、図
９に示す様に、外部接続用バンプ２２が形成されたセラ
ミック基板１０の基板面にソルダレジスト等の有機物か
ら成る絶縁層３２が形成されていることが好ましい。絶
縁層３２によって、半導体装置をプラスチック製の実装
基板に実装したとき、半導体装置を構成するセラミック
基板１０とプラスチック製の実装基板との熱膨張率差に
起因して発生する外部接続用バンプ２２に対する応力集
中を可及的に緩和できる。また、針状部材３４が挿入さ
れた外部接続用バンプ２２を形成する場合には、図１０
に示す様に、外部接続用バンプ２２をセラミック基板１
０の基板面に、接着層３６を介して形成されたパッド３
８上に形成してもよい。半導体装置をプラスチック製の
実装基板に実装したとき、半導体装置を構成するセラミ
ック基板１０とプラスチック製の実装基板との熱膨張率
差に起因して発生する応力に対し、セラミック基板１０
を貫通してビア２４が形成され且つビア２４と外部接続
用バンプ２２との中心軸に沿って針状部材３４が挿入さ
れている図１０に示す外部接続用バンプ２２は、充分に
対抗できるからである。尚、外部接続用バンプ２２を形
成するパッド３８は、セラミック基板１０の基板面に接
着層３６を介して接着した銅箔等の金属箔にフォトリソ
法等を施して形成できる。Thus, also in the semiconductor device having the external connection bumps 22 in which the needle-shaped members 34 are inserted, as shown in FIG. 9, the substrate surface of the ceramic substrate 10 having the external connection bumps 22 is formed. It is preferable that an insulating layer 32 made of an organic material such as a solder resist is formed on. With the insulating layer 32, when the semiconductor device is mounted on a plastic mounting substrate, the external connection bumps 22 are generated due to the difference in the coefficient of thermal expansion between the ceramic substrate 10 and the plastic mounting substrate forming the semiconductor device. Stress concentration can be relaxed as much as possible. Further, in the case of forming the external connection bump 22 in which the needle-shaped member 34 is inserted, FIG.
As shown in FIG.
Pad 3 formed on the substrate surface of 0 with an adhesive layer 36 interposed
8 may be formed. When the semiconductor device is mounted on a plastic mounting substrate, the ceramic substrate 10 is subjected to a stress caused by a difference in coefficient of thermal expansion between the ceramic substrate 10 and the plastic mounting substrate forming the semiconductor device.
The external connection bump 22 shown in FIG. 10 in which the via 24 is formed through the needle and the needle-like member 34 is inserted along the central axis of the via 24 and the external connection bump 22 can sufficiently oppose. Is. The pad 38 for forming the bump 22 for external connection can be formed by subjecting a metal foil such as a copper foil adhered to the substrate surface of the ceramic substrate 10 via the adhesive layer 36 to a photolithography method or the like.
【００１６】図１０に示す針状部材３４が挿入された外
部接続用バンプ２２を具備する半導体装置を実装基板に
実装した状態を図１１及び図１２に示す。図１１及び図
１２に示す様に、実装された半導体装置のセラミック基
板１０と実装基板４０との基板面間の間隔は、実装基板
４０のパッド４２と当接する針状部材３４によって決定
される。このため、外接続用バンプ２２を形成するはん
だ等の金属ろう材量が少量である場合、図１１に示す様
に、外接続用バンプ２２の中心部径が他部径よりも小径
の鼓状となり、外接続用バンプ２２を形成するはんだ等
の金属ろう材量が大量である場合、図１１に示す様に、
外接続用バンプ２２の中心部径が他部径よりも大径の太
鼓状となる。従って、半導体装置を実装したとき、外接
続用バンプ２２が都合のよい形状とすべく、外接続用バ
ンプ２２を形成するはんだ等の金属ろう材量を調整する
ことが好ましい。11 and 12 show a state in which the semiconductor device having the external connection bumps 22 into which the needle-shaped members 34 shown in FIG. 10 are inserted is mounted on a mounting board. As shown in FIGS. 11 and 12, the space between the substrate surfaces of the mounted ceramic substrate 10 and the mounting substrate 40 of the semiconductor device is determined by the needle-shaped member 34 that abuts the pad 42 of the mounting substrate 40. Therefore, when the amount of the metal brazing material such as solder forming the external connection bumps 22 is small, as shown in FIG. 11, the central portion diameter of the external connection bumps 22 is smaller than the diameter of the other portions. When there is a large amount of metal brazing material such as solder for forming the bumps 22 for external connection, as shown in FIG.
The external connection bump 22 has a drum-like shape having a central portion diameter larger than the diameters of other portions. Therefore, when the semiconductor device is mounted, it is preferable to adjust the amount of metal brazing material such as solder forming the external connection bump 22 so that the external connection bump 22 has a convenient shape.
【００１７】図１〜図２に示す半導体装置用基板を用い
た図３〜図１０に示す半導体装置では、セラミック基板
１０の一面に接着層１２を介して接着された銅箔等の金
属箔１４から導体パターン２０を形成するため、メタラ
イズにより導体パターンを形成する工程を省略でき、半
導体装置の製造コストの低減を図ることができる。更
に、導体パターン２０が銅箔等の金属箔１４から形成さ
れているため、タングステン金属等をメタライズして形
成した導体パターンに比較してインダクタンス等の電気
的特性を向上できる。また、図３〜図１０に示す半導体
装置では、接着層１２が熱抵抗となるものの、はんだ等
の金属ろう材がセラミック基板１０を貫通するビア用穴
部１６に充填されて形成されたビア２４を介してセラミ
ック基板１０に熱が拡散されるため、熱拡散性が良好で
あり、且つ接着層１２の誘電率は、通常、セラミックよ
りも低いため、キャパシタンス低減に有効である。しか
も、外部接続用バンプ２２は、セラミック基板１０を貫
通するビア用穴部１６に、はんだ等の金属ろう材が充填
されて成るビア２４と一体化されている。このため、半
導体装置をプラスチック製の実装基板に実装したとき、
セラミック基板１０とプラスチック実装基板との熱膨張
率差に起因して発生する応力に対し、外部接続用バンプ
２２とビア２４とに境界面が実質的に存在しないことと
相俟って、外部接続用バンプ２２は充分に対抗できる。In the semiconductor device shown in FIGS. 3 to 10 using the semiconductor device substrate shown in FIGS. 1 to 2, a metal foil 14 such as a copper foil adhered to one surface of the ceramic substrate 10 via an adhesive layer 12. Since the conductor pattern 20 is formed from the above, the step of forming the conductor pattern by metallization can be omitted, and the manufacturing cost of the semiconductor device can be reduced. Further, since the conductor pattern 20 is formed from the metal foil 14 such as copper foil, the electrical characteristics such as inductance can be improved as compared with the conductor pattern formed by metalizing tungsten metal or the like. Further, in the semiconductor device shown in FIGS. 3 to 10, although the adhesive layer 12 has a thermal resistance, the via 24 formed by filling the via hole portion 16 penetrating the ceramic substrate 10 with the metal brazing material such as solder. Since the heat is diffused to the ceramic substrate 10 via the ceramic substrate 10, the thermal diffusivity is good, and the dielectric constant of the adhesive layer 12 is usually lower than that of the ceramic, which is effective in reducing the capacitance. Moreover, the external connection bumps 22 are integrated with the vias 24 formed by filling the via holes 16 penetrating the ceramic substrate 10 with a metal brazing material such as solder. Therefore, when the semiconductor device is mounted on a plastic mounting board,
With respect to the stress generated due to the difference in the coefficient of thermal expansion between the ceramic substrate 10 and the plastic mounting substrate, the external connection bumps 22 and the vias 24 do not substantially have a boundary surface, and the external connection is performed. The bumps 22 can sufficiently oppose each other.
【００１８】[0018]
実施例１ ９２重量％のアルミナから成るセッラミックグリーンシ
ートに、径が約０．３６ｍｍの貫通孔の複数個をピッチ
約１．５ｍｍでマトリックス状にパンチ加工した。この
セッラミックグリーンシートを大気中で約１５６０℃で
１時間焼成して貫通孔がマトリックス状に形成されたセ
ラミック基板を得た。次いで、得られたセラミック基板
に形成された貫通孔に対応するように、スルーホールが
穿設されたポリイミド系接着剤から成る厚さ約２５μｍ
のボンディングシート体をセラミック基板の一面に載置
した後、厚さ約１８μｍの銅箔をボンディングシート体
上に積層し、１７５℃で３０ｋｇ／ｃｍ2 の圧力で圧着
して半導体装置用基板を得た。得られた半導体装置用基
板は、図１に示す様に、セラミック基板１０を貫通し底
面を銅箔とするビア用穴部１６がセラミック基板１０の
他面に開口されているものであった。Example 1 A ceramic green sheet made of 92 wt% alumina was punched into a matrix with a plurality of through holes each having a diameter of about 0.36 mm at a pitch of about 1.5 mm. This ceramic green sheet was fired in the atmosphere at about 1560 ° C. for 1 hour to obtain a ceramic substrate having through holes formed in a matrix. Next, a thickness of about 25 μm made of a polyimide adhesive in which through holes are formed so as to correspond to the through holes formed in the obtained ceramic substrate.
After the bonding sheet body of 1 is placed on one surface of the ceramic substrate, a copper foil having a thickness of about 18 μm is laminated on the bonding sheet body and pressure-bonded at 175 ° C. under a pressure of 30 kg / cm 2 to obtain a semiconductor device substrate. It was As shown in FIG. 1, the obtained semiconductor device substrate had a via hole 16 penetrating the ceramic substrate 10 and having a bottom surface made of copper foil, which was opened on the other surface of the ceramic substrate 10.
【００１９】その後、銅箔に感光性レジストを塗布し、
所定パターンに露光・現像してからエッチング加工によ
って導体パターン２０を形成した後、セラミック基板１
０の導体パターン２０の形成面に半導体素子を搭載し封
止した。更に、セラミック基板１０を貫通するビア用穴
部１６に、錫・鉛共晶はんだから成る線材を所定長さに
切断したピンを挿入し、セラミック基板１０の一面から
加熱する異方性加熱を施すことによって、ビア用穴部１
６を錫・鉛共晶はんだで充填すると共に、外部接続用バ
ンプを形成して半導体装置を得た。得られた半導体装置
の外部接続用バンプは、図６に示す様に、セラミック基
板の他面に対して垂直方向に延ばされた楕円球状の外部
接続用バンプ２２ｂであった。この半導体装置をプラス
チック製の実装基板に実装した状態で、加熱・冷却サイ
クルを一定時間毎に繰り返すヒートショック試験を施し
ても、外部接続用バンプには何等の異常も現れなかっ
た。Then, a photosensitive resist is applied to the copper foil,
After exposing and developing to a predetermined pattern and forming the conductor pattern 20 by etching, the ceramic substrate 1 is formed.
A semiconductor element was mounted and sealed on the surface on which the conductor pattern 20 of 0 was formed. Furthermore, a pin obtained by cutting a wire made of tin / lead eutectic solder into a predetermined length is inserted into the via hole 16 penetrating the ceramic substrate 10, and anisotropic heating is performed by heating from one surface of the ceramic substrate 10. By this, the via hole 1
6 was filled with tin / lead eutectic solder, and bumps for external connection were formed to obtain a semiconductor device. The external connection bumps of the obtained semiconductor device were elliptic spherical external connection bumps 22b extending in a direction perpendicular to the other surface of the ceramic substrate, as shown in FIG. Even when a heat shock test in which the semiconductor device was mounted on a plastic mounting substrate and a heating / cooling cycle was repeated at regular intervals was performed, no abnormality appeared on the external connection bumps.
【００２０】実施例２ ９７重量％の窒化アルミニウムから成るセッラミックグ
リーンシートに、径が約０．５ｍｍの貫通孔の複数個を
ピッチ約２．５ｍｍでマトリックス状にパンチ加工し
た。このセッラミックグリーンシートをドライ窒素中で
約１８５０℃で３時間焼成して貫通孔がマトリックス状
に形成されたセラミック基板を得た。次いで、得られた
セラミック基板に形成された貫通孔に対応するように、
スルーホールが穿設された厚さ２５μｍのポリイミド系
接着剤から成るボンディングシート体をセラミック基板
の両面に載置した後、セラミック基板の一面側に載置し
たボンディングシート体上には、厚さ約３５μｍの銅箔
を積層すると共に、セラミック基板の他面側に載置した
ボンディングシート体上には、セラミック基板に形成さ
れた貫通孔に対応するように、スルーホールが穿設され
た厚さ約３５μｍの銅箔を積層した。これら銅箔は、実
施例１と同様にして圧着し半導体装置用基板を得た。得
られた半導体装置用基板は、セラミック基板１０を貫通
し且つセラミック基板１０の一面に圧着された銅箔を底
面とするビア用穴部１６がセラミック基板１０の他面に
圧着された銅箔面に開口されているものであった。Example 2 A ceramic green sheet made of 97% by weight of aluminum nitride was punched into a matrix with a plurality of through holes having a diameter of about 0.5 mm at a pitch of about 2.5 mm. This ceramic green sheet was baked in dry nitrogen at about 1850 ° C. for 3 hours to obtain a ceramic substrate having through holes formed in a matrix. Then, so as to correspond to the through holes formed in the obtained ceramic substrate,
After a bonding sheet body made of polyimide adhesive having a thickness of 25 μm and having through holes formed thereon is placed on both sides of the ceramic substrate, the thickness of the bonding sheet body placed on one side of the ceramic substrate is about A copper foil having a thickness of 35 μm is laminated, and a through hole is formed on the bonding sheet body placed on the other surface side of the ceramic substrate so as to correspond to the through hole formed in the ceramic substrate. A 35 μm copper foil was laminated. These copper foils were pressure-bonded in the same manner as in Example 1 to obtain a semiconductor device substrate. The obtained semiconductor device substrate is a copper foil surface having a via hole portion 16 penetrating the ceramic substrate 10 and having a bottom surface of the copper foil pressure-bonded to one surface of the ceramic substrate 10 to the other surface of the ceramic substrate 10. It had been opened to.
【００２１】その後、セラミック基板１０の両面に圧着
された銅箔の各々に感光性レジストを塗布し、所定パタ
ーンに露光・現像してからエッチング加工によって、セ
ラミック基板１０の一面に導体パターン２０を形成する
と共に、セラミック基板１０の他面に外部接続用バンプ
を形成するパッド３８（図１０）を形成した。更に、セ
ラミック基板１０の導体パターン２０の形成面に半導体
素子を搭載し封止した後、セラミック基板１０を貫通す
るビア用穴部１６に、錫・鉛共晶はんだをコーティング
した銅線材を所定長さに切断したピンを挿入し、セラミ
ック基板１０の一面から加熱する異方性加熱を施すこと
によって、ビア用穴部１６を錫・鉛共晶はんだで充填す
ると共に、半球状の外部接続用バンプ２２を形成した。
この外部接続用バンプ２２上に突出した銅線を切断し、
図１０に示す外部接続用バンプ２２を具備する半導体装
置を完成させた。この半導体装置をプラスチック製の実
装基板に実装したところ、図１１に示す様に、外部接続
用バンプ２２は、その中心部径が他部径よりも小径の鼓
状となった。かかる半導体装置を、プラスチック製の実
装基板に実装した状態において、加熱・冷却サイクルを
一定時間毎に繰り返すヒートショック試験を施しても、
外部接続用バンプには何等の異常も現れなかった。After that, a photosensitive resist is applied to each of the copper foils which are pressure-bonded on both sides of the ceramic substrate 10, exposed and developed into a predetermined pattern, and then etched to form a conductor pattern 20 on one surface of the ceramic substrate 10. At the same time, pads 38 (FIG. 10) for forming bumps for external connection were formed on the other surface of the ceramic substrate 10. Further, after the semiconductor element is mounted and sealed on the surface of the ceramic substrate 10 on which the conductor pattern 20 is formed, the via hole portion 16 penetrating the ceramic substrate 10 is coated with tin / lead eutectic solder for a predetermined length of copper wire material. By inserting the pin cut into pieces into the via hole and performing anisotropic heating by heating from one surface of the ceramic substrate 10, the via hole portion 16 is filled with tin-lead eutectic solder, and a hemispherical external connection bump is formed. 22 was formed.
Cut the copper wire protruding above the bump 22 for external connection,
A semiconductor device having the bumps 22 for external connection shown in FIG. 10 was completed. When this semiconductor device was mounted on a plastic mounting substrate, as shown in FIG. 11, the external connection bump 22 had a drum shape with its central portion diameter being smaller than the other portion diameter. Even if a heat shock test is repeated in which the semiconductor device is mounted on a plastic mounting substrate and a heating / cooling cycle is repeated at regular intervals,
No abnormality appeared on the bump for external connection.
【００２２】[0022]
【発明の効果】本発明によれば、半導体装置用基板を成
形する際に、メタライズによって導体パターンを形成す
ることを要せず、セラミック基板を使用した半導体装置
の製造コストの低減を図ることができる。また、半導体
装置をプラスチック製の実装基板に実装したとき、セラ
ミック基板とプラスチック実装基板との熱膨張率差に起
因して発生する応力に対し、外部接続用バンプが充分に
対抗できるため、実装基板に実装した半導体装置の耐熱
性を向上できる。According to the present invention, it is possible to reduce the manufacturing cost of a semiconductor device using a ceramic substrate without forming a conductor pattern by metallization when molding a semiconductor device substrate. it can. Further, when the semiconductor device is mounted on a plastic mounting board, the external connection bumps can sufficiently oppose the stress generated due to the difference in the coefficient of thermal expansion between the ceramic board and the plastic mounting board. The heat resistance of the semiconductor device mounted on can be improved.
【図１】本発明に係る半導体装置用基板の一例を示す部
分断面図である。FIG. 1 is a partial cross-sectional view showing an example of a semiconductor device substrate according to the present invention.
【図２】本発明に係る半導体装置用基板の他の例を示す
部分断面図である。FIG. 2 is a partial cross-sectional view showing another example of a semiconductor device substrate according to the present invention.
【図３】本発明に係る半導体装置の一例を示す部分断面
図である。FIG. 3 is a partial cross-sectional view showing an example of a semiconductor device according to the present invention.
【図４】本発明に係る半導体装置の他の例を示す部分断
面図である。FIG. 4 is a partial cross-sectional view showing another example of the semiconductor device according to the present invention.
【図５】本発明に係る半導体装置に設けられた外部接続
用バンプの他の例を示す部分断面図である。FIG. 5 is a partial cross-sectional view showing another example of the external connection bump provided in the semiconductor device according to the present invention.
【図６】本発明に係る半導体装置に設けられた外部接続
用バンプの他の例を示す部分断面図である。FIG. 6 is a partial cross-sectional view showing another example of the external connection bump provided in the semiconductor device according to the present invention.
【図７】本発明に係る半導体装置に設けられた外部接続
用バンプの他の例を示す部分断面図である。FIG. 7 is a partial cross-sectional view showing another example of the external connection bump provided in the semiconductor device according to the present invention.
【図８】本発明に係る半導体装置に設けられた外部接続
用バンプの他の例を示す部分断面図である。FIG. 8 is a partial cross-sectional view showing another example of the external connection bump provided in the semiconductor device according to the present invention.
【図９】本発明に係る半導体装置に設けられた外部接続
用バンプの他の例を示す部分断面図である。FIG. 9 is a partial cross-sectional view showing another example of the external connection bump provided in the semiconductor device according to the present invention.
【図１０】本発明に係る半導体装置に設けられた外部接
続用バンプの他の例を示す部分断面図である。FIG. 10 is a partial cross-sectional view showing another example of the external connection bump provided in the semiconductor device according to the present invention.
【図１１】図１０に示す外部接続用バンプを具備する半
導体装置を実装基板に実装した一態様を説明するための
部分断面図である。FIG. 11 is a partial cross-sectional view for explaining one mode in which the semiconductor device having the external connection bumps shown in FIG. 10 is mounted on a mounting substrate.
【図１２】図１０に示す外部接続用バンプを具備する半
導体装置を実装基板に実装した他の態様を説明するため
の部分断面図である。12 is a partial cross-sectional view for explaining another mode in which the semiconductor device having the external connection bump shown in FIG. 10 is mounted on a mounting substrate.
【図１３】従来の半導体装置を説明するための部分断面
図である。FIG. 13 is a partial cross-sectional view illustrating a conventional semiconductor device.
【符号の説明】 １０ セラミック基板 １２、３６ 接着層 １４ 金属箔 １６ ビア用穴部 ２０ 導体パターン ２２、２２ａ、２２ｂ 外部接続用バンプ ２４ ビア ３２ 絶縁層 ３４ 針状部材 ３８、４２ パッド ４０ 実装基板[Explanation of Codes] 10 Ceramic Substrate 12, 36 Adhesive Layer 14 Metal Foil 16 Via Hole 20 Conductor Pattern 22, 22a, 22b External Connection Bump 24 Via 32 Insulating Layer 34 Needle Member 38, 42 Pad 40 Mounting Board
Claims (8)
載されると共に、外部接続用バンプが前記セラミック基
板の他面から突出するように形成される半導体装置用基
板において、 該半導体素子が搭載されるセラミック基板の一面に、導
体パターンが形成される銅箔等の金属箔が接着層を介し
て接着され、 且つ前記金属箔を底面としセラミック基板を貫通して他
面に開口されている穴部が形成されていると共に、 前記穴部が、セラミック基板の一面に前記金属箔から形
成される導体パターンと、前記穴部の開口部に形成され
るはんだ等の金属ろう材から成る外部接続用バンプとを
電気的に接続するように、はんだ等の金属ろう材が充填
されて外部接続用バンプと一体化されるビアを形成す
る、ビア用穴部であることを特徴とする半導体装置用基
板。1. A semiconductor device is mounted on one surface of a ceramic substrate, and a semiconductor device substrate is formed such that external connection bumps are formed so as to project from the other surface of the ceramic substrate. A metal foil such as a copper foil on which a conductor pattern is formed is adhered to one surface of the ceramic substrate via an adhesive layer, and a hole portion which penetrates the ceramic substrate and is opened to the other surface is formed with the metal foil as a bottom surface. Along with the formation of the hole, a conductor pattern formed of the metal foil on one surface of the ceramic substrate, and an external connection bump formed of a metal brazing material such as solder formed in the opening of the hole. For a semiconductor device, which is a via hole filled with a metal brazing material such as solder to form a via integrated with an external connection bump so as to electrically connect substrate.
金属ろう材がビア用穴部に充填されている請求項１記載
の半導体装置用基板。2. The substrate for a semiconductor device according to claim 1, wherein the via hole is filled with a metal brazing material such as solder forming a bump for external connection.
の開口部近傍の基板面に、ソルダレジスト等の有機物か
ら成る絶縁層が形成されている請求項１又は請求項２記
載の半導体装置用基板。3. The semiconductor device according to claim 1, wherein an insulating layer made of an organic material such as a solder resist is formed on the substrate surface near the opening of the via hole opened in the ceramic substrate. substrate.
箔が、導体パターンに形成されている請求項１〜３のい
ずれか一項記載の半導体装置用基板。4. The substrate for a semiconductor device according to claim 1, wherein a metal foil adhered to one surface of the ceramic substrate is formed in a conductor pattern.
載され、且つ前記セラミック基板の他面に外部接続用バ
ンプが突出して形成された半導体装置において、 該半導体素子が搭載されるセラミック基板の一面に接着
層を介して接着された銅箔等の金属箔から成る導体パタ
ーンが形成されていると共に、 前記導体パターンを底面とし前記セラミック基板を貫通
して他面に開口されたビア用穴部に、はんだ等の金属ろ
う材が充填されて形成されたビアと、前記ビア用穴部の
開口部に形成されたはんだ等の金属ろう材から成る外部
接続用バンプとが一体に形成されていることを特徴とす
る半導体装置。5. A semiconductor device in which a semiconductor element is mounted on one surface of a ceramic substrate, and external connection bumps are formed to project on the other surface of the ceramic substrate, wherein the semiconductor element is mounted on one surface of the ceramic substrate. A conductor pattern made of a metal foil such as a copper foil adhered via an adhesive layer is formed, and a via hole opened on the other surface through the ceramic substrate with the conductor pattern as a bottom surface, A via formed by being filled with a metal brazing material such as solder, and an external connection bump formed of a metal brazing material such as solder formed in the opening of the via hole are integrally formed. Characteristic semiconductor device.
に対して垂直方向に延ばされた楕円球状である請求項５
記載の半導体装置。6. The bump for external connection has an elliptic spherical shape extending in a direction perpendicular to the surface of the ceramic substrate.
13. The semiconductor device according to claim 1.
の開口部近傍の基板面に、ソルダレジスト等の有機物か
ら成る絶縁層が形成されている請求項５又は請求項６記
載の半導体装置。7. The semiconductor device according to claim 5, wherein an insulating layer made of an organic material such as a solder resist is formed on the substrate surface near the opening of the via hole opened in the ceramic substrate.
軸に沿って、針状部材が挿入されている請求項５〜７の
いずれか一項記載の半導体装置。8. The semiconductor device according to claim 5, wherein a needle-shaped member is inserted along the central axes of the external connection bump and the via hole.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6637496A JPH09260529A (en) | 1996-03-22 | 1996-03-22 | Substrate for semiconductor device, and semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6637496A JPH09260529A (en) | 1996-03-22 | 1996-03-22 | Substrate for semiconductor device, and semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH09260529A true JPH09260529A (en) | 1997-10-03 |
Family
ID=13313999
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6637496A Pending JPH09260529A (en) | 1996-03-22 | 1996-03-22 | Substrate for semiconductor device, and semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH09260529A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000049257A (en) * | 1998-07-30 | 2000-02-18 | Kyocera Corp | Head radiation circuit board |
| JP2000243776A (en) * | 1999-02-19 | 2000-09-08 | Micronas Gmbh | Thin-film structure unit and fabrication method thereof |
| JP2014103152A (en) * | 2012-11-16 | 2014-06-05 | Renesas Electronics Corp | Semiconductor device |
| CN110574158A (en) * | 2017-05-09 | 2019-12-13 | 国际商业机器公司 | through substrate via with self-aligned solder bumps |
-
1996
- 1996-03-22 JP JP6637496A patent/JPH09260529A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000049257A (en) * | 1998-07-30 | 2000-02-18 | Kyocera Corp | Head radiation circuit board |
| JP2000243776A (en) * | 1999-02-19 | 2000-09-08 | Micronas Gmbh | Thin-film structure unit and fabrication method thereof |
| JP2014103152A (en) * | 2012-11-16 | 2014-06-05 | Renesas Electronics Corp | Semiconductor device |
| CN110574158A (en) * | 2017-05-09 | 2019-12-13 | 国际商业机器公司 | through substrate via with self-aligned solder bumps |
| JP2020520090A (en) * | 2017-05-09 | 2020-07-02 | インターナショナル・ビジネス・マシーンズ・コーポレーションＩｎｔｅｒｎａｔｉｏｎａｌ Ｂｕｓｉｎｅｓｓ Ｍａｃｈｉｎｅｓ Ｃｏｒｐｏｒａｔｉｏｎ | Method and semiconductor structure for manufacturing a semiconductor device including a through-substrate via with self-aligned solder bumps |
| CN110574158B (en) * | 2017-05-09 | 2024-02-20 | 国际商业机器公司 | Substrate via with self-aligned solder bump |
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