JP3350269B2 - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JP3350269B2
JP3350269B2 JP2165595A JP2165595A JP3350269B2 JP 3350269 B2 JP3350269 B2 JP 3350269B2 JP 2165595 A JP2165595 A JP 2165595A JP 2165595 A JP2165595 A JP 2165595A JP 3350269 B2 JP3350269 B2 JP 3350269B2
Authority
JP
Japan
Prior art keywords
semiconductor element
external lead
sintered body
lead terminals
insulating base
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2165595A
Other languages
Japanese (ja)
Other versions
JPH08222661A (en
Inventor
民男 草野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP2165595A priority Critical patent/JP3350269B2/en
Publication of JPH08222661A publication Critical patent/JPH08222661A/en
Application granted granted Critical
Publication of JP3350269B2 publication Critical patent/JP3350269B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明はコンピューター等の情報
処理装置に使用される半導体装置に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device used for an information processing device such as a computer.

【0002】[0002]

【従来の技術】従来、コンピューター等の情報処理装置
に使用される半導体装置は、半導体素子と、半導体素子
を搭載するダイパッドと、ダイパッドの周辺から所定間
隔で延びる多数の外部リード端子と、前記半導体素子、
ダイパッド及び外部リード端子の一部を被覆するモール
ド樹脂とから構成されており、ダイパッドと多数の外部
リード端子とが枠状の連結帯を介して一体的に連結形成
されたリードフレームを準備するとともに該リードフレ
ームのダイパッド上面に半導体素子を搭載固定し、次に
前記半導体素子の各電極と外部リード端子とをボンディ
ングワイヤを介して電気的に接続するとともに前記半導
体素子、ダイパッド及び外部リード端子の一部をモール
ド樹脂により被覆することによって製作されている。
2. Description of the Related Art Conventionally, a semiconductor device used for an information processing apparatus such as a computer includes a semiconductor element, a die pad on which the semiconductor element is mounted, a large number of external lead terminals extending at predetermined intervals from the periphery of the die pad, and the semiconductor device. element,
A die pad and a mold resin that covers a part of the external lead terminals are provided, and a lead frame in which the die pad and a large number of external lead terminals are integrally connected to each other through a frame-shaped connection band is prepared. A semiconductor element is mounted and fixed on the upper surface of the die pad of the lead frame. Next, each electrode of the semiconductor element is electrically connected to an external lead terminal via a bonding wire, and one of the semiconductor element, the die pad and the external lead terminal is connected. It is manufactured by covering the part with a mold resin.

【0003】尚、前記リードフレームは、銅や鉄を主成
分とする金属から成り、該銅や鉄を主成分とする金属の
薄板に従来周知の打ち抜き加工やエッチング加工等の金
属加工を施すことによって製作される。
The lead frame is made of a metal containing copper or iron as a main component, and a thin plate of the metal containing copper or iron as a main component is subjected to conventionally known metal working such as punching or etching. Produced by

【0004】またかかる従来の半導体装置は半導体素子
及び外部リード端子の一部をモールド樹脂で被覆した
後、外部リード端子を枠状の連結帯より切断分離させ、
各々の外部リード端子を電気的に独立させるとともに各
外部リード端子を外部電気回路に接続させることによっ
て内部の半導体素子は外部電気回路に電気的に接続され
る。
In such a conventional semiconductor device, after a semiconductor element and a part of an external lead terminal are covered with a mold resin, the external lead terminal is cut and separated from a frame-shaped connecting band.
By making each external lead terminal electrically independent and connecting each external lead terminal to an external electric circuit, the internal semiconductor element is electrically connected to the external electric circuit.

【0005】[0005]

【発明が解決しようとする課題】しかしながら、近時、
半導体素子は高密度化、高集積化が急激に進み電極数が
大幅に増大してきており、これに伴って半導体素子の各
電極を外部電気回路に接続する外部リード端子も線幅が
0.3mm以下と細く、且つ隣接する外部リード端子の
間隔も0.3mm以下と極めて狭いものとなってきた。
そのためこの従来の半導体装置は外部リード端子に例え
ば、外部リード端子を外部電気回路に接続させる際等に
おいて外力が印加されると該外力よって容易に変形し、
隣接する外部リード端子が接触して短絡を発生したり、
外部リード端子を所定の外部電気回路に正確、且つ強固
に電気的接続することができないという欠点を有してい
た。
However, recently,
Semiconductor devices have rapidly increased in density and integration, and the number of electrodes has increased significantly. With this, the external lead terminals connecting each electrode of the semiconductor device to an external electric circuit have a line width of 0.3 mm. The distance between adjacent external lead terminals has become extremely narrow, not more than 0.3 mm.
Therefore, this conventional semiconductor device is easily deformed by an external force when an external force is applied to the external lead terminal, for example, when the external lead terminal is connected to an external electric circuit,
Adjacent external lead terminals may touch and cause a short circuit,
There is a disadvantage that the external lead terminals cannot be accurately and firmly electrically connected to a predetermined external electric circuit.

【0006】そこで上記欠点を解消するために、上面中
央部に半導体素子が搭載される搭載部及び該搭載部周辺
から外周部にかけて扇状に導出する複数個の配線層を有
する絶縁基体と、前記絶縁基体の搭載部に搭載され、電
極が前記配線層の一端に接続されている半導体素子と、
前記配線層の他端に取着され、半導体素子を外部電気回
路に接続する複数個の外部リード端子と、前記絶縁基
体、半導体素子及び外部リード端子の一部を被覆するモ
ールド樹脂とから成る半導体装置、或いは上面中央部に
半導体素子が搭載される搭載部を有する金属基体と、前
記金属基体の上面外周部に取着され、内周部から外周部
にかけて扇状に導出する複数個の配線層を有する絶縁枠
体と、前記金属基体の搭載部に搭載され、電極が前記配
線層の一端に接続されている半導体素子と、前記配線層
の他端に取着され、半導体素子を外部電気回路に接続す
る複数個の外部リード端子と、前記金属基体、絶縁枠
体、半導体素子及び外部リード端子の一部を被覆するモ
ールド樹脂とから成る半導体装置が提案されたり、考え
られる。
In order to solve the above-mentioned drawbacks, an insulating base having a mounting portion on which a semiconductor element is mounted at the center of the upper surface and a plurality of wiring layers extending in a fan shape from the periphery of the mounting portion to the outer periphery is provided. A semiconductor element mounted on the mounting portion of the base body and having an electrode connected to one end of the wiring layer;
A semiconductor comprising a plurality of external lead terminals attached to the other end of the wiring layer and connecting the semiconductor element to an external electric circuit, and a molding resin covering a part of the insulating base, the semiconductor element and the external lead terminals A device, or a metal base having a mounting portion on which a semiconductor element is mounted in the center of the upper surface, and a plurality of wiring layers attached to the outer periphery of the upper surface of the metal base and led out in a fan shape from the inner periphery to the outer periphery. An insulating frame body, a semiconductor element mounted on the mounting portion of the metal base, and an electrode connected to one end of the wiring layer, and attached to the other end of the wiring layer, and the semiconductor element is connected to an external electric circuit. A semiconductor device comprising a plurality of external lead terminals to be connected and a mold resin covering a part of the metal base, the insulating frame, the semiconductor element and the external lead terminals has been proposed or considered.

【0007】かかる半導体装置によれば外部リード端子
が扇状に広がった配線層に取着されることから外部リー
ド端子の線幅及び隣接間隔を広いものとして外部リード
端子の変形を有効に防止しつつ隣接する外部リード端子
間の電気的絶縁を維持することが可能となる。
According to such a semiconductor device, since the external lead terminals are attached to the wiring layer which spreads in a fan shape, the line widths and adjacent intervals of the external lead terminals are increased to effectively prevent deformation of the external lead terminals. Electrical insulation between adjacent external lead terminals can be maintained.

【0008】しかしながら、これら半導体装置おいては
上面に半導体素子及び外部リード端子が搭載取着された
絶縁基体、或いは上面に半導体素子、絶縁枠体及び外部
リード端子が配された金属基体を所定の治具内にセット
するととも該治具内にエポキシ等の液状樹脂を滴下注入
し、しかる後、注入した樹脂を180 ℃程度の温度、100K
gf/mm 2 の圧力を加え熱硬化させることによって絶縁基
体や半導体素子等をモールド樹脂で被覆しており、絶縁
基体や金属基体は一般に中心線平均粗さ(Ra)がRa
≦0.3μm以下と平滑であることから絶縁基体や金属
基体がセットされた治具内にエポキシ等の液状樹脂を滴
下注入すると、該液状樹脂の絶縁基体下面や金属基体下
面における流れ性が上面側の流れ性に対し異なってしま
い、その結果、モールド樹脂内に空気が抱き込まれ、モ
ールド樹脂に貫通孔が形成されて半導体素子の気密封止
が破れ、半導体素子を長期間にわたり正常、且つ安定に
作動させることができなくなったり、モールド樹脂内の
空気によって熱の外部への伝導放散が阻害され、半導体
素子が該半導体素子自身の発する熱で高温となり、半導
体素子に熱破壊や特性に熱変化を招来させるという欠点
が誘発されてしまう。
However, in these semiconductor devices, an insulating base on which a semiconductor element and external lead terminals are mounted or mounted on an upper surface, or a metal base on which a semiconductor element, an insulating frame and external lead terminals are disposed on an upper surface, is provided. When set in a jig, a liquid resin such as epoxy is dropped into the jig, and then the injected resin is cooled to a temperature of about 180 ° C. and 100 K
The insulating base and the semiconductor element are coated with a mold resin by applying a pressure of gf / mm 2 and thermally cured, and the insulating base and the metal base generally have a center line average roughness (Ra) of Ra.
When the liquid resin such as epoxy is dropped and injected into a jig on which the insulating base and the metal base are set, the flowability of the liquid resin on the lower surface of the insulating base and the lower surface of the metal base is higher than 0.3 μm. The flow characteristics on the side are different, as a result, air is entrapped in the mold resin, a through hole is formed in the mold resin, the hermetic sealing of the semiconductor element is broken, and the semiconductor element is normal for a long time, and The semiconductor device cannot be operated stably, or conduction and dissipation of heat to the outside are hindered by air in the mold resin, and the semiconductor device becomes high in temperature due to the heat generated by the semiconductor device itself. The disadvantage of inducing change is induced.

【0009】[0009]

【発明の目的】本発明は上記諸欠点に鑑み案出されたも
ので、その目的はモールド樹脂内に空気が抱き込まれる
のを有効に防止し、半導体素子を長期間にわたり正常、
且つ安定に作動させることのできる半導体装置を提供す
ることにある。
SUMMARY OF THE INVENTION The present invention has been devised in view of the above-mentioned drawbacks, and has as its object to effectively prevent air from being entrapped in a mold resin and to allow a semiconductor element to operate normally for a long period of time.
It is another object of the present invention to provide a semiconductor device which can be operated stably.

【0010】[0010]

【課題を解決するための手段】本発明は上面中央部に半
導体素子が搭載される搭載部及び該搭載部周辺から外周
部にかけて扇状に導出する複数個の配線層を有する、酸
化アルミニウム質焼結体、窒化アルミニウム質焼結体、
ムライト質焼結体、炭化珪素質焼結体およびガラスセラ
ミックス焼結体のいずれかから成る絶縁基体と、前記絶
縁基体の半導体素子搭載部に搭載され、電極が前記配線
層の一端に接続されている半導体素子と、前記配線層の
他端に取着され、半導体素子を外部電気回路に接続する
複数個の外部リード端子と、前記絶縁基体、半導体素子
及び外部リード端子の一部を被覆するエポキシ樹脂から
成るモールド樹脂とから成る半導体装置であって、前記
絶縁基体下面の表面粗さがJIS−B−0601に規定
の中心線平均粗さ(Ra)で0.5μm≦Ra≦2.0
μmであることを特徴とするものである。
According to the present invention, there is provided an aluminum oxide sintered body having a mounting portion on which a semiconductor element is mounted at a central portion of an upper surface and a plurality of wiring layers which are led out in a fan-like manner from the periphery of the mounting portion to the outer peripheral portion. Body, aluminum nitride sintered body,
An insulating base made of any of a mullite-based sintered body, a silicon carbide-based sintered body, and a glass-ceramic sintered body, and mounted on a semiconductor element mounting portion of the insulating base; and an electrode connected to one end of the wiring layer. A semiconductor element, a plurality of external lead terminals attached to the other end of the wiring layer and connecting the semiconductor element to an external electric circuit, and an epoxy covering a part of the insulating base, the semiconductor element and the external lead terminal. A semiconductor device comprising a mold resin made of a resin, wherein a surface roughness of a lower surface of the insulating base is 0.5 μm ≦ Ra ≦ 2.0 at a center line average roughness (Ra) specified in JIS-B-0601.
μm.

【0011】[0011]

【0012】[0012]

【作用】本発明の半導体装置によれば、上面に半導体素
子等が配されている絶縁基体の下面をJIS−B−06
01に規定の中心線平均粗さ(Ra)で0.5μm≦R
a≦2.0μmの粗面としたことから上面に半導体素子
及び外部リード端子が搭載取着された絶縁基体を所定の
治具内にセットし、該治具内にエポキシの液状樹脂を滴
下注入して半導体素子等をモールド樹脂で被覆する際、
絶縁基板下面における液状樹脂の流れ性が上面側の流れ
性に対し略等しくなってモールド樹脂内への空気の抱き
込みが有効に阻止され、その結果、半導体素子をモール
ド樹脂で完全に気密封止し、半導体素子を長期間にわた
り正常、且つ安定に作動させることが可能となるととも
に半導体素子の作動時に発する熱を外部に良好に放散さ
せ、半導体素子に熱破壊が生じたり、特性の熱変化が招
来されるのを有効に防止することができる。
According to the semiconductor device of the present invention, the lower surface of the insulating base on which the semiconductor elements and the like are disposed is formed according to JIS-B-06.
0.5 at the center line average roughness (Ra) specified in 01 ≦ R
Since the surface was roughened to a ≦ 2.0 μm, the insulating substrate on which the semiconductor element and the external lead terminals were mounted on the upper surface was set in a predetermined jig, and a liquid epoxy resin was dropped into the jig. When coating semiconductor elements with mold resin
The flowability of the liquid resin on the lower surface of the insulating substrate is almost equal to the flowability on the upper surface side, effectively preventing the entrapment of air in the mold resin. As a result, the semiconductor element is completely hermetically sealed with the mold resin. In addition, it is possible to operate the semiconductor element normally and stably for a long period of time, and to radiate the heat generated during the operation of the semiconductor element to the outside. It can be effectively prevented from being invited.

【0013】[0013]

【実施例】次に本発明を添付図面に基づき詳細に説明す
る。図1は本発明の半導体装置の一実施例を示し、1は
絶縁基体、2は外部リード端子、3は半導体素子であ
る。
BRIEF DESCRIPTION OF THE DRAWINGS FIG. FIG. 1 shows an embodiment of a semiconductor device according to the present invention, wherein 1 is an insulating base, 2 is an external lead terminal, and 3 is a semiconductor element.

【0014】前記絶縁基体1はその上面中央域に半導体
素子3が搭載される搭載部1aを有しており、該搭載部
1aには半導体素子3が樹脂、ガラス、ロウ材等の接着
材を介して接着固定される。
The insulating substrate 1 has a mounting portion 1a in the center of the upper surface on which the semiconductor element 3 is mounted. The mounting portion 1a is made of a semiconductor element 3 made of an adhesive such as resin, glass, brazing material or the like. It is bonded and fixed through.

【0015】前記絶縁基体1は酸化アルミニウム質焼結
体、窒化アルミニウム質焼結体、ムライト質焼結体、炭
化珪素質焼結体およびガラスセラミックス焼結体のいず
れかから成る電気絶縁材料から成り、例えば酸化アルミ
ニウム質焼結体から成る場合には酸化アルミニウム、酸
化珪素、酸化カルシウム、酸化マグネシウム等の原料粉
末に適当なバインダー、溶剤を添加混合して泥漿状とな
すとともにこれを従来周知のドクターブレード法やカレ
ンダーロール法等によりシート状に成形してセラミック
グリーンシート(セラミック生シート)を得、しかる
後、前記セラミックグリーンシートを打ち抜き加工法等
により適当な形状に打ち抜くとともに必要に応じて複数
枚を積層し、最後に前記セラミックグリーンシートを還
元雰囲気中、約1600℃の温度で焼成することによっ
て製作される。
The insulating substrate 1 is made of an electrically insulating material made of any of an aluminum oxide sintered body, an aluminum nitride sintered body, a mullite sintered body, a silicon carbide sintered body and a glass ceramic sintered body. For example, in the case of an aluminum oxide sintered body, a raw material powder such as aluminum oxide, silicon oxide, calcium oxide, and magnesium oxide is mixed with a suitable binder and a solvent to form a slurry, which is then mixed with a conventionally known doctor. A ceramic green sheet (ceramic green sheet) is obtained by forming into a sheet by a blade method, a calendar roll method, or the like. Thereafter, the ceramic green sheet is punched into an appropriate shape by a punching method or the like, and a plurality of sheets are formed as necessary. And finally, the ceramic green sheet is placed in a reducing atmosphere for about 16 hours. It is manufactured by firing at a temperature of 0 ° C..

【0016】前記絶縁基体1はまたその上面の半導体素
子搭載部1a周辺から外周部にかけて扇状に広がる多数
の配線層4が被着形成されており、該配線層4の半導体
素子搭載部1a周辺部位には半導体素子3の各電極がボ
ンディングワイヤ5を介して電気的に接続され、また絶
縁基体1の外周部位には外部電気回路と接続される外部
リード端子2が取着されている。
The insulating substrate 1 is formed with a large number of wiring layers 4 extending in a fan shape from the periphery of the semiconductor element mounting portion 1a on the upper surface thereof to the outer peripheral portion thereof, and a portion of the wiring layer 4 around the semiconductor element mounting portion 1a. Each electrode of the semiconductor element 3 is electrically connected via a bonding wire 5, and an external lead terminal 2 connected to an external electric circuit is attached to an outer peripheral portion of the insulating base 1.

【0017】前記配線層4はタングステン、モリブデ
ン、マンガン、アルミニウム等の金属材料から成り、タ
ングステン、モリブデン、マンガン等の高融点金属から
成る場合にはタングステン等の粉末に適当なバインダ
ー、溶剤を添加混合して得た金属ペーストを前記絶縁基
体1となるセラミックグリーンシートに予め従来周知の
スクリーン印刷法等の厚膜手法により所定パターンに印
刷塗布しておくことによって絶縁基体1の半導体素子搭
載部1a周辺から外周部にかけて扇状に広がるように被
着形成され、またアルミニウム等から成る場合には絶縁
基体1の上面に蒸着法やスパッタリング法等によって所
定厚みのアルミニウム膜を被着させ、しかる後、前記ア
ルミニウム膜を従来周知のフォトリソグラフィ技術によ
り所定パターンに加工することによって絶縁基体1上で
半導体素子搭載部1a周辺から外周部にかけて扇状に広
がるように被着形成される。
The wiring layer 4 is made of a metal material such as tungsten, molybdenum, manganese, or aluminum. When the wiring layer 4 is made of a metal having a high melting point such as tungsten, molybdenum, or manganese, an appropriate binder or solvent is added to a powder of tungsten or the like. The metal paste obtained as described above is applied to a ceramic green sheet serving as the insulating substrate 1 in a predetermined pattern in advance by a known thick film method such as a screen printing method, so that the periphery of the semiconductor element mounting portion 1a of the insulating substrate 1 is formed. From an aluminum or the like, and an aluminum film having a predetermined thickness is deposited on the upper surface of the insulating substrate 1 by a vapor deposition method, a sputtering method, or the like. Process the film into a predetermined pattern using the well-known photolithography technology It is deposited and formed so as to fan out to the outer portion from the semiconductor element mounting portion 1a around on the insulating substrate 1 by Rukoto.

【0018】また前記配線層4に取着される外部リード
端子2は内部に収容する半導体素子3を外部電気回路に
接続する作用を為し、外部リード端子2を外部電気回路
基板の配線導体に接続することによって半導体素子3が
配線層4及び外部リード端子2を介して外部電気回路に
電気的に接続されることとなる。
The external lead terminals 2 attached to the wiring layer 4 serve to connect the semiconductor element 3 housed therein to an external electric circuit, and connect the external lead terminals 2 to the wiring conductors of the external electric circuit board. By the connection, the semiconductor element 3 is electrically connected to an external electric circuit via the wiring layer 4 and the external lead terminal 2.

【0019】前記外部リード端子2は該外部リード端子
2の取着される配線層4が絶縁基体1の上面中央域に位
置する半導体素子搭載部1a周辺から外周部にかけて扇
状に広がっており、絶縁基体1の外周部における線幅及
び隣接する配線層4間の間隔が広いものとなっているこ
とからその線幅及び隣接間隔を広いものとなすことがで
き、その結果、外部リード端子2に外力が印加されたと
しても該外部リード端子2に大きな変形を発生させるこ
とはなく、隣接する外部リード端子2間の電気的絶縁を
維持しつつ外部リード端子2を所定の外部電気回路に正
確、且つ確実に電気的接続することが可能となる。
The external lead terminal 2 has a wiring layer 4 to which the external lead terminal 2 is attached. The wiring layer 4 extends in a fan shape from the periphery of the semiconductor element mounting portion 1a located in the center region of the upper surface of the insulating base 1 to the outer peripheral portion. Since the line width at the outer peripheral portion of the base 1 and the space between adjacent wiring layers 4 are wide, the line width and the space between adjacent lines can be widened. As a result, external force is applied to the external lead terminals 2. Is applied, the external lead terminal 2 does not cause a large deformation, and the external lead terminal 2 is accurately connected to a predetermined external electric circuit while maintaining electrical insulation between the adjacent external lead terminals 2. It is possible to reliably perform the electrical connection.

【0020】尚、前記外部リード端子2は銅を主成分と
する銅系合金や鉄を主成分とする鉄系合金等の金属から
成り、例えば銅を主成分とする銅系合金のインゴット
(塊)を従来周知の圧延加工法を採用して所定厚みの板
状となすとともにこれにエッチング加工やパンチング加
工を施し、所定の形状となすことによって製作される。
The external lead terminal 2 is made of a metal such as a copper alloy containing copper as a main component or an iron alloy containing iron as a main component. For example, an ingot of a copper alloy containing copper as a main component is used. ) Is formed into a plate having a predetermined thickness by using a conventionally known rolling method, and is subjected to etching or punching to form a predetermined shape.

【0021】また前記外部リード端子2の配線層4への
取着は外部リード端子2を配線層4に金−錫−鉛−銀合
金や金−錫−鉛−パラジウム合金等から成るロウ材を介
しロウ付けすることによって、或いは外部リード端子2
を配線層4に超音波接合、具体的には配線層4の上面に
外部リード端子2を載置させ、しかる後、前記外部リー
ド端子2に超音波振動子(ホーン)を0.5〜5.0kgf/mm2
の圧力で押圧させるとともに振動数20〜60kHz、振幅1.0
〜10.0μmの超音波振動を0.3〜1.0秒印加することによ
って行なわれる。
The external lead terminals 2 are attached to the wiring layer 4 by using a brazing material made of a gold-tin-lead-silver alloy, a gold-tin-lead-palladium alloy, or the like. By external brazing or through external lead terminals 2
To the wiring layer 4, specifically, the external lead terminal 2 is placed on the upper surface of the wiring layer 4, and then an ultrasonic vibrator (horn) is attached to the external lead terminal 2 by 0.5 to 5.0 kgf / mm 2
With a pressure of 20 to 60 kHz and an amplitude of 1.0
It is performed by applying ultrasonic vibration of 110.0 μm for 0.3 to 1.0 second.

【0022】更に前記半導体素子3及び外部リード端子
2が取着された絶縁基板1は外部リード端子2の一部を
残してエポキシ樹脂から成るモールド樹脂6で被覆され
ており、半導体素子3を外気から完全に遮断することに
よって最終製品としての半導体装置となる。
Further, the insulating substrate 1 to which the semiconductor element 3 and the external lead terminals 2 are attached is covered with a mold resin 6 made of an epoxy resin except for a part of the external lead terminals 2. By completely isolating the semiconductor device from the semiconductor device, a semiconductor device as a final product is obtained.

【0023】前記半導体素子3及び外部リード端子2の
モールド樹脂6による被覆は、上面に半導体素子3及び
外部リード端子2が取着された絶縁基体1を所定の治具
内にセットするとともに該治具内にエポキシの液状樹脂
を滴下注入し、しかる後、注入した樹脂を180℃程度の
温度、100Kgf/mm2の圧力を加え熱硬化させることによっ
て行われる。
The coating of the semiconductor element 3 and the external lead terminals 2 with the molding resin 6 is performed by setting the insulating substrate 1 on which the semiconductor element 3 and the external lead terminals 2 are attached on the upper surface in a predetermined jig, and This is carried out by dropping and injecting a liquid epoxy resin into the component, and then thermally curing the injected resin by applying a temperature of about 180 ° C. and a pressure of 100 kgf / mm 2 .

【0024】また前記半導体素子3及び外部リード端子
2が取着された絶縁基体1はその下面がJIS−B−0
601に規定の中心線平均粗さ(Ra)で0.5μm≦
Ra≦2.0μmの粗さとなっており、これによって上
面に半導体素子3及び外部リード端子2が搭載取着され
た絶縁基体1を所定の治具内にセットし、該治具内にエ
ポキシの液状樹脂を滴下注入して半導体素子3等をモー
ルド樹脂6で被覆する際、絶縁基体1下面における液状
樹脂の流れ性が上面側の流れ性に対し略等しくなってモ
ールド樹脂6内に空気が抱き込まれるのが有効に阻止さ
れ、その結果、半導体素子3はモールド樹脂6で完全に
気密封止され、半導体素子3を長期間にわたり正常、且
つ安定に作動させることが可能になるとともに半導体素
子3の作動時に発する熱を絶縁基体1やモールド樹脂6
を介して外部に良好に放散させ、半導体素子3を常に低
温として半導体素子3に熱破壊が発生したり、特性に熱
変化を招来させたりすることがなくなる。
The lower surface of the insulating substrate 1 on which the semiconductor element 3 and the external lead terminals 2 are attached is JIS-B-0.
601: 0.5 μm ≦ in center line average roughness (Ra)
The roughness is Ra ≦ 2.0 μm, whereby the insulating substrate 1 on which the semiconductor element 3 and the external lead terminals 2 are mounted and mounted on the upper surface is set in a predetermined jig. When the semiconductor element 3 and the like are covered with the mold resin 6 by dropping and injecting the liquid resin, the flowability of the liquid resin on the lower surface of the insulating base 1 is substantially equal to the flowability on the upper surface side, so that air is held in the mold resin 6. The semiconductor element 3 is completely hermetically sealed with the mold resin 6 so that the semiconductor element 3 can be operated normally and stably for a long period of time. Heat generated during the operation of the insulating substrate 1 and the mold resin 6
And the semiconductor element 3 is always kept at a low temperature, thereby preventing the semiconductor element 3 from being thermally destructed or causing a characteristic change due to heat.

【0025】尚、前記絶縁基体1下面の粗さは中心線平
均粗さ(Ra)が0.5μm>Ra、或いはRa>2.
0μmとなると絶縁基体1がセットされた治具内にエポ
キシの液状樹脂を滴下注入した際、液状樹脂の絶縁基体
1下面における流れ性が上面側の流れ性に対し異なった
ものとなってモールド樹脂6内に空気を抱き込んでしま
う。従って、前記絶縁基体1下面の粗さは中心線平均粗
さ(Ra)で0.5μm≦Ra≦2.0μmの範囲に特
定される。
The roughness of the lower surface of the insulating substrate 1 is such that the center line average roughness (Ra) is 0.5 μm> Ra, or Ra> 2.
When the thickness is 0 μm, when the epoxy liquid resin is dropped into the jig on which the insulating base 1 is set, the flowability of the liquid resin on the lower surface of the insulating base 1 is different from the flowability on the upper surface side, and the molding resin is changed. 6 embraces the air. Therefore, the roughness of the lower surface of the insulating base 1 is specified in the range of 0.5 μm ≦ Ra ≦ 2.0 μm in center line average roughness (Ra).

【0026】[0026]

【0027】[0027]

【0028】[0028]

【0029】かくして本発明の半導体装置は外部リード
端子を外部電気回路に接続させ、内部の半導体素子を外
部電気回路に電気的に接続することによってコンピュー
ター等の情報処理装置に搭載されることとなる。
Thus, the semiconductor device of the present invention is mounted on an information processing apparatus such as a computer by connecting the external lead terminals to an external electric circuit and electrically connecting the internal semiconductor elements to the external electric circuit. .

【0030】[0030]

【発明の効果】本発明の半導体装置によれば、上面に半
導体素子等が配されている絶縁基体の下面をJIS−B
−0601に規定の中心線平均粗さ(Ra)で0.5μ
m≦Ra≦2.0μmの粗面としたことから上面に半導
体素子及び外部リード端子が搭載取着された絶縁基体を
所定の治具内にセットし、該治具内にエポキシの液状樹
脂を滴下注入して半導体素子等をモールド樹脂で被覆す
る際、絶縁基体下面における液状樹脂の流れ性が上面側
の流れ性に対し略等しくなってモールド樹脂内への空気
の抱き込みが有効に阻止され、その結果、半導体素子を
モールド樹脂で完全に気密封止し、半導体素子を長期間
にわたり正常、且つ安定に作動させることが可能となる
とともに半導体素子の作動時に発する熱を外部に良好に
放散させ、半導体素子に熱破壊が生じたり、特性の熱変
化が招来されるのを有効に防止することができる。
According to the semiconductor device of the present invention, the lower surface of the insulating base on which the semiconductor element and the like are disposed on the upper surface is JIS-B
0.5 μm in center line average roughness (Ra) specified in −0601
Since the surface was roughened so that m ≦ Ra ≦ 2.0 μm, the insulating substrate on which the semiconductor element and the external lead terminals were mounted on the upper surface was set in a predetermined jig, and a liquid epoxy resin was set in the jig. When the semiconductor element and the like are coated with the mold resin by dropping and injecting, the flowability of the liquid resin on the lower surface of the insulating base is substantially equal to the flowability on the upper surface side, and the entrapment of air in the mold resin is effectively prevented. As a result, the semiconductor element is completely hermetically sealed with the mold resin, and the semiconductor element can be operated normally and stably for a long period of time, and the heat generated during the operation of the semiconductor element is radiated well to the outside. In addition, it is possible to effectively prevent the semiconductor element from being thermally destructed or from causing a thermal change in characteristics.

【図面の簡単な説明】[Brief description of the drawings]

【図1】 本発明の半導体装置の一実施例を示す断面図
である。
FIG. 1 is a sectional view showing one embodiment of a semiconductor device of the present invention.

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】上面中央部に半導体素子が搭載される搭載
部及び該搭載部周辺から外周部にかけて扇状に導出する
複数個の配線層を有する、酸化アルミニウム質焼結体、
窒化アルミニウム質焼結体、ムライト質焼結体、炭化珪
素質焼結体およびガラスセラミックス焼結体のいずれか
から成る絶縁基体と、前記絶縁基体の半導体素子搭載部
に搭載され、電極が前記配線層の一端に接続されている
半導体素子と、前記配線層の他端に取着され、半導体素
子を外部電気回路に接続する複数個の外部リード端子
と、前記絶縁基体、半導体素子及び外部リード端子の一
部を被覆するエポキシ樹脂から成るモールド樹脂とから
成る半導体装置であって、前記絶縁基体下面の表面粗さ
がJIS0601に規定の中心線平均粗さ(R
a)で0.5μm≦Ra≦2.0μmであることを特徴
とする半導体装置。
An aluminum oxide sintered body having a mounting portion on which a semiconductor element is mounted at a central portion of an upper surface, and a plurality of wiring layers which are led out in a fan shape from a periphery of the mounting portion to an outer peripheral portion ;
Aluminum nitride sintered body, mullite sintered body, silicon carbide
Either an elementary sintered body or a glass ceramic sintered body
An insulating base comprising: a semiconductor element mounted on a semiconductor element mounting portion of the insulating base; an electrode connected to one end of the wiring layer; and a semiconductor element mounted on the other end of the wiring layer. A semiconductor device comprising: a plurality of external lead terminals connected to a circuit; and a mold resin made of an epoxy resin covering a part of the insulating base, the semiconductor element and the external lead terminals, wherein a surface roughness of a lower surface of the insulating base is provided. Is the center line average roughness (R) specified in JIS - B - 0601.
a) the semiconductor device according to a), wherein 0.5 μm ≦ Ra ≦ 2.0 μm.
JP2165595A 1995-02-09 1995-02-09 Semiconductor device Expired - Fee Related JP3350269B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2165595A JP3350269B2 (en) 1995-02-09 1995-02-09 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2165595A JP3350269B2 (en) 1995-02-09 1995-02-09 Semiconductor device

Publications (2)

Publication Number Publication Date
JPH08222661A JPH08222661A (en) 1996-08-30
JP3350269B2 true JP3350269B2 (en) 2002-11-25

Family

ID=12061072

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2165595A Expired - Fee Related JP3350269B2 (en) 1995-02-09 1995-02-09 Semiconductor device

Country Status (1)

Country Link
JP (1) JP3350269B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1187572A (en) * 1997-09-10 1999-03-30 Oki Electric Ind Co Ltd Resin sealed semiconductor device and production thereof
JP7083256B2 (en) * 2018-02-19 2022-06-10 富士電機株式会社 Semiconductor module and its manufacturing method

Also Published As

Publication number Publication date
JPH08222661A (en) 1996-08-30

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