JPH08222661A - Semiconductor - Google Patents
SemiconductorInfo
- Publication number
- JPH08222661A JPH08222661A JP2165595A JP2165595A JPH08222661A JP H08222661 A JPH08222661 A JP H08222661A JP 2165595 A JP2165595 A JP 2165595A JP 2165595 A JP2165595 A JP 2165595A JP H08222661 A JPH08222661 A JP H08222661A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- external lead
- lead terminals
- insulating substrate
- wiring layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明はコンピューター等の情報
処理装置に使用される半導体装置に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device used in an information processing device such as a computer.
【0002】[0002]
【従来の技術】従来、コンピューター等の情報処理装置
に使用される半導体装置は、半導体素子と、半導体素子
を搭載するダイパッドと、ダイパッドの周辺から所定間
隔で延びる多数の外部リード端子と、前記半導体素子、
ダイパッド及び外部リード端子の一部を被覆するモール
ド樹脂とから構成されており、ダイパッドと多数の外部
リード端子とが枠状の連結帯を介して一体的に連結形成
されたリードフレームを準備するとともに該リードフレ
ームのダイパッド上面に半導体素子を搭載固定し、次に
前記半導体素子の各電極と外部リード端子とをボンディ
ングワイヤを介して電気的に接続するとともに前記半導
体素子、ダイパッド及び外部リード端子の一部をモール
ド樹脂により被覆することによって製作されている。2. Description of the Related Art Conventionally, a semiconductor device used in an information processing device such as a computer includes a semiconductor element, a die pad on which the semiconductor element is mounted, a large number of external lead terminals extending from the periphery of the die pad at predetermined intervals, and the semiconductor element. element,
A lead frame, which is composed of a die pad and a mold resin that covers a part of the external lead terminals, and in which the die pad and a large number of external lead terminals are integrally connected and formed via a frame-like connecting band, is prepared. A semiconductor element is mounted and fixed on the upper surface of the die pad of the lead frame, and then each electrode of the semiconductor element and an external lead terminal are electrically connected through a bonding wire and one of the semiconductor element, the die pad and the external lead terminal is connected. It is manufactured by covering the part with a mold resin.
【0003】尚、前記リードフレームは、銅や鉄を主成
分とする金属から成り、該銅や鉄を主成分とする金属の
薄板に従来周知の打ち抜き加工やエッチング加工等の金
属加工を施すことによって製作される。The lead frame is made of a metal containing copper or iron as a main component, and a thin plate of the metal containing copper or iron as a main component is subjected to metal processing such as conventionally known punching or etching. Produced by.
【0004】またかかる従来の半導体装置は半導体素子
及び外部リード端子の一部をモールド樹脂で被覆した
後、外部リード端子を枠状の連結帯より切断分離させ、
各々の外部リード端子を電気的に独立させるとともに各
外部リード端子を外部電気回路に接続させることによっ
て内部の半導体素子は外部電気回路に電気的に接続され
る。Further, in such a conventional semiconductor device, after covering a part of the semiconductor element and the external lead terminal with a molding resin, the external lead terminal is cut and separated from a frame-shaped connecting band,
By electrically separating each external lead terminal and connecting each external lead terminal to the external electric circuit, the internal semiconductor element is electrically connected to the external electric circuit.
【0005】[0005]
【発明が解決しようとする課題】しかしながら、近時、
半導体素子は高密度化、高集積化が急激に進み電極数が
大幅に増大してきており、これに伴って半導体素子の各
電極を外部電気回路に接続する外部リード端子も線幅が
0.3mm以下と細く、且つ隣接する外部リード端子の
間隔も0.3mm以下と極めて狭いものとなってきた。
そのためこの従来の半導体装置は外部リード端子に例え
ば、外部リード端子を外部電気回路に接続させる際等に
おいて外力が印加されると該外力よって容易に変形し、
隣接する外部リード端子が接触して短絡を発生したり、
外部リード端子を所定の外部電気回路に正確、且つ強固
に電気的接続することができないという欠点を有してい
た。However, in recent years,
The number of electrodes of semiconductor devices is rapidly increasing due to the higher density and higher integration, and along with this, the external lead terminals for connecting each electrode of the semiconductor device to an external electric circuit have a line width of 0.3 mm. The distance between the external lead terminals is as narrow as the following, and the distance between the adjacent external lead terminals is extremely narrow at 0.3 mm or less.
Therefore, this conventional semiconductor device is easily deformed by an external force when the external force is applied to the external lead terminal, for example, when the external lead terminal is connected to an external electric circuit,
Adjacent external lead terminals may come into contact with each other to cause a short circuit,
It has a drawback that the external lead terminals cannot be accurately and firmly electrically connected to a predetermined external electric circuit.
【0006】そこで上記欠点を解消するために、上面中
央部に半導体素子が搭載される搭載部及び該搭載部周辺
から外周部にかけて扇状に導出する複数個の配線層を有
する絶縁基体と、前記絶縁基体の搭載部に搭載され、電
極が前記配線層の一端に接続されている半導体素子と、
前記配線層の他端に取着され、半導体素子を外部電気回
路に接続する複数個の外部リード端子と、前記絶縁基
体、半導体素子及び外部リード端子の一部を被覆するモ
ールド樹脂とから成る半導体装置、或いは上面中央部に
半導体素子が搭載される搭載部を有する金属基体と、前
記金属基体の上面外周部に取着され、内周部から外周部
にかけて扇状に導出する複数個の配線層を有する絶縁枠
体と、前記金属基体の搭載部に搭載され、電極が前記配
線層の一端に接続されている半導体素子と、前記配線層
の他端に取着され、半導体素子を外部電気回路に接続す
る複数個の外部リード端子と、前記金属基体、絶縁枠
体、半導体素子及び外部リード端子の一部を被覆するモ
ールド樹脂とから成る半導体装置が提案されたり、考え
られる。In order to solve the above-mentioned drawbacks, an insulating substrate having a mounting portion on which a semiconductor element is mounted in the central portion of the upper surface and a plurality of wiring layers extending in a fan shape from the periphery of the mounting portion to the outer peripheral portion, and the insulation A semiconductor element mounted on the mounting portion of the base body and having an electrode connected to one end of the wiring layer;
A semiconductor including a plurality of external lead terminals attached to the other end of the wiring layer and connecting a semiconductor element to an external electric circuit, and a mold resin covering a part of the insulating substrate, the semiconductor element and the external lead terminal. A device, or a metal base having a mounting portion on which a semiconductor element is mounted in the center of the top surface, and a plurality of wiring layers attached to the outer circumference of the top surface of the metal base and leading out in a fan shape from the inner circumference to the outer circumference. An insulating frame having the same, a semiconductor element mounted on the mounting portion of the metal base and having an electrode connected to one end of the wiring layer, and attached to the other end of the wiring layer to attach the semiconductor element to an external electric circuit. A semiconductor device including a plurality of external lead terminals to be connected and a mold resin that covers a part of the metal base, the insulating frame, the semiconductor element, and the external lead terminals has been proposed or considered.
【0007】かかる半導体装置によれば外部リード端子
が扇状に広がった配線層に取着されることから外部リー
ド端子の線幅及び隣接間隔を広いものとして外部リード
端子の変形を有効に防止しつつ隣接する外部リード端子
間の電気的絶縁を維持することが可能となる。According to such a semiconductor device, since the external lead terminals are attached to the wiring layer spreading in a fan shape, the external lead terminals are effectively prevented from being deformed by increasing the line width and the adjacent space of the external lead terminals. It is possible to maintain the electrical insulation between the adjacent external lead terminals.
【0008】しかしながら、これら半導体装置おいては
上面に半導体素子及び外部リード端子が搭載取着された
絶縁基体、或いは上面に半導体素子、絶縁枠体及び外部
リード端子が配された金属基体を所定の治具内にセット
するととも該治具内にエポキシ等の液状樹脂を滴下注入
し、しかる後、注入した樹脂を180 ℃程度の温度、100K
gf/mm 2 の圧力を加え熱硬化させることによって絶縁基
体や半導体素子等をモールド樹脂で被覆しており、絶縁
基体や金属基体は一般に中心線平均粗さ(Ra)がRa
≦0.3μm以下と平滑であることから絶縁基体や金属
基体がセットされた治具内にエポキシ等の液状樹脂を滴
下注入すると、該液状樹脂の絶縁基体下面や金属基体下
面における流れ性が上面側の流れ性に対し異なってしま
い、その結果、モールド樹脂内に空気が抱き込まれ、モ
ールド樹脂に貫通孔が形成されて半導体素子の気密封止
が破れ、半導体素子を長期間にわたり正常、且つ安定に
作動させることができなくなったり、モールド樹脂内の
空気によって熱の外部への伝導放散が阻害され、半導体
素子が該半導体素子自身の発する熱で高温となり、半導
体素子に熱破壊や特性に熱変化を招来させるという欠点
が誘発されてしまう。However, in these semiconductor devices, an insulating base having a semiconductor element and external lead terminals mounted and attached on the upper surface, or a metal base having the semiconductor element, an insulating frame and external lead terminals arranged on the upper surface is predetermined. When set in the jig, liquid resin such as epoxy is dropped and injected into the jig, and then the injected resin is heated at a temperature of about 180 ° C for 100K.
The insulating substrate, the semiconductor element, etc. are covered with the mold resin by applying a pressure of gf / mm 2 and thermosetting, and the insulating substrate and the metal substrate generally have a center line average roughness (Ra) of Ra.
Since a liquid resin such as epoxy is dropped into a jig in which an insulating substrate or a metal substrate is set, the fluidity of the liquid resin on the lower surface of the insulating substrate or the lower surface of the metal substrate is the upper surface because the smoothness is ≦ 0.3 μm or less. As a result, air is enclosed in the mold resin, a through hole is formed in the mold resin, the airtight sealing of the semiconductor element is broken, and the semiconductor element is kept normal for a long period of time. It becomes impossible to operate it stably, or the air inside the mold resin blocks the conduction and dissipation of heat to the outside, and the semiconductor element becomes high temperature due to the heat generated by the semiconductor element itself, causing the semiconductor element to be destroyed by heat or its characteristics. The drawback is that it induces change.
【0009】[0009]
【発明の目的】本発明は上記諸欠点に鑑み案出されたも
ので、その目的はモールド樹脂内に空気が抱き込まれる
のを有効に防止し、半導体素子を長期間にわたり正常、
且つ安定に作動させることのできる半導体装置を提供す
ることにある。DISCLOSURE OF THE INVENTION The present invention has been devised in view of the above-mentioned drawbacks, and its purpose is to effectively prevent air from being trapped in the mold resin, and to keep the semiconductor element normal for a long period of time.
Another object of the present invention is to provide a semiconductor device that can be stably operated.
【0010】[0010]
【課題を解決するための手段】本発明は上面中央部に半
導体素子が搭載される搭載部及び該搭載部周辺から外周
部にかけて扇状に導出する複数個の配線層を有する絶縁
基体と、前記絶縁基体の半導体素子搭載部に搭載され、
電極が前記配線層の一端に接続されている半導体素子
と、前記配線層の他端に取着され、半導体素子を外部電
気回路に接続する複数個の外部リード端子と、前記絶縁
基体、半導体素子及び外部リード端子の一部を被覆する
モールド樹脂とから成る半導体装置であって、前記絶縁
基体下面の表面粗さがJISーBー0601に規定の中
心線平均粗さ(Ra)で0.5μm≦Ra≦2.0μm
であることを特徴とするものである。According to the present invention, there is provided an insulating base having a mounting portion on which a semiconductor element is mounted in a central portion of an upper surface and a plurality of wiring layers extending in a fan shape from a periphery of the mounting portion to an outer peripheral portion, and the insulating body. It is mounted on the semiconductor element mounting part of the base,
A semiconductor element having electrodes connected to one end of the wiring layer, a plurality of external lead terminals attached to the other end of the wiring layer to connect the semiconductor element to an external electric circuit, the insulating substrate, and the semiconductor element. And a mold resin that covers a part of the external lead terminals, wherein the surface roughness of the lower surface of the insulating substrate is 0.5 μm in terms of center line average roughness (Ra) specified in JIS-B-0601. ≦ Ra ≦ 2.0 μm
It is characterized by being.
【0011】また本発明は上面中央部に半導体素子が搭
載される搭載部を有する金属基体と、前記金属基体の上
面外周部に取着され、内周部から外周部にかけて扇状に
導出する複数個の配線層を有する絶縁枠体と、前記金属
基体の半導体素子搭載部に搭載され、電極が前記配線層
の一端に接続されている半導体素子と、前記配線層の他
端に取着され、半導体素子を外部電気回路に接続する複
数個の外部リード端子と、前記金属基体、絶縁枠体、半
導体素子及び外部リード端子の一部を被覆するモールド
樹脂とから成る半導体装置であって、前記金属基体下面
の表面粗さがJISーBー0601に規定の中心線平均
粗さ(Ra)で0.5μm≦Ra≦2.0μmであるこ
とを特徴とするものである。Further, according to the present invention, a metal base having a mounting portion on which a semiconductor element is mounted in the center of the upper surface, and a plurality of metal bases attached to the outer peripheral surface of the upper surface and led out in a fan shape from the inner peripheral portion to the outer peripheral portion. An insulating frame having a wiring layer, a semiconductor element mounted on a semiconductor element mounting portion of the metal base, and having electrodes connected to one end of the wiring layer; and a semiconductor element attached to the other end of the wiring layer. What is claimed is: 1. A semiconductor device comprising: a plurality of external lead terminals for connecting an element to an external electric circuit; and a metal base, an insulating frame, a semiconductor element, and a mold resin that covers a part of the external lead terminal. It is characterized in that the surface roughness of the lower surface is 0.5 μm ≦ Ra ≦ 2.0 μm in terms of center line average roughness (Ra) specified in JIS-B-0601.
【0012】[0012]
【作用】本発明の半導体装置によれば、上面に半導体素
子等が配されている絶縁基体や金属基体の下面をJIS
ーBー0601に規定の中心線平均粗さ(Ra)で0.
5μm≦Ra≦2.0μmの粗面としたことから上面に
半導体素子及び外部リード端子が搭載取着された絶縁基
体、或いは上面に半導体素子、絶縁枠体及び外部リード
端子が配された金属基体を所定の治具内にセットし、該
治具内にエポキシ等の液状樹脂を滴下注入して半導体素
子等をモールド樹脂で被覆する際、絶縁基体下面や金属
基体下面における液状樹脂の流れ性が上面側の流れ性に
対し略等しくなってモールド樹脂内への空気の抱き込み
が有効に阻止され、その結果、半導体素子をモールド樹
脂で完全に気密封止し、半導体素子を長期間にわたり正
常、且つ安定に作動させることが可能となるとともに半
導体素子の作動時に発する熱を外部に良好に放散させ、
半導体素子に熱破壊が生じたり、特性に熱変化が招来す
るのを有効に防止することができる。According to the semiconductor device of the present invention, the lower surface of the insulating base or the metal base on which the semiconductor element and the like are arranged is JIS.
-B-0601 has a center line average roughness (Ra) of 0.
Since it is a rough surface of 5 μm ≦ Ra ≦ 2.0 μm, an insulating substrate on which a semiconductor element and an external lead terminal are mounted and attached on the upper surface, or a metal substrate on which a semiconductor element, an insulating frame and an external lead terminal are arranged Is set in a predetermined jig, and when a liquid resin such as epoxy is dropped into the jig and the semiconductor element or the like is covered with the mold resin, the flowability of the liquid resin on the lower surface of the insulating substrate or the lower surface of the metal substrate is reduced. The flowability on the upper surface side is almost equal to effectively prevent the inclusion of air in the molding resin, and as a result, the semiconductor element is completely hermetically sealed with the molding resin, and the semiconductor element is kept normal for a long period of time. In addition, it is possible to operate stably and dissipate the heat generated during the operation of the semiconductor element to the outside well,
It is possible to effectively prevent the semiconductor element from being thermally destroyed and the characteristics from being thermally changed.
【0013】[0013]
【実施例】次に本発明を添付図面に基づき詳細に説明す
る。図1は本発明の半導体装置の一実施例を示し、1は
絶縁基体、2は外部リード端子、3は半導体素子であ
る。The present invention will now be described in detail with reference to the accompanying drawings. FIG. 1 shows an embodiment of a semiconductor device of the present invention, 1 is an insulating substrate, 2 is an external lead terminal, and 3 is a semiconductor element.
【0014】前記絶縁基体1はその上面中央域に半導体
素子3が搭載される搭載部1aを有しており、該搭載部
1aには半導体素子3が樹脂、ガラス、ロウ材等の接着
材を介して接着固定される。The insulating base 1 has a mounting portion 1a on the upper surface of which a semiconductor element 3 is mounted, and the mounting portion 1a is covered with an adhesive material such as resin, glass or brazing material. It is adhesively fixed through.
【0015】前記絶縁基体1は酸化アルミニウム質焼結
体、窒化アルミニウム質焼結体、ムライト質焼結体、炭
化珪素質焼結体、ガラスセラミックス焼結体等の電気絶
縁材料から成り、例えば酸化アルミニウム質焼結体から
成る場合には酸化アルミニウム、酸化珪素、酸化カルシ
ウム、酸化マグネシウム等の原料粉末に適当なバインダ
ー、溶剤を添加混合して泥漿状となすとともにこれを従
来周知のドクターブレード法やカレンダーロール法等に
よりシート状に成形してセラミックグリーンシート(セ
ラミック生シート)を得、しかる後、前記セラミックグ
リーンシートを打ち抜き加工法等により適当な形状に打
ち抜くとともに必要に応じて複数枚を積層し、最後に前
記セラミックグリーンシートを還元雰囲気中、約160
0℃の温度で焼成することによって製作される。The insulating substrate 1 is made of an electrically insulating material such as an aluminum oxide sintered body, an aluminum nitride sintered body, a mullite sintered body, a silicon carbide sintered body, and a glass ceramic sintered body. When it is made of an aluminum-based sintered body, it is made into a sludge form by adding and mixing an appropriate binder and solvent to raw material powders of aluminum oxide, silicon oxide, calcium oxide, magnesium oxide, etc. A ceramic green sheet (ceramic green sheet) is obtained by forming it into a sheet shape by a calender roll method or the like, and thereafter, the ceramic green sheet is punched into an appropriate shape by a punching method or the like, and a plurality of sheets are laminated as necessary. Finally, in the reducing atmosphere, the ceramic green sheet is about 160
It is manufactured by firing at a temperature of 0 ° C.
【0016】前記絶縁基体1はまたその上面の半導体素
子搭載部1a周辺から外周部にかけて扇状に広がる多数
の配線層4が被着形成されており、該配線層4の半導体
素子搭載部1a周辺部位には半導体素子3の各電極がボ
ンディングワイヤ5を介して電気的に接続され、また絶
縁基体1の外周部位には外部電気回路と接続される外部
リード端子2が取着されている。On the upper surface of the insulating substrate 1, a large number of wiring layers 4 that spread out in a fan shape from the periphery of the semiconductor element mounting portion 1a to the outer peripheral portion are adhered and formed, and the wiring layer 4 is surrounded by the semiconductor element mounting portion 1a. The electrodes of the semiconductor element 3 are electrically connected to each other via bonding wires 5, and external lead terminals 2 connected to an external electric circuit are attached to the outer peripheral portion of the insulating substrate 1.
【0017】前記配線層4はタングステン、モリブデ
ン、マンガン、アルミニウム等の金属材料から成り、タ
ングステン、モリブデン、マンガン等の高融点金属から
成る場合にはタングステン等の粉末に適当なバインダ
ー、溶剤を添加混合して得た金属ペーストを前記絶縁基
体1となるセラミックグリーンシートに予め従来周知の
スクリーン印刷法等の厚膜手法により所定パターンに印
刷塗布しておくことによって絶縁基体1の半導体素子搭
載部1a周辺から外周部にかけて扇状に広がるように被
着形成され、またアルミニウム等から成る場合には絶縁
基体1の上面に蒸着法やスパッタリング法等によって所
定厚みのアルミニウム膜を被着させ、しかる後、前記ア
ルミニウム膜を従来周知のフォトリソグラフィ技術によ
り所定パターンに加工することによって絶縁基体1上で
半導体素子搭載部1a周辺から外周部にかけて扇状に広
がるように被着形成される。The wiring layer 4 is made of a metal material such as tungsten, molybdenum, manganese and aluminum. By surrounding the semiconductor element mounting portion 1a of the insulating substrate 1 by printing and applying the metal paste thus obtained in advance to the ceramic green sheet to be the insulating substrate 1 in a predetermined pattern by a thick film method such as a conventionally known screen printing method. From the aluminum to the outer peripheral portion so as to spread in a fan shape, and when it is made of aluminum or the like, an aluminum film having a predetermined thickness is deposited on the upper surface of the insulating substrate 1 by a vapor deposition method, a sputtering method, or the like. The film is processed into a predetermined pattern by the well-known photolithography technology. It is deposited and formed so as to fan out to the outer portion from the semiconductor element mounting portion 1a around on the insulating substrate 1 by Rukoto.
【0018】また前記配線層4に取着される外部リード
端子2は内部に収容する半導体素子3を外部電気回路に
接続する作用を為し、外部リード端子2を外部電気回路
基板の配線導体に接続することによって半導体素子3が
配線層4及び外部リード端子2を介して外部電気回路に
電気的に接続されることとなる。The external lead terminals 2 attached to the wiring layer 4 have a function of connecting the semiconductor element 3 housed therein to an external electric circuit, and the external lead terminals 2 serve as wiring conductors of the external electric circuit board. By connecting, the semiconductor element 3 is electrically connected to the external electric circuit via the wiring layer 4 and the external lead terminal 2.
【0019】前記外部リード端子2は該外部リード端子
2の取着される配線層4が絶縁基体1の上面中央域に位
置する半導体素子搭載部1a周辺から外周部にかけて扇
状に広がっており、絶縁基体1の外周部における線幅及
び隣接する配線層4間の間隔が広いものとなっているこ
とからその線幅及び隣接間隔を広いものとなすことがで
き、その結果、外部リード端子2に外力が印加されたと
しても該外部リード端子2に大きな変形を発生させるこ
とはなく、隣接する外部リード端子2間の電気的絶縁を
維持しつつ外部リード端子2を所定の外部電気回路に正
確、且つ確実に電気的接続することが可能となる。In the external lead terminal 2, the wiring layer 4 to which the external lead terminal 2 is attached spreads in a fan shape from the periphery of the semiconductor element mounting portion 1a located in the central area of the upper surface of the insulating substrate 1 to the outer peripheral portion, and insulation is provided. Since the line width in the outer peripheral portion of the base 1 and the space between the adjacent wiring layers 4 are wide, the line width and the space between adjacent wiring layers can be wide, and as a result, external force is applied to the external lead terminals 2. Does not cause large deformation of the external lead terminals 2, and the external lead terminals 2 are accurately and accurately connected to a predetermined external electric circuit while maintaining electrical insulation between the adjacent external lead terminals 2. It is possible to make a reliable electrical connection.
【0020】尚、前記外部リード端子2は銅を主成分と
する銅系合金や鉄を主成分とする鉄系合金等の金属から
成り、例えば銅を主成分とする銅系合金のインゴット
(塊)を従来周知の圧延加工法を採用して所定厚みの板
状となすとともにこれにエッチング加工やパンチング加
工を施し、所定の形状となすことによって製作される。The external lead terminals 2 are made of a metal such as a copper-based alloy containing copper as a main component or an iron-based alloy containing iron as a main component. For example, an ingot (lump) of a copper-based alloy containing copper as a main component is used. ) Is formed into a plate having a predetermined thickness by using a well-known rolling method, and is subjected to etching or punching to obtain a predetermined shape.
【0021】また前記外部リード端子2の配線層4への
取着は外部リード端子2を配線層4に金ー錫ー鉛ー銀合
金や金ー錫ー鉛ーパラジウム合金等から成るロウ材を介
しロウ付けすることによって、或いは外部リード端子2
を配線層4に超音波接合、具体的には配線層4の上面に
外部リード端子2を載置させ、しかる後、前記外部リー
ド端子2に超音波振動子(ホーン)を0.5 〜5.0Kgf/mm
2 の圧力で押圧させるとともに振動数20〜60KHz 、振幅
1.0 〜10.0μm の超音波振動を0.3 〜1.0 秒印加するこ
とによって行われる。The external lead terminals 2 are attached to the wiring layer 4 by connecting the external lead terminals 2 to the wiring layer 4 through a brazing material made of gold-tin-lead-silver alloy or gold-tin-lead-palladium alloy. By brazing or external lead terminal 2
Is ultrasonically bonded to the wiring layer 4, specifically, the external lead terminal 2 is placed on the upper surface of the wiring layer 4, and then an ultrasonic transducer (horn) is placed on the external lead terminal 2 at 0.5 to 5.0 kgf /. mm
Pressing with pressure of 2 and vibration frequency 20-60KHz, amplitude
It is performed by applying ultrasonic vibration of 1.0 to 10.0 μm for 0.3 to 1.0 seconds.
【0022】更に前記半導体素子3及び外部リード端子
2が取着された絶縁基体1は外部リード端子2の一部を
残してエポキシ樹脂等から成るモールド樹脂6で被覆さ
れており、半導体素子3を外気から完全に遮断すること
によって最終製品としての半導体装置となる。Further, the insulating substrate 1 to which the semiconductor element 3 and the external lead terminals 2 are attached is covered with a mold resin 6 made of epoxy resin or the like, leaving a part of the external lead terminals 2, and the semiconductor element 3 is The semiconductor device as the final product is obtained by completely shutting off from the outside air.
【0023】前記半導体素子3及び外部リード端子2の
モールド樹脂6による被覆は、上面に半導体素子3及び
外部リード端子2が取着された絶縁基体1を所定の治具
内にセットするとともに該治具内にエポキシ等の液状樹
脂を滴下注入し、しかる後、注入した樹脂を180 ℃程度
の温度、100Kgf/mm 2 の圧力を加え熱硬化させることに
よって行われる。To cover the semiconductor element 3 and the external lead terminals 2 with the mold resin 6, the insulating substrate 1 having the semiconductor element 3 and the external lead terminals 2 attached to the upper surface is set in a predetermined jig and the curing is performed. Liquid resin such as epoxy is dropped into the tool, and then the injected resin is thermally cured by applying a temperature of about 180 ° C. and a pressure of 100 Kgf / mm 2 .
【0024】また前記半導体素子3及び外部リード端子
2が取着された絶縁基体1はその下面がJISーBー0
601に規定の中心線平均粗さ(Ra)で0.5μm≦
Ra≦2.0μmの粗さとなっており、これによって上
面に半導体素子3及び外部リード端子2が搭載取着され
た絶縁基体1を所定の治具内にセットし、該治具内にエ
ポキシ等の液状樹脂を滴下注入して半導体素子3等をモ
ールド樹脂6で被覆する際、絶縁基体1下面における液
状樹脂の流れ性が上面側の流れ性に対し略等しくなって
モールド樹脂6内に空気が抱き込まれるのが有効に阻止
され、その結果、半導体素子3はモールド樹脂6で完全
に気密封止され、半導体素子3を長期間にわたり正常、
且つ安定に作動させることが可能になるとともに半導体
素子3の作動時に発する熱を絶縁基体1やモールド樹脂
6を介して外部に良好に放散させ、半導体素子3を常に
低温として半導体素子3に熱破壊が発生したり、特性に
熱変化を招来させたりすることがなくなる。The lower surface of the insulating substrate 1 to which the semiconductor element 3 and the external lead terminals 2 are attached is JIS-B-0.
The center line average roughness (Ra) specified in 601 is 0.5 μm ≦
The roughness is Ra ≦ 2.0 μm, whereby the insulating substrate 1 having the semiconductor element 3 and the external lead terminals 2 mounted and attached on the upper surface is set in a predetermined jig, and epoxy or the like is placed in the jig. When the semiconductor element 3 and the like are covered with the molding resin 6 by dripping and injecting the liquid resin, the flowability of the liquid resin on the lower surface of the insulating substrate 1 becomes substantially equal to the flowability on the upper surface side, so that air flows into the molding resin 6. The hugging is effectively prevented, and as a result, the semiconductor element 3 is completely hermetically sealed with the molding resin 6, and the semiconductor element 3 is kept normal for a long period of time.
In addition, the semiconductor element 3 can be stably operated, and the heat generated during the operation of the semiconductor element 3 is satisfactorily dissipated to the outside through the insulating substrate 1 and the molding resin 6, so that the semiconductor element 3 is always kept at a low temperature and thermally destroyed by the semiconductor element 3. It does not occur that the heat generation occurs or the characteristics change due to heat.
【0025】尚、前記絶縁基体1下面の粗さは中心線平
均粗さ(Ra)が0.5μm≧Ra、或いはRa≧2.
0μmとなると絶縁基体1がセットされた治具内にエポ
キシ等の液状樹脂を滴下注入した際、液状樹脂の絶縁基
体1下面における流れ性が上面側の流れ性に対し異なっ
たものとなってモールド樹脂6内に空気を抱き込んでし
まう。従って、前記絶縁基体1下面の粗さは中心線平均
粗さ(Ra)で0.5μm≦Ra≦2.0μmの範囲に
特定される。The roughness of the lower surface of the insulating substrate 1 has a center line average roughness (Ra) of 0.5 μm ≧ Ra, or Ra ≧ 2.
When it becomes 0 μm, when liquid resin such as epoxy is dropped and injected into the jig in which the insulating base 1 is set, the flowability of the liquid resin on the lower surface of the insulating base 1 becomes different from that on the upper surface side, and the mold is formed. The air is caught in the resin 6. Therefore, the roughness of the lower surface of the insulating substrate 1 is specified in the range of 0.5 μm ≦ Ra ≦ 2.0 μm in terms of center line average roughness (Ra).
【0026】また図2は本発明の他の実施例を示し、半
導体装置は、上面中央部に半導体素子10が搭載される搭
載部11a を有する金属基体11と、前記金属基体11の上面
外周部に取着され、内周部から外周部にかけて扇状に導
出する複数個の配線層12を有する絶縁枠体13と、前記金
属基体11の半導体素子搭載部11a に搭載され、電極が前
記配線層12の一端に接続されている半導体素子10と、前
記配線層12の他端に取着され、半導体素子10を外部電気
回路に接続する複数個の外部リード端子14と、前記金属
基体11、絶縁枠体13、半導体素子10及び外部リード端子
14の一部を被覆するモールド樹脂15とで形成されてい
る。FIG. 2 shows another embodiment of the present invention. In a semiconductor device, a metal base 11 having a mounting portion 11a on which a semiconductor element 10 is mounted in the center of the top surface, and an outer peripheral portion of the top surface of the metal base 11. Is mounted on the semiconductor element mounting portion 11a of the metal base 11 and the insulating frame 13 having a plurality of wiring layers 12 which are attached to the outer peripheral portion in a fan shape from the inner peripheral portion to the outer peripheral portion, and the electrodes are mounted on the wiring layer 12 A semiconductor element 10 connected to one end of the wiring layer 12, a plurality of external lead terminals 14 attached to the other end of the wiring layer 12 for connecting the semiconductor element 10 to an external electric circuit, the metal base 11, an insulating frame. Body 13, semiconductor element 10 and external lead terminals
It is formed of a mold resin 15 which covers a part of 14.
【0027】かかる半導体装置は絶縁枠体13に設けた配
線層12が内周部から外周部にかけて扇状に広がってお
り、絶縁枠体13の外周部における線幅及び隣接する配線
層12間の間隔が広いものとなっていることから配線層12
に取着される外部リード端子14もその線幅及び隣接間隔
を広いものとなすことができ、その結果、外部リード端
子14に外力が印加されたとしても該外部リード端子14に
大きな変形を発生させることはなく、隣接する外部リー
ド端子14間の電気的絶縁を維持しつつ外部リード端子14
を所定の外部電気回路に正確、且つ確実に電気的接続す
ることが可能となる。In such a semiconductor device, the wiring layer 12 provided on the insulating frame body 13 spreads in a fan shape from the inner peripheral portion to the outer peripheral portion, and the line width in the outer peripheral portion of the insulating frame body 13 and the space between the adjacent wiring layers 12 are arranged. The wiring layer 12
The external lead terminal 14 attached to the external lead terminal 14 can also have a wide line width and a large adjacent spacing, and as a result, even if an external force is applied to the external lead terminal 14, the external lead terminal 14 is largely deformed. External lead terminals 14 while maintaining electrical insulation between adjacent external lead terminals 14.
Can be accurately and reliably electrically connected to a predetermined external electric circuit.
【0028】更にかかる半導体装置は金属基体11下面の
表面粗さがJISーBー0601に規定の中心線平均粗
さ(Ra)で0.5μm≦Ra≦2.0μmとなってお
り、これによって上面に半導体素子10や絶縁枠体13及び
外部リード端子14が配された金属基体11を所定の治具内
にセットし、該治具内にエポキシ等の液状樹脂を滴下注
入して半導体素子10等をモールド樹脂15で被覆する際、
金属基体11下面における液状樹脂の流れ性が上面側の流
れ性に対し略等しくなってモールド樹脂15内に空気が抱
き込まれるのが有効に阻止され、その結果、半導体素子
10はモールド樹脂15で完全に気密封止され、半導体素子
10を長期間にわたり正常、且つ安定に作動させることが
可能となるとともに半導体素子10の作動時に発する熱を
金属基体11やモールド樹脂15を介して外部に良好に放散
させ、半導体素子10を常に低温として半導体素子10に熱
破壊が発生したり、特性に熱変化を招来させたりするこ
とがなくなる。Further, in such a semiconductor device, the surface roughness of the lower surface of the metal substrate 11 is 0.5 μm ≦ Ra ≦ 2.0 μm in terms of center line average roughness (Ra) specified in JIS-B-0601. A metal substrate 11 having the semiconductor element 10, the insulating frame 13 and the external lead terminals 14 arranged on the upper surface is set in a predetermined jig, and a liquid resin such as epoxy is dropped and injected into the jig to form the semiconductor element 10 When coating etc. with mold resin 15,
The flowability of the liquid resin on the lower surface of the metal substrate 11 is substantially equal to the flowability on the upper surface side, and the air is effectively prevented from being trapped in the mold resin 15. As a result, the semiconductor element
10 is completely hermetically sealed with mold resin 15
It becomes possible to operate the semiconductor device 10 normally and stably for a long period of time, and the heat generated during the operation of the semiconductor device 10 is satisfactorily dissipated to the outside through the metal base 11 and the molding resin 15, so that the semiconductor device 10 is always kept at a low temperature. As a result, the semiconductor element 10 will not be thermally destroyed and the characteristics will not be thermally changed.
【0029】かくして本発明の半導体装置は外部リード
端子を外部電気回路に接続させ、内部の半導体素子を外
部電気回路に電気的に接続することによってコンピュー
ター等の情報処理装置に搭載されることとなる。Thus, the semiconductor device of the present invention is mounted on an information processing device such as a computer by connecting external lead terminals to an external electric circuit and electrically connecting internal semiconductor elements to the external electric circuit. .
【0030】[0030]
【発明の効果】本発明の半導体装置によれば、上面に半
導体素子等が配されている絶縁基体や金属基体の下面を
JISーBー0601に規定の中心線平均粗さ(Ra)
で0.5μm≦Ra≦2.0μmの粗面としたことから
上面に半導体素子及び外部リード端子が搭載取着された
絶縁基体、或いは上面に半導体素子、絶縁枠体及び外部
リード端子が配された金属基体を所定の治具内にセット
し、該治具内にエポキシ等の液状樹脂を滴下注入して半
導体素子等をモールド樹脂で被覆する際、絶縁基体下面
や金属基体下面における液状樹脂の流れ性が上面側の流
れ性に対し略等しくなってモールド樹脂内への空気の抱
き込みが有効に阻止され、その結果、半導体素子をモー
ルド樹脂で完全に気密封止し、半導体素子を長期間にわ
たり正常、且つ安定に作動させることが可能となるとと
もに半導体素子の作動時に発する熱を外部に良好に放散
させ、半導体素子に熱破壊が生じたり、特性に熱変化が
招来するのを有効に防止することができる。According to the semiconductor device of the present invention, the center line average roughness (Ra) specified in JIS-B-0601 is used for the lower surface of the insulating base or the metal base on which the semiconductor element or the like is arranged.
Since it is a rough surface of 0.5 μm ≦ Ra ≦ 2.0 μm, the semiconductor element and the external lead terminal are mounted and attached on the upper surface, or the semiconductor element, the insulating frame and the external lead terminal are arranged on the upper surface. When the metal base is set in a predetermined jig and liquid resin such as epoxy is dropped into the jig to cover the semiconductor element and the like with the mold resin, the liquid resin on the lower surface of the insulating base or the lower surface of the metal base is The flowability is almost equal to the flowability on the upper surface side, effectively preventing the inclusion of air in the molding resin, and as a result, the semiconductor element is completely hermetically sealed with the molding resin and the semiconductor element is kept for a long time. It is possible to operate normally and stably over a long period of time, and to dissipate the heat generated during the operation of the semiconductor element to the outside satisfactorily, which effectively causes the semiconductor element to be thermally destroyed and the characteristics to be thermally changed. Can be prevented.
【図1】本発明の半導体装置の一実施例を示す断面図で
ある。FIG. 1 is a sectional view showing an embodiment of a semiconductor device of the present invention.
【図2】本発明の他の実施例を示す断面図である。FIG. 2 is a sectional view showing another embodiment of the present invention.
1・・・・・・絶縁基体 1a・・・・・半導体素子搭載部 2・・・・・・外部リード端子 3・・・・・・半導体素子 4・・・・・・配線層 6・・・・・・モールド樹脂 1-Insulating substrate 1a-Semiconductor element mounting part 2--External lead terminal 3--Semiconductor element 4--Wiring layer 6- .... Mold resin
Claims (2)
部及び該搭載部周辺から外周部にかけて扇状に導出する
複数個の配線層を有する絶縁基体と、前記絶縁基体の半
導体素子搭載部に搭載され、電極が前記配線層の一端に
接続されている半導体素子と、前記配線層の他端に取着
され、半導体素子を外部電気回路に接続する複数個の外
部リード端子と、前記絶縁基体、半導体素子及び外部リ
ード端子の一部を被覆するモールド樹脂とから成る半導
体装置であって、前記絶縁基体下面の表面粗さがJIS
ーBー0601に規定の中心線平均粗さ(Ra)で0.
5μm≦Ra≦2.0μmであることを特徴とする半導
体装置。1. An insulating base having a mounting portion on which a semiconductor element is mounted at a central portion of an upper surface and a plurality of wiring layers extending in a fan shape from a periphery of the mounting portion to an outer peripheral portion, and a semiconductor element mounting portion of the insulating base. A semiconductor element mounted and having electrodes connected to one end of the wiring layer; a plurality of external lead terminals attached to the other end of the wiring layer for connecting the semiconductor element to an external electric circuit; A semiconductor device comprising a semiconductor element and a mold resin covering a part of an external lead terminal, wherein the surface roughness of the lower surface of the insulating substrate is JIS.
-B-0601 has a center line average roughness (Ra) of 0.
A semiconductor device characterized in that 5 μm ≦ Ra ≦ 2.0 μm.
部を有する金属基体と、前記金属基体の上面外周部に取
着され、内周部から外周部にかけて扇状に導出する複数
個の配線層を有する絶縁枠体と、前記金属基体の半導体
素子搭載部に搭載され、電極が前記配線層の一端に接続
されている半導体素子と、前記配線層の他端に取着さ
れ、半導体素子を外部電気回路に接続する複数個の外部
リード端子と、前記金属基体、絶縁枠体、半導体素子及
び外部リード端子の一部を被覆するモールド樹脂とから
成る半導体装置であって、前記金属基体下面の表面粗さ
がJISーBー0601に規定の中心線平均粗さ(R
a)で0.5μm≦Ra≦2.0μmであることを特徴
とする半導体装置。2. A metal base having a mounting portion on which a semiconductor element is mounted at the center of the top surface, and a plurality of wirings attached to the outer periphery of the top surface of the metal base and led out in a fan shape from the inner periphery to the outer periphery. An insulating frame having a layer, a semiconductor element mounted on a semiconductor element mounting portion of the metal base and having electrodes connected to one end of the wiring layer, and a semiconductor element attached to the other end of the wiring layer to form a semiconductor element. What is claimed is: 1. A semiconductor device comprising: a plurality of external lead terminals connected to an external electric circuit; and a metal base, an insulating frame, a semiconductor element, and a mold resin that covers a part of the external lead terminals. The surface roughness is the center line average roughness specified by JIS-B-0601 (R
The semiconductor device according to a), wherein 0.5 μm ≦ Ra ≦ 2.0 μm.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2165595A JP3350269B2 (en) | 1995-02-09 | 1995-02-09 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2165595A JP3350269B2 (en) | 1995-02-09 | 1995-02-09 | Semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH08222661A true JPH08222661A (en) | 1996-08-30 |
JP3350269B2 JP3350269B2 (en) | 2002-11-25 |
Family
ID=12061072
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2165595A Expired - Fee Related JP3350269B2 (en) | 1995-02-09 | 1995-02-09 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP3350269B2 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6541306B2 (en) * | 1997-09-10 | 2003-04-01 | Oki Electric Industry Co., Ltd. | Resin-sealed semiconductor device and method of manufacturing the device |
WO2019159798A1 (en) * | 2018-02-19 | 2019-08-22 | 富士電機株式会社 | Semiconductor module and method for manufacturing same |
-
1995
- 1995-02-09 JP JP2165595A patent/JP3350269B2/en not_active Expired - Fee Related
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6541306B2 (en) * | 1997-09-10 | 2003-04-01 | Oki Electric Industry Co., Ltd. | Resin-sealed semiconductor device and method of manufacturing the device |
WO2019159798A1 (en) * | 2018-02-19 | 2019-08-22 | 富士電機株式会社 | Semiconductor module and method for manufacturing same |
JP2019145612A (en) * | 2018-02-19 | 2019-08-29 | 富士電機株式会社 | Semiconductor module and manufacturing method thereof |
US11749581B2 (en) | 2018-02-19 | 2023-09-05 | Fuji Electric Co., Ltd. | Semiconductor module and method for manufacturing same |
Also Published As
Publication number | Publication date |
---|---|
JP3350269B2 (en) | 2002-11-25 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP4452235B2 (en) | Package structure and manufacturing method thereof | |
US5760466A (en) | Semiconductor device having improved heat resistance | |
US20200402873A1 (en) | Electronic device mounting board, electronic package, and electronic module | |
JPH08222661A (en) | Semiconductor | |
JPH06132425A (en) | Semiconductor device | |
JP3279849B2 (en) | Semiconductor device | |
JP3181008B2 (en) | Semiconductor device | |
JP3215006B2 (en) | Semiconductor device | |
JP3279844B2 (en) | Semiconductor device and manufacturing method thereof | |
JP3441194B2 (en) | Semiconductor device and manufacturing method thereof | |
JPH11176995A (en) | Semiconductor device | |
JP3359521B2 (en) | Method for manufacturing semiconductor device | |
JPH06188334A (en) | Semiconductor device | |
JPH08115993A (en) | Semiconductor device | |
JP3281778B2 (en) | Semiconductor device | |
JP4416269B2 (en) | Electronic equipment | |
EP1365450A1 (en) | An improved wire-bonded chip on board package | |
US20030205793A1 (en) | Wire-bonded chip on board package | |
JP3752447B2 (en) | Package for storing semiconductor elements | |
JP2006041287A (en) | Package for containing electronic component and electronic device | |
JPH09162324A (en) | Semiconductor element housing package | |
JPH06188324A (en) | Semiconductor device | |
JPH08148630A (en) | Manufacture of semiconductor device | |
JPH06283641A (en) | Lead frame and its manufacture | |
JP2001358256A (en) | Substrate for mounting electronic component and electronic component device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20070913 Year of fee payment: 5 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20080913 Year of fee payment: 6 |
|
LAPS | Cancellation because of no payment of annual fees |