CN2463958Y - Integrated circuit - Google Patents
Integrated circuit Download PDFInfo
- Publication number
- CN2463958Y CN2463958Y CN 01200542 CN01200542U CN2463958Y CN 2463958 Y CN2463958 Y CN 2463958Y CN 01200542 CN01200542 CN 01200542 CN 01200542 U CN01200542 U CN 01200542U CN 2463958 Y CN2463958 Y CN 2463958Y
- Authority
- CN
- China
- Prior art keywords
- integrated circuit
- substrate
- signal input
- weld pads
- metal wires
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
Landscapes
- Wire Bonding (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The utility model relates to an integrated circuit which comprises a basal plate, an integrated circuit, a plurality of metal wires, and two sealing glue layers, wherein the basal plate has an upper surface and a lower surface provided with a signal input terminal and a signal output terminal. The integrated circuit is provided with a lower surface of which both ends are provided with a plurality of welding pads. When the lower surface of the integrated circuit is fixed on the basal plate, the welding pads are exposed out of the basal plate. The metal wires are connected with the welding pads of the integrated circuit and the signal input terminal of the lower surface of the basal plate in the way of throwing. The sealing glue layers are filled at both ends of the basal plate and the integrated circuit, and seal the metal wires. The size of the integrated circuit is equal to that of a chip, and the requirements of lightness, thinness, shortness and smallness are satisfied. The integrated circuit has the advantages of convenient manufacture and production cost reduction.
Description
The utility model relates to a kind of integrated circuit, refer to especially a kind of have the chip size size, can make that product has gently, approaches, short and small advantage, meet the integrated circuit of product demand now.
As shown in Figure 1, existing integrated circuits comprises a substrate 10, and it has a upper surface 12 and a lower surface 14, and upper surface 12 has a signal input part 16, and lower surface has a signal output part 18, and it is connected with a printed circuit board (PCB) 19; One integrated circuit 20 is arranged on the upper surface 12 of substrate 10, and has several weld pads 22 on it, and it is connected to the signal input part 16 of substrate 10 by several metal wires 24; One adhesive layer 26 is sealed in integrated circuit 20 and substrate 10 tops, and several metal wires 24 are covered, and is used for protecting integrated circuit 20 and several metal wires 24.
Above-mentioned encapsulation, the area of substrate 10 must be greater than the area of integrated circuit 20, so that metal wire 24 routings be not integrated on the surface that circuit 20 covers at substrate 10, so, the volume of the integrated circuit finished of encapsulation is bigger, can't reach that product is light, book, short and small requirement.
For the encapsulation volume that makes chip reaches measure-alike requirement with chip, to reach compact purpose, chip is directly overlayed on the substrate, directly be connected on the substrate, do not need just to finish electrical connection by extra metal routing operation by the metallic contact on the chip pad, therefore, substrate can be made into measure-alike with chip, and reaches the requirement identical with the size of chip, yet, this kind method for packing cost is quite high, and is not suitable for the encapsulation of all chips.
Main purpose of the present utility model is to provide a kind of integrated circuit, and its size with chip is identical, satisfies light, thin, short and small demand.
Another purpose of the present utility model is to provide a kind of integrated circuit, and it is convenient to make, and reduces production costs.
The purpose of this utility model realizes by the following technical solutions:
A kind of integrated circuit, it comprises:
One substrate, it has a upper surface and a lower surface, and this lower surface is provided with a signal input part and and is electrically connected on this signal input part, is used to be connected to the signal output part on the printed circuit board (PCB);
One integrated circuit, it is provided with one in order to be fixed to the lower surface of this upper surface of base plate, and these lower surface two ends have a plurality of weld pads, and when the lower surface of this integrated circuit was fixed on this substrate, these a plurality of weld pads were exposed by this substrate;
A plurality of metal wires, it is electrically connected to a plurality of weld pads of this integrated circuit and the signal input part of base lower surface in the routing mode;
Two be filled in this substrate and integrated circuit both sides respectively, in order to adhesive layer with these a plurality of metal wires sealings.
The area of described substrate is less than the area of this integrated circuit, and when this integrated circuit was fixed to the upper surface of this substrate, a plurality of weld pads on this integrated circuit exposed outside this substrate.
Described substrate both sides have a hollow slots respectively with respect to the position that integrated circuit is provided with a plurality of weld pads, when this integrated circuit is fixed on this substrate, expose in the hollow slots of a plurality of weld pads in its both sides by this substrate.
The lower surface of described integrated circuit and the upper surface of this substrate cohere mutually.
The signal output part of described substrate is the ball grid array Metal Ball.
The signal input part of described substrate is positioned at the both sides of this substrate.
The utility model can reduce the material usage of substrate, has reduced production cost; Make the integrated circuit package dimension identical with the chip size size, reach light, thin, to weak point, little demand; With the identical method for packing of chip size size, its manufacture process is easy, has reduced production cost.
The utility model is described in further detail below in conjunction with drawings and Examples:
Fig. 1 is the cutaway view of existing integrated circuits.
Fig. 2 is the cutaway view of the utility model one embodiment.
Fig. 3 is the cutaway view of another embodiment of the utility model.
As shown in Figure 2, the utility model includes:
One substrate 28, it has a upper surface 30 and a lower surface 32, the signal output part 36 that lower surface 32 both sides are provided with signal input part 34 and are connected with signal input part 34, signal output part 36 is the ball grid array Metal Ball, be used for being connected, the signal of substrate 28 is delivered to printed circuit board (PCB) 38 with printed circuit board (PCB) 38.
One integrated circuit 40, it is provided with a lower surface 42 that is used for fixing at substrate 28 upper surfaces 30, and there are several weld pads 44 lower surface 42 both sides, make that several weld pads 44 expose outside substrate 28 when the lower surface 42 of integrated circuit 40 is fixed on the upper surface 30 of substrate 28; Integrated circuit 40 is bigger than substrate 28 in the present embodiment, and therefore, weld pad on the integrated circuit 40 44 is unlikely to be covered by substrate 28, can be exposed by substrate 28.
Two adhesive layers 48 are filled in the both sides of substrate 28 and integrated circuit 40 respectively, and with several metal 46 linear sealings, it is used for protecting a plurality of metal wires 46.
So, the integrated circuit 40 that both sides can be provided with weld pad 44 is encapsulated in one than on the little substrate 28 of integrated circuit size, make the measure-alike of size after integrated circuit 40 encapsulation and integrated circuit 40, reach the encapsulation requirement identical with chip size, have compact characteristics, and its fabrication schedule is quite simple, can reduce the production cost of encapsulation.
Be illustrated in figure 3 as another embodiment of the present utility model, substrate 28 has a upper surface 30 and a lower surface 32, the signal output part 36 that lower surface 32 both sides are provided with signal input part 34 and are electrically connected with signal input part 34, signal output part 36 is the ball grid array Metal Ball, be used to be connected to printed circuit board (PCB) 38, the signal of substrate 28 is passed to printed circuit board (PCB) 38.
These substrate 28 both sides are provided with the hollow slots 50 that runs through substrate 28; when the lower surface 42 of integrated circuit 40 sticks together upper surface 30 at substrate 28; the weld pad 44 of integrated circuit 40 both sides is exposed by the hollow slots 50 of substrate 28; make a plurality of metal wires 46 pass the signal input part 34 of weld pad 44 that hollow slots 50 is connected to integrated circuit 40 and substrate 28; adhesive layer 48 tunnel is filled in the hollow slots 50, is used to protect a plurality of metal wires 46.
Claims (6)
1, a kind of integrated circuit is characterized in that, it comprises:
One substrate, it has a upper surface and a lower surface, and this lower surface is provided with a signal input part and and is electrically connected on this signal input part, is used to be connected to the signal output part on the printed circuit board (PCB);
One integrated circuit, it is provided with one in order to be fixed to the lower surface of this upper surface of base plate, and these lower surface two ends have a plurality of weld pads, and when the lower surface of this integrated circuit was fixed on this substrate, these a plurality of weld pads were exposed by this substrate;
A plurality of metal wires, it is electrically connected to a plurality of weld pads of this integrated circuit and the signal input part of base lower surface in the routing mode;
Two be filled in this substrate and integrated circuit both sides respectively, in order to adhesive layer with these a plurality of metal wires sealings.
2, a kind of integrated circuit as claimed in claim 1 is characterized in that: described this substrate area is less than the area of this integrated circuit, and when this integrated circuit was fixed to the upper surface of this substrate, a plurality of weld pads on this integrated circuit exposed outside this substrate.
3, a kind of integrated circuit as claimed in claim 1, it is characterized in that: described these substrate both sides have a hollow slots respectively with respect to the position that integrated circuit is provided with a plurality of weld pads, when this integrated circuit is fixed on this substrate, expose in the hollow slots of a plurality of weld pads in its both sides by this substrate.
4, a kind of integrated circuit as claimed in claim 1 is characterized in that: the lower surface of described this integrated circuit and the upper surface of this substrate cohere mutually.
5, a kind of integrated circuit as claimed in claim 1 is characterized in that: the signal output part of described this substrate is the ball grid array Metal Ball.
6, a kind of integrated circuit as claimed in claim 1 is characterized in that: the signal input part of described this substrate is positioned at the both sides of this substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 01200542 CN2463958Y (en) | 2001-02-01 | 2001-02-01 | Integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 01200542 CN2463958Y (en) | 2001-02-01 | 2001-02-01 | Integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN2463958Y true CN2463958Y (en) | 2001-12-05 |
Family
ID=33622806
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 01200542 Expired - Lifetime CN2463958Y (en) | 2001-02-01 | 2001-02-01 | Integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN2463958Y (en) |
-
2001
- 2001-02-01 CN CN 01200542 patent/CN2463958Y/en not_active Expired - Lifetime
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CX01 | Expiry of patent term |
Expiration termination date: 20110201 Granted publication date: 20011205 |