CN1157781C - IC package structure and its manufacture - Google Patents
IC package structure and its manufacture Download PDFInfo
- Publication number
- CN1157781C CN1157781C CNB001362321A CN00136232A CN1157781C CN 1157781 C CN1157781 C CN 1157781C CN B001362321 A CNB001362321 A CN B001362321A CN 00136232 A CN00136232 A CN 00136232A CN 1157781 C CN1157781 C CN 1157781C
- Authority
- CN
- China
- Prior art keywords
- integrated circuit
- substrate
- package structure
- groove
- adhesive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/10155—Shape being other than a cuboid
- H01L2924/10158—Shape being other than a cuboid at the passive surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Dicing (AREA)
Abstract
The present invention discloses an integrated circuit package structure and a manufacture method thereof. The integrated circuit package structure comprises a substrate, an integrated circuit, an adhesive layer and a plurality of conducting wires, wherein the integrated circuit comprises a lower surface and an upper surface, a groove is respectively arranged on both sides of the lower surface, and a plurality of solder pads are arranged on the upper surface; the adhesive layer is used for gluing the lower surface of the integrated circuit on the substrate, and the conducting wires are connected between the solder pads of the integrated circuit and the substrate. When the integrated circuit is glued on the substrate by the adhesive layer, the overflow glue of the adhesive layer is filled in the grooves of the integrated circuit, so the signal input end of the substrate can not be covered. Thereby, the glue overflow problem of the integrated circuit package can be effectively avoided.
Description
Technical field
The present invention relates to a kind of integrated circuit package structure and manufacture method thereof, refer in particular to a kind of excessive glue problem that can effectively solve generation when adhering to integrated circuit on the substrate, make integrated circuit can reach the integrated circuit package structure and the manufacture method thereof of the packaging effect of identical with wafer size (Chip Scale Package).
Background technology
At sciemtifec and technical sphere, every sci-tech product all needs gently, approaches, short and small, and the volume of integrated circuit is unreasonablely to think more for a short time; Make it meet the demand of product.Therefore, the encapsulation technology of a kind of identical with wafer size (Chip ScalePackage) can make the integrated circuit volume after being encapsulated dwindle, and reach compact demand.
As shown in Figure 1, encapsulation technology for existing integrated circuits, when integrated circuit 10 adheres on the substrate 12, because adhesive-layer 14 may be controlled bad, often cause viscose glue to overflow the bonding plane of integrated circuit 10, and overflow to substrate 12, the excessive glue 16 that overflows may cover the signal input part 18 of substrate 12, and has influence on the routing operation of lead 20.Therefore, generally the signal input part 18 for fear of substrate 12 is covered by excessive glue 16, usually substrate 12 is enlarged, make signal input part 18 on it away from integrated circuit 10, so, the glue 16 that overflows will be unlikely the signal input part 18 that covers substrate 12, and solve the situation of above-mentioned excessive glue.
So, the encapsulation volume of whole integrated circuit will become big along with the expansion of substrate 12, can't reach the encapsulation of so-called identical with wafer size (Chip Scale Package); And can't reach light, thin, short and small demand.
Summary of the invention
Main purpose of the present invention is to provide integrated circuit package structure and manufacture method thereof, and it can effectively solve the problem of the glue that overflows.
Another object of the present invention is to provide integrated circuit package structure and manufacture method thereof, it has the effect that reduces package dimension, to reach light, thin, short and small demand.
The objective of the invention is to be achieved through the following technical solutions:
A, a kind of integrated circuit package structure, it comprises:
One has the substrate of a first surface and a second surface, and this first surface is provided with signal input part; Second surface is provided with the signal output part that is connected to circuit board;
One includes the integrated circuit of an a lower surface and a upper surface, and respectively there is a groove these lower surface both sides, and upper surface is provided with several weld pads;
One adhesive-layer that is used for the lower surface of integrated circuit is adhered to the first surface of substrate;
The lead of the weld pad of several connection integrated circuits and the signal input part of substrate;
One adhesive layer that several wires and integrated circuit are enveloped.
The signal output part of the second surface of described substrate has ball grid array Metal Ball (Ball GridArray); When integrated circuit adhered to substrate, the formed excessive glue of adhesive-layer was to be filled in the groove of integrated circuit lower surface; The groove of the lower surface of integrated circuit is a vertical configuration; The groove of the lower surface of integrated circuit is an inclined plane shape; The groove of the lower surface of integrated circuit forms with the cutter cutting.
The manufacture method of b, a kind of integrated circuit, it comprises the following steps:
One, provides a substrate;
Two, provide a wafer with several integrated circuits, each adjacent integrated circuit has line of cut, the line of cut cutting proper depth of cutter on wafer with a broad, make each integrated circuit both sides form groove, cut at the line of cut of wafer with the less cutter of a width again, to finish the cutting of integrated circuit;
Three, provide an adhesive-layer that integrated circuit is adhered on the substrate;
Four, connect integrated circuit and substrate with several wires;
Five, provide an adhesive layer to coat several wires and integrated circuit.
Described substrate has ball grid array Metal Ball (Ball Grid Array); When integrated circuit adhered to substrate, the formed excessive glue of adhesive-layer was to be filled in the groove of lower surface of integrated circuit; The groove of integrated circuit is a vertical configuration.
Because when adhesive-layer adheres to integrated circuit on the substrate, the excessive glue of adhesive-layer will be filled in the groove of integrated circuit, and can not cover the signal input part of substrate, therefore, can effectively prevent the excessive glue situation of integrated circuit encapsulation.Simultaneously, do not need to add large substrates, thus the effect that reduces package dimension had, to reach light, thin, short and small demand.
Description of drawings
The present invention is further detailed explanation below in conjunction with accompanying drawing.
Fig. 1 is the cross-sectional schematic of existing integrated circuit encapsulation.
Fig. 2 is the cross-sectional schematic of integrated circuit of the present invention.
Fig. 3 is an embodiment schematic diagram of integrated circuit of the present invention.
Fig. 4 is the top view of wafer.
Fig. 5 is the cutting schematic diagram of integrated circuit of the present invention.
Embodiment
As shown in Figure 2, integrated circuit of the present invention includes a substrate 24, and it has a first surface 26 and a second surface 28, and first surface 26 has a signal input part 30, is delivered to substrate 24 in order to the signal with integrated circuit 32.The second surface 28 of substrate 24 has a signal output part 34, is used for the signal of integrated circuit 32 is delivered on the circuit board, and signal output part 34 can be the Metal Ball (Ball Grid Array) of spherical grid array type.
One end of several wires 42 is connected on the weld pad 39 of integrated circuit 32, the other end is connected on the signal input part 30 of substrate 24, the signal of integrated circuit 32 is delivered on the substrate 24, several wires 42 can be connected on the weld pad 39 of integrated circuit 32 with wedge shape routing (Wedge Bond), this several wires 42 is positioned at the edge of the upper surface 38 of integrated circuit 32, in addition, the also available ball routing of this several wires 42 (ball bond) mode is connected on the weld pad 39 of integrated circuit 32.
Adhesive-layer 44 is to be coated between integrated circuit 32 and the substrate 24, be used for making integrated circuit 32 to adhere on the substrate 24, because the control of the glue amount of general adhesive-layer 44 is difficult for, make the glue of adhesive-layer 44 that the problem of the lower surface 36 that overflows integrated circuit 32 often be arranged, in the present invention, the excessive glue 46 that adhesive-layer 44 is overflowed will be filled in the groove 40 of integrated circuit 32, and not have the problem of the signal input part 30 of covered substrate 24.
As shown in Figure 3, the groove 40 of integrated circuit 32 can be inclined plane shape, and when excessive glue amount may be controlled to more after a little while, excessive glue can be filled in the groove 40 completely, and can not make groove 40 have bigger gap to exist.
As shown in Figure 4, have several integrated circuits 32 on the wafer 48,32 of each integrated circuits have a line of cut 50, therefore, and when making the groove 40 of integrated circuit 32, as shown in Figure 5, at first cut a groove 40 that does not run through wafer 48 from line of cut 50, cut from line of cut 50 with a narrower cutting tool again and wear whole wafer with the cutting tool of a broad, like this, each integrated circuit 32 on the wafer 48 can be separated, and make each integrated circuit 32 be formed with groove 40.
The groove 40 of integrated circuit 32 of the present invention is easy to make, makes the unlikely significantly raising of manufacturing cost of integrated circuit 32; The integrated circuit 32 of apparatus fluted 40 encapsulates, and the problem that does not have the glue that overflows produces, the manufacturing that can be convenient to encapsulate, and can reduce production costs, improve the production acceptance rate; Owing to solved the problem of excessive glue; Substrate 24 can be made into identical with wafer size, and reaches the encapsulation (Chip.Scale Package) with the identical size of wafer size, makes product satisfy light, thin, short and small demand.
Claims (10)
1, integrated circuit package structure, it comprises:
One has the substrate of a first surface and a second surface, and this first surface is provided with signal input part, and second surface is provided with the signal output part that is connected to circuit board;
One includes the integrated circuit of an a lower surface and a upper surface, and upper surface is provided with several weld pads;
One adhesive-layer that is used for the lower surface of integrated circuit is adhered to the first surface on the substrate;
Several are connected the lead between the signal input part of the weld pad of integrated circuit and substrate;
One adhesive layer that several wires and integrated circuit are enveloped is characterized in that:
Respectively there is a groove both sides of described integrated circuit lower surface.
2, integrated circuit package structure as claimed in claim 1 is characterized in that: the signal output part of the second surface of described substrate has the ball grid array Metal Ball.
3, integrated circuit package structure as claimed in claim 1 is characterized in that: when described integrated circuit adhered on the substrate, the formed excessive glue of adhesive-layer was to be filled in the groove of integrated circuit lower surface.
4, integrated circuit package structure as claimed in claim 1 is characterized in that: the groove of the lower surface of described integrated circuit is a vertical configuration.
5, integrated circuit package structure as claimed in claim 1 is characterized in that: the groove of the lower surface of described integrated circuit is an inclined plane shape.
6, integrated circuit package structure as claimed in claim 1 is characterized in that: the groove of the lower surface of described integrated circuit forms with the cutter cutting.
7, the manufacture method of integrated circuit package structure, it comprises the following steps:
A, provide a substrate;
B, provide a wafer with several integrated circuits, each adjacent integrated circuit has line of cut, the line of cut cutting proper depth of cutter on wafer with a broad, make each integrated circuit both sides form groove, cut at the line of cut of wafer with the less cutter of a width again; The circuit both sides form groove, cut at the line of cut of wafer with the less cutter of a width again;
C, provide an adhesive-layer that integrated circuit is adhered on the substrate;
D, connect integrated circuit and substrate with several wires;
E, provide an adhesive layer to coat several wires and integrated circuit.
8, the manufacture method of integrated circuit package structure as claimed in claim 7 is characterized in that: described substrate has the ball grid array Metal Ball.
9, the manufacture method of integrated circuit package structure as claimed in claim 7 is characterized in that: when described integrated circuit adhered on the substrate, the formed excessive glue of adhesive-layer was to be filled in the groove of integrated circuit lower surface.
10, the manufacture method of integrated circuit package structure as claimed in claim 7 is characterized in that: the groove of described integrated circuit is a vertical configuration.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB001362321A CN1157781C (en) | 2000-12-14 | 2000-12-14 | IC package structure and its manufacture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB001362321A CN1157781C (en) | 2000-12-14 | 2000-12-14 | IC package structure and its manufacture |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1357916A CN1357916A (en) | 2002-07-10 |
| CN1157781C true CN1157781C (en) | 2004-07-14 |
Family
ID=4597154
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB001362321A Expired - Fee Related CN1157781C (en) | 2000-12-14 | 2000-12-14 | IC package structure and its manufacture |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1157781C (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100444361C (en) * | 2005-09-30 | 2008-12-17 | 日月光半导体制造股份有限公司 | Chip packing structure |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5075469B2 (en) * | 2007-05-08 | 2012-11-21 | 株式会社オーディオテクニカ | Gooseneck microphone |
| CN102543910A (en) * | 2012-02-06 | 2012-07-04 | 三星半导体(中国)研究开发有限公司 | Chip packaging component and manufacturing method thereof |
-
2000
- 2000-12-14 CN CNB001362321A patent/CN1157781C/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100444361C (en) * | 2005-09-30 | 2008-12-17 | 日月光半导体制造股份有限公司 | Chip packing structure |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1357916A (en) | 2002-07-10 |
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| C14 | Grant of patent or utility model | ||
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| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20040714 Termination date: 20151214 |
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| EXPY | Termination of patent right or utility model |