CN2524375Y - Spherical grid array metal ball integrated circuit package assembly - Google Patents

Spherical grid array metal ball integrated circuit package assembly Download PDF

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Publication number
CN2524375Y
CN2524375Y CN01274949U CN01274949U CN2524375Y CN 2524375 Y CN2524375 Y CN 2524375Y CN 01274949 U CN01274949 U CN 01274949U CN 01274949 U CN01274949 U CN 01274949U CN 2524375 Y CN2524375 Y CN 2524375Y
Authority
CN
China
Prior art keywords
integrated circuit
circuit body
grid array
circuit package
lower floor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
CN01274949U
Other languages
Chinese (zh)
Inventor
丁荣丰
何孟南
杜修文
叶乃华
彭镇滨
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kingpak Technology Inc
Original Assignee
Kingpak Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kingpak Technology Inc filed Critical Kingpak Technology Inc
Priority to CN01274949U priority Critical patent/CN2524375Y/en
Application granted granted Critical
Publication of CN2524375Y publication Critical patent/CN2524375Y/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

The utility model relates to a spherical grid array metal ball integrated circuit package assembly. The utility model is provided aiming at providing an integrated circuit package which protects spherical grid array metal ball, prolongs service life of the integrated circuit package and is convenient to be processed. The utility model comprises a mutually integrated lower layer circuit package body and more than one upper layer circuit package body; the lower layer circuit package body is provided with a plurality of first surfaces electrically connected to first contacts of a printed circuit board and a plurality of second surfaces of second contacts; the upper layer circuit package body is arranged on the second surfaces of the lower layer circuit package body and is electrically connected with the second contacts of the lower layer circuit package body; the lower layer circuit package body and the upper layer circuit package body arranged on the second surface of the lower layer circuit package body are provided with resin encapsulation to cover the plurality of the second contacts.

Description

Ball grid array Metal Ball integrated circuit piled-up packing assembly
Technical field
The utility model belongs to encapsulated integrated circuit, particularly a kind of ball grid array Metal Ball integrated circuit piled-up packing assembly.
Background technology
As shown in Figure 1, known ball grid array Metal Ball integrated circuit piled-up packing assembly system is with lower floor's integrated circuit body 10 and upper strata integrated circuit body 12 mutual stacked combination.
Lower floor's integrated circuit body 10 includes substrate 14, integrated circuit 16, plural wires 18 and a plurality of ball grid array Metal Ball 20.The lower surface 22 of substrate 14 is provided with first contact 24, and its upper surface 26 is provided with second contact 28.Integrated circuit 16 is to be arranged on the upper surface 26 of substrate 14, by plural wires 18 integrated circuit 16 is formed with substrate 14 and is electrically connected, and a plurality of Metal Ball 20 are to be arranged on first contact 24 of substrate 14, in order to be electrically connected with printed circuit board (PCB) 30.
Upper strata integrated circuit body 12 is upper surface 26 tops that are stacked and placed on the substrate 14 of lower floor's integrated circuit body 10, a plurality of Metal Ball 32 on it are to be electrically connected on second contact 28 of upper surface 26 of substrate 14, so, upper and lower laminate circuit body 10,12 forms stacked structures.
Aforesaid known integrated circuit piled-up packing assembly, not only a plurality of Metal Ball 32 of its upper strata integrated circuit body 12 are to be exposed to the external world, and are therefore easily impaired and the useful life of integrated circuit and processing procedure complexity are piled up in influence.
Summary of the invention
The purpose of this utility model provides a kind of useful life of protecting ball grid array Metal Ball, growth to pile up integrated circuit, processing procedure ball grid array Metal Ball integrated circuit piled-up packing assembly easily.
The utility model comprises lower floor's integrated circuit body and the more than one upper strata integrated circuit body that piles up mutually; Lower floor's integrated circuit body is provided with a plurality of second surfaces that are electrically connected to the first surface of printed circuit board (PCB) first contact and are provided with a plurality of second contacts; Upper strata integrated circuit body is stacked and placed on lower floor's integrated circuit body second surface and is electrically connected second contact of lower floor's integrated circuit body; Lower floor's integrated circuit body and be stacked and placed between the upper strata integrated circuit body of lower floor's integrated circuit body second surface and be provided with the adhesive body that is used to cover plural second contact.
Wherein:
First and second contact of lower floor's integrated circuit body forms the ball grid array Metal Ball respectively.
Lower floor's integrated circuit body comprises substrate, is arranged at integrated circuit and plural wires on the substrate; Substrate is provided with hollow slots; Plural wires system is positioned at hollow slots, and its two ends form with integrated circuit and substrate respectively and are electrically connected.
Upper strata integrated circuit body comprises substrate, is arranged at integrated circuit and plural wires on the substrate; Substrate is provided with hollow slots; Plural wires system is positioned at hollow slots, and its two ends form with integrated circuit and substrate respectively and are electrically connected.
The sealing system is filled between lower floor's integrated circuit body and upper strata integrated circuit body in the encapsulating mode.
Because the utility model comprises lower floor's integrated circuit body and the more than one upper strata integrated circuit body that piles up mutually; Lower floor's integrated circuit body is provided with a plurality of second surfaces that are electrically connected to the first surface of printed circuit board (PCB) first contact and are provided with a plurality of second contacts; Upper strata integrated circuit body is stacked and placed on lower floor's integrated circuit body second surface and is electrically connected second contact of lower floor's integrated circuit body; Lower floor's integrated circuit body and be stacked and placed between the upper strata integrated circuit body of lower floor's integrated circuit body second surface and be provided with the adhesive body that is used to cover plural second contact.After a plurality of ball grid array Metal Ball integrated circuit body stacked package, have the effect that can protect the ball grid array Metal Ball, integrated circuit is piled up after, its ball grid array Metal Ball is unlikely impaired; Protect ball grid array Metal Ball and integrated circuit simultaneously in the encapsulating mode, suitable facility on processing procedure.Not only protect the ball grid array Metal Ball, increase the useful life of piling up integrated circuit, and the processing procedure facility, thereby reach the purpose of this utility model.
Description of drawings
Fig. 1, be known ball grid array Metal Ball integrated circuit piled-up packing assembly structural representation cutaway view.
Fig. 2, be the utility model structural representation cutaway view (not encapsulation state).
Fig. 3, for the utility model structural representation cutaway view (piling up two-layer).
Fig. 4, for the utility model structural representation cutaway view (piling up three layers).
Embodiment
As shown in Figure 2, the utility model comprises lower floor's integrated circuit body 40 and upper strata integrated circuit body 42.
Lower floor's integrated circuit body 40 is provided with first surface 44 and second surface 46; First surface is provided with first contact 48 of a plurality of formation ball grid array Metal Ball (Ball Grid Array) 50; Second surface 46 forms in order to be electrically connected a plurality of second contacts 51 of upper strata integrated circuit body 42.
Lower floor's integrated circuit body 40 comprises substrate 52, is arranged at integrated circuit 54 and plural wires 56 on the substrate 52.Substrate 52 is provided with hollow slots 58.Integrated circuit 54 is provided with a plurality of weld pads 57 that exposed by substrate 52 hollow slots 58.Plural wires 56 is to be positioned at hollow slots 58, and its two ends form with integrated circuit 54 weld pads 57 and substrate 52 respectively and are electrically connected.
Upper strata integrated circuit body 42 is provided with first surface and the second surface that is formed with a plurality of formation ball grid array Metal Ball 60.
Upper strata integrated circuit body 42 is stacked and placed on the second surface 46 of lower floor's integrated circuit body 40, make second contact 51 of the ball grid array Metal Ball 60 electrical connection lower floor integrated circuit bodies 40 on it, so, promptly finish the stacked combination of upper and lower laminate circuit body 40,42.
Upper strata integrated circuit body 42 is identical structure with lower floor integrated circuit body 40, and it comprises substrate 52, is arranged at integrated circuit 54 and plural wires 56 on the substrate 52.Substrate 52 is provided with hollow slots 58.Integrated circuit 54 is provided with a plurality of weld pads 57 that exposed by substrate 52 hollow slots 58.Plural wires 56 is to be positioned at hollow slots 58, and its two ends form with integrated circuit 54 weld pads 57 and substrate 52 respectively and are electrically connected.
As shown in Figure 3, after upper and lower laminate circuit body 40,42 stacked combination of finishing as shown in Figure 2, adhesive body 62 is filled in 40 of upper strata integrated circuit body 42 and lower floor's integrated circuit bodies in the encapsulating mode, so, adhesive body 62 envelopes in order to ball grid array Metal Ball 60 that is electrically connected upper and lower laminate circuit body 42,40 and integrated circuit 54, and the reason external factor is impaired and influence useful life of the present utility model to make it.And in the sealing process, can simultaneously integrated circuit 54 be enveloped, to protect integrated circuit 54.
As shown in Figure 4; also a plurality of integrated circuit bodies 40,42,43 can be piled up mutually; again adhesive body 62 is poured between each adjacent integrated circuit body; so; can protect the ball grid array Metal Ball 60 of mutual electrical connection simultaneously; and the ball grid array Metal Ball 50 of lower floor's integrated circuit body 40 is in order to be electrically connected on the printed circuit board (PCB) 64, the signal of a plurality of integrated circuit bodies 40,42 and 43 is passed on the printed circuit board (PCB) 64.
As mentioned above, the utlity model has following advantage:
1, with after a plurality of ball grid array Metal Ball integrated circuit body stacked package, have the effect that can protect the ball grid array Metal Ball, integrated circuit is piled up after, its ball grid array Metal Ball is unlikely impaired.
2, after it can pile up several integrated circuit bodies, protect ball grid array Metal Ball and integrated circuit simultaneously, suitable facility on processing procedure in the encapsulating mode.

Claims (5)

1, a kind of ball grid array Metal Ball integrated circuit piled-up packing assembly, it comprises lower floor's integrated circuit body and the more than one upper strata integrated circuit body that piles up mutually; Lower floor's integrated circuit body is provided with a plurality of second surfaces that are electrically connected to the first surface of printed circuit board (PCB) first contact and are provided with a plurality of second contacts; Upper strata integrated circuit body is stacked and placed on lower floor's integrated circuit body second surface and is electrically connected second contact of lower floor's integrated circuit body; Lower floor's integrated circuit body and be stacked and placed between the upper strata integrated circuit body of lower floor's integrated circuit body second surface and be provided with the adhesive body that is used to cover plural second contact.
2, ball grid array Metal Ball integrated circuit piled-up packing assembly according to claim 1 is characterized in that first and second contact of described lower floor integrated circuit body forms the ball grid array Metal Ball respectively.
3, ball grid array Metal Ball integrated circuit piled-up packing assembly according to claim 1 is characterized in that described lower floor integrated circuit body comprises substrate, is arranged at integrated circuit and plural wires on the substrate; Substrate is provided with hollow slots; Plural wires system is positioned at hollow slots, and its two ends form with integrated circuit and substrate respectively and are electrically connected.
4, ball grid array Metal Ball integrated circuit piled-up packing assembly according to claim 1 is characterized in that described upper strata integrated circuit body comprises substrate, is arranged at integrated circuit and plural wires on the substrate; Substrate is provided with hollow slots; Plural wires system is positioned at hollow slots, and its two ends form with integrated circuit and substrate respectively and are electrically connected.
5, ball grid array Metal Ball integrated circuit piled-up packing assembly according to claim 1 is characterized in that described sealing system is filled between lower floor's integrated circuit body and upper strata integrated circuit body in the encapsulating mode.
CN01274949U 2001-11-27 2001-11-27 Spherical grid array metal ball integrated circuit package assembly Expired - Lifetime CN2524375Y (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN01274949U CN2524375Y (en) 2001-11-27 2001-11-27 Spherical grid array metal ball integrated circuit package assembly

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN01274949U CN2524375Y (en) 2001-11-27 2001-11-27 Spherical grid array metal ball integrated circuit package assembly

Publications (1)

Publication Number Publication Date
CN2524375Y true CN2524375Y (en) 2002-12-04

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ID=33679464

Family Applications (1)

Application Number Title Priority Date Filing Date
CN01274949U Expired - Lifetime CN2524375Y (en) 2001-11-27 2001-11-27 Spherical grid array metal ball integrated circuit package assembly

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CN (1) CN2524375Y (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100539131C (en) * 2007-11-29 2009-09-09 日月光半导体制造股份有限公司 Electronic element packaging structure
US7884486B2 (en) 2007-04-30 2011-02-08 Chipmos Technology Inc. Chip-stacked package structure and method for manufacturing the same
CN103219327A (en) * 2003-12-22 2013-07-24 英特尔公司 Integrating passive components on spacer in stacked dies
WO2018126542A1 (en) * 2017-01-04 2018-07-12 华为技术有限公司 Pop (package on package) structure and terminal

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103219327A (en) * 2003-12-22 2013-07-24 英特尔公司 Integrating passive components on spacer in stacked dies
CN103219327B (en) * 2003-12-22 2016-08-03 英特尔公司 Integrating passive components on pad between stacked-up type tube core
US7884486B2 (en) 2007-04-30 2011-02-08 Chipmos Technology Inc. Chip-stacked package structure and method for manufacturing the same
CN100539131C (en) * 2007-11-29 2009-09-09 日月光半导体制造股份有限公司 Electronic element packaging structure
WO2018126542A1 (en) * 2017-01-04 2018-07-12 华为技术有限公司 Pop (package on package) structure and terminal
CN108780790A (en) * 2017-01-04 2018-11-09 华为技术有限公司 A kind of stack package structure and terminal
CN108780790B (en) * 2017-01-04 2020-10-27 华为技术有限公司 Stack packaging structure and terminal

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C14 Grant of patent or utility model
GR01 Patent grant
C17 Cessation of patent right
CX01 Expiry of patent term

Expiration termination date: 20111127

Granted publication date: 20021204