CN206364006U - A kind of semiconductor package - Google Patents
A kind of semiconductor package Download PDFInfo
- Publication number
- CN206364006U CN206364006U CN201621406797.6U CN201621406797U CN206364006U CN 206364006 U CN206364006 U CN 206364006U CN 201621406797 U CN201621406797 U CN 201621406797U CN 206364006 U CN206364006 U CN 206364006U
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- CN
- China
- Prior art keywords
- tin ball
- bonding wire
- chip
- pin
- solder joint
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85009—Pre-treatment of the connector or the bonding area
- H01L2224/85051—Forming additional members, e.g. for "wedge-on-ball", "ball-on-wedge", "ball-on-ball" connections
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
The utility model is related to a kind of semiconductor package, belongs to technical field of semiconductor encapsulation.It includes lead frame（1）, the lead frame（1）Including Ji Dao（6）And pin（7）, the Ji Dao（6）It is upper to pass through bonding material（8）Chip is just housed（2）, the chip（2）Bonding wire zone position be provided with tin ball（3）, the tin ball（3）With pin（7）Between pass through bonding wire（4）It is electrically connected with, the bonding wire（4）First solder joint at two ends（9）With the second solder joint（10）Respectively with tin ball（3）And pin（7）It is combined, the tin ball（3）Wrap up bonding wire（4）The first solder joint（9）, the Ji Dao（6）, pin（7）, chip（2）, tin ball（3）And bonding wire（4）Periphery is encapsulated with plastic packaging material（5）.A kind of semiconductor package of the utility model, by using tin ball is planted on chip, tin ball is melted the mode for firmly wrapping bonding wire after routing on tin ball increases the bond strength of bonding wire and chip, so as to solve the problems, such as that the ball being likely to occur takes off and product failure.
Description
Technical field
The utility model is related to a kind of semiconductor package, belongs to technical field of semiconductor encapsulation.
Background technology
Existing ball bonding mode, is the gold thread using high-purity（Au）, copper cash（Cu）, aluminum steel（Al）Or alloy wire is core
Piece nip and lead are connected by the method for welding.Nip is the outer contact of on-chip circuitry, and lead is on lead frame
Tie point.Wherein, the binding site of bonding wire and nip be in line connection process, successive process or product when subsequently using
Now abnormal more place, it is limited to the factors such as nip size, the thickness of nip metal level, it is possible to create following these lack
Fall into：First, if nip metal level is too thin, routing engagement difficulty can be very big, and routing pressure is overweight easily to make electricity under nip
Road is damaged, and causes product failure；Second, if routing pressure kicks the beam, soldered ball can not pressed with nip, so as to cause product rosin joint
Or open circuit, or during the use in later stage because occur soldered ball come off and caused by product failure.
To solve this problem, industry common practice is all to add the gimmicks such as tight Row control, optimization bonding wire parameter, but seldom
The angle changed from product design and technique goes to improve.
Utility model content
Technical problem to be solved in the utility model is to provide a kind of semiconductor package for above-mentioned prior art,
By using tin ball is planted on chip, make on tin ball after routing tin ball melt the mode for firmly wrapping bonding wire increase bonding wire with
The bond strength of chip, so as to solve the problems, such as that the ball being likely to occur takes off and product failure.
The technical scheme in the invention for solving the above technical problem is：A kind of semiconductor package, it includes drawing
Wire frame, the lead frame is included on Ji Dao and pin, the Ji Dao by bonding material just equipped with chip, the chip
Bonding wire zone position is provided with tin ball, is electrically connected between the tin ball and pin by bonding wire, first weldering at the bonding wire two ends
Point and the second solder joint be combined respectively with tin ball and pin, the tin ball parcel bonding wire the first solder joint, the Ji Dao, pin,
Chip, tin ball and bonding wire periphery are encapsulated with plastic packaging material.
Compared with prior art, the utility model has the advantage of：
1st, routing is carried out on tin ball, tin ball air exercise line pressure plays cushioning effect, so as to reduce electric under chip nip
The risk that road is cracked because routing pressure is excessive, improves the yield of product.In addition, need not also increase aluminium mat thickness or again
New design chips structure improves the combination effect of the first solder joint, can reduce manufacturing cost.
2nd, the routing on tin ball, and after Reflow Soldering, the first solder joint of bonding wire is wrapped in the inside by tin ball, bonding wire with
The binding site of tin ball is transferred to inside tin ball by tin ball surface, makes to combine more fully, product reliability is higher.
Brief description of the drawings
Fig. 1 is a kind of schematic diagram of semiconductor package of the utility model.
Fig. 2 ~ Fig. 9 is a kind of each operation flow chart of the process of semiconductor package of the utility model.
Fig. 7 is the enlarged drawing at Fig. 6 circles position.
Wherein：
Lead frame 1
Chip 2
Tin ball 3
Bonding wire 4
Plastic packaging material 5
Base island 6
Pin 7
Bonding material 8
First solder joint 9
Second solder joint 10.
Embodiment
The utility model is described in further detail below in conjunction with accompanying drawing embodiment.
As shown in figure 1, a kind of semiconductor package in the present embodiment, it includes lead frame 1, the lead frame
1 is included on base island 6 and pin 7, the base island 6 by bonding material 8 just equipped with chip 2, and the bonding wire zone position of the chip 2 is set
Tin ball 3 is equipped with, is electrically connected between the tin ball 3 and pin 7 by bonding wire 4, first solder joint 9 at the two ends of bonding wire 4 and
Two solder joints 10 are combined with tin ball 3 and pin 7 respectively, and the tin ball 3 wraps up the first solder joint 9 of bonding wire 4, the base island 6, pin
7th, chip 2, tin ball 3 and the periphery of bonding wire 4 are encapsulated with plastic packaging material 5.
Its process is as follows：
Step 1: referring to Fig. 2, taking a lead frame；
Step 2, referring to Fig. 3,4, the base island front surface coated of step one lead frame is conductive or non-conductive bonding material,
Then chip is implanted on bonding material, the bonding wire nip position of chip is implanted with tin ball；
Step 3, referring to Fig. 5, routing operation, institute are carried out between tin ball and the pin front of chip bonding wire nip position
The material of bonding wire is stated using the material of gold, silver, copper, aluminium or alloy；
Step 4, referring to Fig. 6, the lead frame that step 3 is completed into routing operation carries out Reflow Soldering, tin ball is melted bag
Wrap up in bonding wire.It is the enlarged drawing at Fig. 6 circles position referring to Fig. 7, after Reflow Soldering, the first solder joint of bonding wire is wrapped in by tin ball
The inside, the binding site of bonding wire and tin ball is transferred to inside tin ball by tin ball surface..
Step 5, referring to Fig. 8, carries out plastic packaging, plastic packaging mode can be adopted by the lead frame in step 4 using plastic packaging material
With mould encapsulating mode, spraying method or use pad pasting mode, it is described can be using having packing material or no-arbitrary pricing material
Epoxy resin；
Step 6: referring to Fig. 9, the semi-finished product that step 5 is completed into plastic packaging are cut or are punched operation, make script battle array
Column plastic-sealed body cuts or is punched independent, obtained single semiconductor package.
In addition to the implementation, the utility model also includes other embodiment, all use equivalents or equivalent
The technical scheme of substitute mode formation, all should fall within the utility model scope of the claims.
Claims (1)
1. a kind of semiconductor package, it is characterised in that：It includes lead frame（1）, the lead frame（1）Including Ji Dao
（6）And pin（7）, the Ji Dao（6）It is upper to pass through bonding material（8）Chip is just housed（2）, the chip（2）Bonding wire position
Install and be equipped with tin ball（3）, the tin ball（3）With pin（7）Between pass through bonding wire（4）It is electrically connected with, the bonding wire（4）Two ends
First solder joint（9）With the second solder joint（10）Respectively with tin ball（3）And pin（7）It is combined, the tin ball（3）Wrap up bonding wire（4）
The first solder joint（9）, the Ji Dao（6）, pin（7）, chip（2）, tin ball（3）And bonding wire（4）Periphery is encapsulated with plastic packaging material
（5）.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621406797.6U CN206364006U (en) | 2016-12-21 | 2016-12-21 | A kind of semiconductor package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621406797.6U CN206364006U (en) | 2016-12-21 | 2016-12-21 | A kind of semiconductor package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN206364006U true CN206364006U (en) | 2017-07-28 |
Family
ID=59375103
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201621406797.6U Active CN206364006U (en) | 2016-12-21 | 2016-12-21 | A kind of semiconductor package |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN206364006U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106783780A (en) * | 2016-12-21 | 2017-05-31 | 长电科技（宿迁）有限公司 | A kind of semiconductor package and its process |
| CN109916744A (en) * | 2019-04-18 | 2019-06-21 | 广东工业大学 | A kind of detection method and equipment of solder joint and substrate tensile strength |
-
2016
- 2016-12-21 CN CN201621406797.6U patent/CN206364006U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106783780A (en) * | 2016-12-21 | 2017-05-31 | 长电科技（宿迁）有限公司 | A kind of semiconductor package and its process |
| CN109916744A (en) * | 2019-04-18 | 2019-06-21 | 广东工业大学 | A kind of detection method and equipment of solder joint and substrate tensile strength |
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| GR01 | Patent grant |