CN206505909U - A kind of diode encapsulating structure of the vertical parallel way of dual chip - Google Patents
A kind of diode encapsulating structure of the vertical parallel way of dual chip Download PDFInfo
- Publication number
- CN206505909U CN206505909U CN201720160787.7U CN201720160787U CN206505909U CN 206505909 U CN206505909 U CN 206505909U CN 201720160787 U CN201720160787 U CN 201720160787U CN 206505909 U CN206505909 U CN 206505909U
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- lead
- chip
- outer lead
- positioning step
- electrode slice
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
- H01L2224/8438—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/84385—Shape, e.g. interlocking features
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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Abstract
The utility model discloses a kind of diode encapsulating structure of the vertical parallel way of dual chip, including the lead frame being made up of outer lead A, outer lead B and slide holder, lead A, lead B, the first chip and the second chip, positioning step is equipped with outer lead A and outer lead B；The positioning step of the positioning step and outer lead B in outer lead A is respectively welded in lead A and lead B；The anode surface of first chip is respectively welded at lead A bottom surface and lead B top surface with cathode plane, and the cathode plane and anode surface of the second chip are respectively welded at lead B bottom surface and the top surface of slide holder.The utility model can make the bigger current capacity of diode device realization and power capability in the size of small-sized encapsulated.
Description
Technical field
The utility model is related to a kind of technical field of semiconductor device, and the two of the vertical parallel way of specifically a kind of dual chip
Polar body encapsulating structure.
Background technology
Limited by packaging appearance size, the chip area maximum that can be enclosed in certain package dimension is certain
's.In order in certain packaging appearance size, make the bigger current capacity of the diode such as TVS device realization and power capability,
The method that someone uses chip-in series in the manufacture of the diode device such as TVS at present, but there are two drawbacks in this method：Its
One, for TVS device, it is necessary to using the chip-in series of two and half load voltage values, for the low of load voltage value≤12V
Voltage TVS device can not realize, reason be low-voltage TVS chips as voltage≤6V, its leakage current it is especially big；Second,
For commutation diode, two chip-in series add forward voltage drop value, and the hair of power consumption and device is added when in use
Heat.The market demand of current capacity and power capability is improved in face of miniaturized device, is badly in need of new scheme.
Utility model content
In order to solve the above technical problems, the utility model provides a kind of diode encapsulation knot of the vertical parallel way of dual chip
Structure, within the size of small-sized encapsulated, can improve the current capacity and power capability of device.
The technical solution adopted in the utility model is：A kind of diode encapsulating structure of the vertical parallel way of dual chip, bag
Lead frame is included, is made up of outer lead A, outer lead B and slide holder, is equipped with above the outer lead A and outer lead B upwards
Positioning step, the outer lead A is integrated with slide holder, and the slide glass countertop is provided with boss；
Lead A, is made up of, the welding the welding arm of electrode slice of the bottom surface provided with boss and side downward bending 90o
The bottom surface of arm is welded between outer lead A positioning step；
Lead B, is made up of, the bottom surface of the welding arm is welded in the welding arm of electrode slice and side downward bending 90o
Between outer lead B positioning step；
First chip, its anode surface and the boss of lead A bottom surfaces weld together, the electricity of its cathode plane and lead B
Pole piece top surface welds together；
Second chip, the electrode slice bottom surface of its cathode plane and lead B welds together, its anode surface and slide glass countertop
Boss weld together.
First chip and the second chip, which are two, has identical function and TVS, the semiconductor discharge tube or two of size
Pole pipe chip.
The manufacture method of the diode encapsulating structure of the vertical parallel way of above-mentioned dual chip, comprises the following steps：
（1）Two leads and two chips are welded into a component：A, lead A upside-down mountings are entered into graphite jig
In positioning hole, b, weld tabs one is packed into the positioning hole of graphite jig, c, presses anode surface direction directed downwardly and fill the first chip
In the positioning hole for inserting graphite jig, d, weld tabs two is packed into the positioning hole of graphite jig, e, lead B upside-down mountings entered into stone
In the positioning hole of black mould, f, weld tabs three is packed into the positioning hole of graphite jig, g, presses cathode plane direction directed downwardly by
Two chips are packed into the positioning hole of graphite jig, h, will the component that assembled place vacuum drying oven in sinter；
（2）The bottom surface of component is pasted on a blue film with taut ring after the completion of sintering；
（3）Using auto welding equipment, by components welding on the lead frames：A, auto welding equipment first exist
Solder(ing) paste, b, aspiration step are coated on outer lead A, outer lead B positioning step and the slide holder of lead frame（2）On middle blue film
Component, c, component be positioned on the solder(ing) paste on lead frame be sintered；
（4）After the completion of sintering, product is encapsulated, solidify afterwards, plastic flash, rib cutting, tin plating, test, lettering, volume is gone
Band, examine, enter warehouse for finished product.
The utility model has the advantages that：The diode chip such as TVS with two same nominal magnitudes of voltage, using vertical parallel connection
The encapsulating structure and manufacture method of mode, have reached the effect for improving device current capability and power capability.
Brief description of the drawings
Fig. 1 is structural representation of the present utility model；
Fig. 2 is the dimensional structure diagram of lead frame in the utility model；
The stereogram that Fig. 3 is lead A in the utility model；
The front view that Fig. 4 is lead A in the utility model；
The structural representation that Fig. 5 is lead B in the utility model；
Fig. 6 is the structural representation of the utility model chips；
In figure, 1, lead frame, 11, outer lead A, 12, outer lead B, 13, slide holder, 14, positioning step, 2, lead
A, 3, welding arm, 4, electrode slice, 5, boss, 6, lead B, the 7, first chip, the 8, second chip.
Embodiment
The technical solution of the utility model is further described with specific embodiment below in conjunction with the accompanying drawings, but this practicality
New protection domain not limited to this.
As shown in Figures 1 to 6, a kind of diode encapsulating structure of the vertical parallel way of dual chip, including lead frame 1,
It is made up of outer lead A 11, outer lead B 12 and slide holder 13, outer lead A 11 and outer lead B 12 are equipped with upward above
Positioning step 14, outer lead A 11 is integrated with slide holder 13, and the top surface of slide holder 13 is provided with boss 5；
Lead A 2, is made up of the welding arm 3 of electrode slice 4 of the bottom surface provided with boss 5 and side downward bending 90o, welds
The bottom surface of arm 3 is welded between outer lead A 11 positioning step 14；
Lead B 6, is made up of, the bottom surface of welding arm 3 is welded in the welding arm 3 of electrode slice 4 and side downward bending 90o
Between outer lead B 12 positioning step 14；
First chip 7, its anode surface and the boss 5 of the bottom surfaces of lead A 2 weld together, its cathode plane and lead B
6 top surface of electrode slice 4 welds together；
Second chip 8, the bottom surface of electrode slice 4 of its cathode plane and lead B 6 welds together, its anode surface and slide holder
The boss 5 of 13 top surfaces welds together.In this, just realize two chips vertically on parallel packaging structure.
Wherein, the first chip 7 and the second chip 8 be two TVS with identical function and size, semiconductor discharge tube or
Diode chip for backlight unit.
The manufacture method of the diode encapsulating structure of the vertical parallel way of above-mentioned dual chip, comprises the following steps：
（1）Two leads and two chips are welded into a component：A, lead A upside-down mountings are entered into graphite jig
In positioning hole, b, weld tabs one is packed into the positioning hole of graphite jig, is placed on the bottom surface boss of lead A electrode slice
On, c, by anode surface direction directed downwardly first chip is packed into the positioning hole of graphite jig, d, weld tabs two is packed into stone
In the positioning hole of black mould, on the cathode plane for being placed on the first chip, e, the positioning hole that lead B upside-down mountings are entered to graphite jig
In, f, weld tabs three is packed into the positioning hole of graphite jig, g, by cathode plane direction directed downwardly second chip is packed into stone
In the positioning hole of black mould, it is placed on lead B electrode slice bottom surface, component assembling is completed, h, puts the component assembled
Put in vacuum drying oven and be sintered；
（2）Go out after the completion of sintering and paste the bottom surface of component on one blue film with taut ring；
（3）Using auto welding equipment, by components welding on the lead frames：A, auto welding equipment first exist
Quantitative solder(ing) paste is coated on the outer lead A of lead frame, outer lead B positioning step, then coats on slide holder quantitative weldering
Tin cream, b, aspiration step（2）Component on middle blue film, c, the positioning table by the lead A of component welding arm alignment outer lead A
Rank, the lead B of component welding arm is directed at outer lead B positioning step, and the second chip is placed on slide holder, completion group
Part is assembled to laggard sintering furnace on lead frame and is sintered；
（4）After the completion of sintering, then product is encapsulated, solidify afterwards, go plastic flash, rib cutting, it is tin plating, test, print
Word, braid, examine, enter warehouse for finished product.
Claims (2)
1. the diode encapsulating structure of the vertical parallel way of a kind of dual chip, it is characterised in that including lead frame, by drawing outside
Upward positioning step is equipped with above line A, outer lead B and slide holder composition, the outer lead A and outer lead B, it is described to draw outside
Line A is integrated with slide holder, and the slide glass countertop is provided with boss；
Lead A, is made up of the welding arm of electrode slice of the bottom surface provided with boss and side downward bending 90o, the welding arm
Bottom surface is welded between outer lead A positioning step；
Lead B, is made up of the welding arm of electrode slice and side downward bending 90o, and the bottom surface of the welding arm is welded in outer draw
Between line B positioning step；
First chip, its anode surface and the boss of lead A bottom surfaces weld together, the electrode slice of its cathode plane and lead B
Top surface welds together；
Second chip, the electrode slice bottom surface of its cathode plane and lead B welds together, and its anode surface is convex with slide glass countertop
Platform welds together.
2. a kind of diode encapsulating structure of the vertical parallel way of dual chip according to claim 1, it is characterised in that institute
Stating the first chip and the second chip is two and has identical function and TVS, semiconductor discharge tube or the diode chip for backlight unit of size.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720160787.7U CN206505909U (en) | 2017-02-22 | 2017-02-22 | A kind of diode encapsulating structure of the vertical parallel way of dual chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720160787.7U CN206505909U (en) | 2017-02-22 | 2017-02-22 | A kind of diode encapsulating structure of the vertical parallel way of dual chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN206505909U true CN206505909U (en) | 2017-09-19 |
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ID=59840266
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201720160787.7U Active CN206505909U (en) | 2017-02-22 | 2017-02-22 | A kind of diode encapsulating structure of the vertical parallel way of dual chip |
Country Status (1)
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| CN (1) | CN206505909U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106783762A (en) * | 2017-02-22 | 2017-05-31 | 捷捷半导体有限公司 | The diode encapsulating structure and manufacture method of a kind of vertical parallel way of dual chip |
| CN113257797A (en) * | 2021-06-25 | 2021-08-13 | 瑞能半导体科技股份有限公司 | Common anode diode device and preparation method thereof |
-
2017
- 2017-02-22 CN CN201720160787.7U patent/CN206505909U/en active Active
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106783762A (en) * | 2017-02-22 | 2017-05-31 | 捷捷半导体有限公司 | The diode encapsulating structure and manufacture method of a kind of vertical parallel way of dual chip |
| CN106783762B (en) * | 2017-02-22 | 2024-01-02 | 捷捷半导体有限公司 | Diode packaging structure with double chips in vertical parallel connection mode and manufacturing method |
| CN113257797A (en) * | 2021-06-25 | 2021-08-13 | 瑞能半导体科技股份有限公司 | Common anode diode device and preparation method thereof |
| CN113257797B (en) * | 2021-06-25 | 2022-04-22 | 瑞能半导体科技股份有限公司 | Common anode diode device and preparation method thereof |
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| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CP02 | Change in the address of a patent holder | ||
| CP02 | Change in the address of a patent holder |
Address after: 226200 Jinggangshan Road, Jinggangshan Road, Sutong science and Technology Industrial Park, Nantong City, Jiangsu Province, No. 6 Patentee after: Agile Semiconductor Ltd Address before: 226200 Jiangsu city of Nantong province science and Technology Industrial Park of Su Tong Jiang Cheng Road No. 1088 Jiang Park Building 3, room 2159, R & D Patentee before: Agile Semiconductor Ltd |