JP2006228953A - Surface mounted package - Google Patents

Surface mounted package Download PDF

Info

Publication number
JP2006228953A
JP2006228953A JP2005040612A JP2005040612A JP2006228953A JP 2006228953 A JP2006228953 A JP 2006228953A JP 2005040612 A JP2005040612 A JP 2005040612A JP 2005040612 A JP2005040612 A JP 2005040612A JP 2006228953 A JP2006228953 A JP 2006228953A
Authority
JP
Japan
Prior art keywords
insulating film
external connection
flexible printed
hole
device chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2005040612A
Other languages
Japanese (ja)
Inventor
Hideji Takagi
秀治 高木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
3M Innovative Properties Co
Original Assignee
3M Innovative Properties Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 3M Innovative Properties Co filed Critical 3M Innovative Properties Co
Priority to JP2005040612A priority Critical patent/JP2006228953A/en
Publication of JP2006228953A publication Critical patent/JP2006228953A/en
Withdrawn legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item

Landscapes

  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a means of sufficiently ensuring mounting reliability of a surface mounted package even if the surface mounted package is miniaturized. <P>SOLUTION: In the surface mounted package 10, a device chip 3 is placed on a flexible printed board 20 and the substrate is insulation-coated. The flexible printed board 20 has an insulating film 1 having drilled through-holes 5 and flat electrodes 6 for external connection formed to close the through-holes 5 on one surface of the insulating film 1. Each of the through-holes 5 exhibits a tapered shape of gradually extending from one surface 8 of the insulating film 1 to the other surface 9, and bumps 4 for internal connection to be electrically connected to the electrodes 6 are formed on the through-holes 5. Further, the device chip 3 is placed on the other surface 9 to the insulating film 1, and is electrically connected to the electrodes 6. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、実装信頼性に優れるチップレベルの表面実装パッケージに関する。   The present invention relates to a chip-level surface-mount package having excellent mounting reliability.

近年、チップレベルの表面実装パッケージにおける実装用基板として、薄く、柔軟性に富むフレキシブルプリント基板（ＦＰＣ、Ｆｌｅｘｉｂｌｅ Ｐｒｉｎｔｅｄ Ｃｉｒｃｕｉｔ）が多用されている。一般に、ＦＰＣは、フィルム状の基材の一の面に回路パターンが形成されたものであって、フィルム状の基材が柔軟性を有する高分子樹脂等でなることにより、屈曲特性を発現するものである。例えば、シリコンウエハに、酸化膜形成、レジスト塗布、露光、現像、エッチング、ドーピング、配線等の手順で回路形成し、ダイシングによりチップ単位に切り分けた後に、ＦＰＣに得られたチップ（デバイスチップ）を載置し、ボンディング、モールディング等を経て、集積回路（ＩＣ）の表面実装パッケージを作製することが出来る。   In recent years, a thin and flexible printed circuit board (FPC, Flexible Printed Circuit) is frequently used as a mounting board in a chip-level surface-mount package. In general, an FPC has a circuit pattern formed on one surface of a film-like substrate, and exhibits bending characteristics when the film-like substrate is made of a flexible polymer resin or the like. Is. For example, after forming a circuit on a silicon wafer according to procedures such as oxide film formation, resist coating, exposure, development, etching, doping, wiring, etc., and cutting into chips by dicing, chips (device chips) obtained in FPC are obtained. Through mounting, bonding, molding, and the like, a surface mount package of an integrated circuit (IC) can be manufactured.

図６及び図７は、従来の表面実装パッケージを示す図であり、図７は斜視図であり、図６は図７におけるＡＡ断面を表す図である。図示される表面実装パッケージ６０では、フレキシブルプリント基板６１（ＦＰＣ６１）の一の面（図中において上面）側にデバイスチップ６３が配置され、同じ面側に内部電極６６が設けられている。デバイスチップ６３は、配線６７で内部電極６６と電気的に接続され、ＦＰＣ６１の貫通孔６５に形成された外部接続用バンプ６４と導通している（即ち、貫通孔６５はビアホールになっている）。外部接続用バンプ６４は、その外部接続に関わる部分がＦＰＣ６１から露出している。そして、外部接続用バンプ６４を除く全体が、絶縁材６２によって被覆され、保護・絶縁が図られている。尚、表面実装パッケージにかかる先行文献として、例えば特許文献１が挙げられる。
特開平９−７４１４９号公報 6 and 7 are views showing a conventional surface mount package, FIG. 7 is a perspective view, and FIG. 6 is a view showing a cross section AA in FIG. In the illustrated surface mount package 60, a device chip 63 is disposed on one surface (upper surface in the drawing) side of a flexible printed circuit board 61 (FPC 61), and an internal electrode 66 is disposed on the same surface side. The device chip 63 is electrically connected to the internal electrode 66 through the wiring 67 and is electrically connected to the external connection bump 64 formed in the through hole 65 of the FPC 61 (that is, the through hole 65 is a via hole). . The external connection bump 64 is exposed from the FPC 61 at a portion related to the external connection. The entire structure excluding the external connection bumps 64 is covered with an insulating material 62 for protection and insulation. For example, Patent Document 1 is cited as a prior document relating to the surface mount package.
JP-A-9-74149

表面実装パッケージでは、従来より、常に小型化の要請があるが、それと同時に実装信頼性を確保することも重要である。例えば、図６に示される従来の表面実装パッケージ６０では、外部接続用バンプ６４を大きくすればするほど実装信頼性は向上する。しかし、ＦＰＣ６１を絶縁材６２によって被覆する際に、貫通孔６５からの絶縁材の漏れを防止するため、外部接続用バンプ６４の内部電極６６に接触する面積は、ＦＰＣ６１に面した内部電極６６の大きさより常に小さくしなければならない。従って、外部接続用バンプ６４を、より大きくして、実装信頼性を更に向上させようとしても、ＦＰＣ６１に面した内部電極６６の大きさによって、常に制限されてしまう。一方、表面実装パッケージ６０を小型化するために内部電極６６のＦＰＣ６１に面した大きさを小さくしようとすれば、上記外部接続用バンプ６４を小さくしなければならない。   In surface mount packages, there has always been a demand for miniaturization, but at the same time, it is important to ensure mounting reliability. For example, in the conventional surface mount package 60 shown in FIG. 6, the mounting reliability increases as the external connection bumps 64 increase. However, in order to prevent leakage of the insulating material from the through hole 65 when the FPC 61 is covered with the insulating material 62, the area of the external connection bump 64 that contacts the internal electrode 66 is the area of the internal electrode 66 facing the FPC 61. It must always be smaller than the size. Therefore, even if the external connection bump 64 is made larger to further improve the mounting reliability, it is always limited by the size of the internal electrode 66 facing the FPC 61. On the other hand, if the size of the internal electrode 66 facing the FPC 61 is to be reduced in order to reduce the size of the surface mount package 60, the external connection bump 64 must be reduced.

本発明は、このような従来の問題に鑑みてなされたものであり、その目的とするところは、表面実装パッケージを小型化しても、その実装信頼性を十分に確保することが出来る手段を提供することにある。研究が重ねられた結果、以下に示す手段により、この目的を達成出来ることが見出された。   The present invention has been made in view of such a conventional problem, and an object of the present invention is to provide means capable of sufficiently ensuring the mounting reliability even if the surface mounting package is downsized. There is to do. As a result of repeated research, it was found that this purpose can be achieved by the following means.

即ち、先ず、本発明によれば、フレキシブルプリント基板にデバイスチップが載置され、絶縁被覆されている表面実装パッケージであって、フレキシブルプリント基板は、貫通孔が開けられた絶縁性フィルムと、その絶縁性フィルムの一の面において貫通孔を塞ぐように形成された平坦な外部接続用電極と、を有し、貫通孔は、絶縁性フィルムの一の面側から他の面側に向けて徐々に広がるテーパー形状を呈するとともに、その貫通孔に、外部接続用電極と電気的に接続される内部接続用バンプが形成され、更に、デバイスチップは、絶縁性フィルムの他の面に載置され、外部接続用電極と電気的に接続されている表面実装パッケージが提供される。   That is, first, according to the present invention, a surface mount package in which a device chip is mounted on a flexible printed circuit board and is insulation-coated, the flexible printed circuit board includes an insulating film having a through hole, and its A flat external connection electrode formed so as to block the through hole on one surface of the insulating film, and the through hole gradually moves from one surface side to the other surface side of the insulating film. The internal connection bumps that are electrically connected to the external connection electrodes are formed in the through-holes, and the device chip is placed on the other surface of the insulating film. A surface mount package electrically connected to an external connection electrode is provided.

本発明の表面実装パッケージにおいて、貫通孔がテーパー形状を呈する、とは、絶縁性フィルムに、意図して、テーパー形状を呈する貫通孔が設けられていることを意味し、直胴状の貫通孔を得ようとしたが打抜加工（機械加工）やレーザ加工における加工精度の限界によって、結果として貫通孔がテーパー形状になったものではない。テーパー形状に加工する手段としては、エッチング、レーザ加工、ドリルによるザグリ加工、プラズマ加工等が採用出来、光学顕微鏡で確認することが出来る。   In the surface mount package of the present invention, that the through-hole has a tapered shape means that the insulating film is intentionally provided with a through-hole having a tapered shape. However, due to the limit of processing accuracy in punching (machining) and laser processing, the through hole does not have a tapered shape as a result. Etching, laser processing, counterbore processing with a drill, plasma processing, etc. can be adopted as means for processing into a tapered shape, which can be confirmed with an optical microscope.

本発明の表面実装パッケージにおいて、上記テーパー形状を呈する貫通孔にかかるテーパー角度は、通常２０〜４５°である。このテーパー角度は、絶縁性フィルムの一の面と、絶縁性フィルムに形成された貫通孔の壁面と、が形成する角度に相当する。   In the surface mount package of the present invention, the taper angle applied to the through hole having the tapered shape is usually 20 to 45 °. This taper angle corresponds to an angle formed by one surface of the insulating film and the wall surface of the through hole formed in the insulating film.

本発明の表面実装パッケージにおいて、絶縁性フィルムとは、主として絶縁材料からなり可撓性、柔軟性を備えた薄膜状体である。絶縁性フィルムは、可撓性、柔軟性を発現し得る限り、その厚さは限定されないが、通常１２５μｍ以下であり、好ましくは、２５〜７５μｍである。絶縁性フィルムを構成する絶縁材料は、特に限定されるものではないが、通常ポリイミドが採用される。   In the surface mount package of the present invention, the insulating film is a thin film body mainly made of an insulating material and having flexibility and flexibility. The thickness of the insulating film is not limited as long as it can exhibit flexibility and flexibility, but is usually 125 μm or less, and preferably 25 to 75 μm. Although the insulating material which comprises an insulating film is not specifically limited, Usually, a polyimide is employ | adopted.

本発明の表面実装パッケージにおいて、外部接続用電極と電気的に接続される内部接続用バンプは、通常、電解ニッケルメッキ又は電解銅メッキで形成され、フレキシブルプリント基板に載置されるデバイスチップと電気的に接続される。電気的な接続にかかる手段として、例えば、ワイヤボンディング、フリップチップ、はんだ付け、等の手段が挙げられる。   In the surface mount package of the present invention, the internal connection bumps that are electrically connected to the external connection electrodes are usually formed by electrolytic nickel plating or electrolytic copper plating, and are electrically connected to the device chip mounted on the flexible printed board. Connected. Examples of means for electrical connection include means such as wire bonding, flip chip, and soldering.

本発明の表面実装パッケージにおいて、平坦な外部接続用電極とは、主として導電性材料からなる薄膜状体であり、外表面が平坦な電極である。限定されるものではないが、平坦な外部接続用電極は、良好な導電性を有する金属層あるいはメッキを施した金属層であり、通常の材料は銅である。   In the surface mount package of the present invention, the flat external connection electrode is a thin film body mainly made of a conductive material, and is an electrode having a flat outer surface. Although not limited, the flat external connection electrode is a metal layer having good conductivity or a plated metal layer, and a normal material is copper.

本発明の表面実装パッケージにおいては、デバイスチップが載置された絶縁性フィルムの他の面が絶縁被覆されているが、その絶縁被覆は、圧力成形法によってされていてもよい。   In the surface mount package of the present invention, the other surface of the insulating film on which the device chip is placed is covered with insulation, but the insulation coating may be performed by a pressure forming method.

圧力成形法とは、圧力にて成形材料を充填する成形方法を指し、具体的手段を限定するものではない。例えば、トランスファー成形法、射出成形法を採用することが出来る。又、絶縁被覆にかかる絶縁材料（絶縁材）は、限定されるものではないが、エポキシ系に代表される熱硬化性の高分子樹脂材料を採用することが出来る。   The pressure molding method refers to a molding method in which a molding material is filled with pressure, and the specific means is not limited. For example, a transfer molding method or an injection molding method can be employed. The insulating material (insulating material) for the insulating coating is not limited, but a thermosetting polymer resin material typified by epoxy can be used.

本発明の表面実装パッケージにおいて、内部接続用バンプの高さは、ワイヤボンディング加工のし易さを考慮すると、通常、絶縁性フィルムの厚さの±１／３の値で形成され、好ましくは、絶縁性フィルムの厚さと同等の値で形成される。   In the surface mount package of the present invention, the height of the bump for internal connection is usually formed with a value of ± 1/3 of the thickness of the insulating film, considering the ease of wire bonding, preferably, It is formed with a value equivalent to the thickness of the insulating film.

本発明の表面実装パッケージにおいては、上記平坦な外部接続用電極は、複数個が適宜備えられていてもよい。   In the surface mount package of the present invention, a plurality of the flat external connection electrodes may be provided as appropriate.

本発明の表面実装パッケージは、外部接続用バンプの大きさが、ＦＰＣに面した内部電極の大きさによって常に制限されてしまうという従来の表面実装パッケージとは異なり、外部接続用電極の大きさは、ＦＰＣに面した内部接続用バンプの大きさによって制限されずに、大きくすることが出来、そのことによって実装信頼性を更に向上させることが可能である。   Unlike the conventional surface mount package in which the size of the external connection bump is always limited by the size of the internal electrode facing the FPC, the surface mount package of the present invention has the size of the external connection electrode of It can be enlarged without being limited by the size of the internal connection bumps facing the FPC, which can further improve the mounting reliability.

又、表面実装パッケージがより小型化しても、ＦＰＣに面した外部接続用電極の大きさは内部接続用バンプの大きさに制限されないので、実装信頼性を十分に確保したまま、小型化することが可能である。   Even if the surface-mount package is further downsized, the size of the external connection electrodes facing the FPC is not limited by the size of the internal connection bumps, so the size must be reduced while ensuring sufficient mounting reliability. Is possible.

更に、本発明の表面実装パッケージは、フレキシブルプリント基板にデバイスチップを載置して絶縁する際に、絶縁性フィルムの他の面側から一の面側へ、絶縁材が貫通孔から外部へ漏れるような圧力が働いても、内部接続用バンプが栓となって絶縁材の漏れを防止することが出来る。そして、内部接続用バンプが栓となって、一の面側に存在する平坦な外部接続用電極へ大きな圧力が伝達されない。即ち、圧力がかかっても、外部接続用電極の剥がれや変形を防止することが可能である。この効果は、デバイスチップが載置された絶縁性フィルムの他の面を、圧力成形法によって絶縁被覆する場合に、特に有効である。   Furthermore, in the surface mount package of the present invention, when the device chip is mounted on the flexible printed board and insulated, the insulating material leaks from the other surface side to the one surface side, and the insulating material leaks from the through hole to the outside. Even when such pressure is applied, the internal connection bumps can act as plugs to prevent leakage of the insulating material. The internal connection bumps serve as plugs, and a large pressure is not transmitted to the flat external connection electrode existing on one surface side. That is, even if pressure is applied, it is possible to prevent peeling and deformation of the external connection electrode. This effect is particularly effective when the other surface of the insulating film on which the device chip is placed is insulated by pressure molding.

以下、本発明の実施にかかる最良の形態について、図面を参酌しながら説明するが、本発明はこれらに限定されて解釈されるべきものではなく、本発明の範囲を逸脱しない限りにおいて、当業者の知識に基づいて、種々の変更、修正、改良を加え得るものである。例えば、図面は、好適な本発明の実施の形態を表すものであるが、本発明は図面に表される態様や図面に示される情報により制限されない。本発明を実施し又は検証する上では、本明細書中に記述されたものと同様の手段若しくは均等な手段が適用され得るが、好適な手段は以下に記述される手段である。   Hereinafter, the best mode for carrying out the present invention will be described with reference to the drawings. However, the present invention should not be construed as being limited to these, and those skilled in the art can be used without departing from the scope of the present invention. Based on this knowledge, various changes, modifications, and improvements can be made. For example, the drawings show preferred embodiments of the present invention, but the present invention is not limited by the modes shown in the drawings or the information shown in the drawings. In practicing or verifying the present invention, means similar to or equivalent to those described in the present specification can be applied, but preferred means are those described below.

図３及び図４はフレキシブルプリント基板を示す斜視図であり、図３は外部接続用電極が形成された（絶縁性フィルムの）一の面側を表しており、図４は（絶縁性フィルムの）他の面側を表している。又、図１、図２、及び図５は、本発明の表面実装パッケージを示す図であり、図５は斜視図であり、図１は図５におけるＢＢ断面を表した図であり、図２は図５におけるＢＢ断面のうち、貫通孔近傍を拡大して表した図である。図３及び図４に示されるフレキシブルプリント基板は、図１、図２、及び図５に示される本発明の表面実装パッケージを構成するものである。   3 and 4 are perspective views showing the flexible printed circuit board. FIG. 3 shows one surface side (of the insulating film) on which the external connection electrodes are formed, and FIG. ) Represents the other surface side. 1, FIG. 2, and FIG. 5 are views showing a surface mount package according to the present invention, FIG. 5 is a perspective view, and FIG. 1 is a view showing a BB cross section in FIG. FIG. 6 is an enlarged view of the vicinity of a through hole in the BB cross section in FIG. 5. The flexible printed circuit board shown in FIGS. 3 and 4 constitutes the surface mount package of the present invention shown in FIGS. 1, 2, and 5.

図３及び図４にそれのみが示され、図１、図２、及び図５においても構成要素として示されるフレキシブルプリント基板２０は、８つの貫通孔５が開けられた絶縁性フィルム１と、その絶縁性フィルム１の一の面８において貫通孔５を塞ぐように形成された、８つの外部接続用電極６を有している。   3 and 4, and the flexible printed circuit board 20 that is also shown as a component in FIGS. 1, 2, and 5 includes an insulating film 1 having eight through-holes 5, Eight external connection electrodes 6 are formed so as to close the through holes 5 on one surface 8 of the insulating film 1.

フレキシブルプリント基板２０において、絶縁性フィルム１に開いた貫通孔５は、絶縁性フィルム１の一の面８側から他の面９側に向けて徐々に広がるテーパー形状を呈している。そして、その貫通孔５には、電解ニッケルメッキによって内部接続用バンプ４が形成されている。貫通孔５にかかるテーパー角度は、絶縁性フィルム１の一の面８と、絶縁性フィルム１に形成された貫通孔５の壁面１１と、が形成する角度に相当する（図２及び図１参照）。フレキシブルプリント基板２０では、そのテーパー角度は３５°になっている。   In the flexible printed circuit board 20, the through hole 5 opened in the insulating film 1 has a tapered shape that gradually widens from one surface 8 side to the other surface 9 side. In the through hole 5, the internal connection bump 4 is formed by electrolytic nickel plating. The taper angle applied to the through hole 5 corresponds to the angle formed by one surface 8 of the insulating film 1 and the wall surface 11 of the through hole 5 formed in the insulating film 1 (see FIGS. 2 and 1). ). In the flexible printed circuit board 20, the taper angle is 35 °.

フレキシブルプリント基板２０において、貫通孔５に形成された内部接続用バンプ４は、その頂部４ａが、絶縁性フィルム１の他の面９と概ね同等の位置に形成されている（図２の破線はそれらが同等の位置に形成されていることを示す）。換言すれば、内部接続用バンプ４の高さは、フレキシブルプリント基板２０の厚さと、概ね同等の値に形成される。   In the flexible printed circuit board 20, the top 4 a of the internal connection bump 4 formed in the through hole 5 is formed at a position substantially equal to the other surface 9 of the insulating film 1 (the broken line in FIG. 2 is Show that they are formed in equivalent positions). In other words, the height of the internal connection bumps 4 is formed to be approximately equal to the thickness of the flexible printed circuit board 20.

図１、図２、及び図５に示される表面実装パッケージ１０は、フレキシブルプリント基板２０にデバイスチップ３が載置され、フレキシブルプリント基板２０のデバイスチップ３を含む面側に、トランスファー成形法によって、絶縁材２で構成された絶縁被覆が施されたパッケージである。デバイスチップ３が載置されている面は、フレキシブルプリント基板２０の絶縁性フィルム１における他の面９側であり、デバイスチップ３は、ワイヤボンディングとして示される導通手段７によって内部接続用バンプ４と導通し、更に、外部接続に利用される外部接続用電極６と導通している。即ち、デバイスチップ３内の回路は、導通手段７、内部接続用バンプ４、外部接続用電極６を経て、外部の回路と電気的に接続される。   1, 2, and 5, a device chip 3 is placed on a flexible printed circuit board 20, and a surface of the flexible printed circuit board 20 including the device chip 3 is transferred by a transfer molding method. This is a package provided with an insulating coating made of an insulating material 2. The surface on which the device chip 3 is placed is the other surface 9 side of the insulating film 1 of the flexible printed circuit board 20, and the device chip 3 is connected to the internal connection bump 4 by the conductive means 7 shown as wire bonding. Further, it is electrically connected to the external connection electrode 6 used for external connection. That is, the circuit in the device chip 3 is electrically connected to an external circuit through the conduction means 7, the internal connection bump 4, and the external connection electrode 6.

次に、本発明の表面実装パッケージの製造方法について、その一例を掲げて説明する。作製対象は、図１、図２、及び図５に示される表面実装パッケージ１０である。   Next, an example of the method for manufacturing the surface mount package of the present invention will be described. The fabrication target is the surface mount package 10 shown in FIGS. 1, 2, and 5.

先ず、絶縁性フィルム１である厚さ５０μｍのポリイミドフィルムに、外部接続用電極６のパターンになっている片面銅配線層（厚さ２５μｍ）が施されたものを準備する。そして、ケミカルエッチングによってポリイミドフィルム部分に約３５°のテーパー角度の貫通孔５を設け、電解銅メッキによってポリイミドフィルムの厚さと概ね同等の高さの内部接続用バンプ４を形成し、フレキシブルプリント基板２０を得る。   First, a polyimide film having a thickness of 50 μm, which is the insulating film 1, is prepared by applying a single-sided copper wiring layer (thickness of 25 μm) in the pattern of the external connection electrode 6. Then, a through hole 5 having a taper angle of about 35 ° is formed in the polyimide film portion by chemical etching, and an internal connection bump 4 having a height substantially equal to the thickness of the polyimide film is formed by electrolytic copper plating. Get.

そして、得られたフレキシブルプリント基板２０における（絶縁性フィルム１の）他の面９側に、別途用意したデバイスチップ３を載置し、デバイスチップ３と内部接続用バンプ４とを、金線によって電気的に接続（ワイヤボンディング）する。その後、トランスファー成形機を使用して、フレキシブルプリント基板２０における（絶縁性フィルム１の）他の面９側に、エポキシ樹脂（絶縁材２）の絶縁被覆（モールディング）を施せば、表面実装パッケージ１０が得られる。   And the device chip 3 prepared separately is mounted in the other surface 9 side (of the insulating film 1) in the obtained flexible printed circuit board 20, and the device chip 3 and the bump 4 for internal connection are attached with a gold wire. Electrical connection (wire bonding). Thereafter, by using a transfer molding machine to apply an insulating coating (molding) of epoxy resin (insulating material 2) to the other surface 9 side (of the insulating film 1) of the flexible printed circuit board 20, the surface mounting package 10 Is obtained.

本発明の表面実装パッケージは、集積回路素子や、抵抗、コンデンサ等の単体素子を含む、あらゆるデバイスチップを実装するためのパッケージとして、利用可能である。   The surface mount package of the present invention can be used as a package for mounting any device chip including an integrated circuit element and single elements such as a resistor and a capacitor.

本発明の表面実装パッケージの一の実施形態を示す図であり、図５におけるＢＢ断面を表した図である。It is a figure which shows one Embodiment of the surface mount package of this invention, and is the figure showing BB cross section in FIG. 本発明の表面実装パッケージの一の実施形態を示す図であり、図５におけるＢＢ断面のうち、貫通孔近傍を拡大して表した図である。It is a figure which shows one Embodiment of the surface mount package of this invention, and is the figure which expanded and represented the through-hole vicinity among BB cross sections in FIG. 本発明に用いられるフレキシブルプリント基板の一の実施形態を示す図であり、絶縁性フィルムの一の面側を表した斜視図である。It is a figure which shows one Embodiment of the flexible printed circuit board used for this invention, and is the perspective view showing the one surface side of the insulating film. 本発明に用いられるフレキシブルプリント基板の一の実施形態を示す図であり、絶縁性フィルムの他の面側を表した斜視図である。It is a figure which shows one Embodiment of the flexible printed circuit board used for this invention, and is the perspective view showing the other surface side of the insulating film. 本発明の表面実装パッケージを示す斜視図である。It is a perspective view which shows the surface mount package of this invention. 従来の表面実装パッケージを示す図であり、図７におけるＡＡ断面を表す図である。It is a figure which shows the conventional surface mount package, and is a figure showing the AA cross section in FIG. 従来の表面実装パッケージを示す斜視図である。It is a perspective view which shows the conventional surface mount package.

符号の説明Explanation of symbols

１…絶縁性フィルム、２…絶縁材、３…デバイスチップ、４…内部接続用バンプ、４ａ…（内部接続用バンプの）頂部、５…貫通孔、６…外部接続用電極、７…導通手段、８…一の面、９…他の面、１０…表面実装パッケージ、１１…（貫通孔の）壁面、２０…フレキシブルプリント基板。 DESCRIPTION OF SYMBOLS 1 ... Insulating film, 2 ... Insulating material, 3 ... Device chip, 4 ... Internal connection bump, 4a ... Top part (of internal connection bump), 5 ... Through-hole, 6 ... External connection electrode, 7 ... Conducting means , 8 ... one surface, 9 ... other surface, 10 ... surface mount package, 11 ... wall surface (through hole), 20 ... flexible printed circuit board.

Claims (2)

フレキシブルプリント基板にデバイスチップが載置され、絶縁被覆されている表面実装パッケージであって、
前記フレキシブルプリント基板は、貫通孔が開けられた絶縁性フィルムと、その絶縁性フィルムの一の面において前記貫通孔を塞ぐように形成された平坦な外部接続用電極と、を有し、
前記貫通孔は、前記絶縁性フィルムの一の面側から他の面側に向けて徐々に広がるテーパー形状を呈するとともに、その貫通孔に、前記外部接続用電極と電気的に接続される内部接続用バンプが形成され、
更に、前記デバイスチップは、前記絶縁性フィルムの他の面に載置され、前記外部接続用電極と電気的に接続されている表面実装パッケージ。 A surface mounting package in which a device chip is mounted on a flexible printed circuit board and is insulation-coated,
The flexible printed circuit board has an insulating film with a through-hole formed therein, and a flat external connection electrode formed so as to close the through-hole on one surface of the insulating film,
The through hole exhibits a tapered shape that gradually spreads from one surface side to the other surface side of the insulating film, and the internal connection electrically connected to the external connection electrode in the through hole Bumps are formed,
Furthermore, the device chip is mounted on the other surface of the insulating film and is electrically connected to the external connection electrode. デバイスチップが載置された前記絶縁性フィルムの他の面が、圧力成形法によって絶縁被覆をされている請求項１に記載の表面実装パッケージ。   The surface mount package according to claim 1, wherein the other surface of the insulating film on which the device chip is placed is covered with an insulating coating by a pressure forming method.
JP2005040612A 2005-02-17 2005-02-17 Surface mounted package Withdrawn JP2006228953A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2005040612A JP2006228953A (en) 2005-02-17 2005-02-17 Surface mounted package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2005040612A JP2006228953A (en) 2005-02-17 2005-02-17 Surface mounted package

Publications (1)

Publication Number Publication Date
JP2006228953A true JP2006228953A (en) 2006-08-31

Family

ID=36990051

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2005040612A Withdrawn JP2006228953A (en) 2005-02-17 2005-02-17 Surface mounted package

Country Status (1)

Country Link
JP (1) JP2006228953A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010147189A (en) * 2008-12-17 2010-07-01 Panasonic Electric Works Co Ltd Light-emitting device
JP2010219128A (en) * 2009-03-13 2010-09-30 Nec Tokin Corp Solid electrolytic capacitor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010147189A (en) * 2008-12-17 2010-07-01 Panasonic Electric Works Co Ltd Light-emitting device
JP2010219128A (en) * 2009-03-13 2010-09-30 Nec Tokin Corp Solid electrolytic capacitor

Similar Documents

Publication Publication Date Title
US7394028B2 (en) Flexible circuit substrate for flip-chip-on-flex applications
US7193329B2 (en) Semiconductor device
CN101091250A (en) Semiconductor component and installation structure
JP5017872B2 (en) Semiconductor device and manufacturing method thereof
JP2006294976A (en) Semiconductor device and its manufacturing method
JP2007005357A (en) Method of manufacturing semiconductor device
JP2006228953A (en) Surface mounted package
JPH0425038A (en) Semiconductor device and manufacture of the same and electronic circuit utilizing the semiconductor device
US8786108B2 (en) Package structure
JP4952365B2 (en) Electronic component mounting structure on a double-sided mounting circuit board, semiconductor device, and manufacturing method of double-sided mounting semiconductor device
JP2005183868A (en) Semiconductor device and its packaging structure
JP5442192B2 (en) Device mounting substrate, semiconductor module, and device mounting substrate manufacturing method
JP2004079710A (en) Semiconductor device and its manufacturing method, circuit board as well as electronic apparatus
JP2007287800A (en) Wiring, package parts for semiconductor device using same, and wiring board
KR20030011433A (en) Manufacturing method for hidden laser via hole of multi-layered printed circuit board
JP2006339276A (en) Substrate for connection and manufacturing method thereof
US7122909B2 (en) Wiring board, stacked wiring board and method of manufacturing the same, semiconductor device and method of manufacturing the same, circuit board, and electronic instrument
JP2000002746A (en) Probe structure
KR101351188B1 (en) Ball grid array package printed-circuit board and manufacturing method thereof
WO2019194200A1 (en) Component-embedded substrate
KR100426493B1 (en) Substrate for manufacturing semiconductor package and method for manufacturing semiconductor package using the same
JP2001156097A (en) Electronic circuit, lsi chip mounting structure and method of manufacturing semiconductor device
JP5005636B2 (en) Wiring board and method for manufacturing wiring board
JP2015159160A (en) wiring board and connection structure
JP2002057243A (en) Semiconductor-chip mounting board, manufacturing method therefor, and semiconductor device

Legal Events

Date Code Title Description
A300 Withdrawal of application because of no request for examination

Free format text: JAPANESE INTERMEDIATE CODE: A300

Effective date: 20080513