WO2019194200A1 - Component-embedded substrate - Google Patents

Component-embedded substrate Download PDF

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Publication number
WO2019194200A1
WO2019194200A1 PCT/JP2019/014692 JP2019014692W WO2019194200A1 WO 2019194200 A1 WO2019194200 A1 WO 2019194200A1 JP 2019014692 W JP2019014692 W JP 2019014692W WO 2019194200 A1 WO2019194200 A1 WO 2019194200A1
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WO
WIPO (PCT)
Prior art keywords
main surface
semiconductor element
component
wiring pattern
cavity
Prior art date
Application number
PCT/JP2019/014692
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French (fr)
Japanese (ja)
Inventor
杉山　裕一
宮崎　政志
猿渡　達郎
Original Assignee
太陽誘電株式会社
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Application filed by 太陽誘電株式会社 filed Critical 太陽誘電株式会社
Priority to JP2020512271A priority Critical patent/JPWO2019194200A1/en
Publication of WO2019194200A1 publication Critical patent/WO2019194200A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits

Definitions

  • the present invention relates to a component-embedded substrate in which a semiconductor element is embedded in a metal core base material.
  • the power circuit easily generates heat because it consumes a large current, and it is difficult to reduce the size because it requires coil components that are larger in size than passive components such as capacitors and resistors.
  • Using a 3D mounting technology such as a component-embedded board to incorporate components other than the coil into the substrate is also effective for the power supply module, but because the heat density increases compared to the surface-mounting substrate, the built-in components are generated. It is required to transfer heat efficiently. For this reason, in recent years, a component-embedded substrate having a metal core base material has been widely used (see, for example, Patent Document 1).
  • a component-embedded substrate having a metal core base material it is required to further improve the heat dissipation efficiency of the built-in component and shorten the wiring length between the electronic component mounted on the mounting surface.
  • an object of the present invention is to provide a component-embedded substrate capable of improving heat dissipation efficiency and shortening the wiring length between a mounting surface and a built-in component.
  • a component-embedded substrate includes a metal core base material, a semiconductor element, a first resin layer, a multilayer wiring layer, and an interlayer connection portion.
  • the core base material penetrates between a first main surface, a second main surface opposite to the first main surface, and the first main surface and the second main surface. And a cavity.
  • the semiconductor element has a thickness smaller than that of the core substrate, is accommodated in the cavity, and is located on the first main surface side with respect to the center of the core substrate.
  • the first resin layer fills the cavity and seals the semiconductor element.
  • the multilayer wiring layer includes a first wiring pattern disposed on the first main surface side and a second wiring pattern disposed on the second main surface side.
  • the interlayer connection portion includes a first via formed at a first height between the first wiring pattern and the semiconductor element, and a gap between the second wiring pattern and the semiconductor element. And a second via formed at a second height greater than the first height.
  • the wiring length with the first wiring pattern can be made relatively short.
  • the second via that communicates with the second wiring pattern can be formed with a larger diameter than the first via, the second via can be made to function as a thermal via. It is possible to improve the heat dissipation efficiency of the element.
  • the second via may include a surface conductor layer that electrically connects the second wiring pattern and the semiconductor element, and a second resin layer filled in the surface conductor layer. Good.
  • the inside of the surface conductor layer may be filled with a conductive paste or Cu plating.
  • the second via may be formed with a larger diameter than the first via.
  • the cavity may have an inner wall surface including an annular protrusion protruding inward, and the semiconductor element may be disposed between the annular protrusion and the first main surface.
  • the component-embedded substrate may further include an electronic component mounted on the first main surface side and electrically connected to the semiconductor element.
  • FIG. 1 is an external perspective view of a circuit module including a component built-in substrate according to an embodiment of the present invention. It is a schematic sectional side view of the principal part of the said circuit module. It is a principal part schematic sectional side view of the said component built-in board
  • FIG. 1 is an external perspective view of a circuit module 100 including a component built-in substrate 10 according to an embodiment of the present invention
  • FIG. 2 is a schematic side sectional view of a main part of the circuit module 100
  • FIG. It is a principal part schematic sectional side view.
  • an X axis, a Y axis, and a Z axis indicate three axial directions orthogonal to each other
  • FIGS. 2 and 3 are cross-sectional views as viewed from the Y axis direction.
  • the circuit module 100 includes a component built-in substrate 10, a plurality of electronic components 21 mounted on the surface (component mounting surface) of the component built-in substrate 10, and built-in components housed in the component built-in substrate 10.
  • the semiconductor element 22 and the mold part 30 that covers the electronic component 21 are provided.
  • circuit module 100 a predetermined electronic circuit including the electronic component 21 and the semiconductor element 22 is three-dimensionally constructed.
  • the circuit module 100 is configured to be capable of being soldered and mounted on a mounting substrate (motherboard) (not shown) via an external connection terminal 31 provided on the back surface (terminal surface) of the component built-in substrate 10.
  • the component-embedded substrate 10 includes a metal core base 110, an exterior part 120, a semiconductor element 22, a multilayer wiring layer 130 (first wiring pattern 131 and second wiring pattern 132), 1 is a substrate module having one resin layer 140 and an interlayer connection 150 (first via 151 and second via 152).
  • the core substrate 110 is a metal plate having a predetermined thickness (for example, 35 to 500 ⁇ m) such as copper, a copper alloy (a metal mainly composed of copper), or an iron alloy such as stainless steel (a metal mainly composed of iron). Composed.
  • the planar shape of the core substrate 110 is rectangular, and has a first main surface 111, a second main surface 112, and four side surfaces 113. Inside the core substrate 110, a plurality of cavities including a first cavity C1 that accommodates the semiconductor element 22 and a second cavity C2 that accommodates a through hole V for interlayer connection are formed.
  • the exterior portion 120 has a stacked structure of a first insulating layer 121, a second insulating layer 122, and a third insulating layer 123.
  • the first insulating layer 121 covers the first main surface 111 of the core base material 110
  • the second insulating layer 122 covers the second main surface 112 of the core base material 110.
  • the third insulating layer 123 covers the side surface 113 of the core substrate 110.
  • the first insulating layer 121, the second insulating layer 122, and the third insulating layer 123 are typically made of the same synthetic resin material.
  • epoxy resin epoxy resin
  • polyimide It is composed of a resin or a composite material in which a filler such as glass fiber is mixed.
  • the first wiring pattern 131 is arranged on the first main surface 111 side, and the second wiring pattern 132 is arranged on the second main surface 12 side. That is, the first wiring pattern 131 is provided on the first main surface 111 of the core substrate 110 via the first insulating layer 121, and the second wiring pattern 132 is interposed via the second insulating layer 122. Provided on the second main surface 112 of the core substrate 110.
  • the first wiring pattern 131 and the second wiring pattern 132 are typically made of copper foil, and are formed in a desired shape.
  • the wiring pattern is composed of pads or electrodes covering vias and through holes, electrodes connected to electronic components, wiring integrated with the pads or electrodes, and the like.
  • a part of the first wiring pattern 131 is connected to the first main surface 111 of the core substrate 110 through a via penetrating the first insulating layer 121.
  • a part of the second wiring pattern 132 is connected to the second main surface 112 of the core substrate 110 through a via penetrating the second insulating layer 122.
  • the connection with the core base material 110 mainly contributes to the grounding of the GND for the purpose of grounding the voltage.
  • the first wiring pattern 131 and the second wiring pattern 132 are covered with an insulating protective film such as solder resist SR1, SR2.
  • the solder resists SR1 and SR2 have openings at appropriate positions, through which the first wiring pattern 131 is connected to the terminal portion of the electronic component 21 and the second wiring pattern 132 is connected to the external connection terminal 31. Connected to each.
  • the substrate surface on which the first wiring pattern 131 is formed is configured as a mounting surface on which the electronic component 21 is surface-mounted.
  • the external connection terminal 31 is made of a brazing material such as solder, for example.
  • the semiconductor element 22 accommodated in the first cavity portion C1 has a thickness that is half or less that of the core substrate 110.
  • the semiconductor element 22 is typically an IC component or a discrete component.
  • a power transistor through which a large current flows is used.
  • the power transistor include a BiP transistor made of Si, a MOSFET, an IGBT, and the like, and a transistor made of SiC, GaN, or the like.
  • the electronic component 21 mounted on the mounting surface an electronic component that is typically larger than the semiconductor element 22 such as a capacitor component or a coil component is used.
  • the semiconductor element 22 is housed in the first cavity portion C1 face-up with its active surface facing the first main surface 111 side.
  • the semiconductor element 22 is located closer to the first main surface 111 than the center of the core substrate 110.
  • the surface or electrode of the semiconductor element 22 is disposed on the same plane as the first main surface 111 of the core substrate 110.
  • the first resin layer 140 is made of an electrically insulating resin material that fills the first cavity portion C1 and the second cavity portion C2 and seals the semiconductor element 22.
  • the first resin layer 140 is typically made of an insulating material containing the same kind or the same organic material as the first to third insulating layers 121 to 123. Thereby, since affinity with the exterior part 120 is improved, the adhesiveness of the 1st resin layer 140 with respect to the exterior part 120 increases.
  • the first resin layer 140 may contain an inorganic filler such as fiber made of glass or carbon, glass cloth, silicon oxide, aluminum oxide, calcium carbonate, etc., similarly to the constituent material of the exterior part 120.
  • the interlayer connection 150 has a first via 151 and a second via 152.
  • the first via 151 is formed between the first wiring pattern 131 and the semiconductor element 22 (active surface thereof).
  • the second via 152 is formed between the second wiring pattern 132 and the semiconductor element 22 (inactive surface thereof).
  • the semiconductor element 22 is located closer to the first main surface 111 side than the center of the core base 110 in the first cavity C1, and in this embodiment, the surface or electrode of the semiconductor element 22 is the first surface.
  • the first main surface 111 is located substantially on the same plane.
  • the first via 151 is connected between the first wiring pattern 131 and the active surface of the semiconductor element 22 via the first insulating layer 121, and the second via 152 includes the second insulating layer 122 and the second insulating layer 122.
  • the second wiring pattern 132 is connected to the non-active surface (back surface electrode) of the semiconductor element 22 through the first resin layer 140.
  • the height (or depth) of the first via 151 is increased. Is smaller (lower) than the height (or depth) of the second via 152.
  • the maximum via diameter tends to increase as the via height (or depth) increases. Therefore, in the present embodiment, the first via 151 can be formed with a finer pitch than the second via 152, and the second via 152 can be formed more than the first via. In addition, a low-resistance via can be formed. Therefore, it is advantageous when a large current flows from the semiconductor element 22 to the second wiring pattern 132 through the second via 152 or when the second via 152 functions as a thermal via for heat dissipation of the semiconductor element 22. It becomes. Further, when the second vias 152 are all formed of a conductor, the peripheral resin and the insulating layer constituting the substrate have a larger coefficient of thermal expansion ( ⁇ ), and thus warp the substrate.
  • ⁇ coefficient of thermal expansion
  • the second via 152 includes a surface conductor layer 521 that electrically connects the second wiring pattern 132 and the semiconductor element 22, and a second conductor 152 that is filled in the surface conductor layer 521. 2 resin layers 522.
  • the surface conductor layer 521 is configured by conductor plating such as copper plating formed on the inner wall surface of the hole formed in the second insulating layer 122 and the first resin layer 140 by a laser processing method or the like.
  • the second resin layer 522 is typically made of a resin material that forms the second insulating layer 122 and is formed simultaneously with the formation of the second insulating layer 122.
  • the number of the second vias 152 is not particularly limited and may be a single number, but typically a plurality of the second vias 152 are provided. All the second vias 152 are not limited to the case where they are connected between the semiconductor element 22 and the second wiring pattern 132, and part of the second vias 152 are formed between the semiconductor element 22 and the core substrate 110. It may be connected between appropriate wiring patterns that are electrically connected to each other.
  • the first via 151 and the second via 152 are provided on the front surface (active surface) and the back surface (inactive surface) of the semiconductor element 22, respectively. Therefore, the conductive path and the heat transfer path are shortened by lowering the resistance value and the thermal resistance as compared with the case where the via is connected to only one side of the component. Moreover, it becomes easy to provide a thermal via, and the heat dissipation of the inactive surface of the semiconductor element 22 can be improved.
  • the semiconductor element 22 is located closer to the first main surface 111 side than the center of the core base material 110 in the first cavity portion C1, fine signal wiring is formed by the first via 151.
  • a wiring and a heat radiation line through which a large current flows can be formed by the second via 152.
  • the substrate can be made smaller and thinner by making the wiring density different between the front and back surfaces of the semiconductor element 22 or by separating the heat radiation line and the fine signal wiring.
  • the second via 152 is constituted by the surface conductor layer 521 and the second resin layer 522, the component-embedded substrate is compared with the case where the second via 152 is filled with a conductor such as metal.
  • a predetermined stress relaxation function can be provided with respect to an external force such as a bending stress acting on 10. Therefore, even when the second via 152 is formed relatively high (or deep), desired connection reliability can be ensured.
  • the second via 152 is filled with a conductor such as a metal, the larger the via height (depth), the more the via is bent. Can keep.
  • the first cavity portion C1 and the second cavity portion C2 are formed by a wet etching method.
  • the cavity portions C1 and C2 are formed by half-etching predetermined regions of the first main surface 111 and the second main surface 112 of the core layer 110, respectively.
  • an annular protrusion (annular protrusion) Cp that protrudes inward of the cavities C1 and C2 may be formed on the inner wall surface corresponding to the confluence of both half-etched regions (see FIG. 3). ).
  • the semiconductor element 22 is located closer to the first main surface 111 side than the center of the core substrate 110 in the first cavity portion C1.
  • the semiconductor element 22 is preferably arranged at a position that does not face the tip of the annular protrusion Cp in a direction orthogonal to the thickness direction (Z-axis direction) of the core layer 110, and typically the annular protrusion Cp and the first Between the first main surface 111 and the first main surface 111.
  • the electronic component 21 is a single product, and the occupation ratio of the area of the core base material surface is from 50% to 100% of the component-embedded substrate. In some cases, the element may have an occupation ratio as close to 50% to 100%. In that case, the connection between the electronic component 21 and the surface of the core substrate 110 leads to a certain degree of reliability due to the rigidity of the electronic component 21 and the mold part 30. On the other hand, the member contributing to this rigidity is not provided on the back surface side of the core substrate 110. Therefore, a large warping force is applied to the back surface side of the core substrate 110.
  • filling the via 152 with the second resin layer 522 generates flexibility in the via 152 itself, and the second via 152 and the second wiring pattern 132 are not connected. Contact failure can be suppressed.
  • the first via 151 is formed to be thin or shallow, the following merit with the electronic component 21 occurs.
  • the electronic component 21 is a capacitor, noise absorption is steep, and malfunction of the semiconductor element 22 can be prevented.
  • the electronic component 21 is a solenoid, it is less likely to pick up noise between the solenoid and the semiconductor element.
  • the current from the power transistor, which is a semiconductor element, to the electronic component has a short path and a small resistance value, which is effective as signal processing. Considering the flow of current, the current flows from the external terminal 31 on the right side to the electronic component through the through hole V in FIG. 2, and then flows from the electronic component 21 to the vertical transistor 22 through the first via 151.
  • the transistor 22 Flows to the left external terminal 31 through the second via 152. Or vice versa, current flows.
  • the transistor 22 generates heat because it flows in the thickness direction of the multilayer substrate, and the second via 152 is deep, and its diameter is larger than that of the first via. Therefore, the transistor 22 greatly contributes as a thermal via.
  • the number of wiring layers (wiring patterns) formed on both main surfaces of the component-embedded substrate 10 is one, but the present invention is not limited to this.
  • a multilayer wiring structure may be employed.
  • a wiring layer is further formed on the wiring patterns 131 and 132 via an interlayer insulating film.
  • the core substrate 110 includes the first cavity portion C1 that houses the semiconductor element 22 .
  • the number of cavity portions that house the built-in components is not limited to one, and a plurality of There may be.
  • the housed component to be accommodated is not limited to a semiconductor element, and may be a passive component such as a capacitor or a resistance element.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

[Problem] To provide a component-embedded substrate that improves heat-dissipation efficiency and makes it possible to shorten the length of wiring between a mounting surface and an embedded component. [Solution] A component-embedded substrate according to an embodiment of the present invention comprises a metal core material, a semiconductor element, a first resin layer, a multilayer wiring layer, and an interlayer connection part. The semiconductor element is thinner than the core material, is housed in a cavity, and is positioned further toward a first main surface side than the center of the core material. The first resin layer fills the cavity, and seals the semiconductor element. The multilayer wiring layer has a first wiring pattern that is disposed on the first main surface side, and a second wiring pattern that is disposed on a second main surface side. The interlayer connection part has a first via that is formed between the first wiring pattern and the semiconductor element and has a first height, and a second via that is formed between the second wiring pattern and the semiconductor element and has a second height greater than the first height.

Description

部品内蔵基板Component built-in board
　本発明は、金属製のコア基材に半導体素子を内蔵した部品内蔵基板に関する。 The present invention relates to a component-embedded substrate in which a semiconductor element is embedded in a metal core base material.
　電子機器に対するニーズは情報通信産業の拡大に伴い多様化し、開発や量産開始の早期化に対するニーズも高まっている。特にスマートフォンでは、電話としての基本機能に加えて、インターネット、電子メール、カメラ、ＧＰＳ、無線ＬＡＮ、ワンセグテレビなどの多様な機能が追加され、機種も増加している。高機能なスマートフォンでは、電池容量の向上が課題となっており、メインボードの高密度実装化、小型・薄型化、及び機能ブロックのモジュール化が進められている。 Demand for electronic devices has become diversified as the information and telecommunications industry expands, and needs for early development and mass production have also increased. In particular, in smartphones, in addition to basic functions as a telephone, various functions such as the Internet, e-mail, camera, GPS, wireless LAN, and 1Seg TV are added, and the number of models is increasing. In high-performance smartphones, improving battery capacity is an issue, and high-density mounting of main boards, miniaturization and thinning, and modularization of functional blocks are being promoted.
　一方、電源回路は、大電流を消費するため発熱しやすく、また、コンデンサや抵抗といった受動部品と比べてサイズが大きいコイル部品が必要なため、小型化が難しい。部品内蔵基板等の三次元実装技術を用いて、コイル以外の部品を基板に内蔵することは電源モジュールにも有効であるが、表層実装基板と比べて熱密度が増大するため、内蔵部品が発する熱を効率よく伝達することが求められる。このため近年では、金属製のコア基材を有する部品内蔵基板が広く用いられている（例えば特許文献１参照）。 On the other hand, the power circuit easily generates heat because it consumes a large current, and it is difficult to reduce the size because it requires coil components that are larger in size than passive components such as capacitors and resistors. Using a 3D mounting technology such as a component-embedded board to incorporate components other than the coil into the substrate is also effective for the power supply module, but because the heat density increases compared to the surface-mounting substrate, the built-in components are generated. It is required to transfer heat efficiently. For this reason, in recent years, a component-embedded substrate having a metal core base material has been widely used (see, for example, Patent Document 1).
特開２０１４－３８９３３号公報JP 2014-38933 A
　金属製のコア基材を有する部品内蔵基板においては、内蔵部品の放熱効率の更なる向上と、実装面に搭載される電子部品との間の配線長の短縮が求められる。 In a component-embedded substrate having a metal core base material, it is required to further improve the heat dissipation efficiency of the built-in component and shorten the wiring length between the electronic component mounted on the mounting surface.
　以上のような事情に鑑み、本発明の目的は、放熱効率の向上と、実装面と内蔵部品との間の配線長の短縮を実現することができる部品内蔵基板を提供することにある。 In view of the circumstances as described above, an object of the present invention is to provide a component-embedded substrate capable of improving heat dissipation efficiency and shortening the wiring length between a mounting surface and a built-in component.
　上記目的を達成するため、本発明の一形態に係る部品内蔵基板は、金属製のコア基材と、半導体素子と、第１の樹脂層と、多層配線層と、層間接続部とを具備する。
　前記コア基材は、第１の主面と、前記第１の主面とは反対側の第２の主面と、前記第１の主面と前記第２の主面との間を貫通するキャビティとを有する。
　前記半導体素子は、前記コア基材よりも小さい厚みを有し、前記キャビティに収容され、前記コア基材の中心よりも前記第１の主面側に位置する。
　前記第１の樹脂層は、前記キャビティに充填され、前記半導体素子を封止する。
　前記多層配線層は、前記第１の主面側に配置された第１の配線パターンと、前記第２の主面側に配置された第２の配線パターンとを有する。
　前記層間接続部は、前記第１の配線パターンと前記半導体素子との間に第１の高さで形成された第１のビアと、前記第２の配線パターンと前記半導体素子との間に前記第１の高さよりも大きい第２の高さで形成された第２のビアとを有する。 In order to achieve the above object, a component-embedded substrate according to an aspect of the present invention includes a metal core base material, a semiconductor element, a first resin layer, a multilayer wiring layer, and an interlayer connection portion. .
The core base material penetrates between a first main surface, a second main surface opposite to the first main surface, and the first main surface and the second main surface. And a cavity.
The semiconductor element has a thickness smaller than that of the core substrate, is accommodated in the cavity, and is located on the first main surface side with respect to the center of the core substrate.
The first resin layer fills the cavity and seals the semiconductor element.
The multilayer wiring layer includes a first wiring pattern disposed on the first main surface side and a second wiring pattern disposed on the second main surface side.
The interlayer connection portion includes a first via formed at a first height between the first wiring pattern and the semiconductor element, and a gap between the second wiring pattern and the semiconductor element. And a second via formed at a second height greater than the first height.
　上記部品内蔵基板においては、半導体素子がコア基材の中心よりも第１の主面側に位置しているため、第１の配線パターンとの配線長を比較的短くすることができる。また、第２の配線パターンと連絡する第２のビアを第１のビアよりも大きな径で形成することができるため、当該第２のビアをサーマルビアとして機能させることが可能となり、これにより半導体素子の放熱効率の向上を図ることができる。 In the component built-in substrate, since the semiconductor element is located on the first main surface side with respect to the center of the core base material, the wiring length with the first wiring pattern can be made relatively short. In addition, since the second via that communicates with the second wiring pattern can be formed with a larger diameter than the first via, the second via can be made to function as a thermal via. It is possible to improve the heat dissipation efficiency of the element.
　前記第２のビアは、前記第２の配線パターンと前記半導体素子との間を電気的に接続する表面導体層と、前記表面導体層の内部に充填された第２の樹脂層とを含んでもよい。
　前記第２の樹脂層の代わりに、導電性ペーストまたはＣｕめっきで前記表面導体層の内部が充填されても良い。 The second via may include a surface conductor layer that electrically connects the second wiring pattern and the semiconductor element, and a second resin layer filled in the surface conductor layer. Good.
Instead of the second resin layer, the inside of the surface conductor layer may be filled with a conductive paste or Cu plating.
　前記第２のビアは、前記第１のビアよりも大きな径で形成されてもよい。 The second via may be formed with a larger diameter than the first via.
　前記キャビティは、内方に向かって突出する環状突起部を含む内壁面を有し、前記半導体素子は、前記環状突起部と前記第１の主面との間に配置されてもよい。 The cavity may have an inner wall surface including an annular protrusion protruding inward, and the semiconductor element may be disposed between the annular protrusion and the first main surface.
　前記部品内蔵基板は、前記第１の主面側に搭載され、前記半導体素子と電気的に接続される電子部品をさらに具備してもよい。 The component-embedded substrate may further include an electronic component mounted on the first main surface side and electrically connected to the semiconductor element.
　以上述べたように、本発明によれば、放熱効率の向上と、実装面と内蔵部品との間の配線長の短縮を実現することができる。 As described above, according to the present invention, it is possible to improve the heat dissipation efficiency and shorten the wiring length between the mounting surface and the built-in component.
本発明の一実施形態に係る部品内蔵基板を備えた回路モジュールの外観斜視図である。1 is an external perspective view of a circuit module including a component built-in substrate according to an embodiment of the present invention. 上記回路モジュールの要部の概略側断面図である。It is a schematic sectional side view of the principal part of the said circuit module. 上記部品内蔵基板の要部概略側断面図である。It is a principal part schematic sectional side view of the said component built-in board | substrate.
　以下、図面を参照しながら、本発明の実施形態を説明する。 Hereinafter, embodiments of the present invention will be described with reference to the drawings.
　図１は、本発明の一実施形態に係る部品内蔵基板１０を備えた回路モジュール１００の外観斜視図、図２は回路モジュール１００の要部の概略側断面図、図３は部品内蔵基板１０の要部概略側断面図である。
　なお、各図においてＸ軸、Ｙ軸及びＺ軸は、相互に直交する３軸方向を示しており、図２及び図３はそれぞれＹ軸方向から見た断面図である。 1 is an external perspective view of a circuit module 100 including a component built-in substrate 10 according to an embodiment of the present invention, FIG. 2 is a schematic side sectional view of a main part of the circuit module 100, and FIG. It is a principal part schematic sectional side view.
In each figure, an X axis, a Y axis, and a Z axis indicate three axial directions orthogonal to each other, and FIGS. 2 and 3 are cross-sectional views as viewed from the Y axis direction.
　本実施形態の回路モジュール１００は、部品内蔵基板１０と、部品内蔵基板１０の表面（部品実装面）に実装された複数の電子部品２１と、部品内蔵基板１０の内部に収容された内蔵部品としての半導体素子２２と、電子部品２１を覆うモールド部３０とを備える。 The circuit module 100 according to the present embodiment includes a component built-in substrate 10, a plurality of electronic components 21 mounted on the surface (component mounting surface) of the component built-in substrate 10, and built-in components housed in the component built-in substrate 10. The semiconductor element 22 and the mold part 30 that covers the electronic component 21 are provided.
　回路モジュール１００においては、電子部品２１と半導体素子２２を含む所定の電子回路が三次元的に構築されている。回路モジュール１００は、部品内蔵基板１０の裏面（端子面）に設けられた外部接続端子３１を介して、図示しない実装基板（マザーボード）上に半田付け実装することが可能に構成される。 In the circuit module 100, a predetermined electronic circuit including the electronic component 21 and the semiconductor element 22 is three-dimensionally constructed. The circuit module 100 is configured to be capable of being soldered and mounted on a mounting substrate (motherboard) (not shown) via an external connection terminal 31 provided on the back surface (terminal surface) of the component built-in substrate 10.
　続いて、部品内蔵基板１０の詳細について説明する。 Subsequently, details of the component-embedded substrate 10 will be described.
　図２に示すように、部品内蔵基板１０は、金属製のコア基材１１０、外装部１２０、半導体素子２２、多層配線層１３０（第１の配線パターン１３１及び第２の配線パターン１３２）、第１の樹脂層１４０及び層間接続部１５０（第１のビア１５１及び第２のビア１５２）を有する基板モジュールである。 As shown in FIG. 2, the component-embedded substrate 10 includes a metal core base 110, an exterior part 120, a semiconductor element 22, a multilayer wiring layer 130 (first wiring pattern 131 and second wiring pattern 132), 1 is a substrate module having one resin layer 140 and an interlayer connection 150 (first via 151 and second via 152).
　コア基材１１０は、銅や銅合金（銅を主材料とした金属）、ステンレス鋼等の鉄合金（鉄を主材料とした金属）などの所定厚み（例えば、３５～５００μｍ）の金属板で構成される。コア基材１１０の平面形状は矩形であり、第１の主面１１１と、第２の主面１１２と、４つの側面１１３とを有する。コア基材１１０の内側には、半導体素子２２を収容する第１のキャビティ部Ｃ１と層間接続用のスルーホールＶを収容する第２のキャビティ部Ｃ２を含む複数のキャビティが形成されている。 The core substrate 110 is a metal plate having a predetermined thickness (for example, 35 to 500 μm) such as copper, a copper alloy (a metal mainly composed of copper), or an iron alloy such as stainless steel (a metal mainly composed of iron). Composed. The planar shape of the core substrate 110 is rectangular, and has a first main surface 111, a second main surface 112, and four side surfaces 113. Inside the core substrate 110, a plurality of cavities including a first cavity C1 that accommodates the semiconductor element 22 and a second cavity C2 that accommodates a through hole V for interlayer connection are formed.
　外装部１２０は、第１の絶縁層１２１と、第２の絶縁層１２２と、第３の絶縁層１２３との積層構造を有する。第１の絶縁層１２１は、コア基材１１０の第１の主面１１１を被覆し、第２の絶縁層１２２は、コア基材１１０の第２の主面１１２を被覆する。第３の絶縁層１２３は、コア基材１１０の側面１１３を被覆する。 The exterior portion 120 has a stacked structure of a first insulating layer 121, a second insulating layer 122, and a third insulating layer 123. The first insulating layer 121 covers the first main surface 111 of the core base material 110, and the second insulating layer 122 covers the second main surface 112 of the core base material 110. The third insulating layer 123 covers the side surface 113 of the core substrate 110.
　第１の絶縁層１２１、第２の絶縁層１２２及び第３の絶縁層１２３は、典型的には、同一の合成樹脂材料で構成され、例えば、エポキシ樹脂、ＢＴ（ビスマレイミドトリアジン）樹脂、ポリイミド樹脂、あるいはこれにガラス繊維等のフィラーが混合された複合材料で構成される。 The first insulating layer 121, the second insulating layer 122, and the third insulating layer 123 are typically made of the same synthetic resin material. For example, epoxy resin, BT (bismaleimide triazine) resin, polyimide It is composed of a resin or a composite material in which a filler such as glass fiber is mixed.
　第１の配線パターン１３１は第１の主面１１１側に配置され、第２の配線パターン１３２は第２の主面１２側に配置される。すなわち、第１の配線パターン１３１は、第１の絶縁層１２１を介してコア基材１１０の第１の主面１１１に設けられ、第２の配線パターン１３２は、第２の絶縁層１２２を介してコア基材１１０の第２の主面１１２に設けられる。 The first wiring pattern 131 is arranged on the first main surface 111 side, and the second wiring pattern 132 is arranged on the second main surface 12 side. That is, the first wiring pattern 131 is provided on the first main surface 111 of the core substrate 110 via the first insulating layer 121, and the second wiring pattern 132 is interposed via the second insulating layer 122. Provided on the second main surface 112 of the core substrate 110.
　第１の配線パターン１３１及び第２の配線パターン１３２は、典型的には銅箔で構成され、任意の形状にパターン形成される。特に、この配線パターンは、ビアやスルーホール上を覆うパッドまたは電極、電子部品と接続される電極、このパッドまたは電極と一体の配線等からなる。第１の配線パターン１３１の一部は、第１の絶縁層１２１を貫通するビアを介してコア基材１１０の第１の主面１１１に接続される。第２の配線パターン１３２の一部は、第２の絶縁層１２２を貫通するビアを介してコア基材１１０の第２の主面１１２に接続される。ここで、コア基材１１０との接続は、主にＧＮＤ接地が目的で電圧の安定等に寄与する。 The first wiring pattern 131 and the second wiring pattern 132 are typically made of copper foil, and are formed in a desired shape. In particular, the wiring pattern is composed of pads or electrodes covering vias and through holes, electrodes connected to electronic components, wiring integrated with the pads or electrodes, and the like. A part of the first wiring pattern 131 is connected to the first main surface 111 of the core substrate 110 through a via penetrating the first insulating layer 121. A part of the second wiring pattern 132 is connected to the second main surface 112 of the core substrate 110 through a via penetrating the second insulating layer 122. Here, the connection with the core base material 110 mainly contributes to the grounding of the GND for the purpose of grounding the voltage.
　第１の配線パターン１３１及び第２の配線パターン１３２は、ソルダレジストＳＲ１、ＳＲ２等の絶縁性保護膜により被覆される。ソルダレジストＳＲ１，ＳＲ２は適宜の位置に開口部を有し、これらの開口部を介して、第１の配線パターン１３１が電子部品２１の端子部に、第２の配線パターン１３２が外部接続端子３１にそれぞれ接続される。第１の配線パターン１３１が形成される基板表面は、電子部品２１が表面実装される実装面として構成される。外部接続端子３１は、例えば、半田などのロウ材からなる。 The first wiring pattern 131 and the second wiring pattern 132 are covered with an insulating protective film such as solder resist SR1, SR2. The solder resists SR1 and SR2 have openings at appropriate positions, through which the first wiring pattern 131 is connected to the terminal portion of the electronic component 21 and the second wiring pattern 132 is connected to the external connection terminal 31. Connected to each. The substrate surface on which the first wiring pattern 131 is formed is configured as a mounting surface on which the electronic component 21 is surface-mounted. The external connection terminal 31 is made of a brazing material such as solder, for example.
　第１のキャビティ部Ｃ１に収容される半導体素子２２は、コア基材１１０の半分以下の厚みを有する。半導体素子２２は、典型的には、ＩＣ部品やディスクリート部品が用いられ、本実施形態では、大電流が流れるパワートランジスタが用いられる。パワートランジスタとしては、ＳｉからなるＢｉＰトランジスタ、ＭＯＳＦＥＴ、ＩＧＢＴなど、また、ＳｉＣやＧａＮなどからなるトランジスタが挙げられる。実装面に搭載される電子部品２１としては、コンデンサ部品やコイル部品など、典型的には半導体素子２２よりも大型の電子部品が用いられる。 The semiconductor element 22 accommodated in the first cavity portion C1 has a thickness that is half or less that of the core substrate 110. The semiconductor element 22 is typically an IC component or a discrete component. In this embodiment, a power transistor through which a large current flows is used. Examples of the power transistor include a BiP transistor made of Si, a MOSFET, an IGBT, and the like, and a transistor made of SiC, GaN, or the like. As the electronic component 21 mounted on the mounting surface, an electronic component that is typically larger than the semiconductor element 22 such as a capacitor component or a coil component is used.
　半導体素子２２は、フェイスアップで、その能動面を第１の主面１１１側に向けて第１のキャビティ部Ｃ１に収容される。半導体素子２２は、コア基材１１０の中心よりも第１の主面１１１側に位置する。本実施形態において半導体素子２２の表面または電極は、コア基材１１０の第１の主面１１１と同一平面上に配置される。 The semiconductor element 22 is housed in the first cavity portion C1 face-up with its active surface facing the first main surface 111 side. The semiconductor element 22 is located closer to the first main surface 111 than the center of the core substrate 110. In the present embodiment, the surface or electrode of the semiconductor element 22 is disposed on the same plane as the first main surface 111 of the core substrate 110.
　第１の樹脂層１４０は、第１のキャビティ部Ｃ１及び第２のキャビティ部Ｃ２の内部に充填され、半導体素子２２を封止する電気絶縁性の樹脂材料で構成される。第１の樹脂層１４０は、典型的には、第１～第３の絶縁層１２１～１２３と同種の又は同一の有機材料を含む絶縁材料で構成される。これにより、外装部１２０との親和性が高められるため、外装部１２０に対する第１の樹脂層１４０の密着性が高まる。第１の樹脂層１４０は、外装部１２０の構成材料と同様に、ガラスまたは炭素からなる繊維、ガラスクロス、シリコン酸化物、酸化アルミニウム、炭酸カルシウム等の無機フィラーを含有してもよい。 The first resin layer 140 is made of an electrically insulating resin material that fills the first cavity portion C1 and the second cavity portion C2 and seals the semiconductor element 22. The first resin layer 140 is typically made of an insulating material containing the same kind or the same organic material as the first to third insulating layers 121 to 123. Thereby, since affinity with the exterior part 120 is improved, the adhesiveness of the 1st resin layer 140 with respect to the exterior part 120 increases. The first resin layer 140 may contain an inorganic filler such as fiber made of glass or carbon, glass cloth, silicon oxide, aluminum oxide, calcium carbonate, etc., similarly to the constituent material of the exterior part 120.
　層間接続部１５０は、第１のビア１５１と、第２のビア１５２とを有する。第１のビア１５１は、第１の配線パターン１３１と半導体素子２２（の能動面）との間に形成される。第２のビア１５２は、第２の配線パターン１３２と半導体素子２２（の非能動面）との間に形成される。 The interlayer connection 150 has a first via 151 and a second via 152. The first via 151 is formed between the first wiring pattern 131 and the semiconductor element 22 (active surface thereof). The second via 152 is formed between the second wiring pattern 132 and the semiconductor element 22 (inactive surface thereof).
　半導体素子２２は上述のように第１のキャビティ部Ｃ１の内部においてコア基材１１０の中心よりも第１の主面１１１側に位置し、本実施形態では、半導体素子２２の表面または電極は第１の主面１１１と実質的に同一平面上に位置する。第１のビア１５１は、第１の絶縁層１２１を介して第１の配線パターン１３１と半導体素子２２の能動面との間に接続され、第２のビア１５２は、第２の絶縁層１２２及び第１の樹脂層１４０を介して第２の配線パターン１３２と半導体素子２２の非能動面（裏面電極）との間に接続される。第１の絶縁層１２１及び第２の絶縁層１２２は第１の主面１１１及び第２の主面１１２上に概ね同一の厚みで形成されるため、第１のビア１５１の高さ（あるいは深さ）は、第２のビア１５２の高さ（あるいは深さ）よりも小さい（低い）。 As described above, the semiconductor element 22 is located closer to the first main surface 111 side than the center of the core base 110 in the first cavity C1, and in this embodiment, the surface or electrode of the semiconductor element 22 is the first surface. The first main surface 111 is located substantially on the same plane. The first via 151 is connected between the first wiring pattern 131 and the active surface of the semiconductor element 22 via the first insulating layer 121, and the second via 152 includes the second insulating layer 122 and the second insulating layer 122. The second wiring pattern 132 is connected to the non-active surface (back surface electrode) of the semiconductor element 22 through the first resin layer 140. Since the first insulating layer 121 and the second insulating layer 122 are formed on the first main surface 111 and the second main surface 112 with substantially the same thickness, the height (or depth) of the first via 151 is increased. Is smaller (lower) than the height (or depth) of the second via 152.
　一般に、ビアの高さ（あるいは深さ）が大きくなるほど、ビアの最大径は大きくなる傾向にある。したがって本実施形態においては、第１のビア１５１にあっては、第２のビア１５２よりも微細なピッチで形成することが可能となり、第２のビア１５２にあっては、第１のビアよりも低抵抗なビアを形成することが可能となる。したがって、第２のビア１５２を介して半導体素子２２から第２の配線パターン１３２へ大電流を流す場合とか、第２のビア１５２を半導体素子２２の放熱のためのサーマルビアとして機能させる場合に有利となる。また、第２のビア１５２が全て導体で形成される場合、基板を構成する周辺の樹脂、絶縁層の方が熱膨張係数（α）の値が大きいため、基板に反りを与えてしまう。その結果、配線パターンとビアの接続部分、半導体素子とビアとの接続部に応力が加わり、コンタクト不良が生じてしまう。しかしながら、ビアの高さ（深さ）があるため、ビア自体がたわみ、αのミスマッチによるクラックを防止できる。詳しくは後述する。 Generally, the maximum via diameter tends to increase as the via height (or depth) increases. Therefore, in the present embodiment, the first via 151 can be formed with a finer pitch than the second via 152, and the second via 152 can be formed more than the first via. In addition, a low-resistance via can be formed. Therefore, it is advantageous when a large current flows from the semiconductor element 22 to the second wiring pattern 132 through the second via 152 or when the second via 152 functions as a thermal via for heat dissipation of the semiconductor element 22. It becomes. Further, when the second vias 152 are all formed of a conductor, the peripheral resin and the insulating layer constituting the substrate have a larger coefficient of thermal expansion (α), and thus warp the substrate. As a result, stress is applied to the connection portion between the wiring pattern and the via and the connection portion between the semiconductor element and the via, resulting in a contact failure. However, since there is a height (depth) of the via, the via itself bends and cracks due to α mismatch can be prevented. Details will be described later.
　図３に示すように、第２のビア１５２は、第２の配線パターン１３２と半導体素子２２との間を電気的に接続する表面導体層５２１と、表面導体層５２１の内部に充填された第２の樹脂層５２２とを含む。表面導体層５２１は、第２の絶縁層１２２及び第１の樹脂層１４０にレーザ加工法等により穿設された孔部の内壁面に形成された銅めっき等の導体めっきで構成される。第２の樹脂層５２２は、典型的には、第２の絶縁層１２２を構成する樹脂材料で構成され、第２の絶縁層１２２の形成と同時に形成される。 As shown in FIG. 3, the second via 152 includes a surface conductor layer 521 that electrically connects the second wiring pattern 132 and the semiconductor element 22, and a second conductor 152 that is filled in the surface conductor layer 521. 2 resin layers 522. The surface conductor layer 521 is configured by conductor plating such as copper plating formed on the inner wall surface of the hole formed in the second insulating layer 122 and the first resin layer 140 by a laser processing method or the like. The second resin layer 522 is typically made of a resin material that forms the second insulating layer 122 and is formed simultaneously with the formation of the second insulating layer 122.
　第２のビア１５２の数は特に限定されず、単数でもよいが、典型的には複数設けられる。すべての第２のビア１５２は、半導体素子２２と第２の配線パターン１３２との間に接続される場合に限られず、第２のビア１５２の一部が、半導体素子２２と、コア基材１１０に電気的に接続される適宜の配線パターンとの間に接続されてもよい。 The number of the second vias 152 is not particularly limited and may be a single number, but typically a plurality of the second vias 152 are provided. All the second vias 152 are not limited to the case where they are connected between the semiconductor element 22 and the second wiring pattern 132, and part of the second vias 152 are formed between the semiconductor element 22 and the core substrate 110. It may be connected between appropriate wiring patterns that are electrically connected to each other.
　以上のように構成される本実施形態の部品内蔵基板１０においては、半導体素子２２の表面（能動面）及び裏面（非能動面）にそれぞれ第１のビア１５１及び第２のビア１５２が設けられているため、部品の片面にのみビアを接続する場合と比較して、抵抗値及び熱抵抗が下がることで導電経路及び伝熱経路が短くなる。また、サーマルビアを設けることが容易となり、半導体素子２２の非能動面の放熱性を高めることができる。 In the component-embedded substrate 10 of the present embodiment configured as described above, the first via 151 and the second via 152 are provided on the front surface (active surface) and the back surface (inactive surface) of the semiconductor element 22, respectively. Therefore, the conductive path and the heat transfer path are shortened by lowering the resistance value and the thermal resistance as compared with the case where the via is connected to only one side of the component. Moreover, it becomes easy to provide a thermal via, and the heat dissipation of the inactive surface of the semiconductor element 22 can be improved.
　また本実施形態によれば、半導体素子２２が第１のキャビティ部Ｃ１においてコア基材１１０の中心よりも第１の主面１１１側に位置するため、第１のビア１５１で微細な信号配線を形成するとともに、第２のビア１５２で大電流が流れる配線や放熱ラインを形成することができる。このように、半導体素子２２の表裏で配線密度を異ならせたり、放熱ラインと微細の信号配線とを分けたりすることで、基板の小型化、薄型化を実現することができる。 Further, according to the present embodiment, since the semiconductor element 22 is located closer to the first main surface 111 side than the center of the core base material 110 in the first cavity portion C1, fine signal wiring is formed by the first via 151. In addition to the formation, a wiring and a heat radiation line through which a large current flows can be formed by the second via 152. In this manner, the substrate can be made smaller and thinner by making the wiring density different between the front and back surfaces of the semiconductor element 22 or by separating the heat radiation line and the fine signal wiring.
　さらに、第２のビア１５２が表面導体層５２１と第２の樹脂層５２２とにより構成されているため、第２のビア１５２が金属等の導体で充填される場合と比較して、部品内蔵基板１０に作用する曲げ応力等の外力に対して所定の応力緩和機能をもたせることができる。このため、第２のビア１５２が比較的高く（あるいは深く）形成される場合でも、所望とする接続信頼性を確保することができる。ただし、第２のビア１５２が金属等の導体で充填される場合でも、ビアの高さ（深さ）を大きくするほど、ビアがたわむため、αのミスマッチによるクラックが生じ難くなり、安定した接続を保つことができる。 Further, since the second via 152 is constituted by the surface conductor layer 521 and the second resin layer 522, the component-embedded substrate is compared with the case where the second via 152 is filled with a conductor such as metal. A predetermined stress relaxation function can be provided with respect to an external force such as a bending stress acting on 10. Therefore, even when the second via 152 is formed relatively high (or deep), desired connection reliability can be ensured. However, even when the second via 152 is filled with a conductor such as a metal, the larger the via height (depth), the more the via is bent. Can keep.
　さらに、半導体素子２２を第１の主面１１１側に偏って配置することで、以下のような作用効果を得ることができる。 Furthermore, by arranging the semiconductor element 22 so as to be biased toward the first main surface 111 side, the following operational effects can be obtained.
　例えば、第１のキャビティ部Ｃ１及び第２のキャビティ部Ｃ２は、ウェットエッチング法によって形成される。本実施形態において各キャビティ部Ｃ１，Ｃ２は、コア層１１０の第１の主面１１１及び第２の主面１１２の所定領域をそれぞれハーフエッチングすることで形成される。このため、両ハーフエッチング領域の合流部に相当する内壁面には、キャビティ部Ｃ１，Ｃ２の内方に突出する環状の突起部（環状突起部）Ｃｐが形成される場合がある（図３参照）。 For example, the first cavity portion C1 and the second cavity portion C2 are formed by a wet etching method. In the present embodiment, the cavity portions C1 and C2 are formed by half-etching predetermined regions of the first main surface 111 and the second main surface 112 of the core layer 110, respectively. For this reason, an annular protrusion (annular protrusion) Cp that protrudes inward of the cavities C1 and C2 may be formed on the inner wall surface corresponding to the confluence of both half-etched regions (see FIG. 3). ).
　上述のように本実施形態においては、半導体素子２２が第１のキャビティ部Ｃ１においてコア基材１１０の中心よりも第１の主面１１１側に位置している。半導体素子２２は、コア層１１０の厚み方向（Ｚ軸方向）と直交する方向に環状突起部Ｃｐの先端と対向しない位置に配置されることが好ましく、典型的には、環状突起部Ｃｐと第１の主面１１１との間に配置される。これにより、環状突起部Ｃｐと半導体素子２２の周面との絶縁距離を確保しやすくなるため、半導体素子２２の絶縁耐圧を向上させることができる。 As described above, in the present embodiment, the semiconductor element 22 is located closer to the first main surface 111 side than the center of the core substrate 110 in the first cavity portion C1. The semiconductor element 22 is preferably arranged at a position that does not face the tip of the annular protrusion Cp in a direction orthogonal to the thickness direction (Z-axis direction) of the core layer 110, and typically the annular protrusion Cp and the first Between the first main surface 111 and the first main surface 111. Thereby, since it becomes easy to ensure the insulation distance of the cyclic | annular protrusion part Cp and the surrounding surface of the semiconductor element 22, the withstand voltage of the semiconductor element 22 can be improved.
　また、本実施形態に於いて、電子部品２１が、単品で、コア基材表面の面積の占有比率で、本部品内蔵基板の５０％から１００％に近い程の占有率であったり、複数の素子で５０％から１００％に近い程の占有率であったりする場合がある。その場合、電子部品２１とコア基材１１０表面との間の接続部は、電子部品２１やモールド部３０の剛性によってある程度の信頼性確保につながる。一方、コア基材１１０の裏面側は、この剛性に寄与する部材が設けられていない。よってコア基材１１０の裏面側は、大きく反りの力が加わることになる。特に第２のビア１５２を金属で完全に埋めてしまうと、その硬さのため、第２のビア１５２と半導体素子２２とのコンタクト部分、第２のビア１５２と第２の配線パターン１３２とのコンタクト部分には、大きな応力が加わることになる。しかしながら、本実施形態の様に、ビア１５２の内部に第２の樹脂層５２２を充填する事により、ビア１５２自体に柔軟性が発生し、第２のビア１５２と第２の配線パターン１３２とのコンタクト不良を抑止することができる。 In the present embodiment, the electronic component 21 is a single product, and the occupation ratio of the area of the core base material surface is from 50% to 100% of the component-embedded substrate. In some cases, the element may have an occupation ratio as close to 50% to 100%. In that case, the connection between the electronic component 21 and the surface of the core substrate 110 leads to a certain degree of reliability due to the rigidity of the electronic component 21 and the mold part 30. On the other hand, the member contributing to this rigidity is not provided on the back surface side of the core substrate 110. Therefore, a large warping force is applied to the back surface side of the core substrate 110. In particular, if the second via 152 is completely filled with metal, due to its hardness, the contact portion between the second via 152 and the semiconductor element 22, and the second via 152 and the second wiring pattern 132 A large stress is applied to the contact portion. However, as in this embodiment, filling the via 152 with the second resin layer 522 generates flexibility in the via 152 itself, and the second via 152 and the second wiring pattern 132 are not connected. Contact failure can be suppressed.
　更には、第１のビア１５１が薄く、または浅く形成される事から、電子部品２１との間で以下のメリットが発生する。
　電子部品２１がコンデンサである場合、ノイズ吸収が急峻であり、半導体素子２２の誤動作を防止できる。また電子部品２１がソレノイドであれば、ソレノイドと半導体素子の間でノイズを拾うことが少なくなる。この様に、半導体素子であるパワートランジスタから電子部品への電流は、パスが短く、抵抗値が小さくなり、信号処理として有効となる。
　電流の流れを考えると、図２において右側の外部端子３１からスルーホールＶを介して電子部品に流れ、そして電子部品２１から第１のビア１５１を介して縦型のトランジスタ２２を流れ、その電流は第２のビア１５２を介して左側の外部端子３１へと流れる。またはその逆で電流が流れる。特に、トランジスタ２２は、多層基板の厚み方向に、流れるため発熱し第２のビア１５２が深いため、その径も第１のビアよりも大きいため、サーマルビアとして大きく寄与する。 Furthermore, since the first via 151 is formed to be thin or shallow, the following merit with the electronic component 21 occurs.
When the electronic component 21 is a capacitor, noise absorption is steep, and malfunction of the semiconductor element 22 can be prevented. Moreover, if the electronic component 21 is a solenoid, it is less likely to pick up noise between the solenoid and the semiconductor element. As described above, the current from the power transistor, which is a semiconductor element, to the electronic component has a short path and a small resistance value, which is effective as signal processing.
Considering the flow of current, the current flows from the external terminal 31 on the right side to the electronic component through the through hole V in FIG. 2, and then flows from the electronic component 21 to the vertical transistor 22 through the first via 151. Flows to the left external terminal 31 through the second via 152. Or vice versa, current flows. In particular, the transistor 22 generates heat because it flows in the thickness direction of the multilayer substrate, and the second via 152 is deep, and its diameter is larger than that of the first via. Therefore, the transistor 22 greatly contributes as a thermal via.
　以上、本発明の実施形態について説明したが、本発明は上述の実施形態にのみ限定されるものではなく種々変更を加え得ることは勿論である。 As mentioned above, although embodiment of this invention was described, this invention is not limited only to the above-mentioned embodiment, Of course, a various change can be added.
　例えば以上の実施形態では、例えば以上の実施形態では、部品内蔵基板１０の両主面に形成される配線層（配線パターン）の数をそれぞれ１層としたが、これに限られず、２層以上の多層配線構造が採用されてもよい。この場合、配線パターン１３１，１３２の上に層間絶縁膜を介して配線層がさらに形成される。 For example, in the above embodiment, for example, in the above embodiment, the number of wiring layers (wiring patterns) formed on both main surfaces of the component-embedded substrate 10 is one, but the present invention is not limited to this. A multilayer wiring structure may be employed. In this case, a wiring layer is further formed on the wiring patterns 131 and 132 via an interlayer insulating film.
　また、以上の実施形態では、コア基材１１０が半導体素子２２を収容する第１のキャビティ部Ｃ１を有する例について説明したが、内蔵部品を収容するキャビティ部の数は１つに限られず、複数あってもよい。この場合、収容される内蔵部品は半導体素子に限られず、コンデンサや抵抗素子等の受動部品であってもよい。 In the above embodiment, the example in which the core substrate 110 includes the first cavity portion C1 that houses the semiconductor element 22 has been described. However, the number of cavity portions that house the built-in components is not limited to one, and a plurality of There may be. In this case, the housed component to be accommodated is not limited to a semiconductor element, and may be a passive component such as a capacitor or a resistance element.
　１０…部品内蔵基板
　２１…電子部品
　２２…半導体素子
　１００…回路モジュール
　１１０…コア基材
　１１１…第１の主面
　１１２…第２の主面
　１３０…多層配線層
　１３１…第１の配線パターン
　１３２…第２の配線パターン
　１４０…第１の樹脂層
　１５０…層間接続部
　１５１…第１のビア
　１５２…第２のビア
　５２１…表面導体層
　５２２…第２の樹脂層
　Ｃ１…第１のキャビティ部
　Ｃｐ…環状突起部 DESCRIPTION OF SYMBOLS 10 ... Component built-in board 21 ... Electronic component 22 ... Semiconductor element 100 ... Circuit module 110 ... Core base material 111 ... 1st main surface 112 ... 2nd main surface 130 ... Multilayer wiring layer 131 ... 1st wiring pattern 132 ... Second wiring pattern 140 ... first resin layer 150 ... interlayer connection 151 ... first via 152 ... second via 521 ... surface conductor layer 522 ... second resin layer C1 ... first cavity Cp ... Annular projection

Claims (7)

  1. 　第１の主面と、前記第１の主面とは反対側の第２の主面と、前記第１の主面と前記第２の主面との間を貫通するキャビティとを有する金属製のコア基材と
    　前記コア基材よりも小さい厚みを有し、前記キャビティに収容され、前記コア基材の中心よりも前記第１の主面側に位置する半導体素子と、
    　前記キャビティに充填され、前記半導体素子を封止する第１の樹脂層と、
    　前記第１の主面側に配置された第１の配線パターンと、前記第２の主面側に配置された第２の配線パターンとを有する多層配線層と、
    　前記第１の配線パターンと前記半導体素子との間に第１の高さで形成された第１のビアと、前記第２の配線パターンと前記半導体素子との間に前記第１の高さよりも大きい第２の高さで形成された第２のビアとを有する層間接続部と
    　を具備する部品内蔵基板。     A metal having a first main surface, a second main surface opposite to the first main surface, and a cavity penetrating between the first main surface and the second main surface A semiconductor element having a thickness smaller than that of the core base material, housed in the cavity, and located on the first main surface side from the center of the core base material,
    A first resin layer that fills the cavity and seals the semiconductor element;
    A multilayer wiring layer having a first wiring pattern disposed on the first main surface side and a second wiring pattern disposed on the second main surface side;
    The first via formed at a first height between the first wiring pattern and the semiconductor element, and the first via between the second wiring pattern and the semiconductor element than the first height. A component-embedded substrate comprising: an interlayer connection portion having a second via formed with a large second height.
  2. 　請求項１に記載の部品内蔵基板であって、
    　前記第２のビアは、前記第２の配線パターンと前記半導体素子との間を電気的に接続する表面導体層と、前記表面導体層の内部に充填された第２の樹脂層とを含む
    　部品内蔵基板。     The component-embedded substrate according to claim 1,
    The second via includes a surface conductor layer that electrically connects the second wiring pattern and the semiconductor element, and a second resin layer filled in the surface conductor layer. Built-in board.
  3. 　請求項１又は２に記載の部品内蔵基板であって、
    　前記第２のビアは、前記第１のビアよりも大きな径で形成される
    　部品内蔵基板。     The component-embedded substrate according to claim 1 or 2,
    The second via is formed with a larger diameter than the first via.
  4. 　請求項１～３のいずれか１つに記載の部品内蔵基板であって、
    　前記キャビティは、内方に向かって突出する環状突起部を含む内壁面を有し、
    　前記半導体素子は、前記環状突起部と前記第１の主面との間に配置される
    　部品内蔵基板。     The component-embedded substrate according to any one of claims 1 to 3,
    The cavity has an inner wall surface including an annular protrusion protruding inward,
    The semiconductor element is disposed between the annular protrusion and the first main surface.
  5. 　請求項１～４のいずれか１つに記載の部品内蔵基板であって、
    　前記第１の主面側に搭載され、前記半導体素子と電気的に接続される電子部品をさらに具備する
    　部品内蔵基板。     The component-embedded substrate according to any one of claims 1 to 4,
    A component built-in substrate further comprising an electronic component mounted on the first main surface side and electrically connected to the semiconductor element.
  6. 　互いに対向する第１の主面および第２の主面を有する金属製のコア基材と、
    　前記第１の主面および前記第２の主面にそれぞれ絶縁処理されて設けられた第１の配線パターンおよび第２の配線パターンと、
    　前記第１の配線パターンと電気的に接続され、前記第１の主面側に実装され前記第１の主面の面積の５０％以上を占有する少なくとも一つの電子部品と、
    　前記第１の主面に設けられ前記電子部を覆うモールド部と、
    　前記コア基材に設けられたキャビティと、
    　前記キャビティに設けられ、前記第１の主面側に偏って配置された、前記コア基材の厚みよりも薄いパワー半導体素子と、
    　前記半導体素子の前記第１の主面側の表面に設けられた第１のビアと、
    　前記半導体素子の前記第２の主面側の裏面に設けられ、前記第１のビアよりも長い第２のビアと、
    　を具備し、
    　前記第２のビアは、その内側表面に設けられた表面導体層と、前記表面導体層で構成される空間に充填された第２の樹脂層と、を有する
    　部品内蔵基板。     A metal core substrate having a first main surface and a second main surface facing each other;
    A first wiring pattern and a second wiring pattern provided by being insulated from the first main surface and the second main surface, respectively;
    At least one electronic component electrically connected to the first wiring pattern, mounted on the first main surface side and occupying 50% or more of the area of the first main surface;
    A mold part provided on the first main surface and covering the electronic part;
    A cavity provided in the core substrate;
    A power semiconductor element which is provided in the cavity and is arranged to be biased toward the first main surface side, and is thinner than the thickness of the core substrate;
    A first via provided on a surface of the semiconductor element on the first main surface side;
    A second via provided on the back surface of the semiconductor element on the second main surface side and longer than the first via;
    Comprising
    The second via includes a surface conductor layer provided on an inner surface of the second via and a second resin layer filled in a space formed by the surface conductor layer.
  7. 　請求項６に記載の部品内蔵基板であって、
    　前記電子部品は、チップコンデンサまたはソレノイドであり、
    　前記パワー半導体素子は、縦型のトランジスタ、パワーＭＯＳ、ＩＧＢＴ、ＳｉＣまたはＧａＮから成る
    　部品内蔵基板。     The component-embedded substrate according to claim 6,
    The electronic component is a chip capacitor or a solenoid,
    The power semiconductor element is a component-embedded substrate made of a vertical transistor, power MOS, IGBT, SiC, or GaN.
PCT/JP2019/014692 2018-04-04 2019-04-02 Component-embedded substrate WO2019194200A1 (en)

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WO2011102561A1 (en) * 2010-02-22 2011-08-25 三洋電機株式会社 Multilayer printed circuit board and manufacturing method therefor
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008182184A (en) * 2006-12-26 2008-08-07 Jtekt Corp Multilayer circuit board and motor drive circuit board
JP2008288298A (en) * 2007-05-16 2008-11-27 Toppan Printing Co Ltd Method for manufacturing printed-wiring board with built-in electronic part
JP2011522403A (en) * 2008-05-30 2011-07-28 アーテー・ウント・エス・オーストリア・テヒノロギー・ウント・ジュステームテッヒニク・アクチェンゲゼルシャフト Method for incorporating at least one electronic component into a printed circuit board and printed circuit board
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