JP2004071858A - Wiring board and electronic device, and manufacturing method of wiring board and manufacturing method of electronic device - Google Patents

Wiring board and electronic device, and manufacturing method of wiring board and manufacturing method of electronic device Download PDF

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JP2004071858A
JP2004071858A JP2002229625A JP2002229625A JP2004071858A JP 2004071858 A JP2004071858 A JP 2004071858A JP 2002229625 A JP2002229625 A JP 2002229625A JP 2002229625 A JP2002229625 A JP 2002229625A JP 2004071858 A JP2004071858 A JP 2004071858A
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Prior art keywords
wiring
wiring board
insulating substrate
substrate
board
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Inventor
Mamoru Onda
御田　護
Takayuki Yoshikazu
吉和　崇之
Takashi Sato
佐藤　隆
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Hitachi Cable Ltd
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Hitachi Cable Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/15321—Connection portion the connection portion being formed on the die mounting surface of the substrate being a ball array, e.g. BGA

Abstract

<P>PROBLEM TO BE SOLVED: To prevent shape defect and exposure defect of a wiring provided to the bottom of a recess in the wiring board provided with the recess for mounting a semiconductor chip. <P>SOLUTION: In the wiring board, a wiring (conductor pattern) is provided to the surface and the inside of an insulating substrate, the insulating substrate has a recess, and the wiring is provided to the surface and the inside of the insulating substrate and the bottom of the recess of the insulation substrate. The wiring board comprises a first wiring substrate provided with a wiring in the surface and the inside of the first insulating substrate with an opening of a predetermined shape and a second wiring substrate provided with a wiring in a region overlapping with an opening of the first insulating substrate of a film-like second insulating substrate. The second wiring substrate is adhered to close one opening end of the opening of the first insulating substrate. <P>COPYRIGHT: (C)2004,JPO

Description

【０００１】
【発明の属する技術分野】
本発明は、配線板及び電子装置、ならびに配線板の製造方法及び電子装置の製造方法に関し、特に、絶縁基板に設けられた凹部内に半導体チップを実装する配線板および半導体チップが実装された電子装置に適用して有効な技術に関するものである。
【０００２】
【従来の技術】
従来、絶縁基板の表面及び内部に配線（導体パターン）が設けられた配線板に半導体チップなどの電子部品を実装した電子装置には、図１９及び図２０に示すように、前記配線板に凹部ＤＨが設けられており、前記配線板の凹部ＤＨ内に半導体チップ８が実装されている半導体装置（電子装置）がある。ここで、図２０は、図１９のＢ−Ｂ’線での断面図である。
【０００３】
このとき、前記配線板の配線１０２は、例えば、図２０に示したように、絶縁体層１０１Ａ，１０１Ｂ，１０１Ｃ，１０１Ｄ，１０１Ｅからなる絶縁基板の表面および内部に層状に設けられている。またこのとき、各層の配線１０２は、例えば、前記絶縁体層１０１Ａ，１０１Ｂ，１０１Ｃ，１０１Ｄ，１０１Ｅに埋め込んだ導電性ペーストからなる接続柱１０３、あるいはめっきスルーホールやビアにより電気的に接続されている。
【０００４】
また、前記配線板の配線１０２のうち、前記半導体チップ８の外部電極８０１と接続される端子部分は、図２０に示したように、前記絶縁基板に設けられた凹部ＤＨの底面に露出しており、前記配線の端子部分と前記半導体チップ８の外部電極８０１とは、例えば、はんだ接合材などのボール状端子９により電気的に接続されている。また、前記配線板と前記半導体チップ８の間は、熱硬化性樹脂などの封止材（アンダーフィル材）１０で封止されている。
【０００５】
また、前記半導体装置では、前記配線板の配線１０２の、実装基板などの配線（接続端子）と接続される端子部分に、例えば、図２０に示したように、はんだ接合材などを用いた外部接続端子１１が設けられている。また、前記配線板の表面に設けられた配線１０２のうち、前記外部接続端子１１が設けられた部分以外の部分は、ソルダレジストなどの保護膜６により保護されている。
【０００６】
前記電子装置（半導体装置）に用いる配線板の製造方法を簡単に説明すると、例えば、まず、図２１に示すように、絶縁体層１０１Ａ，１０１Ｂ，１０１Ｃ，１０１Ｄ，１０１Ｅからなる絶縁基板の表面および内部に配線（導体パターン）１０２が形成された積層体を形成する。このとき、前記積層体は、例えば、ビルドアップ法や一括積層法により形成する。
【０００７】
次に、前記積層体の凹部を形成する領域ＤＨＡＲの絶縁体層を削り、図２２に示すように、前記絶縁基板に凹部ＤＨを形成する。このとき、前記凹部ＤＨは、例えば、数値制御されたルータを用いて、前記絶縁基板に設けられた配線１０２のうち、半導体チップの外部電極と接続される部分が、前記凹部ＤＨの底面に露出するように形成する。
【０００８】
また、前記配線板を用いて、図２０に示したような、前記電子装置（半導体装置）を形成するときには、例えば、半導体チップ８の外部電極８０１上に、はんだ接合材を用いたボール状端子９を形成しておき、前記配線板の凹部ＤＨ内に前記半導体チップ８をフリップチップ実装し、前記配線板と前記半導体チップ８の間に、熱硬化性樹脂などの封止材（アンダーフィル材）１０を流し込む。その後、前記配線板の配線１０２のうち、表面に露出した部分に、例えば、はんだ接合材などを用いた外部接続端子１１を形成する。
【０００９】
また、前記電子装置（半導体装置）に用いる配線板では、層状に設けられた前記配線間の電気的接続に、図２０に示したような接続柱１０３を用いる代わりに、図２３に示すように、めっきスルーホールＰＴＨを用いる場合もある。また、前記配線板に前記半導体チップ８を実装するときには、図２０に示したようなフリップチップ実装に限らず、図２３に示したように、前記配線板の配線１０２と前記半導体チップ８の外部電極８０１をボンディングワイヤ１２で接続するフェースアップ実装をする場合もある。前記半導体チップ８をフェースアップ実装する場合、図２３では省略しているが、前記半導体チップ８の外部電極８０１と前記配線１０２の接続部は、熱硬化性樹脂などの封止材で封止されている。
【００１０】
【発明が解決しようとする課題】
しかしながら、前記従来の技術では、図２１に示したように、前記各絶縁体層１０１Ａ，１０１Ｂ，１０１Ｃ，１０１Ｄ，１０１Ｅを形成した後、図２２に示したように、前記積層された絶縁体層の不要な部分をルータで削って前記凹部ＤＨを形成している。このとき、前記ルータで削る量、すなわち、前記絶縁基板の凹部ＤＨの深さは、前記各絶縁体層１０１Ａ，１０１Ｂ，１０１Ｃ，１０１Ｄの厚さに基づいて設定するが、前記各絶縁体層１０１Ａ，１０１Ｂ，１０１Ｃ，１０１Ｄには、厚さのばらつきがある。そのため、前記絶縁体層をルータで削ったときに、前記凹部ＤＨの底面に露出させる配線を削ってしまう、あるいは、削る量が足りなくて前記凹部ＤＨの底面に配線が正常な状態で露出しないという問題があった。
【００１１】
また、前記ルータを用いて前記配線板の凹部ＤＨを形成する場合、前記凹部ＤＨの底面に露出した配線１０２が削れて形状が変化すると、電気的特性が変化してしまう。そこで、前記配線板の凹部ＤＨの底面に露出した配線の形状の変化による電気的特性の変化を少なくするために、図２０などで示したように、前記凹部ＤＨの底面から異なる層へ配線を引き出し、前記配線板の凹部ＤＨの底面に露出する配線の面積を小さくすることが多い。そのため、前記配線板は、凹部ＤＨの底面部分の薄型化が難しく、前記配線板を用いた電子装置（半導体装置）の薄型化が難しいという問題があった。
【００１２】
また、図２０などで示したように、前記配線板の凹部底面の配線１０２を、接続柱１０３により他の層に引き出すためのスペースが必要であるため、前記配線板の配線の高密度化、小型化が難しく、前記配線板を用いた電子装置（半導体装置）の小型化が難しいという問題があった。
【００１３】
また、図２３に示したように、配線１０２をめっきスルーホールＰＴＨで接続する場合には、隣り合うめっきスルーホールＰＴＨの間隔を狭くすることが難しいため、前記配線板の高密度化、小型化が難しく、前記配線板を用いた電子装置（半導体装置）の小型化が難しいという問題があった。
【００１４】
本発明の目的は、半導体チップを実装するための凹部が設けられた配線板において、凹部の底面に設けられた配線の形状不良や露出不良を防ぐことが可能な技術を提供することにある。
【００１５】
本発明の他の目的は、半導体チップを実装するための凹部が設けられた配線板において、配線の高密度化が可能な技術を提供することにある。
【００１６】
本発明の他の目的は、半導体チップを実装するための凹部が設けられた配線板において、配線板の小型化、薄型化が可能な技術を提供することにある。
【００１７】
本発明の他の目的は、配線板に設けられた凹部内に半導体チップを実装した電子装置において、電子装置の小型化、薄型化が可能な技術を提供することにある。
【００１８】
本発明の前記ならびにその他の目的と新規な特徴は、本明細書の記述及び添付図面によって明らかになるであろう。
【００１９】
【課題を解決するための手段】
本願において開示される発明の概要を説明すれば、以下の通りである。
【００２０】
（１）前記絶縁基板の表面及び内部に配線（導体パターン）が設けられてなり、前記絶縁基板は凹部を有し、前記配線は、前記絶縁基板の表面及び内部、ならびに前記絶縁基板の凹部の底面に設けられた配線板であって、あらかじめ定められた形状の開口部を有する第１絶縁基板の表面及び内部に配線が設けられた第１配線基板と、平板状の第２絶縁基板の前記第１絶縁基板の開口部と重なる領域に配線（導体パターン）が設けられた第２配線基板とからなり、前記第２配線基板は、前記第１絶縁基板の開口部の一方の開口端をふさぐように接着されている配線板である。
【００２１】
前記（１）の手段によれば、前記第２配線基板が、前記第１絶縁基板の開口部の一方の開口端をふさぐように接着されているため、ルータなどにより絶縁基板を削ることなく、前記配線板に凹部を設けることができる。また、前記絶縁基板を削ることなく前記凹部を設けることができるため、前記配線板の凹部の底面に設けられた配線の形状不良や露出不良を防ぐことができる。
【００２２】
また、前記配線板の凹部の底面に設けられた配線の形状不良を防ぐことができるので、前記配線板の凹部の底面に設ける配線、すなわち、前記第２配線基板に設ける配線を微細化、あるいは高密度化することができる。また、前記第２配線基板に設ける配線を微細化、あるいは高密度化することができるので、前記第２配線基板の厚さ、すなわち、前記配線板の凹部の底面部分の厚さを薄くすることが容易になる。そのため、前記配線板を薄型化することができる。
【００２３】
また、前記（１）の手段において、前記第１配線基板の配線と前記第２配線基板の配線を、突起状導体で電気的に接続することにより、前記第１配線基板の配線と前記第２配線基板の配線との接続部を微細化（高密度化）することができる。そのため、前記配線板の小型化が容易になる。
【００２４】
またこのとき、前記第１配線基板の配線と前記第２配線基板の配線との接続部の周囲に接合材を設けることにより、前記第１配線基板の配線と前記第２配線基板の配線との電気的接続の信頼性が高くなる。
【００２５】
また、前記（１）の手段において、前記第２配線基板の配線を前記第２絶縁基板の両面に設けると、前記第２配線基板の配線をより高密度化することができる。またこのとき、前記第１配線基板が接着された面の裏面の配線にも前記突起状導体を設けると、前記配線板の凹部内に電子部品を実装して半導体装置（電子装置）を形成したときに、前記前記第１配線基板が接着された面の裏面の配線に設けられた前記突起状導体を利用して、他の電子装置（半導体装置）に積層することができる。
【００２６】
（２）前記絶縁基板の表面及び内部に配線（導体パターン）が設けられた配線板と、前記配線板上に設けられた電子部品とからなり、前記絶縁基板は凹部を有し、前記配線は、前記絶縁基板の表面及び内部、ならびに前記絶縁基板の凹部の底面に設けられており、前記電子部品が、前記配線板の凹部内に設けられている電子装置であって、前記配線板は、あらかじめ定められた形状の開口部を有する第１絶縁基板の表面及び内部に配線が設けられた第１配線基板と、平板状の第２絶縁基板の前記第１絶縁基板の開口部と重なる領域に配線（導体パターン）が設けられた第２配線基板とからなり、前記第２配線基板は、前記第１絶縁基板の開口部の一方の開口端をふさぐように接着されている電子装置である。
【００２７】
前記（２）の手段によれば、前記配線板は、前記第２配線基板が、前記第１絶縁基板の開口部の一方の開口端をふさぐように接着されているため、ルータなどにより絶縁基板を削ることなく、前記配線板に凹部を設けることができる。また、前記絶縁基板を削ることなく前記凹部を設けることができるため、前記配線板の凹部の底面に設けられた配線の形状不良や露出不良を防ぐことができる。
【００２８】
また、前記配線板の凹部の底面に設けられた配線の形状不良を防ぐことができるので、前記配線板の凹部の底面に設ける配線、すなわち、前記第２配線基板に設ける配線を微細化、あるいは高密度化することができる。また、前記第２配線基板に設ける配線を微細化、あるいは高密度化することができるので、前記第２配線基板の厚さ、すなわち、前記配線板の凹部の底面部分の厚さを薄くすることが容易になる。そのため、前記配線板を薄型化することができ、前記電子装置を薄型化することができる。
【００２９】
また、前記（２）の手段において、前記第１配線基板の配線と前記第２配線基板の配線を、突起状導体で電気的に接続することにより、前記第１配線基板の配線と前記第２配線基板の配線との接続部を微細化（高密度化）することができる。そのため、前記配線板の小型化が容易になり、前記電子装置を小型化することができる。
【００３０】
またこのとき、前記第１配線基板の配線と前記第２配線基板の配線との接続部の周囲に接合材を設けることにより、前記第１配線基板の配線と前記第２配線基板の配線との電気的接続の信頼性が高くなる。
【００３１】
また、前記（２）の手段において、前記第２配線基板の配線を前記第２絶縁基板の両面に設けると、前記第２配線基板の配線をより高密度化することができる。またこのとき、前記第１配線基板が接着された面の裏面の配線にも前記突起状導体を設けると、前記第２配線基板の、前記前記第１配線基板が接着された面の裏面の配線に設けられた前記突起状導体を利用して、他の電子装置に積層することができる。
【００３２】
（３）前記絶縁基板の表面及び内部に配線（導体パターン）が形成された配線板の製造方法であって、あらかじめ定められた形状の開口部が形成された第１絶縁基板の表面及び内部に配線が形成された第１配線基板を形成する第１配線基板形成工程と、平板状の第２絶縁基板の表面に配線（導体パターン）が形成された第２配線基板を形成する第２配線基板形成工程と、前記第１配線基板と前記第２配線基板とを接着して、前記第１配線基板の配線と前記第２配線基板の配線とを電気的に接続する配線基板接着工程とを備え、前記配線基板接着工程は、前記第２配線基板を、前記第１配線基板の開口部の一方の開口端をふさぐように接着する配線板の製造方法である。
【００３３】
前記（３）の手段によれば、前記第１配線基板と前記第２配線基板とを接着することにより、前記第１配線基板の開口部及び前記第２配線基板による凹部が形成される。このとき、前記第２配線基板の配線の一部が、前記第１配線基板の開口部と重なる領域を通るように形成すれば、前記凹部の底面に配線が露出した配線板を容易に製造することができる。また、前記第１配線基板と前記第２配線基板とを接着することにより、前記凹部の底面に形成した配線の形状不良や露出不良を防ぐことができる。
【００３４】
また、前記第１配線基板形成工程、あるいは前記第２配線基板形成工程において、前記第１配線基板の配線、あるいは前記第２配線基板の配線上に突起状導体を形成しておき、前記第１配線基板の配線と前記第２配線基板の配線とを前記突起状導体で電気的に接続することにより、前記配線の電気的接続が容易になる。
【００３５】
また、前記（３）の手段において、前記突起状導体を形成するときに、前記第１配線基板と前記第２配線基板との接着面とは異なる表面の配線にも突起状導体を形成しておくと、前記配線板を用いて電子装置を製造したときに、製造した電子装置を他の電子装置と積層することが容易になる。
【００３６】
（４）前記絶縁基板の表面及び内部に配線（導体パターン）が形成された配線板を形成する配線板形成工程と、前記配線板上に電子部品を実装する電子部品実装工程とを備える電子装置の製造方法であって、前記配線板形成工程は、あらかじめ定められた形状の開口部を有する第１絶縁基板の表面および内部に配線が設けられた第１配線基板と、平板状の第２絶縁基板の表面に配線（導体パターン）が設けられた第２配線基板とを接着し、前記第１配線基板の配線と前記第２配線基板の配線とを電気的に接続する電子装置の製造方法である。
【００３７】
前記（４）の手段によれば、前記配線基板形成工程において、前記第１配線基板と前記第２配線基板とを接着することにより、前記第１配線基板の開口部および前記第２配線基板による凹部が形成される。このとき、前記第２配線基板の配線の一部が、前記第１配線基板の開口部と重なる領域を通るように形成しておけば、前記凹部の底面に配線が露出した配線板を容易に製造することができる。また、前記第１配線基板と前記第２配線基板とを接着することにより、前記凹部の底面に形成した配線の形状不良や露出不良を防ぐことができる。
【００３８】
また、前記第１配線基板形成工程、あるいは前記第２配線基板形成工程において、前記第１配線基板の配線、あるいは前記第２配線基板の配線上に突起状導体を形成しておき、前記第１配線基板の配線と前記第２配線基板の配線とを前記突起状導体で電気的に接続することにより、前記配線の電気的接続が容易になる。
【００３９】
また、前記（４）の手段において、前記突起状導体を形成するときに、前記第１配線基板と前記第２配線基板との接着面とは異なる表面の配線にも突起状導体を形成しておくと、前記配線板を用いて電子装置を製造したときに、製造した電子装置を他の電子装置と積層することが容易になる。
【００４０】
以下、本発明について、図面を参照して実施の形態（実施例）とともに詳細に説明する。
【００４１】
なお、実施例を説明するための全図において、同一機能を有するものは、同一符号を付け、その繰り返しの説明は省略する。
【００４２】
【発明の実施の形態】
（実施例１）
図１乃至図３は、本発明による実施例１の配線板の概略構成を示す模式図であり、図１は配線板の平面図、図２は図１のＡ−Ａ’線での断面図、図３は図２の部分拡大断面図である。
【００４３】
図１乃至図３において、１は第１配線基板、１０１Ａ，１０１Ｂ，１０１Ｃは絶縁体層、１０２は第１配線基板の配線、２は第２配線基板、２０１は第２絶縁基板、２０２は第２絶縁基板の配線、３は接着材、４は突起状導体、５は接合材である。
【００４４】
本実施例１の配線板は、図１および図２に示すように、絶縁体層１０１Ａ，１０１Ｂ，１０１Ｃからなる第１絶縁基板の表面および内部に配線（導体パターン）１０２が設けられた第１配線基板１と、第２絶縁基板２０１の表面に配線（導体パターン）２０２が設けられた第２配線基板２とからなる。
【００４５】
また、前記配線板には、図１および図２に示したように、半導体チップを収容することが可能な大きさの凹部ＤＨが設けられている。本実施例１の配線板では、前記第１配線基板１に設けられた開口部（貫通穴）の一方の開口端を、前記第２配線基板２でふさぐことにより前記凹部ＤＨを設けている。またこのとき、前記第２配線基板２と前記第１配線基板１は、接着材３で接着されている。
【００４６】
また、前記第１配線基板１の配線１０２と前記第２配線基板２の配線２０２とは、図２に示したように、突起状導体４により電気的に接続されている。またこのとき、前記第１配線基板１の配線１０２及び前記第２配線基板２の配線２０２、ならびに前記突起状導体４の周囲には、図３に示すように、接合材５が設けられており、前記第１配線基板１の配線１０２と前記第２配線基板２の配線２０２との接続部は、前記接合材５により固定された状態になっている。
【００４７】
また、本実施例１の配線板を用いて電子装置（半導体装置）を製造するときには、一般に、前記第１配線基板１の開口部と前記第２配線基板２により構成される凹部ＤＨ内に半導体チップを収容する。そのため、前記第２配線基板２の配線２０２の一部が、前記第１配線基板１の開口部と平面的に重なる領域、すなわち、前記凹部ＤＨの底面に露出するように設けられている。またこのとき、前記配線２０２には、例えば、前記半導体チップを実装する領域ＡＲ１内に、前記半導体チップの外部電極と接続される端子部２０２Ａが設けられている。
【００４８】
図４乃至図１１は、本実施例１の配線板の製造方法を説明するための模式図であり、図４（ａ）は第１配線基板の断面図、図４（ｂ）は第２配線基板の断面図、図５（ａ）は第１配線基板のコア基板を形成する工程の断面図、図５（ｂ）は第１配線基板の配線を積層する工程の断面図、図６は第１配線基板の配線上に接合材を形成する工程の断面図、図７（ａ）は第２配線基板の突起状導体を形成する工程の断面図、図７（ｂ）は第２配線基板の配線を形成する工程の断面図、図８は第２配線基板の配線上に接合材を形成する工程の断面図、図９は第２配線基板の製造方法を説明するための平面図、図１０は第１配線基板と第２配線基板を接着する工程の断面図、図１１は第１配線基板と第２配線基板を接着する工程の部分拡大断面図である。
【００４９】
本実施例１の配線板を製造する工程は、大きく分けると、例えば、図４（ａ）に示すように、絶縁体層１０１Ａ，１０１Ｂ，１０１Ｃからなり、あらかじめ定められた領域に開口部（貫通穴）ＤＨ’を有する第１絶縁基板の表面および内部に配線１０２が設けられた第１配線基板１を形成する第１配線基板形成工程と、図４（ｂ）に示すように、第２絶縁基板２０１の表面に配線２０２が設けられた第２配線基板２を形成する第２配線基板形成工程と、前記第１配線基板１と前記第２配線基板２を接着し、前記第１配線基板１の配線１０２と前記第２配線基板２の配線２０２を電気的に接続する配線基板接着工程とに分けられる。以下、本実施例１の配線板の製造方法を、図５乃至図１１を参照しながら説明する。
【００５０】
なお、以下の配線板の製造方法では、図４（ｂ）に示したように、前記第１配線基板１と前記第２配線基板を接着する接着材３、および前記第１配線基板１の配線１０２と前記第２配線基板２の配線２０２を電気的に接続する突起状導体４を、前記第２配線基板２側に形成する場合について説明する。
【００５１】
前記第１配線基板形成工程は、例えば、まず、図５（ａ）に示すように、絶縁体層１０１Ｂの両表面に配線１０２が設けられたコア基板を形成する。このとき、前記コア基板は、例えば、前記絶縁体層１０１Ｂに貫通穴（図示しない）を形成し、前記貫通穴に導電性ペーストを埋め込んで接続柱１０３を形成した後、前記接続柱１０３が形成された絶縁体層１０１Ｂの両面に銅箔などの導体膜を張り合わせ、前記導体膜の不要な部分をエッチングで除去して前記配線１０２を形成する。また、前記導電性ペーストからなる接続柱１０３の代わりに、前記絶縁体層１０１Ｂの両面の配線をビアやめっきスルーホールで電気的に接続する場合には、あらかじめ導体膜を張り合わせた絶縁体層１０１Ｂを開口して前記ビアやめっきスルーホールを形成した後、前記導体膜の不要な部分を除去して配線１０２を形成する。
【００５２】
次に、図５（ｂ）に示したように、前記コア基板の一方の面に、絶縁体層１０１Ａを介在させて配線１０２を形成し、他方の面にも、絶縁体層１０１Ｃを介在させて配線１０２を形成する。このとき、前記絶縁体層１０１Ａ，１０１Ｃを介在させた配線１０２は、例えば、ビルドアップ法を用いて、接続柱１０３が形成された絶縁体層１０１Ａ，１０１Ｃおよび導体膜を張り合わせ、前記導体膜の不要な部分をエッチングで除去して配線１０２を形成する。また、前記配線１０２を前記接続柱１０３の代わりにビアで接続する場合には、前記接続柱１０３を形成していない絶縁体層１０１Ａ，１０１Ｃおよび導体膜を前記コア基板に張り合わせ、前記導体膜および前記絶縁体層１０１Ａ，１０１Ｃを開口して、例えば、電気銅めっきによりビアを形成した後、前記導体膜の不要な部分を除去して配線１０２を形成する。
【００５３】
またこのとき、前記絶縁体層１０１Ａ上に形成する配線１０２は、例えば、実装基板に実装するときの端子部分１０２Ａを形成する。
【００５４】
また、後の工程で半導体チップを収容する開口部を形成する領域ＤＨＡＲには、前記配線１０２を形成しないでおく。
【００５５】
次に、図６に示したように、例えば、前記絶縁体層１０１Ａの表面に露出した配線１０２の、前記端子部分１０２Ａ以外の部分を保護する保護膜６を形成し、前記端子部分１０２Ａ上、および前記絶縁体層１０１Ｃの表面に露出した配線１０２上に、接合材５を形成する。このとき、前記接合材５は、例えば、錫銀合金めっきで形成する。
【００５６】
その後、図５（ｂ）に示したように、前記絶縁体層１０１Ａ，１０１Ｂ，１０１Ｃが積層された部分のうち、半導体チップを収容する開口部を形成する領域ＤＨＡＲを、例えば、金型を用いた打ち抜き加工、あるいは切削加工などにより開口して、図４（ａ）に示したような開口部（貫通穴）ＤＨ’を形成する。その後、切断線ＳＬで切断して個片化すると、本実施例１の配線板に用いる第１配線基板１が得られる。
【００５７】
また、前記第２配線基板形成工程は、まず、図７（ａ）に示すように、第２絶縁基板２０１の表面に銅箔などの導体膜２０２’を張り合わせた後、前記導体膜２０２’上にめっきレジスト７を形成し、例えば、電気銅めっきにより突起状導体４を形成する。このとき、前記突起状導体４は、例えば、高さが２５μｍ程度になるように形成する。
【００５８】
次に、前記めっきレジスト７を除去し、図７（ｂ）に示すように、前記導体膜２０２’の不要な部分をエッチングで除去して配線２０２を形成する。
【００５９】
次に、図８に示すように、例えば、前記配線２０２の半導体チップの外部端子と接続される端子部分２０２Ａと、前記突起状導体４が形成された部分を除く領域に保護膜６を形成し、前記配線２０２の露出した面及び突起状導体４上に接合材５を形成する。前記接合材５は、例えば、錫銀合金めっきで形成する。またこのとき、図示は省略するが、前記配線２０２の、半導体チップの外部電極と接続される端子部分２０２Ａ上にも前記接合材５を形成する。
【００６０】
その後、前記突起状導体４が形成された領域の周辺、言い換えると、前記第１配線基板１と接着される領域に接着材３を形成すると、図４（ｂ）に示したような第２配線基板２が得られる。
【００６１】
また、前記第２配線基板形成工程では、前記第２絶縁基板２０１は、例えば、図１０に示したように、一方向に長尺なテープ状の基板を用い、リールツーリール（ｒｅｅｌ　ｔｏ　ｒｅｅｌ）方式により、前記第２配線基板２として用いる領域ＡＲ２を連続的に形成する。
【００６２】
前記手順に沿って形成した前記第１配線基板１と前記第２配線基板２を接着し、前記第１配線基板１の配線１０２と前記第２配線基板２の配線２０２を電気的に接続する配線基板接着工程は、図１０に示すように、前記第２配線基板２の前記突起状導体４および前記接着材３が形成された面に、前記手順で形成した第１配線基板１を配置し、例えば、２５０℃に加熱して熱プレスを行う。このとき、２５０℃に加熱することにより、前記接着材３が軟化し、流動性が高くなるので、前記突起状導体４が前記接着材３を押しのけ、図１１に示したように、前記第１配線基板１の配線１０２と前記突起状導体４が接触する。そして、この状態でプレスを行うと、前記第１配線基板１の配線１０２上、及び前記突起状導体４上に形成されたそれぞれの接合材５が溶融して一体になる。そのため、熱プレス後に室温に戻したときに、前記第１配線基板１の配線１０２と前記第２配線基板２の配線２０２の接続部の周囲が、図３に示したように、前記接合材５で固定された状態になり、本実施例１の配線板を得ることができる。
【００６３】
前記手順により配線板を製造する場合、前記配線板の凹部ＤＨの底面に設けられる配線は、前記第２配線基板２に形成されているので、従来の配線板の製造方法のように、絶縁基板（絶縁体層）を削らなくてもよい。そのため、前記配線板の凹部ＤＨの底面に設けられる配線が削れて形状不良になるのを防ぐことができる。
【００６４】
また、前記配線板の凹部ＤＨの底面に設けられる配線、すなわち、前記第２配線基板２の配線２０２は、形状不良を起こしにくいので、微細化が容易である。
そのため、前記第２配線基板２の配線２０２を微細化、高密度化することにより、従来の配線板に比べて小型化することができる。
【００６５】
また、前記第１配線基板１の配線１０２と前記第２配線基板２の配線２０２を電気的に接続する突起状導体４は、容易に形成することができるとともに、導電性ペーストを用いた接続柱や、ビア、めっきスルーホールなどに比べて、微細化が容易である。そのため、隣り合う突起状導体４の間隔を狭くすることが容易であり、前記配線板を小型化することができる。
【００６６】
また、前記第２配線基板２の配線２０２の微細化、高密度化が容易であるため、前記第２配線基板２の薄型化ができ、前記配線板の凹部ＤＨの底面部分の厚さを薄くできるので、配線板を薄型化することができる。
【００６７】
図１２は、本実施例１の配線板を用いた電子装置の概略構成を示す模式断面図である。
【００６８】
本実施例１の配線板を用いて電子装置を製造するときには、例えば、図１２に示すように、前記配線板の凹部ＤＨ、すなわち、前記第１配線基板１の開口部（貫通穴）ＤＨ’と前記第２配線基板２により形成された凹部ＤＨ内に半導体チップ８を配置し、前記半導体チップ８の外部電極（図示しない）と前記配線板の凹部ＤＨの底面（第２配線基板２）に設けられた配線の端子部分２０２Ａとを、例えば、はんだ接合材などのボール状端子９で電気的に接続する。このとき、前記半導体チップ８は複数個あってもよいし、また、前記半導体チップ８以外の、抵抗素子や容量素子などのチップ状の電子部品を実装してもよい。
【００６９】
また、前記配線板の凹部ＤＨの底面（第２配線基板２）と前記半導体チップ８の間は、例えば、熱硬化性樹脂などの封止材（アンダーフィル材）を流し込んで封止する。また、前記配線板の、前記第１配線基板１の表面の配線の端子部分１０２Ａには、例えば、はんだ接合材からなる外部接続端子１１を形成する。
【００７０】
以上説明したように、本実施例１の配線板によれば、前記開口部ＤＨ’を有する第１配線基板１と、第２配線基板２とを接着して、前記半導体チップ８を収容可能な大きさの凹部ＤＨを設けることにより、前記凹部ＤＨの底面に設けられた配線の形状不良を防ぐことができる。
【００７１】
また、前記配線板の凹部ＤＨの底面に設けられた配線の形状不良を防ぐことができるため、前記凹部ＤＨの底面に設けられる部分の配線の微細化、高密度化が容易になり、配線板を小型化、薄型化することができる。
【００７２】
また、前記第１配線基板１の配線１０２と前記第２配線基板２の配線２０２を、前記突起状導体４で接続する場合、接続柱やビア、めっきスルーホールに比べて微細化が容易であるので、隣り合う突起状導体４の間隔を狭くし、配線板を小型化することができる。
【００７３】
また、前記配線板を小型化、薄型化できるため、前記配線板を用いた電子装置を小型化、薄型化することができる。
【００７４】
また、前記実施例１の配線板では、前記接合材５として、錫銀合金などのはんだ接合材を例にあげて説明したが、これに限らず、例えば、前記接合材５として金めっきを形成してもよい。前記接合材５として金めっきを形成した場合、超音波接合により、前記第１配線基板１の配線１０２上の金めっきと前記突起状導体４上の金めっきを接合させる。
【００７５】
また、前記実施例１の配線板では、前記接合材５を用いて、前記第１配線基板１の配線１０２と前記第２配線基板２の配線２０２の接続部を固定する例を示したが、これに限らず、前記接合材５を用いないで接続してもよい。このとき、前記接着材３には、例えば、異方性導電フィルム（ＡＣＦ）や非導電性フィルム（ＮＣＦ）を用いる。
【００７６】
また、前記実施例１の配線板では、前記突起状導体４及び前記接着材３を、前記第２配線基板２上に形成したが、これに限らず、前記第１配線基板１の配線１０２上に前記突起状導体４及び前記接着材３を形成してもよい。また、前記突起状導体４と前記接着材３が、それぞれ別の配線基板に形成されていてもよい。
【００７７】
また、前記実施例１では、前記配線板を用いた電子装置として、前記半導体チップ８をフリップチップ実装した電子装置（半導体装置）を例にあげたが、これに限らず、半導体チップをフェースアップ実装して、前記半導体チップの外部電極と前記配線板の配線をボンディングワイヤで電気的に接続する電子装置（半導体装置）に用いることもできる。
【００７８】
（実施例２）
図１３は、本発明による実施例２の配線板の概略構成を示す模式断面図である。
【００７９】
本実施例２の配線板は、図１３に示すように、絶縁体層１０１Ａ，１０１Ｂ，１０１Ｃからなる第１絶縁基板の表面及び内部に配線（導体パターン）１０２が設けられた第１配線基板１と、第２絶縁基板２０１の表面に配線（導体パターン）２０２が設けられた第２配線基板２とからなる。
【００８０】
また、前記配線板には、図１３に示したように、半導体チップを収容することが可能な大きさの凹部ＤＨが設けられている。本実施例１の配線板では、前記第１配線基板１に設けられた開口部（貫通穴）の一方の開口端を、前記第２配線基板２でふさぐことにより前記凹部ＤＨを設けている。このとき、前記第２配線基板２と前記第１配線基板１は、接着材３で接着されている。
【００８１】
また、前記第２配線基板２の配線２０２は、前記第１配線基板１が接着された面およびその裏面の両面に設けられており、各面の配線２０２は、例えば、前記第２絶縁基板２０１に設けられた接続柱２０３により電気的に接続されている。
【００８２】
また、前記第１配線基板１の配線１０２と前記第２配線基板２の配線２０２とは、図１３に示したように、突起状導体４により電気的に接続されている。またこのとき、図示は省略するが、前記第１配線基板１の配線１０２及び前記第２配線基板２の配線２０２、ならびに前記突起状導体４の周囲には、前記実施例１で説明したように、接合材５が設けられており、前記第１配線基板１の配線１０２と前記第２配線基板２の配線２０２との接続部は、前記接合材５により固定された状態になっている。
【００８３】
また、本実施例２の配線板では、前記第２配線基板２の、前記第１配線基板１が接着された面の裏面の配線２０２上にも、前記突起状導体４が設けられている。またこのとき、図示は省略するが、前記前記第１配線基板１が接着された面の裏面の配線２０２上の突起状導体４の表面にも接合材５が設けられているとする。
【００８４】
図１４及び図１５は、本実施例２の配線板の製造方法を説明するための模式図であり、図１４（ａ）は第２配線基板の突起状導体を形成する工程の断面図、図１４（ｂ）は第２配線基板の配線を形成する工程の断面図、図１５は第２配線基板上に接着材を形成する工程の断面図である。
【００８５】
本実施例２の配線板を製造する工程も、大きく分けると、図４（ａ）に示したような、絶縁体層１０１Ａ，１０１Ｂ，１０１Ｃからなり、あらかじめ定められた位置に開口部（貫通穴）ＤＨ’を有する第１絶縁基板の表面及び内部に配線１０２が設けられた第１配線基板１を形成する第１配線基板形成工程と、第２絶縁基板２０１の表面に配線２０２が設けられた第２配線基板２を形成する第２配線基板形成工程と、前記第１配線基板１と前記第２配線基板２を接着し、前記第１配線基板１の配線１０２と前記第２配線基板２の配線２０２を電気的に接続する配線基板接着工程とに分けられる。以下、本実施例２の配線板の製造方法を、図１４および図１５を参照しながら説明する。
【００８６】
前記第１配線基板形成工程は、前記実施例１で説明した手順と同様の手順であるため、説明は省略する。
【００８７】
前記第２配線基板形成工程は、まず、例えば、図１４（ａ）に示したように、接続柱２０３が形成された第２絶縁基板２の両面に、銅箔などの導体膜２０２’を張り合わせ、前記導体膜２０２’上にめっきレジスト７を形成して、例えば、電気銅めっきにより突起状導体４を形成する。
【００８８】
次に、前記めっきレジスト７を除去し、図１４（ｂ）に示すように、前記導体膜２０２’の不要な部分をエッチングで除去して配線２０２を形成する。
【００８９】
その後、図示は省略するが、前記実施例１で説明したように、前記配線２０２上および前記突起状導体４上に、例えば、錫銀合金めっきなどの接合材５を形成した後、図１５に示すように、前記第１配線基板１と接着される領域に接着材３を形成する。
【００９０】
前記手順で形成した前記第１配線基板１と前記第２配線基板２を接着する配線基板接着工程は、前記実施例１で説明した手順と同様の手順であるため、説明は省略する。
【００９１】
本実施例２の配線板の製造方法においても、前記配線板の凹部ＤＨの底面に設けられる配線は、前記第２配線基板２に形成されているので、従来の配線板の製造方法のように、絶縁基板（絶縁体層）を削らなくてもよい。そのため、前記配線板の凹部の底面に設けられる配線が削れて形状不良になるのを防ぐことができる。
【００９２】
また、前記配線板の凹部ＤＨの底面に設けられる配線、すなわち、前記第２配線基板２の配線２０２は、形状不良を起こしにくいので、微細化が容易である。
そのため、前記第２配線基板２の配線２０２を微細化、高密度化することにより、従来の配線板に比べて小型化することができる。
【００９３】
また、前記第１配線基板１の配線１０２と前記第２配線基板２の配線２０２を電気的に接続する突起状導体４は、容易に形成することができるとともに、導電性ペーストを用いた接続柱や、ビア、めっきスルーホールなどに比べて、微細化が容易である。そのため、隣り合う突起状導体４の間隔を狭くすることが容易であり、前記配線板を小型化することができる。
【００９４】
また、前記第２配線基板２の配線２０２の微細化、高密度化が容易であるため、前記第２配線基板２を薄型化でき、前記配線板の凹部の底面部分の厚さを薄くできるので、配線板を薄型化することができる。
【００９５】
図１６乃至図１８は、本実施例２の配線板を用いた電子装置の製造方法を説明するための模式図であり、図１６は本実施例２の配線板を用いた電子装置（半導体装置）の概略構成を示す断面図、図１７及び図１８は本実施例２の配線板を用いた電子装置を他の電子装置（半導体装置）と積層する工程の断面図である。
【００９６】
本実施例２の配線板を用いて電子装置（半導体装置）を製造するときには、例えば、図１６に示すように、前記配線板の凹部、すなわち、前記第１配線基板１の開口部ＤＨと前記第２配線基板２により形成された空間内に半導体チップ８を配置し、前記半導体チップ８の外部電極（図示しない）と前記配線板の凹部の底面（第２配線基板２）に設けられた配線の端子部分２０２Ａとを、例えば、はんだ接合材などのボール状端子９で電気的に接続する。また、前記配線板の凹部ＤＨの底面（第２配線基板２）と前記半導体チップ８の間は、例えば、熱硬化性樹脂などの封止材（アンダーフィル材）を流し込んで封止する。このとき、前記半導体チップ８は複数個あってもよいし、また、前記半導体チップ８以外の、抵抗素子や容量素子などのチップ状の電子部品を実装してもよい。
【００９７】
このとき、前記第２配線基板２の前記第１配線基板１が接着された面の裏面に形成された突起状導体４は、例えば、図１７に示すように、本実施例２の配線板を用いて製造した第１半導体装置ＰＫＧ１を、前記実施例１で説明した配線板を用いて製造した第２半導体装置ＰＫＧ２と積層するときに用いることができる。
【００９８】
前記第１半導体装置ＰＫＧ１と前記第２半導体装置ＰＫＧ２を積層するときには、図１７に示したように、例えば、前記第１半導体装置ＰＫＧ１に接着材３を形成し、前記第１配線基板１と前記第２配線基板２を接着する配線基板接着工程と同様の方法で積層することができ、積層後は、図１８に示すように、前記第１半導体装置ＰＫＧ１の第２配線基板２の配線２０２と、前記第２半導体装置ＰＫＧ２の第１配線基板１の配線１０２が、前記突起状導体４で電気的に接続された状態になる。このとき、前記第１半導体装置ＰＫＧ１に実装された半導体チップ８Ａと前記第２半導体装置ＰＫＧ２に実装された半導体チップ８Ｂは、同種の半導体チップであってもよいし、異なる種類の半導体チップであってもよい。
【００９９】
以上説明したように、本実施例２の配線板によれば、前記開口部（貫通穴）ＤＨ’を有する第１配線基板１と、第２配線基板２とを接着して、前記半導体チップ８を収容可能な大きさの凹部ＤＨを設けることにより、前記凹部ＤＨの底面に設けられた配線の形状不良を防ぐことができる。
【０１００】
また、前記配線板の凹部ＤＨの底面に設けられた配線の形状不良を防ぐことができるため、前記凹部ＤＨの底面に設けられる部分の配線の微細化、高密度化が容易になり、配線板を小型化、薄型化することができる。
【０１０１】
また、前記第１配線基板１の配線１０２と前記第２配線基板２の配線２０２を、前記突起状導体４で接続する場合、接続柱やビア、めっきスルーホールに比べて微細化が容易であるので、隣り合う突起状導体４の間隔を狭くし、配線板を小型化することができる。
【０１０２】
また、前記配線板を小型化、薄型化できるため、前記配線板を用いた電子装置を小型化、薄型化することができる。
【０１０３】
また、本実施例２の配線板のように、前記第２絶縁基板２の両面に配線２０２が設けられた第２配線基板２を形成し、各面の配線２０２上に前記突起状導体４を形成しておくと、前記配線板を用いて製造した電子装置（半導体装置）を、他の電子装置（半導体装置）に容易に積層することができる。
【０１０４】
また、前記実施例２の配線板では、前記接合材５として、錫銀合金などのはんだ接合材を例にあげて説明したが、これに限らず、例えば、前記接合材５として金めっきを形成してもよい。前記接合材５として金めっきを形成した場合、超音波接合により、前記第１配線基板１の配線１０２上の金めっきと前記突起状導体４上の金めっきを接合させる。
【０１０５】
また、前記実施例２の配線板では、前記接合材５を用いて、前記第１配線基板１の配線１０２と前記第２配線基板２の配線２０２の接続部を固定する例を示したが、これに限らず、前記接合材５を用いないで接続してもよい。このとき、前記接着材３には、例えば、異方性導電フィルム（ＡＣＦ）や非導電性フィルム（ＮＣＦ）を用いる。
【０１０６】
また、前記実施例２の配線板では、前記突起状導体４および前記接着材３を、前記第２配線基板２上に形成したが、これに限らず、前記第１配線基板１の配線１０２上に前記突起状導体４および前記接着材３を形成してもよい。また、前記突起状導体４と前記接着材３が、それぞれ別の配線基板に形成されていてもよい。
【０１０７】
また、前記実施例２では、前記配線板を用いた電子装置として、前記半導体チップ８をフリップチップ実装した電子装置（半導体装置）を例にあげたが、これに限らず、半導体チップをフェースアップ実装して、前記半導体チップの外部電極と前記配線板の配線をボンディングワイヤで電気的に接続する電子装置（半導体装置）に用いることもできる。
【０１０８】
以上、本発明を、前記実施例に基づき具体的に説明したが、本発明は、前記実施例に限定されるものではなく、その要旨を逸脱しない範囲において、種々変更可能であることはもちろんである。
【０１０９】
【発明の効果】
本願において開示される発明のうち、代表的なものによって得られる効果を簡単に説明すれば、以下の通りである。
【０１１０】
（１）半導体チップを実装するための凹部が設けられた配線板において、凹部の底面に設けられた配線の形状不良や露出不良を防ぐことができる。
【０１１１】
（２）半導体チップを実装するための凹部が設けられた配線板において、配線を高密度化することができる。
【０１１２】
（３）半導体チップを実装するための凹部が設けられた配線板において、配線板を小型化、薄型化することができる。
【０１１３】
（４）配線板に設けられた凹部内に半導体チップを実装した電子装置において、電子装置を小型化、薄型化することができる。
【図面の簡単な説明】
【図１】本発明による実施例１の配線板の概略構成を示す模式平面図である。
【図２】本実施例１の配線板の概略構成を示す模式図であり、図１のＡ−Ａ’線での断面図である。
【図３】本実施例１の配線板の概略構成を示す模式図であり、図２の部分拡大断面図である。
【図４】本実施例１の配線板の製造方法を説明するための模式図であり、図４（ａ）は配線板に用いる第１配線基板の断面図、図４（ｂ）は配線板に用いる第２配線基板の断面図である。
【図５】本実施例１の配線板の製造方法を説明するための模式図であり、図５（ａ）は第１配線基板のコア基板を形成する工程の断面図、図５（ｂ）は第１配線基板の配線を積層する工程の断面図である。
【図６】本実施例１の配線板の製造方法を説明するための模式図であり、第１配線基板の配線上に接合材を形成する工程の断面図である。
【図７】本実施例１の配線板の製造方法を説明するための模式図であり、図７（ａ）は第２配線基板の突起状導体を形成する工程の断面図、図７（ｂ）は第２配線基板の配線を形成する工程の断面図である。
【図８】本実施例１の配線板の製造方法を説明するための模式図であり、第２配線基板の配線上に接合材を形成する工程の断面図である。
【図９】本実施例１の配線板の製造方法を説明するための模式図であり、第２配線基板の製造方法を説明するための平面図である。
【図１０】本実施例１の配線板の製造方法を説明するための模式図であり、第１配線基板と第２配線基板を接着する工程の断面図である。
【図１１】本実施例１の配線板の製造方法を説明するための模式図であり、第１配線基板と第２配線基板を接着する工程の部分拡大断面図である。
【図１２】本実施例１の配線板を用いた電子装置の概略構成を示す模式断面図である。
【図１３】本発明による実施例２の配線板の概略構成を示す模式断面図である。
【図１４】本実施例２の配線板の製造方法を説明するための模式図であり、図１４（ａ）は第２配線基板の突起状導体を形成する工程の断面図、図１４（ｂ）は第２配線基板の配線を形成する工程の断面図である。
【図１５】本実施例２の配線板の製造方法を説明するための模式図であり、第２配線基板上に接着材を形成する工程の断面図である。
【図１６】本実施例２の配線板を用いた電子装置の概略構成を示す模式断面図である。
【図１７】本実施例２の配線板を用いた電子装置を他の電子装置（半導体装置）と積層する工程の模式断面図である。
【図１８】本実施例３の配線板を用いた電子装置を他の電子装置（半導体装置）と積層する工程の断面図である。
【図１９】従来の電子装置（半導体装置）の概略構成を示す模式平面図である。
【図２０】従来の電子装置（半導体装置）の概略構成を示す模式図であり、図１９のＢ−Ｂ’線での断面図である。
【図２１】従来の電子装置に用いる配線板の製造方法を説明するための模式断面図である。
【図２２】従来の電子装置に用いる配線板の製造方法を説明するための模式断面図である。
【図２３】従来の、他の電子装置（半導体装置）の概略構成を示す模式断面図である。
【符号の説明】
１　第１配線基板
１０１Ａ，１０１Ｂ，１０１Ｃ　絶縁体層
１０２　第１配線基板の配線
２　第２配線基板
２０１　第２絶縁基板
２０２　第２配線基板の配線
３　接着材
４　突起状導体
５　接合材
６　保護膜
７　めっきレジスト
８　半導体チップ
９　ボール状接合材
１０　封止材（アンダーフィル材）
１１　外部接続端子
１２　ボンディングワイヤ[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a wiring board and an electronic device, and a method for manufacturing a wiring board and a method for manufacturing an electronic device. More particularly, the present invention relates to a wiring board for mounting a semiconductor chip in a concave portion provided on an insulating substrate and an electronic device on which the semiconductor chip is mounted. The present invention relates to technology that is effective when applied to an apparatus.
[0002]
[Prior art]
Conventionally, in an electronic device in which electronic parts such as semiconductor chips are mounted on a wiring board provided with wiring (conductor pattern) on the surface and inside of an insulating substrate, as shown in FIGS. There is a semiconductor device (electronic device) in which a DH is provided, and a semiconductor chip 8 is mounted in a concave portion DH of the wiring board. Here, FIG. 20 is a cross-sectional view taken along line BB ′ of FIG.
[0003]
At this time, for example, as shown in FIG. 20, the wiring 102 of the wiring board is provided in the form of a layer on the surface and inside of an insulating substrate composed of the insulating layers 101A, 101B, 101C, 101D, and 101E. At this time, the wiring 102 of each layer is electrically connected, for example, by a connection pillar 103 made of a conductive paste embedded in the insulator layers 101A, 101B, 101C, 101D, and 101E, or a plated through hole or via. I have.
[0004]
As shown in FIG. 20, a terminal portion of the wiring 102 of the wiring board connected to the external electrode 801 of the semiconductor chip 8 is exposed on the bottom surface of the concave portion DH provided on the insulating substrate. The terminal portion of the wiring and the external electrode 801 of the semiconductor chip 8 are electrically connected by a ball-shaped terminal 9 such as a solder joint material. The space between the wiring board and the semiconductor chip 8 is sealed with a sealing material (underfill material) 10 such as a thermosetting resin.
[0005]
Further, in the semiconductor device, as shown in FIG. 20, for example, as shown in FIG. 20, an external part using a solder joint material is provided at a terminal portion of the wiring 102 of the wiring board connected to a wiring (connection terminal) such as a mounting board. A connection terminal 11 is provided. Further, of the wiring 102 provided on the surface of the wiring board, a portion other than the portion where the external connection terminals 11 are provided is protected by a protective film 6 such as a solder resist.
[0006]
A method of manufacturing a wiring board used in the electronic device (semiconductor device) will be briefly described. For example, first, as shown in FIG. 21, the surface of an insulating substrate formed of insulator layers 101A, 101B, 101C, 101D, and 101E and A laminate in which the wiring (conductor pattern) 102 is formed is formed. At this time, the laminate is formed by, for example, a build-up method or a batch lamination method.
[0007]
Next, the insulator layer in a region DHAR in which the concave portion of the laminate is formed is shaved, and a concave portion DH is formed in the insulating substrate as shown in FIG. At this time, the concave portion DH is formed, for example, by using a numerically controlled router, to expose a portion of the wiring 102 provided on the insulating substrate, which is connected to the external electrode of the semiconductor chip, to the bottom surface of the concave portion DH. It is formed so that
[0008]
When the electronic device (semiconductor device) as shown in FIG. 20 is formed using the wiring board, for example, a ball-shaped terminal using a solder bonding material is formed on the external electrode 801 of the semiconductor chip 8. 9 is formed, the semiconductor chip 8 is flip-chip mounted in the recess DH of the wiring board, and a sealing material (such as an underfill material) such as a thermosetting resin is provided between the wiring board and the semiconductor chip 8. ) Pour 10 in. Thereafter, the external connection terminals 11 using, for example, a solder bonding material or the like are formed on portions of the wiring 102 of the wiring board exposed on the surface.
[0009]
In the wiring board used for the electronic device (semiconductor device), instead of using the connection pillar 103 as shown in FIG. 20 for electrical connection between the wirings provided in layers, as shown in FIG. In some cases, a plated through hole PTH may be used. Further, when the semiconductor chip 8 is mounted on the wiring board, the semiconductor chip 8 is not limited to the flip-chip mounting as shown in FIG. 20, but as shown in FIG. In some cases, face-up mounting in which the electrodes 801 are connected by the bonding wires 12 is performed. When the semiconductor chip 8 is mounted face-up, although omitted in FIG. 23, the connection between the external electrode 801 of the semiconductor chip 8 and the wiring 102 is sealed with a sealing material such as a thermosetting resin. ing.
[0010]
[Problems to be solved by the invention]
However, according to the conventional technique, as shown in FIG. 21, after forming each of the insulating layers 101A, 101B, 101C, 101D, and 101E, as shown in FIG. Unnecessary portions are shaved by a router to form the concave portions DH. At this time, the amount of shaving by the router, that is, the depth of the concave portion DH of the insulating substrate is set based on the thickness of each of the insulator layers 101A, 101B, 101C, and 101D. , 101B, 101C, and 101D have variations in thickness. Therefore, when the insulator layer is shaved by a router, the wiring exposed on the bottom surface of the recess DH is shaved, or the wire is not exposed in a normal state on the bottom surface of the recess DH because the shaving amount is insufficient. There was a problem.
[0011]
In the case where the recess DH of the wiring board is formed using the router, if the wiring 102 exposed on the bottom surface of the recess DH is shaved to change its shape, the electrical characteristics will change. Therefore, in order to reduce a change in electrical characteristics due to a change in the shape of the wiring exposed on the bottom surface of the concave portion DH of the wiring board, wiring is transferred from the bottom surface of the concave portion DH to a different layer as shown in FIG. In many cases, the area of the wiring exposed and exposed on the bottom surface of the concave portion DH of the wiring board is reduced. Therefore, the wiring board has a problem that it is difficult to reduce the thickness of the bottom portion of the concave portion DH, and it is difficult to reduce the thickness of an electronic device (semiconductor device) using the wiring board.
[0012]
Further, as shown in FIG. 20 and the like, since a space is required for drawing out the wiring 102 on the bottom surface of the concave portion of the wiring board to another layer by the connection pillar 103, the wiring density of the wiring board can be increased. There is a problem that miniaturization is difficult and it is difficult to miniaturize an electronic device (semiconductor device) using the wiring board.
[0013]
Further, as shown in FIG. 23, when the wiring 102 is connected by the plated through holes PTH, it is difficult to reduce the distance between the adjacent plated through holes PTH, so that the density and the size of the wiring board are reduced. And it is difficult to reduce the size of an electronic device (semiconductor device) using the wiring board.
[0014]
SUMMARY OF THE INVENTION An object of the present invention is to provide a technique capable of preventing a wiring pattern provided on the bottom surface of a concave portion from being defective in shape and exposure in a wiring board provided with a concave portion for mounting a semiconductor chip.
[0015]
Another object of the present invention is to provide a technique capable of increasing the density of wiring in a wiring board provided with a concave portion for mounting a semiconductor chip.
[0016]
It is another object of the present invention to provide a technique capable of reducing the size and thickness of a wiring board provided with a recess for mounting a semiconductor chip.
[0017]
It is another object of the present invention to provide a technology capable of reducing the size and thickness of an electronic device in an electronic device in which a semiconductor chip is mounted in a recess provided in a wiring board.
[0018]
The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
[0019]
[Means for Solving the Problems]
The outline of the invention disclosed in the present application is as follows.
[0020]
(1) Wiring (conductor pattern) is provided on the surface and inside of the insulating substrate, the insulating substrate has a concave portion, and the wiring is formed on the surface and inside of the insulating substrate and the concave portion of the insulating substrate. A first wiring board provided with wiring on the surface and inside of a first insulating substrate having an opening of a predetermined shape, wherein the first wiring board is a wiring board provided on a bottom surface; A second wiring board provided with wiring (conductor pattern) in a region overlapping with the opening of the first insulating substrate, wherein the second wiring board covers one opening end of the opening of the first insulating substrate; The wiring board is adhered as described above.
[0021]
According to the means of (1), since the second wiring board is adhered so as to cover one opening end of the opening of the first insulating substrate, the insulating substrate is not cut off by a router or the like. A recess may be provided in the wiring board. Further, since the concave portion can be provided without shaving the insulating substrate, it is possible to prevent a defective shape or defective exposure of the wiring provided on the bottom surface of the concave portion of the wiring board.
[0022]
In addition, since it is possible to prevent the shape of the wiring provided on the bottom surface of the concave portion of the wiring board from being defective, the wiring provided on the bottom surface of the concave portion of the wiring board, that is, the wiring provided on the second wiring substrate is miniaturized, or High density can be achieved. Further, since the wiring provided on the second wiring board can be miniaturized or densified, the thickness of the second wiring board, that is, the thickness of the bottom surface of the concave portion of the wiring board is reduced. Becomes easier. Therefore, the wiring board can be reduced in thickness.
[0023]
In the means of the above (1), the wiring of the first wiring board and the wiring of the second wiring board are electrically connected by a protruding conductor, so that the wiring of the first wiring board and the second wiring board are electrically connected to each other. The connection portion of the wiring board with the wiring can be miniaturized (densified). Therefore, miniaturization of the wiring board is facilitated.
[0024]
At this time, by providing a bonding material around a connection portion between the wiring of the first wiring board and the wiring of the second wiring board, the wiring between the wiring of the first wiring board and the wiring of the second wiring board is provided. The reliability of the electrical connection is increased.
[0025]
In the means (1), if the wiring of the second wiring substrate is provided on both surfaces of the second insulating substrate, the density of the wiring of the second wiring substrate can be further increased. Further, at this time, when the protruding conductor was also provided on the wiring on the back surface of the surface to which the first wiring substrate was bonded, an electronic component was mounted in the recess of the wiring board to form a semiconductor device (electronic device). In some cases, the semiconductor device can be stacked on another electronic device (semiconductor device) by using the projecting conductor provided on the wiring on the back surface of the surface to which the first wiring substrate is bonded.
[0026]
(2) A wiring board provided with wiring (conductor pattern) on the surface and inside of the insulating substrate, and an electronic component provided on the wiring board, wherein the insulating substrate has a concave portion, and the wiring The electronic device is provided on the surface and inside of the insulating substrate, and on the bottom surface of the concave portion of the insulating substrate, and the electronic component is provided in the concave portion of the wiring board. A first wiring substrate provided with wiring on the surface and inside of a first insulating substrate having an opening of a predetermined shape, and a flat-plate-shaped second insulating substrate in a region overlapping with the opening of the first insulating substrate; An electronic device comprising a second wiring substrate provided with wiring (conductor pattern), wherein the second wiring substrate is adhered so as to cover one opening end of the opening of the first insulating substrate.
[0027]
According to the means of (2), the wiring board is bonded to the insulating substrate by a router or the like because the second wiring substrate is adhered so as to cover one opening end of the opening of the first insulating substrate. A concave portion can be provided in the wiring board without shaving. Further, since the concave portion can be provided without shaving the insulating substrate, it is possible to prevent a defective shape or defective exposure of the wiring provided on the bottom surface of the concave portion of the wiring board.
[0028]
In addition, since it is possible to prevent the shape of the wiring provided on the bottom surface of the concave portion of the wiring board from being defective, the wiring provided on the bottom surface of the concave portion of the wiring board, that is, the wiring provided on the second wiring substrate is miniaturized, or High density can be achieved. Further, since the wiring provided on the second wiring board can be miniaturized or densified, the thickness of the second wiring board, that is, the thickness of the bottom surface of the concave portion of the wiring board is reduced. Becomes easier. Therefore, the wiring board can be reduced in thickness, and the electronic device can be reduced in thickness.
[0029]
In the means of the above (2), the wiring of the first wiring board and the wiring of the second wiring board are electrically connected by a protruding conductor, so that the wiring of the first wiring board and the second wiring board are electrically connected to each other. The connection portion of the wiring board with the wiring can be miniaturized (densified). Therefore, the size of the wiring board can be easily reduced, and the size of the electronic device can be reduced.
[0030]
At this time, by providing a bonding material around a connection portion between the wiring of the first wiring board and the wiring of the second wiring board, the wiring between the wiring of the first wiring board and the wiring of the second wiring board is provided. The reliability of the electrical connection is increased.
[0031]
In the means (2), if the wiring of the second wiring board is provided on both surfaces of the second insulating substrate, the density of the wiring of the second wiring board can be further increased. Also, at this time, if the protruding conductor is also provided on the wiring on the back surface of the surface to which the first wiring substrate is bonded, the wiring on the back surface of the surface of the second wiring substrate to which the first wiring substrate is bonded is provided. The electronic device can be laminated on another electronic device by using the projecting conductor provided on the electronic device.
[0032]
(3) A method for manufacturing a wiring board in which wiring (conductor pattern) is formed on the surface and inside of the insulating substrate, wherein the opening and the predetermined shape are formed on the surface and inside of the first insulating substrate. A first wiring board forming step of forming a first wiring board having wiring formed thereon, and a second wiring board forming a second wiring board having wiring (conductor pattern) formed on the surface of a flat second insulating substrate Forming a wiring board and bonding the first wiring board and the second wiring board to each other to electrically connect the wiring of the first wiring board and the wiring of the second wiring board. The wiring board bonding step is a method of manufacturing a wiring board for bonding the second wiring board so as to cover one opening end of the opening of the first wiring board.
[0033]
According to the means of (3), the first wiring board and the second wiring board are bonded to each other, so that the opening of the first wiring board and the concave portion of the second wiring board are formed. At this time, if a part of the wiring of the second wiring board is formed so as to pass through a region overlapping with the opening of the first wiring board, a wiring board in which the wiring is exposed on the bottom surface of the concave portion can be easily manufactured. be able to. In addition, by bonding the first wiring board and the second wiring board, it is possible to prevent the wiring formed on the bottom surface of the concave portion from being defective in shape and exposure.
[0034]
Further, in the first wiring board forming step or the second wiring board forming step, a projecting conductor is formed on the wiring of the first wiring board or the wiring of the second wiring board, By electrically connecting the wiring of the wiring board and the wiring of the second wiring board with the protruding conductor, the electrical connection of the wiring is facilitated.
[0035]
In the means of the above (3), when the projecting conductor is formed, the projecting conductor is also formed on the wiring on the surface different from the bonding surface between the first wiring board and the second wiring board. In other words, when an electronic device is manufactured using the wiring board, it is easy to stack the manufactured electronic device with another electronic device.
[0036]
(4) An electronic device comprising: a wiring board forming step of forming a wiring board having a wiring (conductor pattern) formed on the surface and inside of the insulating substrate; and an electronic component mounting step of mounting an electronic component on the wiring board. Wherein the wiring board forming step comprises the steps of: forming a first wiring board provided with wiring on the surface and inside of a first insulating substrate having an opening having a predetermined shape; A method for manufacturing an electronic device, comprising: bonding a second wiring board provided with wiring (conductor pattern) on the surface of a substrate; and electrically connecting the wiring of the first wiring board and the wiring of the second wiring board. is there.
[0037]
According to the means of (4), in the step of forming the wiring board, the first wiring board and the second wiring board are bonded to each other so that the first wiring board and the opening of the first wiring board are bonded together. A recess is formed. At this time, if a part of the wiring of the second wiring board is formed so as to pass through a region overlapping with the opening of the first wiring board, the wiring board having the wiring exposed at the bottom surface of the recess can be easily formed. Can be manufactured. In addition, by bonding the first wiring board and the second wiring board, it is possible to prevent the wiring formed on the bottom surface of the concave portion from being defective in shape and exposure.
[0038]
Further, in the first wiring board forming step or the second wiring board forming step, a projecting conductor is formed on the wiring of the first wiring board or the wiring of the second wiring board, By electrically connecting the wiring of the wiring board and the wiring of the second wiring board with the protruding conductor, the electrical connection of the wiring is facilitated.
[0039]
In the means of the above (4), when the projecting conductor is formed, the projecting conductor is also formed on the wiring on the surface different from the bonding surface between the first wiring board and the second wiring board. In other words, when an electronic device is manufactured using the wiring board, it is easy to stack the manufactured electronic device with another electronic device.
[0040]
Hereinafter, the present invention will be described in detail with embodiments (examples) with reference to the drawings.
[0041]
In all the drawings for describing the embodiments, components having the same function are denoted by the same reference numerals, and the repeated description thereof will be omitted.
[0042]
BEST MODE FOR CARRYING OUT THE INVENTION
(Example 1)
1 to 3 are schematic diagrams showing a schematic configuration of a wiring board according to a first embodiment of the present invention. FIG. 1 is a plan view of the wiring board, and FIG. 2 is a cross-sectional view taken along line AA ′ of FIG. FIG. 3 is a partially enlarged sectional view of FIG.
[0043]
1 to 3, 1 is a first wiring board, 101A, 101B, and 101C are insulating layers, 102 is a wiring of the first wiring board, 2 is a second wiring board, 201 is a second insulating board, and 202 is a second wiring board. 2 Wiring of the insulating substrate, 3 is an adhesive, 4 is a protruding conductor, and 5 is a joining material.
[0044]
As shown in FIGS. 1 and 2, the wiring board according to the first embodiment includes a first insulating substrate including insulating layers 101A, 101B, and 101C. It comprises a wiring substrate 1 and a second wiring substrate 2 having a wiring (conductor pattern) 202 provided on the surface of a second insulating substrate 201.
[0045]
In addition, as shown in FIGS. 1 and 2, the wiring board is provided with a concave portion DH having a size capable of accommodating a semiconductor chip. In the wiring board according to the first embodiment, the concave portion DH is provided by closing one opening end of an opening (through hole) provided in the first wiring substrate 1 with the second wiring substrate 2. At this time, the second wiring board 2 and the first wiring board 1 are adhered with an adhesive 3.
[0046]
The wiring 102 of the first wiring board 1 and the wiring 202 of the second wiring board 2 are electrically connected by the protruding conductor 4 as shown in FIG. At this time, as shown in FIG. 3, a bonding material 5 is provided around the wiring 102 of the first wiring board 1, the wiring 202 of the second wiring board 2, and the periphery of the protruding conductor 4. The connection between the wiring 102 of the first wiring board 1 and the wiring 202 of the second wiring board 2 is fixed by the bonding material 5.
[0047]
When an electronic device (semiconductor device) is manufactured using the wiring board of the first embodiment, the semiconductor device is generally placed in a recess DH formed by the opening of the first wiring substrate 1 and the second wiring substrate 2. Accommodate chips. Therefore, a part of the wiring 202 of the second wiring board 2 is provided so as to be exposed in a region overlapping the opening of the first wiring board 1 in a plane, that is, the bottom surface of the concave portion DH. At this time, the wiring 202 is provided with, for example, a terminal portion 202A connected to an external electrode of the semiconductor chip in a region AR1 where the semiconductor chip is mounted.
[0048]
4 to 11 are schematic views for explaining the method of manufacturing the wiring board of the first embodiment, wherein FIG. 4A is a cross-sectional view of the first wiring board, and FIG. FIG. 5A is a cross-sectional view of a step of forming a core substrate of the first wiring board, FIG. 5B is a cross-sectional view of a step of stacking wiring of the first wiring board, and FIG. 7A is a cross-sectional view of a step of forming a bonding material on the wiring of one wiring board, FIG. 7A is a cross-sectional view of a step of forming a projecting conductor of the second wiring board, and FIG. FIG. 8 is a cross-sectional view of a step of forming a wiring, FIG. 8 is a cross-sectional view of a step of forming a bonding material on the wiring of the second wiring board, FIG. 9 is a plan view for explaining a method of manufacturing the second wiring board, and FIG. Is a cross-sectional view of a step of bonding the first wiring board and the second wiring board, and FIG. 11 is a partially enlarged cross-sectional view of a step of bonding the first wiring board and the second wiring board.
[0049]
The process of manufacturing the wiring board according to the first embodiment is roughly divided into, for example, as shown in FIG. 4A, insulating layers 101A, 101B, and 101C, and openings (penetrations) are formed in predetermined regions. Hole) DH ', a first wiring board forming step of forming a first wiring board 1 having a wiring 102 provided on the surface and inside of the first insulating board, and a second insulating board as shown in FIG. A second wiring board forming step of forming a second wiring board 2 having a wiring 202 provided on a surface of a substrate 201, and bonding the first wiring board 1 and the second wiring board 2 to each other; And a wiring board bonding step of electrically connecting the wiring 102 of the second wiring board 2 with the wiring 202 of the second wiring board 2. Hereinafter, a method for manufacturing the wiring board according to the first embodiment will be described with reference to FIGS.
[0050]
In the following method for manufacturing a wiring board, as shown in FIG. 4B, an adhesive 3 for bonding the first wiring board 1 and the second wiring board, and wiring of the first wiring board 1 The case where the projecting conductor 4 for electrically connecting the wiring 102 and the wiring 202 of the second wiring board 2 are formed on the second wiring board 2 will be described.
[0051]
In the first wiring substrate forming step, for example, first, as shown in FIG. 5A, a core substrate having the wiring 102 provided on both surfaces of the insulator layer 101B is formed. At this time, in the core substrate, for example, a through-hole (not shown) is formed in the insulator layer 101B, and a conductive paste is buried in the through-hole to form the connection pillar 103. Then, the connection pillar 103 is formed. A conductor film such as a copper foil is adhered to both surfaces of the insulator layer 101B, and unnecessary portions of the conductor film are removed by etching to form the wiring 102. When the wiring on both sides of the insulator layer 101B is electrically connected by vias or plated through holes instead of the connection pillar 103 made of the conductive paste, the insulator layer 101B in which a conductor film is bonded in advance is used. Then, the via and the plated through hole are formed, and then unnecessary portions of the conductor film are removed to form the wiring 102.
[0052]
Next, as shown in FIG. 5B, the wiring 102 is formed on one surface of the core substrate with the insulating layer 101A interposed therebetween, and the insulating layer 101C is also formed on the other surface. Then, the wiring 102 is formed. At this time, the wiring 102 with the insulating layers 101A and 101C interposed therebetween is bonded to the insulating layers 101A and 101C on which the connection pillars 103 are formed and the conductive film by using, for example, a build-up method. Unnecessary portions are removed by etching to form the wiring 102. When the wiring 102 is connected by a via instead of the connection pillar 103, the insulator layers 101A and 101C and the conductor film on which the connection pillar 103 is not formed are bonded to the core substrate, and the conductor film and After the insulating layers 101A and 101C are opened and vias are formed by, for example, electrolytic copper plating, unnecessary portions of the conductor film are removed to form the wirings 102.
[0053]
At this time, the wiring 102 formed on the insulator layer 101A forms, for example, a terminal portion 102A when mounted on a mounting board.
[0054]
The wiring 102 is not formed in a region DHAR in which an opening for accommodating a semiconductor chip is formed in a later step.
[0055]
Next, as shown in FIG. 6, for example, a protective film 6 for protecting a portion of the wiring 102 exposed on the surface of the insulator layer 101A other than the terminal portion 102A is formed. The bonding material 5 is formed on the wiring 102 exposed on the surface of the insulator layer 101C. At this time, the bonding material 5 is formed by, for example, tin-silver alloy plating.
[0056]
Thereafter, as shown in FIG. 5B, of the portion where the insulator layers 101A, 101B and 101C are stacked, a region DHAR for forming an opening for accommodating a semiconductor chip is formed using, for example, a mold. An opening (through hole) DH ′ as shown in FIG. 4A is formed by punching or cutting. After that, when the wafer is cut along the cutting line SL into individual pieces, the first wiring board 1 used for the wiring board of the first embodiment is obtained.
[0057]
In the second wiring substrate forming step, first, as shown in FIG. 7A, after a conductor film 202 ′ such as a copper foil is laminated on the surface of the second insulating substrate 201, Then, a plating resist 7 is formed, and the projecting conductor 4 is formed by, for example, electrolytic copper plating. At this time, the protruding conductor 4 is formed, for example, to have a height of about 25 μm.
[0058]
Next, the plating resist 7 is removed, and as shown in FIG. 7B, an unnecessary portion of the conductor film 202 'is removed by etching to form the wiring 202.
[0059]
Next, as shown in FIG. 8, for example, a protective film 6 is formed in a region other than the terminal portion 202A connected to the external terminal of the semiconductor chip of the wiring 202 and the portion where the projecting conductor 4 is formed. Then, a bonding material 5 is formed on the exposed surface of the wiring 202 and the projecting conductor 4. The bonding material 5 is formed by, for example, tin-silver alloy plating. At this time, although not shown, the bonding material 5 is also formed on the terminal portion 202A of the wiring 202 connected to the external electrode of the semiconductor chip.
[0060]
After that, when the adhesive 3 is formed around the area where the protruding conductor 4 is formed, in other words, in the area where it is bonded to the first wiring board 1, the second wiring as shown in FIG. The substrate 2 is obtained.
[0061]
In the second wiring board forming step, as the second insulating board 201, for example, as shown in FIG. 10, a tape-shaped board that is long in one direction is used, and a reel-to-reel is used. The area AR2 used as the second wiring board 2 is continuously formed by the method.
[0062]
Wiring for bonding the first wiring board 1 and the second wiring board 2 formed according to the above procedure and electrically connecting the wiring 102 of the first wiring board 1 and the wiring 202 of the second wiring board 2 In the board bonding step, as shown in FIG. 10, the first wiring board 1 formed in the above procedure is arranged on the surface of the second wiring board 2 on which the protruding conductors 4 and the adhesive 3 are formed, For example, heat pressing is performed by heating to 250 ° C. At this time, by heating to 250 ° C., the adhesive 3 is softened and the fluidity is increased. Therefore, the projecting conductor 4 pushes the adhesive 3 away, and as shown in FIG. The wiring 102 of the wiring board 1 comes into contact with the projecting conductor 4. Then, when pressing is performed in this state, the respective bonding materials 5 formed on the wirings 102 of the first wiring board 1 and on the protruding conductors 4 are melted and integrated. Therefore, when the temperature is returned to room temperature after the hot pressing, the periphery of the connection between the wiring 102 of the first wiring board 1 and the wiring 202 of the second wiring board 2 is, as shown in FIG. Thus, the wiring board according to the first embodiment can be obtained.
[0063]
When the wiring board is manufactured according to the above procedure, the wiring provided on the bottom surface of the concave portion DH of the wiring board is formed on the second wiring board 2. (Insulator layer) need not be removed. Therefore, it is possible to prevent the wiring provided on the bottom surface of the concave portion DH of the wiring board from being shaved and causing a shape defect.
[0064]
In addition, the wiring provided on the bottom surface of the concave portion DH of the wiring board, that is, the wiring 202 of the second wiring board 2 is less likely to cause a shape defect, and is therefore easily miniaturized.
Therefore, by miniaturizing and increasing the density of the wiring 202 of the second wiring board 2, the size can be reduced as compared with a conventional wiring board.
[0065]
Further, the protruding conductor 4 for electrically connecting the wiring 102 of the first wiring board 1 and the wiring 202 of the second wiring board 2 can be easily formed, and can be formed by connecting columns using a conductive paste. It is easier to miniaturize as compared to a via, a via, a plated through hole, and the like. Therefore, it is easy to narrow the interval between the adjacent protruding conductors 4, and the size of the wiring board can be reduced.
[0066]
Further, since the wiring 202 of the second wiring board 2 can be easily miniaturized and increased in density, the thickness of the second wiring board 2 can be reduced, and the thickness of the bottom portion of the concave portion DH of the wiring board can be reduced. As a result, the thickness of the wiring board can be reduced.
[0067]
FIG. 12 is a schematic cross-sectional view illustrating a schematic configuration of an electronic device using the wiring board according to the first embodiment.
[0068]
When an electronic device is manufactured using the wiring board of the first embodiment, for example, as shown in FIG. 12, a concave portion DH of the wiring board, that is, an opening (through-hole) DH ′ of the first wiring board 1 is formed. And a semiconductor chip 8 is arranged in a concave portion DH formed by the second wiring substrate 2 and an external electrode (not shown) of the semiconductor chip 8 and a bottom surface (second wiring substrate 2) of the concave portion DH of the wiring board. The terminal portion 202A of the provided wiring is electrically connected to a ball-shaped terminal 9 such as a solder bonding material. At this time, a plurality of the semiconductor chips 8 may be provided, or chip-like electronic components such as a resistance element and a capacitance element other than the semiconductor chip 8 may be mounted.
[0069]
In addition, for example, a sealing material (underfill material) such as a thermosetting resin is poured between the bottom surface of the concave portion DH (the second wiring substrate 2) of the wiring board and the semiconductor chip 8 to be sealed. External connection terminals 11 made of, for example, a solder bonding material are formed on the terminal portions 102A of the wiring on the surface of the first wiring substrate 1 of the wiring board.
[0070]
As described above, according to the wiring board of the first embodiment, the first wiring board 1 having the opening DH ′ and the second wiring board 2 can be bonded to accommodate the semiconductor chip 8. By providing the concave portion DH having the size, it is possible to prevent a defective shape of the wiring provided on the bottom surface of the concave portion DH.
[0071]
Further, since it is possible to prevent a defective shape of the wiring provided on the bottom surface of the concave portion DH of the wiring board, it is easy to miniaturize and increase the density of the wiring provided on the bottom surface of the concave portion DH. Can be reduced in size and thickness.
[0072]
Further, when the wiring 102 of the first wiring board 1 and the wiring 202 of the second wiring board 2 are connected by the projecting conductor 4, miniaturization is easier than connecting pillars, vias, and plated through holes. Therefore, the interval between the adjacent protruding conductors 4 can be reduced, and the size of the wiring board can be reduced.
[0073]
Further, since the wiring board can be reduced in size and thickness, an electronic device using the wiring board can be reduced in size and thickness.
[0074]
Further, in the wiring board of the first embodiment, the soldering material such as a tin-silver alloy has been described as an example of the bonding material 5. However, the present invention is not limited thereto. For example, gold plating is formed as the bonding material 5. May be. When gold plating is formed as the bonding material 5, the gold plating on the wiring 102 of the first wiring board 1 and the gold plating on the projecting conductor 4 are bonded by ultrasonic bonding.
[0075]
Further, in the wiring board of the first embodiment, an example in which the connection portion between the wiring 102 of the first wiring board 1 and the wiring 202 of the second wiring board 2 is fixed using the bonding material 5 has been described. The connection is not limited to this, and the connection may be performed without using the bonding material 5. At this time, for example, an anisotropic conductive film (ACF) or a non-conductive film (NCF) is used as the adhesive 3.
[0076]
In the wiring board of the first embodiment, the protruding conductors 4 and the adhesive 3 are formed on the second wiring board 2. However, the present invention is not limited to this. The protrusion-shaped conductor 4 and the adhesive 3 may be formed on the substrate. Further, the protruding conductor 4 and the adhesive 3 may be formed on different wiring boards, respectively.
[0077]
Further, in the first embodiment, as an electronic device using the wiring board, an electronic device (semiconductor device) in which the semiconductor chip 8 is flip-chip mounted is described as an example. It can also be used for an electronic device (semiconductor device) that is mounted and electrically connects the external electrodes of the semiconductor chip and the wiring of the wiring board with bonding wires.
[0078]
(Example 2)
FIG. 13 is a schematic sectional view illustrating a schematic configuration of a wiring board according to a second embodiment of the present invention.
[0079]
As shown in FIG. 13, the wiring board according to the second embodiment includes a first wiring board 1 having a wiring (conductor pattern) 102 provided on the surface and inside of a first insulating substrate including insulating layers 101A, 101B, and 101C. And the second wiring board 2 having the wiring (conductor pattern) 202 provided on the surface of the second insulating substrate 201.
[0080]
Further, as shown in FIG. 13, the wiring board is provided with a concave portion DH large enough to accommodate a semiconductor chip. In the wiring board according to the first embodiment, the concave portion DH is provided by closing one opening end of an opening (through hole) provided in the first wiring substrate 1 with the second wiring substrate 2. At this time, the second wiring board 2 and the first wiring board 1 are bonded with an adhesive 3.
[0081]
The wirings 202 of the second wiring board 2 are provided on both surfaces of the surface to which the first wiring board 1 is bonded and the back surface thereof. Are electrically connected by connecting pillars 203 provided at the center.
[0082]
Further, the wiring 102 of the first wiring board 1 and the wiring 202 of the second wiring board 2 are electrically connected by the protruding conductor 4 as shown in FIG. At this time, though not shown, the wiring 102 of the first wiring board 1, the wiring 202 of the second wiring board 2, and the periphery of the projecting conductor 4, as described in the first embodiment, The bonding material 5 is provided, and a connection portion between the wiring 102 of the first wiring board 1 and the wiring 202 of the second wiring board 2 is fixed by the bonding material 5.
[0083]
In the wiring board according to the second embodiment, the protruding conductors 4 are also provided on the wiring 202 on the back surface of the second wiring substrate 2 on the surface to which the first wiring substrate 1 is adhered. At this time, though not shown, it is assumed that the bonding material 5 is also provided on the surface of the protruding conductor 4 on the wiring 202 on the back surface of the surface to which the first wiring substrate 1 is adhered.
[0084]
14 and 15 are schematic views for explaining a method of manufacturing a wiring board according to the second embodiment. FIG. 14A is a cross-sectional view of a step of forming a projecting conductor of the second wiring board. 14B is a cross-sectional view of a step of forming wiring of the second wiring board, and FIG. 15 is a cross-sectional view of a step of forming an adhesive on the second wiring board.
[0085]
The process of manufacturing the wiring board according to the second embodiment is roughly divided into insulating layers 101A, 101B, and 101C as shown in FIG. 4A, and has openings (through holes) at predetermined positions. ) A first wiring board forming step of forming the first wiring board 1 having the wiring 102 provided on the surface and inside of the first insulating substrate having DH ′, and the wiring 202 provided on the surface of the second insulating substrate 201 A second wiring board forming step of forming a second wiring board 2; bonding the first wiring board 1 and the second wiring board 2 to each other to form a wiring 102 of the first wiring board 1 and a second wiring board 2; The process is divided into a wiring board bonding step of electrically connecting the wiring 202. Hereinafter, a method for manufacturing a wiring board according to the second embodiment will be described with reference to FIGS. 14 and 15.
[0086]
The first wiring board forming step is the same as the procedure described in the first embodiment, and a description thereof will be omitted.
[0087]
In the second wiring substrate forming step, first, as shown in FIG. 14A, for example, a conductive film 202 ′ such as a copper foil is bonded to both surfaces of the second insulating substrate 2 on which the connection pillars 203 are formed. Then, a plating resist 7 is formed on the conductor film 202 ', and the projecting conductor 4 is formed by, for example, electrolytic copper plating.
[0088]
Next, the plating resist 7 is removed, and as shown in FIG. 14B, an unnecessary portion of the conductor film 202 'is removed by etching to form a wiring 202.
[0089]
Thereafter, although not shown, as described in the first embodiment, after a bonding material 5 such as tin-silver alloy plating is formed on the wiring 202 and the protruding conductor 4, FIG. As shown, an adhesive 3 is formed in a region to be bonded to the first wiring board 1.
[0090]
The wiring board bonding step of bonding the first wiring board 1 and the second wiring board 2 formed in the above procedure is the same procedure as that described in the first embodiment, and thus the description is omitted.
[0091]
Also in the method for manufacturing a wiring board according to the second embodiment, since the wiring provided on the bottom surface of the concave portion DH of the wiring board is formed on the second wiring board 2, the wiring is provided as in the conventional method for manufacturing a wiring board. In addition, the insulating substrate (insulator layer) does not have to be shaved. For this reason, it is possible to prevent the wiring provided on the bottom surface of the concave portion of the wiring board from being scraped and causing a shape defect.
[0092]
In addition, the wiring provided on the bottom surface of the concave portion DH of the wiring board, that is, the wiring 202 of the second wiring board 2 is less likely to cause a shape defect, and is therefore easily miniaturized.
Therefore, by miniaturizing and increasing the density of the wiring 202 of the second wiring board 2, the size can be reduced as compared with a conventional wiring board.
[0093]
Further, the protruding conductor 4 for electrically connecting the wiring 102 of the first wiring board 1 and the wiring 202 of the second wiring board 2 can be easily formed, and can be formed by connecting columns using a conductive paste. It is easier to miniaturize as compared to a via, a via, a plated through hole, and the like. Therefore, it is easy to narrow the interval between the adjacent protruding conductors 4, and the size of the wiring board can be reduced.
[0094]
Further, since the wiring 202 of the second wiring board 2 can be easily miniaturized and increased in density, the second wiring board 2 can be made thinner, and the thickness of the bottom surface of the concave portion of the wiring board can be made thinner. In addition, the thickness of the wiring board can be reduced.
[0095]
16 to 18 are schematic diagrams for explaining a method of manufacturing an electronic device using the wiring board of the second embodiment. FIG. 16 is an electronic device (semiconductor device) using the wiring board of the second embodiment. 17 and 18 are cross-sectional views showing a process of laminating an electronic device using the wiring board according to the second embodiment with another electronic device (semiconductor device).
[0096]
When an electronic device (semiconductor device) is manufactured using the wiring board of the second embodiment, for example, as shown in FIG. 16, the concave portion of the wiring board, that is, the opening DH of the first wiring board 1 is The semiconductor chip 8 is arranged in the space formed by the second wiring board 2, and the external electrodes (not shown) of the semiconductor chip 8 and the wiring provided on the bottom surface of the concave portion of the wiring board (the second wiring board 2). Is electrically connected to the terminal portion 202A by a ball-shaped terminal 9 such as a solder joint material. In addition, for example, a sealing material (underfill material) such as a thermosetting resin is poured between the bottom surface of the concave portion DH (the second wiring substrate 2) of the wiring board and the semiconductor chip 8 to be sealed. At this time, a plurality of the semiconductor chips 8 may be provided, or chip-like electronic components such as a resistance element and a capacitance element other than the semiconductor chip 8 may be mounted.
[0097]
At this time, the projecting conductor 4 formed on the back surface of the surface of the second wiring substrate 2 to which the first wiring substrate 1 is adhered is, for example, as shown in FIG. The first semiconductor device PKG1 manufactured by using the same can be used when the second semiconductor device PKG2 manufactured by using the wiring board described in the first embodiment is laminated.
[0098]
When stacking the first semiconductor device PKG1 and the second semiconductor device PKG2, as shown in FIG. 17, for example, an adhesive 3 is formed on the first semiconductor device PKG1, and the first wiring substrate 1 The second wiring board 2 can be laminated by the same method as in the wiring board bonding step of bonding. After the lamination, as shown in FIG. 18, the wiring 202 of the second wiring board 2 of the first semiconductor device PKG1 is Then, the wiring 102 of the first wiring board 1 of the second semiconductor device PKG2 is electrically connected by the protruding conductor 4. At this time, the semiconductor chip 8A mounted on the first semiconductor device PKG1 and the semiconductor chip 8B mounted on the second semiconductor device PKG2 may be the same type of semiconductor chip or different types of semiconductor chips. You may.
[0099]
As described above, according to the wiring board of the second embodiment, the first wiring board 1 having the opening (through-hole) DH ′ and the second wiring board 2 are bonded to each other to form the semiconductor chip 8. By providing the concave portion DH having a size capable of accommodating the above, it is possible to prevent a defective shape of the wiring provided on the bottom surface of the concave portion DH.
[0100]
Further, since it is possible to prevent a defective shape of the wiring provided on the bottom surface of the concave portion DH of the wiring board, it is easy to miniaturize and increase the density of the wiring provided on the bottom surface of the concave portion DH. Can be reduced in size and thickness.
[0101]
Further, when the wiring 102 of the first wiring board 1 and the wiring 202 of the second wiring board 2 are connected by the projecting conductor 4, miniaturization is easier than connecting pillars, vias, and plated through holes. Therefore, the interval between the adjacent protruding conductors 4 can be reduced, and the size of the wiring board can be reduced.
[0102]
Further, since the wiring board can be reduced in size and thickness, an electronic device using the wiring board can be reduced in size and thickness.
[0103]
Further, like the wiring board of the second embodiment, a second wiring board 2 having wirings 202 provided on both surfaces of the second insulating substrate 2 is formed, and the projecting conductors 4 are formed on the wirings 202 on each surface. When formed, an electronic device (semiconductor device) manufactured using the wiring board can be easily stacked on another electronic device (semiconductor device).
[0104]
Further, in the wiring board of the second embodiment, the soldering material such as a tin-silver alloy has been described as an example of the bonding material 5. However, the present invention is not limited to this. For example, gold plating is formed as the bonding material 5. May be. When gold plating is formed as the bonding material 5, the gold plating on the wiring 102 of the first wiring board 1 and the gold plating on the projecting conductor 4 are bonded by ultrasonic bonding.
[0105]
Further, in the wiring board of the second embodiment, an example is shown in which the connecting portion between the wiring 102 of the first wiring board 1 and the wiring 202 of the second wiring board 2 is fixed using the bonding material 5. The connection is not limited to this, and the connection may be performed without using the bonding material 5. At this time, for example, an anisotropic conductive film (ACF) or a non-conductive film (NCF) is used as the adhesive 3.
[0106]
In the wiring board of the second embodiment, the protruding conductors 4 and the adhesive 3 are formed on the second wiring board 2. However, the present invention is not limited to this. The protruding conductors 4 and the adhesive 3 may be formed on the substrate. Further, the protruding conductor 4 and the adhesive 3 may be formed on different wiring boards, respectively.
[0107]
Further, in the second embodiment, as the electronic device using the wiring board, an electronic device (semiconductor device) in which the semiconductor chip 8 is flip-chip mounted is described as an example. It can also be used for an electronic device (semiconductor device) that is mounted and electrically connects the external electrodes of the semiconductor chip and the wiring of the wiring board with bonding wires.
[0108]
As described above, the present invention has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and it is needless to say that various modifications can be made without departing from the gist of the invention. is there.
[0109]
【The invention's effect】
The effects obtained by typical aspects of the invention disclosed in the present application will be briefly described as follows.
[0110]
(1) In a wiring board provided with a concave portion for mounting a semiconductor chip, it is possible to prevent a defective shape or exposure of a wiring provided on a bottom surface of the concave portion.
[0111]
(2) In a wiring board provided with a concave portion for mounting a semiconductor chip, the density of wiring can be increased.
[0112]
(3) In a wiring board provided with a recess for mounting a semiconductor chip, the size and thickness of the wiring board can be reduced.
[0113]
(4) In an electronic device in which a semiconductor chip is mounted in a recess provided in a wiring board, the size and thickness of the electronic device can be reduced.
[Brief description of the drawings]
FIG. 1 is a schematic plan view illustrating a schematic configuration of a wiring board according to a first embodiment of the present invention.
FIG. 2 is a schematic diagram illustrating a schematic configuration of the wiring board according to the first embodiment, and is a cross-sectional view taken along line AA ′ of FIG.
FIG. 3 is a schematic diagram illustrating a schematic configuration of a wiring board according to the first embodiment, and is a partially enlarged cross-sectional view of FIG. 2;
FIGS. 4A and 4B are schematic views for explaining a method of manufacturing the wiring board according to the first embodiment. FIG. 4A is a cross-sectional view of a first wiring board used for the wiring board, and FIG. FIG. 4 is a cross-sectional view of a second wiring board used for the first embodiment.
5A and 5B are schematic views for explaining a method of manufacturing a wiring board according to the first embodiment. FIG. 5A is a cross-sectional view of a step of forming a core substrate of a first wiring board, and FIG. FIG. 5 is a cross-sectional view of a step of stacking the wiring of the first wiring board.
FIG. 6 is a schematic view for explaining the method for manufacturing the wiring board of the first embodiment, and is a cross-sectional view of a step of forming a bonding material on the wiring of the first wiring board.
7A and 7B are schematic views for explaining a method of manufacturing the wiring board according to the first embodiment. FIG. 7A is a cross-sectional view of a step of forming a protruding conductor of a second wiring board, and FIG. () Is a cross-sectional view of the step of forming the wiring of the second wiring board.
FIG. 8 is a schematic view for explaining the method for manufacturing the wiring board of the first embodiment, and is a cross-sectional view of a step of forming a bonding material on the wiring of the second wiring board.
FIG. 9 is a schematic view for explaining the method for manufacturing the wiring board of the first embodiment, and is a plan view for explaining the method for manufacturing the second wiring board.
FIG. 10 is a schematic view for explaining the method for manufacturing the wiring board of the first embodiment, and is a cross-sectional view of a step of bonding the first wiring board and the second wiring board.
FIG. 11 is a schematic view for explaining the method for manufacturing the wiring board of the first embodiment, and is a partially enlarged cross-sectional view of a step of bonding the first wiring board and the second wiring board.
FIG. 12 is a schematic cross-sectional view illustrating a schematic configuration of an electronic device using the wiring board according to the first embodiment.
FIG. 13 is a schematic sectional view showing a schematic configuration of a wiring board according to a second embodiment of the present invention.
14A and 14B are schematic views for explaining a method of manufacturing a wiring board according to the second embodiment. FIG. 14A is a cross-sectional view of a step of forming a protruding conductor of a second wiring board, and FIG. () Is a cross-sectional view of the step of forming the wiring of the second wiring board.
FIG. 15 is a schematic view for explaining the method for manufacturing the wiring board of the second embodiment, and is a cross-sectional view of a step of forming an adhesive on the second wiring board.
FIG. 16 is a schematic cross-sectional view illustrating a schematic configuration of an electronic device using the wiring board according to the second embodiment.
FIG. 17 is a schematic cross-sectional view of a step of laminating an electronic device using the wiring board according to the second embodiment with another electronic device (semiconductor device).
FIG. 18 is a sectional view of a step of laminating an electronic device using the wiring board of the third embodiment with another electronic device (semiconductor device).
FIG. 19 is a schematic plan view illustrating a schematic configuration of a conventional electronic device (semiconductor device).
20 is a schematic diagram showing a schematic configuration of a conventional electronic device (semiconductor device), and is a cross-sectional view taken along line BB ′ of FIG.
FIG. 21 is a schematic cross-sectional view for explaining a method of manufacturing a wiring board used for a conventional electronic device.
FIG. 22 is a schematic cross-sectional view for explaining a method of manufacturing a wiring board used for a conventional electronic device.
FIG. 23 is a schematic cross-sectional view showing a schematic configuration of another conventional electronic device (semiconductor device).
[Explanation of symbols]
1 First wiring board
101A, 101B, 101C Insulator layer
102 Wiring of first wiring board
2 Second wiring board
201 second insulating substrate
202 Wiring of the second wiring board
3 adhesive
4 projecting conductor
5 Joining materials
6 Protective film
7 Plating resist
8 Semiconductor chip
9 Ball-shaped joining material
10. Sealant (underfill material)
11 External connection terminal
12 Bonding wire

Claims (16)

絶縁基板の表面及び内部に配線（導体パターン）が設けられてなり、前記絶縁基板は凹部を有し、前記配線は、前記絶縁基板の表面及び内部、ならびに前記絶縁基板の凹部の底面に設けられた配線板であって、
あらかじめ定められた形状の開口部を有する第１絶縁基板の表面及び内部に配線が設けられた第１配線基板と、
平板状の第２絶縁基板の前記第１絶縁基板の開口部と重なる領域に配線（導体パターン）が設けられた第２配線基板とからなり、
前記第２配線基板は、前記第１絶縁基板の開口部の一方の開口端をふさぐように接着されていることを特徴とする配線板。Wiring (conductor pattern) is provided on the surface and inside of the insulating substrate, the insulating substrate has a concave portion, and the wiring is provided on the surface and inside of the insulating substrate, and on the bottom surface of the concave portion of the insulating substrate. Wiring board,
A first wiring board provided with wiring on the surface and inside of a first insulating substrate having an opening of a predetermined shape;
A second wiring board in which a wiring (conductor pattern) is provided in a region of the plate-shaped second insulating substrate overlapping with the opening of the first insulating substrate;
The wiring board, wherein the second wiring board is adhered so as to cover one opening end of the opening of the first insulating substrate. 前記第１配線基板の配線と前記第２配線基板の配線は、突起状導体により電気的に接続されていることを特徴とする請求項１に記載の配線板。The wiring board according to claim 1, wherein the wiring of the first wiring board and the wiring of the second wiring board are electrically connected by a protruding conductor. 前記第１配線基板の配線と前記第２配線基板の配線との接続部の周囲に、接合材が設けられていることを特徴とする請求項１または請求項２に記載の配線板。The wiring board according to claim 1, wherein a bonding material is provided around a connection portion between the wiring of the first wiring board and the wiring of the second wiring board. 前記第２配線基板は、前記第２絶縁基板の前記第１配線基板が接着された面、及びその裏面に前記配線が設けられていることを特徴とする請求項１乃至請求項３のいずれか１項に記載の配線板。4. The second wiring substrate according to claim 1, wherein the wiring is provided on a surface of the second insulating substrate to which the first wiring substrate is bonded, and on a back surface thereof. Item 2. The wiring board according to item 1. 前記第２配線基板の、前記第１配線基板が接着された面の裏面に設けられた配線上に、突起状導体が設けられていることを特徴とする請求項４に記載の配線板。5. The wiring board according to claim 4, wherein a protruding conductor is provided on a wiring provided on a back surface of the second wiring board to which the first wiring board is adhered. 6. 絶縁基板の表面及び内部に配線（導体パターン）が設けられた配線板と、前記配線板上に設けられた電子部品とからなり、前記絶縁基板は凹部を有し、前記配線は、前記絶縁基板の表面及び内部、ならびに前記絶縁基板の凹部の底面に設けられており、前記電子部品が、前記配線板の凹部内に設けられている電子装置であって、
前記配線板は、
あらかじめ定められた形状の開口部を有する第１絶縁基板の表面及び内部に配線が設けられた第１配線基板と、
平板状の第２絶縁基板の前記第１絶縁基板の開口部と重なる領域に配線（導体パターン）が設けられた第２配線基板とからなり、
前記第２配線基板は、前記第１絶縁基板の開口部の一方の開口端をふさぐように接着されていることを特徴とする電子装置。A wiring board provided with wiring (conductor pattern) on the surface and inside of the insulating substrate; and an electronic component provided on the wiring board, wherein the insulating substrate has a concave portion, and the wiring comprises the insulating substrate. An electronic device, wherein the electronic component is provided in the concave portion of the wiring board, wherein the electronic component is provided on the surface and inside of the concave portion of the insulating substrate.
The wiring board,
A first wiring board provided with wiring on the surface and inside of a first insulating substrate having an opening of a predetermined shape;
A second wiring board in which a wiring (conductor pattern) is provided in a region of the plate-shaped second insulating substrate overlapping with the opening of the first insulating substrate;
The electronic device according to claim 1, wherein the second wiring board is adhered so as to cover one opening end of the opening of the first insulating substrate. 前記第１配線基板の配線と前記第２配線基板の配線は、突起状導体で電気的に接続されていることを特徴とする請求項６に記載の電子装置。The electronic device according to claim 6, wherein the wiring of the first wiring board and the wiring of the second wiring board are electrically connected by a protruding conductor. 前記第１配線基板の配線と前記第２配線基板の配線との接続部の周囲に接合材が設けられていることを特徴とする請求項６または請求項７に記載の電子装置。8. The electronic device according to claim 6, wherein a bonding material is provided around a connection between the wiring of the first wiring board and the wiring of the second wiring board. 9. 前記第２配線基板の配線は、前記第２絶縁基板の前記第１配線基板が接着された面、及びその裏面に設けられていることを特徴とする請求項６乃至請求項８のいずれか１項に記載の電子装置。9. The wiring according to claim 6, wherein the wiring of the second wiring substrate is provided on a surface of the second insulating substrate to which the first wiring substrate is bonded, and on a back surface thereof. An electronic device according to the item. 前記第２配線基板の、前記第１配線基板が接着された面の裏面の配線上に、突起状導体が設けられていることを特徴とする請求項９に記載の電子装置。The electronic device according to claim 9, wherein a protruding conductor is provided on a wiring on a back surface of the second wiring substrate to which the first wiring substrate is adhered. 絶縁基板の表面および内部に配線（導体パターン）が形成された配線板の製造方法であって、
あらかじめ定められた形状の開口部が形成された第１絶縁基板の表面および内部に配線が形成された第１配線基板を形成する第１配線基板形成工程と、
平板状の第２絶縁基板の表面に配線（導体パターン）が形成された第２配線基板を形成する第２配線基板形成工程と、
前記第１配線基板と前記第２配線基板とを接着して、前記第１配線基板の配線と前記第２配線基板の配線とを電気的に接続する配線基板接着工程とを備え、
前記配線基板接着工程は、前記第２配線基板を、前記第１配線基板の開口部の一方の開口端をふさぐように接着することを特徴とする配線板の製造方法。A method for manufacturing a wiring board having wiring (conductor pattern) formed on the surface and inside of an insulating substrate,
A first wiring board forming step of forming a first wiring board in which wiring is formed on the surface and inside of the first insulating substrate in which an opening having a predetermined shape is formed;
A second wiring board forming step of forming a second wiring board in which wiring (conductor pattern) is formed on the surface of a flat second insulating substrate;
A wiring board bonding step of bonding the first wiring board and the second wiring board and electrically connecting the wiring of the first wiring board and the wiring of the second wiring board;
The method of manufacturing a wiring board, wherein the wiring board bonding step includes bonding the second wiring board so as to cover one opening end of the opening of the first wiring board. 前記第１配線基板形成工程、あるいは前記第２配線基板形成工程は、前記第１配線基板の配線、あるいは前記第２配線基板の配線上に突起状導体を形成する工程を備え、
前記配線基板接着工程は、前記第１配線基板の配線と前記第２配線基板の配線とを前記突起状導体で電気的に接続することを特徴とする請求項１１に記載の配線板の製造方法。The first wiring board forming step or the second wiring board forming step includes a step of forming a projecting conductor on the wiring of the first wiring board or the wiring of the second wiring board,
The method of manufacturing a wiring board according to claim 11, wherein in the wiring board bonding step, the wiring of the first wiring board and the wiring of the second wiring board are electrically connected by the protruding conductor. . 前記突起状導体を形成する工程の後、前記突起状導体上に接合材を形成する工程を備えることを特徴とする請求項１２に記載の配線板の製造方法。The method of manufacturing a wiring board according to claim 12, further comprising, after the step of forming the projecting conductor, a step of forming a bonding material on the projecting conductor. 絶縁基板の表面及び内部に配線（導体パターン）が形成された配線板を形成する配線板形成工程と、前記配線板上に電子部品を実装する電子部品実装工程とを備える電子装置の製造方法であって、
前記配線板形成工程は、
あらかじめ定められた形状の開口部を有する第１絶縁基板の表面及び内部に配線が設けられた第１配線基板と、平板状の第２絶縁基板の表面に配線（導体パターン）が設けられた第２配線基板とを接着し、前記第１配線基板の配線と前記第２配線基板の配線とを電気的に接続することを特徴とする電子装置の製造方法。A method of manufacturing an electronic device, comprising: a wiring board forming step of forming a wiring board having a wiring (conductor pattern) formed on the surface and inside of an insulating substrate; and an electronic component mounting step of mounting an electronic component on the wiring board. So,
The wiring board forming step,
A first wiring board having wiring provided on the surface and inside of a first insulating substrate having an opening of a predetermined shape, and a first wiring board having wiring (conductor pattern) provided on the surface of a flat second insulating substrate. 2. A method of manufacturing an electronic device, comprising: bonding a wiring substrate; and electrically connecting the wiring of the first wiring substrate and the wiring of the second wiring substrate. 前記第１配線基板形成工程、あるいは前記第２配線基板形成工程は、前記第１配線基板の配線、あるいは前記第２配線基板の配線上に突起状導体を形成する工程を備え、
前記配線基板接着工程は、前記第１配線基板の配線と前記第２配線基板の配線とを前記突起状導体で電気的に接続することを特徴とする請求項１４に記載の電子装置の製造方法。The first wiring board forming step or the second wiring board forming step includes a step of forming a projecting conductor on the wiring of the first wiring board or the wiring of the second wiring board,
15. The method according to claim 14, wherein in the wiring board bonding step, the wiring of the first wiring board and the wiring of the second wiring board are electrically connected by the protruding conductor. . 前記突起状導体を形成する工程の後、前記突起状導体上に接合材を形成する工程を備えることを特徴とする請求項１５に記載の電子装置の製造方法。The method according to claim 15, further comprising, after the step of forming the projecting conductor, a step of forming a bonding material on the projecting conductor.
JP2002229625A 2002-08-07 2002-08-07 Wiring board and electronic device, and manufacturing method of wiring board and manufacturing method of electronic device Withdrawn JP2004071858A (en)

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WO2007069606A1 (en) * 2005-12-14 2007-06-21 Shinko Electric Industries Co., Ltd. Substrate with built-in chip and method for manufacturing substrate with built-in chip
JP2011055018A (en) * 2010-12-20 2011-03-17 Fujikura Ltd Electronic device
CN105789161A (en) * 2014-12-22 2016-07-20 恒劲科技股份有限公司 Packaging structure and manufacturing method therefor

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007069606A1 (en) * 2005-12-14 2007-06-21 Shinko Electric Industries Co., Ltd. Substrate with built-in chip and method for manufacturing substrate with built-in chip
US7989707B2 (en) 2005-12-14 2011-08-02 Shinko Electric Industries Co., Ltd. Chip embedded substrate and method of producing the same
US8793868B2 (en) 2005-12-14 2014-08-05 Shinko Electric Industries Co., Ltd. Chip embedded substrate and method of producing the same
US9451702B2 (en) 2005-12-14 2016-09-20 Shinko Electric Industries Co., Ltd. Chip embedded substrate and method of producing the same
US9768122B2 (en) 2005-12-14 2017-09-19 Shinko Electric Industries Co., Ltd. Electronic part embedded substrate and method of producing an electronic part embedded substrate
US10134680B2 (en) 2005-12-14 2018-11-20 Shinko Electric Industries Co., Ltd. Electronic part embedded substrate and method of producing an electronic part embedded substrate
JP2011055018A (en) * 2010-12-20 2011-03-17 Fujikura Ltd Electronic device
CN105789161A (en) * 2014-12-22 2016-07-20 恒劲科技股份有限公司 Packaging structure and manufacturing method therefor

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