JPH10335566A - Resin-sealed semiconductor device and circuit member used therein, and manufacture of resin-sealed semiconductor device - Google Patents

Resin-sealed semiconductor device and circuit member used therein, and manufacture of resin-sealed semiconductor device

Info

Publication number
JPH10335566A
JPH10335566A JP9201001A JP20100197A JPH10335566A JP H10335566 A JPH10335566 A JP H10335566A JP 9201001 A JP9201001 A JP 9201001A JP 20100197 A JP20100197 A JP 20100197A JP H10335566 A JPH10335566 A JP H10335566A
Authority
JP
Japan
Prior art keywords
terminal
semiconductor device
resin
external
terminal portion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9201001A
Other languages
Japanese (ja)
Inventor
Yutaka Yagi
裕 八木
Yoichi Hitomi
陽一 人見
Makoto Nakamura
誠 中村
Masahito Sasaki
将人 佐々木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Dai Nippon Printing Co Ltd
Original Assignee
Dai Nippon Printing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Dai Nippon Printing Co Ltd filed Critical Dai Nippon Printing Co Ltd
Priority to JP9201001A priority Critical patent/JPH10335566A/en
Priority to US09/052,984 priority patent/US6201292B1/en
Priority to KR1019980011659A priority patent/KR100297464B1/en
Publication of JPH10335566A publication Critical patent/JPH10335566A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68377Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support with parts of the auxiliary support remaining in the finished device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

PROBLEM TO BE SOLVED: To increase a chip area in a semiconductor-device package size, to reduce the device size, and to reduce packaging area on a circuit substrate, by mounting the semiconductor device on a die pad electrically isolated from terminal parts. SOLUTION: A semiconductor device 110 is mounted on a die pad 120, with a surface opposite to a terminal 111 side surface faced down, via a die attach member 115, and attached to the die pad 120. The terminal 111 of the semiconductor device 110 and an inner terminal 132 of a terminal part 130 are electrically connected via a wire 140. Further, a part of an external terminal 134 of the terminal part 130 is exposed, and the entire device is sealed with resin 150. The internal terminal 132 for electrical connection with the terminal 111 of the semiconductor device 110 and the external terminal 134 for connection to an external circuit are integrally provided in correspondence with each other, on both surfaces of the terminal part 130. A plurality of terminal parts 130 are two-dimensionally provided within approximately one plane, electrically isolated from each other. By this arrangement, the chip area can be increased, and the size of the semiconductor device can be reduced, further, the packaging area on the circuit substrate can be reduced.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は,半導体素子を搭載
する樹脂封止型の半導体装置(プラスチックパッケー
ジ)に関し、特に、パッケージサイズの小型化に対応
し、その実装性を向上させることができる半導体装置と
その製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resin-encapsulated semiconductor device (plastic package) on which a semiconductor element is mounted, and more particularly to a semiconductor device capable of responding to a reduction in package size and improving its mountability. The present invention relates to an apparatus and a manufacturing method thereof.

【0002】[0002]

【従来の技術】近年、半導体装置は、高集積化、小型化
技術の進歩と電子機器の高性能化と軽薄短小化の傾向
(時流)から、LSIのASICに代表されるように、
ますます高集積化、高機能化になってきている。これに
伴い、リードフレームを用いた封止型の半導体装置にお
いても、その開発のトレンドが、SOJ(Small
Outline J−Leaded Package)
やQFP(Quad Flat Package)のよ
うな表面実装型のパッケージを経て、TSOP(Thi
n Small OutlinePackage)の開
発による薄型化を主軸としたパッケージの小型化へ、さ
らにはパッケージ内部の3次元化によるチップ収納効率
向上を目的としたLOC(Lead On Chip)
の構造へと進展してきた。しかし、樹脂封止型半導体装
置パッケージには、高集積化、高機能化とともに、更に
一層の多ピン化、薄型化、小型化が求めらており、上記
従来のパッケージにおいてもチップ外周部分のリードの
引き回しがあるため、パッケージの小型化に限界が見え
てきた。また、TSOP等の小型パッケージにおいて
は、リードの引き回し、ピンピッチから多ピン化に対し
ても限界が見えてきた。
2. Description of the Related Art In recent years, due to the progress of high integration and miniaturization technologies and the tendency of electronic devices to have higher performance and lighter, thinner and smaller size (current trend), semiconductor devices have been represented by LSI ASICs.
It is becoming more and more highly integrated and highly functional. Accordingly, the development trend of the encapsulated semiconductor device using the lead frame is also based on SOJ (Small).
Outline J-Leaded Package)
Through a surface mount type package such as QFP (Quad Flat Package) or TSOP (Thick Flat Package).
n Small Outline Package) to reduce the size of the package, with the main axis being thinner, and to improve chip storage efficiency by making the package three-dimensional, LOC (Lead On Chip)
Structure. However, the resin-encapsulated semiconductor device package is required to have higher integration, higher functionality, more pins, thinner, and smaller size. This has led to a limitation in miniaturization of packages. Further, in a small package such as TSOP, there is a limit to the number of pins due to lead routing and pin pitch.

【0003】[0003]

【発明が解決しようとする課題】上記のように、更なる
樹脂封止型半導体装置の高集積化、高機能化が求められ
ており、樹脂封止型半導体装置パッケージの一層の多ピ
ン化、薄型化、小型化が求められている。本発明は、こ
のような状況のもと、半導体装置パッケージサイズにお
けるチップの占有率を上げ、半導体装置の小型化に対応
させ、回路基板への実装面積を低減できる、即ち、回路
基板への実装密度を向上させることができる樹脂封止型
半導体装置を提供しようとするものである。また、同時
に従来のTSOP等の小型パッケージに困難であった更
なる多ピン化を実現しようとするものである。
As described above, further high integration and high functionality of the resin-encapsulated semiconductor device are required, and the number of pins of the resin-encapsulated semiconductor device package is increased. Thinning and miniaturization are required. Under such circumstances, the present invention can increase the occupancy of the chip in the package size of the semiconductor device, reduce the size of the semiconductor device, and reduce the mounting area on the circuit board. It is an object of the present invention to provide a resin-sealed semiconductor device capable of improving the density. At the same time, it is intended to further increase the number of pins, which has been difficult for a small package such as a conventional TSOP.

【0004】[0004]

【課題を解決するための手段】本発明の樹脂封止型半導
体装置は、エッチングにより外形加工された、半導体素
子の端子と電気的に結線するための内部端子部と、外部
回路への接続のための外部端子部とがその表裏に相対す
るように一体的に設けられた端子部を略一平面内に二次
元的に複数個、それぞれ互いに電気的に独立して配置
し、且つ端子部の内部端子と半導体素子の端子とをワイ
ヤにて電気的に接続し、端子部の外部端子の一部を外部
に露出させて樹脂封止した樹脂封止型半導体装置、また
は前記樹脂封止型半導体装置の端子部の、外部に露出し
た外部端子部の面に、回路基板等への実装のための半田
からなる外部電極を設けた樹脂封止型半導体装置であっ
て、半導体素子が、端子部とは電気的に独立したダイパ
ッド上に搭載されたものであることを特徴とするもので
ある。そして、上記において、ダイパッドの一部が外部
に露出されていることを特徴とするものである。また、
本発明の樹脂封止型半導体装置は、エッチングにより外
形加工された、半導体素子の端子と電気的に結線するた
めの内部端子部と、外部回路への接続のための外部端子
部とがその表裏に相対するように一体的に設けられた端
子部を略一平面内に二次元的に複数個、それぞれ互いに
電気的に独立して配置し、且つ端子部の内部端子と半導
体素子の端子とをワイヤにて電気的に接続し、端子部の
外部端子の一部を外部に露出させて樹脂封止した樹脂封
止型半導体装置、または前記樹脂封止型半導体装置の端
子部の、外部に露出した外部端子部の面に、回路基板等
への実装のための半田からなる外部電極を設けた樹脂封
止型半導体装置であって、端子部を二次元的に配置する
平面に沿い、各端子部が電気的に独立した状態にして、
端子部と一体的に連結したリードを設け、半導体素子が
該リード上に搭載されたものであることを特徴とするも
のである。そして、上記半導体装置において、半導体素
子の端子は半導体素子の端子面の一対の辺の略中心部線
上にそって配置されており、端子部は前記中心線を挾む
ように対向する前記一対の各辺に沿い、それぞれ設けら
れていることを特徴とするものである。
According to the present invention, there is provided a resin-encapsulated semiconductor device having an internal terminal portion, which is externally processed by etching and electrically connected to a terminal of a semiconductor element, and a connection terminal to an external circuit. A plurality of externally provided terminal portions are integrally provided so as to face each other on the front and back sides, and a plurality of terminal portions are two-dimensionally arranged substantially in a plane, each of which is electrically independent of each other, and A resin-sealed semiconductor device in which an internal terminal and a terminal of a semiconductor element are electrically connected by a wire, and a part of the external terminal of the terminal portion is exposed to the outside and resin-sealed; A resin-encapsulated semiconductor device in which an external electrode made of solder for mounting on a circuit board or the like is provided on a surface of an external terminal portion exposed to the outside of a terminal portion of the device, wherein the semiconductor element has a terminal portion. And mounted on an electrically independent die pad Is characterized in that the at it. In the above, a part of the die pad is exposed to the outside. Also,
In the resin-encapsulated semiconductor device of the present invention, the inner and outer terminals for electrical connection to the terminals of the semiconductor element and the outer terminals for connection to an external circuit are processed by etching. A plurality of terminal portions integrally provided so as to be opposed to each other are arranged two-dimensionally in a substantially one plane, each of which is electrically independent from each other, and the internal terminal of the terminal portion and the terminal of the semiconductor element are connected to each other. A resin-sealed semiconductor device that is electrically connected by a wire and partially sealed to the outside by exposing a part of the external terminal of the terminal portion to the outside, or the terminal portion of the resin-sealed semiconductor device is exposed to the outside. A resin-encapsulated semiconductor device provided with external electrodes made of solder for mounting on a circuit board or the like on the surface of the external terminal portion, wherein each terminal extends along a plane on which the terminal portion is two-dimensionally arranged. The parts are electrically independent,
A lead integrally connected to the terminal portion is provided, and the semiconductor element is mounted on the lead. In the above-mentioned semiconductor device, the terminals of the semiconductor element are arranged along a substantially central line of a pair of sides of the terminal surface of the semiconductor element, and the terminal portion is provided on each of the pair of sides facing each other so as to sandwich the center line. , And are provided respectively.

【0005】本発明の回路部材は、エッチングにより外
形加工された、半導体素子の端子と電気的に結線するた
めの内部端子部と、外部回路への接続のための外部端子
部とが、その表裏に相対するように一体的に設けたられ
た端子部を、略一平面内に複数個、それぞれ互いに独立
して配置し、各端子部が接続リードを介して、全体を保
持する外枠部に一体連結していることを特徴とするもの
である。そして、上記において、ダイパッドを有し、且
つダイパッドが、接続リードを介して、全体を保持する
外枠部に一体連結していることを特徴とするものであ
り、ダイパッドの一方の面と外部端子部の面とが同じ一
平面上に設けられていることを特徴とするものである。
また、回路部材は、ダイパッドを持たないもので、且つ
接続リードとは別の半導体素子搭載用のリードをそれぞ
れ各端子部に一体連結して設けたことを特徴とするもの
である。
In the circuit member of the present invention, the inner and outer terminals for electrical connection to the terminals of the semiconductor element and the outer terminals for connection to the external circuit are processed by etching. A plurality of terminal portions provided integrally so as to be opposed to each other are arranged in a substantially one plane independently of each other, and each terminal portion is connected to an outer frame portion holding the whole via a connection lead. It is characterized by being integrally connected. In the above, there is provided a die pad, wherein the die pad is integrally connected to an outer frame portion which holds the whole through a connection lead, and one surface of the die pad is connected to an external terminal. The surface of the portion is provided on the same one plane.
The circuit member does not have a die pad, and is provided with a lead for mounting a semiconductor element different from the connection lead, which is integrally connected to each terminal.

【0006】本発明の樹脂封止型半導体装置の製造方法
は、エッチングにより外形加工された、半導体素子の端
子と電気的に結線するための内部端子部と、外部回路へ
の接続のための外部端子部とがその表裏に相対するよう
に一体的に設けられた端子部を略一平面内に二次元的に
複数個、それぞれ互いに電気的に独立して配置し、端子
部の内部端子と半導体素子の端子とをワイヤにて電気的
に接続し、端子部の外部端子の一部を外部に露出させて
全体を樹脂封止した樹脂封止型半導体装置の製造方法、
または前記樹脂封止型半導体装置の端子部の、外部に露
出した外部端子部の面に、回路基板等への実装のための
半田からなる外部電極を設けた樹脂封止型半導体装置の
製造方法であって、少なくとも、(A)エッチング加工
にて、半導体素子の端子と電気的に結線するための内部
端子部と、外部回路への接続のための外部端子部とがそ
の表裏に相対するように一体的に設けられた端子部を略
一平面内に二次元的に複数個、それぞれ互いに独立して
配置し、各端子部が接続リードを介して全体を保持する
外枠部に一体連結している回路部材を作成する回路部材
作成工程と、(B)半導体素子を搭載する半導体素子搭
載工程と、(C)半導体素子の端子と、回路部材の内部
端子部とをワイヤにて電気的に接続するワイヤボンディ
ング工程と、(D)端子部の外部端子の一部を外部に露
出させ、樹脂封止する樹脂封止工程と、(E)回路部材
の各接続リードを切断し、外枠部を除去する外枠部分離
除去工程とを有することを特徴とするものである。そし
て、上記における回路部材が、ダイパッドを有し、且つ
ダイパッドが、接続リードを介して、全体を保持する外
枠部に一体連結しているもので、半導体素子搭載工程に
おいて、半導体素子をダイアタッチ剤によりダイパッド
部に、その端子面側でない面にて搭載するものであるこ
とを特徴とするものであり、回路部材のダイパッドは、
その一方の面と外部端子部の面とが同じ一平面上に設け
られているものであることを特徴とするものである。そ
してまた、上記樹脂封止工程において、ダイパッドの一
部を外部に露出するように、樹脂封止することを特徴と
するものである。また、回路部材が、ダイパッドをもた
ないもので、接続リードとは別の半導体素子搭載用のリ
ードをそれぞれ各端子部に一体連結して設けたもので、
且つ、半導体素子をダイアタッチ剤により前記リード
に、その端子面側でない面にて搭載するものであること
を特徴とするものである。
According to the method of manufacturing a resin-encapsulated semiconductor device of the present invention, an external terminal for electrically connecting to a terminal of a semiconductor element and an external terminal for connection to an external circuit are formed by etching. A plurality of terminal portions are provided two-dimensionally and substantially electrically independent of each other in a substantially one plane so that the terminal portions and the front and rear surfaces thereof are integrally provided. A method of manufacturing a resin-sealed semiconductor device in which the terminals of the element are electrically connected by wires, and a part of the external terminals of the terminal portion is exposed to the outside, and the whole is resin-sealed.
Alternatively, a method of manufacturing a resin-encapsulated semiconductor device in which external terminals made of solder for mounting on a circuit board or the like are provided on the surface of the external terminal portion exposed to the outside of the terminal portion of the resin-encapsulated semiconductor device At least (A) In the etching process, the internal terminal for electrically connecting to the terminal of the semiconductor element and the external terminal for connection to the external circuit are opposed to each other. A plurality of terminal parts provided integrally with each other are arranged two-dimensionally in a substantially one plane, independently of each other, and each terminal part is integrally connected to an outer frame part which holds the whole through connection leads. (B) a semiconductor element mounting step of mounting a semiconductor element, and (C) electrically connecting terminals of the semiconductor element and internal terminal portions of the circuit member by wires. A wire bonding step for connecting; (D A resin sealing step of exposing a part of the external terminal of the terminal part to the outside and sealing with a resin, and (E) an outer frame part separating and removing step of cutting each connection lead of the circuit member and removing the outer frame part. It is characterized by having. The circuit member described above has a die pad, and the die pad is integrally connected to an outer frame portion that holds the whole via connection leads, and the semiconductor element is die-attached in the semiconductor element mounting step. The die pad portion is mounted on a surface other than the terminal surface side by the agent, and the die pad of the circuit member is
One of the surfaces and the surface of the external terminal portion are provided on the same plane. Further, in the resin sealing step, resin sealing is performed so that a part of the die pad is exposed to the outside. Also, the circuit member does not have a die pad, and a lead for mounting a semiconductor element different from the connection lead is provided integrally connected to each terminal portion,
In addition, the semiconductor element is mounted on the lead by a die attach agent on a surface other than the terminal surface side.

【0007】[0007]

【作用】本発明の樹脂封止型半導体装置は、上記のよう
な構成にすることにより、半導体装置パッケージサイズ
におけるチップの占有率を上げ、半導体装置の小型化に
対応できるものとしている。即ち、半導体装置の回路基
板への実装面積を低減し、回路基板への実装密度の向上
を可能としている。また、端子部を二次元的に複数行、
複数列設けることにより、従来のTSOP等の小型パッ
ケージに困難であった更なる多ピン化の実現を可能とし
ている。外部端子部に一体的に連結した外部電極部を半
田ボールにて形成することにより、BGA(Ball
Grid Array)タイプのようにすることもでき
る。詳しくは、エッチングにより外形加工された、半導
体素子の端子と電気的に結線するための内部端子部と、
外部回路への接続のための外部端子部とその表裏に相
対するように一体的に設けられた端子部を略一平面内に
二次元的に複数個、それぞれ互いに電気的に独立して配
置し、且つ端子部の内部端子と半導体素子の端子とをワ
イヤにて電気的に接続し、端子部の外部端子の一部を外
部に露出させて樹脂封止した樹脂封止型半導体装置、ま
たは前記樹脂封止型半導体装置の端子部の、外部に露出
した外部端子部の面に、回路基板等への実装のための半
田からなる外部電極を設けた樹脂封止型半導体装置であ
って、半導体素子が、端子部とは電気的に独立したダイ
パッド上に搭載されたものであることにより、これを達
成している。また、エッチングにより外形加工された、
半導体素子の端子と電気的に結線するための内部端子部
と、外部回路への接続のための外部端子部とその表裏
に相対するように一体的に設けられた端子部を略一平面
内に二次元的に複数個、それぞれ互いに電気的に独立し
て配置し、且つ端子部の内部端子と半導体素子の端子と
をワイヤにて電気的に接続し、端子部の外部端子の一部
を外部に露出させて樹脂封止した樹脂封止型半導体装
置、または前記樹脂封止型半導体装置の端子部の、外部
に露出した外部端子部の面に、回路基板等への実装のた
めの半田からなる外部電極を設けた樹脂封止型半導体装
置であって、端子部を二次元的に配置する平面に沿い、
各端子部が電気的に独立した状態にして、端子部と一体
的に連結したリードを設け、半導体素子が該リード上に
搭載されたものであることにより、これを達成してい
る。ダイバッドに半導体素子を搭載する場合には、ダイ
パッドの一部を外部に露出させることにより、放熱性の
良いものとできる。また、上記において、半導体素子の
端子は半導体素子の端子面の一対の辺の略中心部線上に
そって配置されており、端子部は前記中心線を挾むよう
に対向する前記一対の各辺に沿い、それぞれ設けられて
おり、全体を簡単な構造とし、量産性に適した構造とし
ている。
The resin-encapsulated semiconductor device of the present invention has the above-described structure, so that the occupancy of the chip in the semiconductor device package size is increased, and the semiconductor device can be made smaller. That is, the mounting area of the semiconductor device on the circuit board is reduced, and the mounting density on the circuit board can be improved. Also, the terminal section is two-dimensionally arranged in a plurality of rows,
By providing a plurality of rows, it is possible to further increase the number of pins, which has been difficult for a small package such as a conventional TSOP. By forming an external electrode portion integrally connected to an external terminal portion with a solder ball, a BGA (Ball) is formed.
(Grid Array) type. Specifically, an internal terminal portion that is externally processed by etching and electrically connected to a terminal of the semiconductor element,
External terminal portion and is two-dimensionally a plurality substantially in one plane a terminal part provided integrally so as to face its front and back for connection to an external circuit, electrically independently of each other, respectively A resin-sealed semiconductor device in which an internal terminal of the terminal portion and a terminal of the semiconductor element are electrically connected by a wire, and a part of the external terminal of the terminal portion is exposed to the outside and resin-sealed; or A resin-encapsulated semiconductor device in which terminal portions of the resin-encapsulated semiconductor device are provided with external electrodes made of solder for mounting on a circuit board or the like on a surface of the external terminal portion exposed to the outside, This is achieved because the semiconductor element is mounted on a die pad that is electrically independent of the terminal section. Also, the outer shape processed by etching,
The internal terminal portions for terminal and electrically connecting the semiconductor element, in substantially one plane a terminal part provided integrally as an external terminal portion for connection to an external circuit is relative to the front and back A plurality of two-dimensionally arranged, electrically independent of each other, and electrically connecting the internal terminal of the terminal portion and the terminal of the semiconductor element with a wire, and partially connecting the external terminal of the terminal portion. A resin-sealed semiconductor device that is exposed to the outside and sealed with a resin, or a solder for mounting on a circuit board or the like, on a surface of an external terminal portion exposed to the outside of a terminal portion of the resin-sealed semiconductor device. A resin-encapsulated semiconductor device provided with external electrodes consisting of:
This is achieved by providing a lead integrally connected to the terminal portion with each terminal portion being electrically independent, and the semiconductor element being mounted on the lead. When a semiconductor element is mounted on a die pad, good heat dissipation can be achieved by exposing a part of the die pad to the outside. Further, in the above, the terminals of the semiconductor element are arranged along a substantially central line of a pair of sides of the terminal surface of the semiconductor element, and the terminal portions extend along each of the pair of sides facing each other so as to sandwich the center line. , Each having a simple structure and a structure suitable for mass production.

【0008】本発明の回路部材は、上記のような構成に
することにより、上記樹脂封止型半導体装置の製造を可
能とするものであるが、通常のリードフレームと同様の
エッチング工程で作製することができる。特に、回路部
材が、ダイパッドを有し、ダイパッドの一方の面と外部
端子部の面とが同じ一平面上に設けられている場合に
は、半導体装置作製における樹脂封止工程の際、外部端
子の一部を外部に露出させるが、同時にダイパッドの一
部を外部に露出しやすい。
The circuit member of the present invention, which has the above-described structure, enables the production of the above-mentioned resin-encapsulated semiconductor device. However, the circuit member is manufactured by the same etching process as that of a normal lead frame. be able to. In particular, when the circuit member has a die pad, and one surface of the die pad and the surface of the external terminal portion are provided on the same plane, the external terminal Is exposed to the outside, but at the same time, a part of the die pad is easily exposed to the outside.

【0009】本発明の樹脂封止型半導体装置の製造方法
は、上記回路部材を用いて、半導体素子を回路部に搭載
し、半導体素子の端子と回路部材の内部端子部とをワイ
ヤにて電気的に接続し、回路部材の端子部の外部端子の
一部を外部に露出させ、樹脂封止し、さらに回路部材の
各接続リードを切断し、外枠部を除去するもので、これ
により、本発明の、半導体装置の小型化が可能で、実装
性の良い樹脂封止型半導体装置の作製を可能としてい
る。
In a method of manufacturing a resin-encapsulated semiconductor device according to the present invention, a semiconductor element is mounted on a circuit portion using the circuit member, and terminals of the semiconductor element and internal terminal portions of the circuit member are electrically connected by wires. It is a thing which removes the outer frame part by connecting, electrically exposing a part of the external terminal of the terminal part of the circuit member to the outside, sealing with resin, and further cutting each connection lead of the circuit member. The semiconductor device of the present invention can be downsized and a resin-encapsulated semiconductor device with good mountability can be manufactured.

【0010】[0010]

【発明の実施の形態】本発明の樹脂封止型半導体装置を
図に基づいて説明する。はじめに、本発明の樹脂封止型
半導体装置の第1の例を挙げる。図1(a)は本発明の
樹脂封止型半導体装置の第1の例の概略断面図であり、
図1(b)はその内部の構成を透視した斜視図であり、
図1(c)はその第2の例の概略断面図である。図1
中、100、100Aは樹脂封止型半導体装置、110
は半導体素子、111は端子(パッド)、115はダイ
アタッチ材、120はダイパッド、130は端子部、1
32は内部端子部、134は外部端子部、134Aは露
出部、140はワイヤ、150は封止用樹脂、160は
銀めっき、170は半田からなる外部電極である。図1
に示す第1の例の樹脂封止型半導体装置100は、後述
するエッチングにて外形加工された回路部材を用い作製
したもので、半導体素子110を、端子(パッド)11
1側の面でない側にて、ダイパッド120にダイアタッ
チ材115を介して接着して搭載し、半導体素子110
の端子(パッド)111と端子部130の内部端子部1
32とをワイヤ140にて電気的に接続し、且つ、端子
部130の外部端子134の一部を外部に露出させ、全
体を封止用樹脂150で樹脂封止したものである。端子
部130は、半導体素子110の端子(パッド)111
と電気的に結線するための内部端子部132と、外部回
路への接続のための外部端子部134とをその表裏に相
対するように一体的に設け、略一平面内に二次元的に複
数個、それぞれ互いに電気的に独立して配置されてい
る。図1に示す第1の例の樹脂封止型半導体装置100
においては、半導体素子110の端子(パッド)111
は半導体素子110の端子面の一対の辺にそって配置さ
れており、端子部130も前記一対の辺に沿い、半導体
素子110の外側にそれぞれ設けられている。そして、
図1(a)に示す半導体装置100は、ダイパッド12
0を端子部130の厚さより薄肉にして、一面を内部端
子132の面132Aに沿うように形成したもので、そ
の外部端子134側は、外部端子134の面134Aよ
り内部端子側に凹んだ構造をしている。
DESCRIPTION OF THE PREFERRED EMBODIMENTS A resin-sealed semiconductor device according to the present invention will be described with reference to the drawings. First, a first example of the resin-sealed semiconductor device of the present invention will be described. FIG. 1A is a schematic cross-sectional view of a first example of a resin-sealed semiconductor device of the present invention,
FIG. 1B is a perspective view in which the internal configuration is seen through,
FIG. 1C is a schematic cross-sectional view of the second example. FIG.
Among them, 100 and 100A are resin-sealed semiconductor devices, 110
Is a semiconductor element, 111 is a terminal (pad), 115 is a die attach material, 120 is a die pad, 130 is a terminal portion,
32 is an internal terminal portion, 134 is an external terminal portion, 134A is an exposed portion, 140 is a wire, 150 is a sealing resin, 160 is silver plating, and 170 is an external electrode made of solder. FIG.
The resin-encapsulated semiconductor device 100 of the first example shown in FIG. 1 is manufactured using a circuit member whose outer shape has been processed by etching described later.
On the side other than the first side, the semiconductor element 110 is bonded and mounted on the die pad 120 via the die attach material 115.
Terminal (pad) 111 and internal terminal 1 of terminal 130
32 are electrically connected to each other by a wire 140, a part of the external terminal 134 of the terminal portion 130 is exposed to the outside, and the whole is resin-sealed with a sealing resin 150. The terminal section 130 is a terminal (pad) 111 of the semiconductor element 110.
An internal terminal portion 132 for electrically connecting the external terminal portion and an external terminal portion 134 for connection to an external circuit are integrally provided so as to face each other, and a plurality of two-dimensionally arranged in substantially one plane are provided. And are individually electrically independent of each other. The resin-sealed semiconductor device 100 of the first example shown in FIG.
, The terminal (pad) 111 of the semiconductor element 110
Are arranged along a pair of sides of the terminal surface of the semiconductor element 110, and the terminal portions 130 are also provided outside the semiconductor element 110 along the pair of sides. And
The semiconductor device 100 shown in FIG.
0 is thinner than the thickness of the terminal portion 130, and one surface is formed along the surface 132A of the internal terminal 132, and the external terminal 134 side is recessed toward the internal terminal from the surface 134A of the external terminal 134. You are.

【0011】図1(c)に示す第2の例の半導体装置1
00Aは、図1(a)に示す第1の例の半導体装置10
0の外部に露出した外部端子部の面134Aに半田から
なる外部電極170を設けたものであり、回路基板へ搭
載される際には、半田を溶解、固化して、外部端子部1
34が外部回路と電気的に接続される。
The semiconductor device 1 of the second example shown in FIG.
00A is the semiconductor device 10 of the first example shown in FIG.
The external electrode 170 made of solder is provided on the surface 134A of the external terminal portion exposed to the outside of the external terminal portion 1, and when mounted on a circuit board, the solder is melted and solidified to form the external terminal portion 1
34 is electrically connected to an external circuit.

【0012】図2(a)、図2(b)に示す半導体装置
は、図1(a)に示す第1の例の半導体装置100の変
形例であり、図2(c)、図2(d)に示す半導体装置
は、図1(c)に示す第2の例の半導体装置100Aの
変形例である。図2(a)に示す半導体装置100a
は、図1(a)に示す半導体装置100において、ダイ
パッド120を端子部130の厚さに形成したものであ
る。そして、図2(b)に示す半導体装置100bは、
図1(a)に示す半導体装置100において、ダイパッ
ド120を端子部130の厚さより薄肉にして、一面を
外部端子134の面134Aに沿うように形成したもの
で、その内部端子132側は、内部端子132の面より
外部端子側に凹んだ構造をしている。図2(c)に示す
半導体装置100cは、図1(c)に示す半導体装置1
00Aにおいて、ダイパッド120を端子部130の厚
さに形成し、且つ、外部端子134の面134Aに半田
からなる外部電極170を設けたものである。図2
(d)に示す半導体装置100dは、図1(c)に示す
半導体装置100Aにおいて、ダイパッド120を端子
部130の厚さより薄肉にして、一面を外部端子134
の面134Aに沿うように形成したもので、内部端子1
32側は、内部端子132の面より外部端子側に凹んだ
構造をしている。
The semiconductor device shown in FIGS. 2A and 2B is a modification of the semiconductor device 100 of the first example shown in FIG. 1A, and is a modification of the semiconductor device 100 shown in FIGS. The semiconductor device shown in d) is a modification of the semiconductor device 100A of the second example shown in FIG. The semiconductor device 100a shown in FIG.
In the semiconductor device 100 shown in FIG. 1A, the die pad 120 is formed to the thickness of the terminal portion 130. Then, the semiconductor device 100b shown in FIG.
In the semiconductor device 100 shown in FIG. 1A, the die pad 120 is made thinner than the thickness of the terminal portion 130, and one surface is formed along the surface 134A of the external terminal 134. It has a structure recessed from the surface of the terminal 132 toward the external terminal. The semiconductor device 100c shown in FIG. 2C is the same as the semiconductor device 1 shown in FIG.
At 00A, the die pad 120 is formed to have the thickness of the terminal portion 130, and the external electrode 170 made of solder is provided on the surface 134A of the external terminal 134. FIG.
A semiconductor device 100d shown in FIG. 1D has the same structure as that of the semiconductor device 100A shown in FIG.
The inner terminal 1 is formed along the surface 134A of
The side 32 has a structure recessed from the surface of the internal terminal 132 toward the external terminal.

【0013】次いで、本発明の樹脂封止型半導体装置の
第3の例を挙げる。図3(a)は本発明の樹脂封止型半
導体装置の第3の例の概略断面図であり、図3(b)は
その内部の構成を透視した斜視図であり、図3(c)は
第4の例の概略断面図である。図3中、200、200
Aは樹脂封止型半導体装置、210は半導体素子、21
1は端子(パッド)、215はダイアタッチ材、225
はリード、230は端子部、232は内部端子部、23
4は外部端子部、234Aは露出部、240はワイヤ、
250は封止用樹脂、260は銀めっき、270は半田
からなる外部電極である。図3(a)に示す半導体装置
200は、端子部230に一体的に連結したリード22
5を設け、半導体素子210をダイアタッチ材215を
介してリード225に搭載している点で、図1(a)に
示す半導体装置100と異なるが、その他の点は同じで
ある。
Next, a third example of the resin-sealed semiconductor device of the present invention will be described. FIG. 3A is a schematic sectional view of a third example of the resin-encapsulated semiconductor device of the present invention, and FIG. 3B is a perspective view showing the internal configuration of the semiconductor device, and FIG. FIG. 9 is a schematic sectional view of a fourth example. 3, 200, 200
A is a resin-sealed semiconductor device, 210 is a semiconductor element, 21
1 is a terminal (pad), 215 is a die attach material, 225
Is a lead, 230 is a terminal, 232 is an internal terminal, 23
4 is an external terminal portion, 234A is an exposed portion, 240 is a wire,
Reference numeral 250 denotes a sealing resin, 260 denotes silver plating, and 270 denotes an external electrode made of solder. The semiconductor device 200 shown in FIG. 3A has the lead 22 integrally connected to the terminal 230.
5 is provided, and the semiconductor element 210 is mounted on the lead 225 via the die attach material 215, but is different from the semiconductor device 100 shown in FIG.

【0014】図3(c)に示す第4の例の半導体装置2
00Aは、図3(a)に示す第3の例の半導体装置20
0の外部に露出した外部端子部の面234Aに半田から
なる外部電極270を設けたものであり、回路基板へ搭
載される際には、半田を溶解、固化して、外部端子部2
34が外部回路と電気的に接続される。
The semiconductor device 2 of the fourth example shown in FIG.
00A is the semiconductor device 20 of the third example shown in FIG.
An external electrode 270 made of solder is provided on the surface 234A of the external terminal portion exposed to the outside of the external terminal portion 270. When the external electrode portion 270 is mounted on a circuit board, the solder is melted and solidified to form the external terminal portion 2
34 is electrically connected to an external circuit.

【0015】尚、本発明の樹脂封止型半導体装置は、図
1、図2、図3に示すように、パッケージ面積が半導体
素子の面積と大きく変わらない、面積的に小型化された
パッケージであるが、厚み方向についても、略1.0m
m厚以下にすることができ、薄型も同時に達成できるも
のである。また、図1、図2、図3に示す例において
は、外部端子部を、半導体素子の端子部(パッド部)に
沿い2列に配列したが、半導体素子の端子の位置をその
四辺に沿い二次元的に配置し、且つ、端子部を該半導体
素子の外側に半導体素子の四辺に沿い、二次元的に配列
することにより、半導体素子の、一層の多ピン化に十分
対応できる。
The resin-encapsulated semiconductor device of the present invention is, as shown in FIGS. 1, 2 and 3, a package having a reduced area in which the package area does not largely differ from the area of the semiconductor element. However, about 1.0m in the thickness direction
m or less, and the thickness can be reduced at the same time. Also, in the examples shown in FIGS. 1, 2 and 3, the external terminals are arranged in two rows along the terminals (pads) of the semiconductor element, but the positions of the terminals of the semiconductor element are arranged along the four sides thereof. By arranging the terminals two-dimensionally and two-dimensionally arranging the terminal portions outside the semiconductor element along the four sides of the semiconductor element, it is possible to sufficiently cope with a further increase in the number of pins of the semiconductor element.

【0016】次に、本発明の回路部材を図に基づいて説
明する。本発明の回路部材は、上記本発明の半導体装置
の作製に用いられるものであるが、エッチングにより外
形加工されるもので、図4(a)、図4(b)に示すよ
うに、半導体素子の端子と電気的に結線するための内部
端子部と、外部回路への接続のための外部端子部とをそ
の表裏に相対するように一体的に設けた端子部を略一平
面内に複数個、それぞれ互いに独立して配置し、各端子
部の外側に、各端子部ないしダイパッドを接続リードを
介して一体連結し、全体を保持する外枠部を設けてい
る。図4(a)の回路部材300は、図1(a)に示す
第1の例、図1(c)に示す第2の例の半導体装置の作
製に用いられるもので、図4(a)(イ)はその平面図
を示す。また、図4(b)の回路部材305は、図3
(a)に示す第3の例、図3(c)に示す第4の例の半
導体装置の作製に用いられるもので、図4(b)(イ)
はその平面図を示す。そして、図4(a)(ロ)、図4
(b)(ロ)はそれぞれ、図4(a)(イ)、図4
(b)(イ)の、C1−C2、C3−C4における概略
断面であるが、実際には、エッチングの特性からそれぞ
れ、図4(a)(ハ)、図4(b)(ハ)のような形状
となる。尚、図2に示す半導体装置に用いられている回
路部材も、その平面形状は図4(a)(イ)に示す形状
と、基本的には同じであるが、図4(a)(イ)のC1
−C2に相当する位置におけるダイパッド部の断面形状
は異なる。図4中、300、305は回路部材、320
はダイパッド、325はリード、330は端子部、33
2は内部端子部、334は外部端子部、350は外枠
部、352は接続リードである。尚、図4中の点線領域
は、回路部材の半導体装置作製に用いられる領域を示し
ている。回路部材300(305)の材質としては42
合金(Ni42%のFe合金)、銅合金等が用いられ、
通常のリードフレームと同様、エッチングにより外形加
工できる。
Next, a circuit member of the present invention will be described with reference to the drawings. The circuit member of the present invention, which is used for manufacturing the above-described semiconductor device of the present invention, is subjected to external processing by etching, and as shown in FIGS. 4 (a) and 4 (b), a semiconductor element. A plurality of terminal parts provided integrally with an internal terminal part for electrically connecting the terminal and an external terminal part for connection to an external circuit so as to face each other in a substantially plane. Are arranged independently of each other, and outside the respective terminal portions, the respective terminal portions or die pads are integrally connected via connection leads, and an outer frame portion for holding the whole is provided. The circuit member 300 shown in FIG. 4A is used for manufacturing the semiconductor devices of the first example shown in FIG. 1A and the second example shown in FIG. (A) shows a plan view thereof. Further, the circuit member 305 in FIG.
FIGS. 4A and 4B are used for manufacturing the semiconductor device of the third example shown in FIG. 4A and the fourth example shown in FIG.
Shows a plan view thereof. 4 (a) (b), FIG.
(B) and (b) are FIGS. 4 (a) and (b), respectively.
4B is a schematic cross-section taken along lines C1-C2 and C3-C4 of FIG. 4A, but in actuality, FIGS. 4A and 4C and FIGS. It becomes such a shape. The planar shape of the circuit member used in the semiconductor device shown in FIG. 2 is basically the same as the shape shown in FIGS. ) C1
The cross-sectional shape of the die pad portion at the position corresponding to -C2 is different. 4, 300 and 305 are circuit members, and 320
Is a die pad, 325 is a lead, 330 is a terminal, 33
2 is an internal terminal, 334 is an external terminal, 350 is an outer frame, and 352 is a connection lead. Note that a dotted line region in FIG. 4 indicates a region used for manufacturing a semiconductor device of a circuit member. The material of the circuit member 300 (305) is 42
Alloy (Ni 42% Fe alloy), copper alloy, etc. are used,
As with a normal lead frame, the outer shape can be processed by etching.

【0017】次いで、図4に示す本発明の回路部材の製
造方法の例、および図2に示す半導体装置に用いられる
回路部材の製造方法の例を図に基づいて説明する。先
ず、図1(a)、図1(c)に示す第1の例、第2の例
の半導体装置に用いられる回路部材、及び図3(a)に
示す第3の例、図3(c)に示す第4の例の半導体装置
に用いられる回路部材の製造を方法を図5を基に説明す
る。尚、図5は、説明を分かり易くするため、端子部周
辺のみを示している。先ず、42合金(Ni42%のF
e合金)等からなる、回路部材の素材である厚さ0.2
mm程度の板材410を準備し、板材410の両面を脱
脂等を行い良く洗浄処理した(図5(a))後、板材4
10の両面に感光性のレジスト420を塗布し、乾燥す
る。(図5(b)) 次いで、板材410の両面から所定のパターン版を用い
てレジストの所定の部分のみに露光を行った後、現像処
理し、レジストパターンを形成する。(図5(c)) 図4(a)に示す回路部材300の作製の場合は、図5
(c)(イ)のように、レジストパターン421、42
2が形成され、図4(b)に示す回路部材305の作製
の場合は、図5(c)(ロ)のように、レジストパター
ン423、424が形成される。尚、レジストとして
は、特に限定はされないが、重クロム酸カリウムを感光
材としたガゼイン系のレジストや、東京応化株式会社製
のネガ型液状レジスト(PMERレジスト)等が使用で
きる。次いで、レジストパターンを耐腐蝕性膜として腐
蝕液にてエッチングを行い、回路部材を作製する。(図
5(d)、図5(e)) 図4(a)に示す回路部材300の作製の場合は、図5
(d)(イ)のように、エッチングが進行し、図5
(e)(イ)のようになりエッチングが完了する。ま
た、図4(b)に示す回路部材305の作製の場合は、
図5(d)(ロ)のように、エッチングが進行し、図5
(e)(ロ)のようになりエッチングは完了する。尚、
図4(a)、図4(b)に示す回路部材の製造の場合、
板材410の表裏のエッチング量を加減することによ
り、薄肉部430の厚さを調整することができる。エッ
チングは、通常、腐蝕液として塩化第二鉄水溶液を用
い、板材の両面からスプレイエッチングにて行う。この
後、レジストを剥膜して、本発明の回路部材を得る。
(図5(f)) 図5に示す方法は、図4に示す回路部材の製造方法の1
例で、これに限定はされない。
Next, an example of a method of manufacturing a circuit member of the present invention shown in FIG. 4 and an example of a method of manufacturing a circuit member used in the semiconductor device shown in FIG. 2 will be described with reference to the drawings. First, a circuit member used in the semiconductor device of the first example and the second example shown in FIGS. 1A and 1C, and a third example shown in FIG. A method of manufacturing a circuit member used in the semiconductor device of the fourth example shown in FIG. FIG. 5 shows only the periphery of the terminal portion for easy understanding of the description. First, a 42 alloy (Ni 42% F
e) and a thickness of 0.2 which is a material of the circuit member.
A plate material 410 of about mm is prepared, and both sides of the plate material 410 are degreased or the like and are thoroughly cleaned (FIG. 5A).
A photosensitive resist 420 is applied to both sides of the substrate 10 and dried. (FIG. 5B) Next, after exposing only a predetermined portion of the resist from both surfaces of the plate material 410 using a predetermined pattern plate, development processing is performed to form a resist pattern. (FIG. 5C) In the case of manufacturing the circuit member 300 shown in FIG.
(C) As shown in (a), the resist patterns 421, 42
2 are formed, and in the case of manufacturing the circuit member 305 shown in FIG. 4B, resist patterns 423 and 424 are formed as shown in FIGS. The resist is not particularly limited, but a casein-based resist using potassium dichromate as a photosensitive material, a negative-type liquid resist (PMER resist) manufactured by Tokyo Ohka Co., Ltd., or the like can be used. Next, the resist pattern is used as a corrosion-resistant film, and etching is performed with a corrosion liquid to produce a circuit member. (FIGS. 5D and 5E) In the case of manufacturing the circuit member 300 shown in FIG.
(D) As shown in (a), the etching proceeds, and FIG.
(E) As shown in (a), the etching is completed. In the case of manufacturing the circuit member 305 shown in FIG.
As shown in FIG. 5D and FIG.
(E) As shown in (b), the etching is completed. still,
In the case of manufacturing the circuit members shown in FIGS. 4A and 4B,
The thickness of the thin portion 430 can be adjusted by adjusting the amount of etching on the front and back of the plate member 410. The etching is usually performed by spray etching from both sides of the plate using an aqueous solution of ferric chloride as a corrosion liquid. Thereafter, the resist is stripped off to obtain the circuit member of the present invention.
(FIG. 5F) The method shown in FIG. 5 is one of the methods for manufacturing the circuit member shown in FIG.
By way of example, and not limitation.

【0018】次に、図1(a)に示す第1の例の半導体
装置100の変形例として挙げられている、図2
(a)、図2(c)に示す半導体装置に用いられる回路
部材、および図2(b)、図2(d)に示す半導体装置
に用いられる回路部材の製造方法を、図6を基に説明す
る。図6も、説明を分かり易くするため、端子部周辺の
みを示している。図5に示す製造方法と同様、42合金
(Ni42%のFe合金)等からなる、回路部材の素材
である厚さ0.2mm程度の板材410を準備し、板材
410の両面を脱脂等を行い良く洗浄処理した(図6
(a))後、板材410の両面に感光性のレジスト42
0を塗布し、乾燥する。(図6(b))次いで、板材4
10の両面から所定のパターン版を用いてレジストの所
定の部分のみに露光を行った後、現像処理し、レジスト
パターンを形成する。(図6(c)) 図2(a)、図2(c)に示す半導体装置に用いられる
回路部材の作製の場合は、図6(c)(イ)のように、
レジストパターン421A、422Aが形成され、図2
(b)、図2(d)に示す半導体装置に用いられる回路
部材の作製の場合は、図6(c)(ロ)のように、レジ
ストパターン423A、424Aが形成される。次い
で、レジストパターンを耐腐蝕性膜として腐蝕液にてエ
ッチングを行い、回路部材を作製する。(図6(d)、
図6(e)) 図2(a)、図2(c)に示す半導体装置に用いられる
回路部材の作製の場合は、図6(d)(イ)のように、
エッチングが進行し、図6(e)(イ)のようになりエ
ッチングが完了する。また、図2(b)、図2(d)に
示す半導体装置に用いられる回路部材の作製の場合は、
図6(d)(ロ)のように、エッチングが進行し、図6
(e)(ロ)のようになりエッチングは完了する。この
後、レジストを剥膜して、本発明の回路部材を得る。
(図6(f))
FIG. 2 shows a modification of the semiconductor device 100 of the first example shown in FIG.
(A), a circuit member used for the semiconductor device shown in FIG. 2 (c) and a method for manufacturing the circuit member used for the semiconductor device shown in FIGS. 2 (b) and 2 (d) will be described with reference to FIG. explain. FIG. 6 also shows only the periphery of the terminal portion for easy understanding. Similar to the manufacturing method shown in FIG. 5, a plate material 410 made of a 42 alloy (Ni 42% Fe alloy) or the like and having a thickness of about 0.2 mm, which is a material of a circuit member, is prepared, and both surfaces of the plate material 410 are degreased. Washing was performed well (Fig. 6
(A)) Then, the photosensitive resist 42 is applied to both sides of the plate material 410.
Apply 0 and dry. (FIG. 6B) Next, the plate material 4
After exposing only a predetermined portion of the resist using a predetermined pattern plate from both sides of 10, development processing is performed to form a resist pattern. (FIG. 6C) In the case of manufacturing a circuit member used for the semiconductor device shown in FIGS. 2A and 2C, as shown in FIGS.
The resist patterns 421A and 422A are formed.
(B) In the case of manufacturing a circuit member used for the semiconductor device shown in FIG. 2D, resist patterns 423A and 424A are formed as shown in FIGS. Next, the resist pattern is used as a corrosion-resistant film, and etching is performed with a corrosion liquid to produce a circuit member. (FIG. 6 (d),
6 (e)) In the case of manufacturing a circuit member used for the semiconductor device shown in FIGS. 2 (a) and 2 (c), as shown in FIGS.
The etching proceeds, and the etching is completed as shown in FIGS. In the case of manufacturing a circuit member used for the semiconductor device illustrated in FIGS. 2B and 2D,
As shown in FIG. 6D and FIG.
(E) As shown in (b), the etching is completed. Thereafter, the resist is stripped off to obtain the circuit member of the present invention.
(FIG. 6 (f))

【0019】上記の回路部材の製造方法は、1ケの半導
体装置を作製するために必要な回路部材1ケの製造方法
であるが、通常は生産性の面から、回路部材をエッチン
グ加工する際、図4に示す回路部材を複数個面付けした
状態で作製し、上記の工程を行う。この場合は、図4に
示す外枠部350の一部に連結する枠部(図示していな
い)をリードフレームの外側に設けて面付け状態とす
る。
The above-described method for manufacturing a circuit member is a method for manufacturing one circuit member necessary for manufacturing one semiconductor device. However, usually, from the viewpoint of productivity, etching of the circuit member is performed. Then, the circuit member shown in FIG. In this case, a frame portion (not shown) connected to a part of the outer frame portion 350 shown in FIG. 4 is provided outside the lead frame to be imposed.

【0020】次いで、本発明の半導体装置の製造方法を
図7に基づいて簡単に説明する。図4(a)に示す回路
部材300を用いた場合について説明する。先ず、図5
のようにして外形加工して作製された、図4(a)に示
す回路部材300を用意する。(図7(a)) 次いで、洗浄処理等を施した後、内部端子部332表面
部に銀めっき処理を行い、銀めっき部510を設ける。
(図7(b)) 尚、銀めっきに代え、金めっきやパラジウムめっきでも
良い。次いで、半導体素子520をダイアタッチ材52
5によりダイパッド320に、その端子面側でない面に
て搭載し、半導体素子520の端子522と、内部端子
部332の銀めっき部510とをワイヤ540にて電気
的に接続する。(図7(c)) この後、端子部330の外部端子部334の一部を外部
に露出させ、全体を封止用樹脂で樹脂封止する。(図7
(d)) 更に、必要に応じて、端子部330の露出した外部端子
部334の一面334Aに半田からなる外部電極560
を形成する。(図7(e)) 次いで、回路部材300の各接続リード352をプレス
により切断し、外枠部350を除去する。(図7(f
1)、図7(f2)) 尚、半田からなる外部電極560の作製は、スクリーン
印刷による半田ペースト塗布や、リフロー等でも、回路
基板と半導体装置との接続に必要な量の半田が得られれ
ば良い。以上、本発明の半導体装置の製造方法を説明し
たが、回路部材は、図4(a)に示すものに限定はされ
ない。
Next, a method of manufacturing a semiconductor device according to the present invention will be briefly described with reference to FIG. The case where the circuit member 300 shown in FIG. 4A is used will be described. First, FIG.
A circuit member 300 shown in FIG. (FIG. 7A) Next, after performing a cleaning process or the like, a silver plating process is performed on the surface of the internal terminal portion 332 to provide a silver plated portion 510.
(FIG. 7B) Note that gold plating or palladium plating may be used instead of silver plating. Next, the semiconductor element 520 is connected to the die attach
5, the terminal 522 of the semiconductor element 520 and the silver plating part 510 of the internal terminal part 332 are electrically connected to each other by a wire 540. (FIG. 7 (c)) Thereafter, a part of the external terminal portion 334 of the terminal portion 330 is exposed to the outside, and the whole is sealed with a sealing resin. (FIG. 7
(D) Further, if necessary, an external electrode 560 made of solder is provided on one surface 334A of the exposed external terminal portion 334 of the terminal portion 330.
To form (FIG. 7E) Next, each connection lead 352 of the circuit member 300 is cut by a press, and the outer frame portion 350 is removed. (FIG. 7 (f
1), FIG. 7 (f2)) In the production of the external electrode 560 made of solder, an amount of solder necessary for connection between the circuit board and the semiconductor device can be obtained even by solder paste application by screen printing or reflow. Good. The method of manufacturing a semiconductor device according to the present invention has been described above, but the circuit member is not limited to the one shown in FIG.

【0021】[0021]

【実施例】更に、本発明の回路部材の実施例を挙げて、
図4に基づいて説明する。図4(a)に示す回路部材3
00で、42合金(Ni42%のFe合金)からなり、
端子部の厚さを0.2mmとする回路部材を、図5に示
すエッチング方法にて作製して得た後、図7に示す半導
体装置の作製方法により、図1に示す半導体装置を作製
したが、品質的には特に問題はなかった。同様に、図4
(b)に示す回路部材305で、銅合金からなり、端子
部の厚さを0.2mm、リード部の厚さ0.05mmと
した回路部材を、図5に示すエッチング方法にて作製し
て得た後、図7に示す半導体装置の作製方法により、図
3に示す半導体装置を作製したが、特に問題はなかっ
た。
EXAMPLES Further, examples of the circuit member of the present invention will be described.
A description will be given based on FIG. Circuit member 3 shown in FIG.
00, consisting of 42 alloy (Ni 42% Fe alloy),
After obtaining a circuit member having a terminal portion having a thickness of 0.2 mm by the etching method shown in FIG. 5, the semiconductor device shown in FIG. 1 was manufactured by the semiconductor device manufacturing method shown in FIG. However, there was no particular problem in quality. Similarly, FIG.
A circuit member made of a copper alloy and having a terminal part thickness of 0.2 mm and a lead part thickness of 0.05 mm is manufactured by the etching method shown in FIG. After that, the semiconductor device shown in FIG. 3 was manufactured by the method for manufacturing a semiconductor device shown in FIG. 7, but there was no particular problem.

【0022】[0022]

【発明の効果】本発明は、上記のように、更なる樹脂封
止型半導体装置の高集積化、高機能化が求められる状況
のもと、半導体装置パッケージサイズにおけるチップの
占有率を上げ、半導体装置の小型化に対応させ、回路基
板への実装面積を低減できる、即ち、回路基板への実装
密度を向上させることができる導体装置の提供を可能と
したものである。本発明は、同時に従来のTSOP等の
小型パッケージに困難であった更なる多ピン化を実現し
た樹脂封止型半導体装置の提供を可能としたものであ
る。
According to the present invention, as described above, under the situation where higher integration and higher functionality of a resin-encapsulated semiconductor device are required, the occupation rate of a chip in a semiconductor device package size is increased. According to the present invention, it is possible to provide a conductor device capable of reducing the mounting area on a circuit board in correspondence with miniaturization of a semiconductor device, that is, improving the mounting density on a circuit board. The present invention makes it possible to provide a resin-encapsulated semiconductor device realizing a further increase in the number of pins, which has been difficult for conventional small packages such as TSOP.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の樹脂封止型半導体装置の第1の例、第
2の例を示した図
FIG. 1 shows a first example and a second example of a resin-sealed semiconductor device of the present invention.

【図2】本発明の樹脂封止型半導体装置の第1の例、第
2の例の変形例を示した図
FIG. 2 is a diagram showing a modified example of the first and second examples of the resin-sealed semiconductor device of the present invention.

【図3】本発明の樹脂封止型半導体装置の第3の例、第
4の例を示した図
FIG. 3 is a view showing a third example and a fourth example of the resin-encapsulated semiconductor device according to the present invention;

【図4】本発明の回路部材を示した図FIG. 4 is a view showing a circuit member of the present invention.

【図5】本発明の回路部材の製造工程図FIG. 5 is a manufacturing process diagram of the circuit member of the present invention.

【図6】本発明の回路部材の製造工程図FIG. 6 is a manufacturing process diagram of the circuit member of the present invention.

【図7】本発明の樹脂封止型半導体装置の製造工程図FIG. 7 is a manufacturing process diagram of the resin-encapsulated semiconductor device of the present invention.

【符号の説明】[Explanation of symbols]

100、100A 樹脂封止型半導体装置 110 半導体素子 111 端子(パッド) 115 ダイアタッチ材 120 ダイパッド 130 端子部 132 内部端子部 134 外部端子部 134A 露出面 140 ワイヤ 150 封止用樹脂 160 銀めっき 170 半田からなる外部電極 200、200A 樹脂封止型半導体装置 210 半導体素子 211 端子(パッド) 215 ダイアタッチ材 225 リード 230 端子部 232 内部端子部 234 外部端子部 234A 露出面 240 ワイヤ 250 封止用樹脂 260 銀めっき 270 半田からなる外部電極 300、305 回路部材 320 ダイパッド 325 リード 330 端子部 332 内部端子部 334 外部端子部 350 外枠部 352 接続リード 410 板材 420 レジスト 421、422、423、424 レジス
トパターン 421A、422A、423A、424A レジス
トパターン 430 薄肉部 500、500A 半導体装置 510 銀めっき 520 半導体素子 522 端子(パッド) 525 ダイアタッチ 540 ワイヤ 550 封止用樹脂 560 半田からなる外部電極
Reference Signs List 100, 100A Resin-sealed semiconductor device 110 Semiconductor element 111 Terminal (pad) 115 Die attach material 120 Die pad 130 Terminal 132 Internal terminal 134 External terminal 134A Exposed surface 140 Wire 150 Sealing resin 160 Silver plating 170 From solder External electrode 200, 200A Resin-sealed semiconductor device 210 Semiconductor element 211 Terminal (pad) 215 Die attach material 225 Lead 230 Terminal section 232 Internal terminal section 234 External terminal section 234A Exposed surface 240 Wire 250 Sealing resin 260 Silver plating 270 External electrodes made of solder 300, 305 Circuit member 320 Die pad 325 Lead 330 Terminal section 332 Internal terminal section 334 External terminal section 350 Outer frame section 352 Connection lead 410 Plate material 420 Resist 421, 22, 423, 424 Resist pattern 421A, 422A, 423A, 424A Resist pattern 430 Thin portion 500, 500A Semiconductor device 510 Silver plating 520 Semiconductor element 522 Terminal (pad) 525 Die attach 540 Wire 550 Sealing resin 560 External made of solder electrode

───────────────────────────────────────────────────── フロントページの続き (72)発明者 佐々木 将人 東京都新宿区市谷加賀町一丁目1番1号 大日本印刷株式会社内 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Masato Sasaki 1-1-1, Ichigaya-Kagacho, Shinjuku-ku, Tokyo Inside Dai Nippon Printing Co., Ltd.

Claims (13)

【特許請求の範囲】[Claims] 【請求項1】 エッチングにより外形加工された、半導
体素子の端子と電気的に結線するための内部端子部と、
外部回路への接続のための外部端子部とがその表裏に相
対するように一体的に設けられた端子部を略一平面内に
二次元的に複数個、それぞれ互いに電気的に独立して配
置し、且つ端子部の内部端子と半導体素子の端子とをワ
イヤにて電気的に接続し、端子部の外部端子の一部を外
部に露出させて樹脂封止した樹脂封止型半導体装置、ま
たは前記樹脂封止型半導体装置の端子部の、外部に露出
した外部端子部の面に、回路基板等への実装のための半
田からなる外部電極を設けた樹脂封止型半導体装置であ
って、半導体素子が、端子部とは電気的に独立したダイ
パッド上に搭載されたものであることを特徴とする樹脂
封止型半導体装置。
1. An internal terminal portion, which is externally processed by etching and electrically connected to a terminal of a semiconductor element,
External terminals for connection to an external circuit and terminals integrally provided so as to face the front and back are two-dimensionally arranged on a substantially single plane, and are electrically independent of each other. A resin-sealed semiconductor device in which an internal terminal of the terminal portion and a terminal of the semiconductor element are electrically connected by a wire, and a part of the external terminal of the terminal portion is exposed to the outside and resin-sealed; or A resin-encapsulated semiconductor device in which terminal portions of the resin-encapsulated semiconductor device are provided with external electrodes made of solder for mounting on a circuit board or the like on a surface of the external terminal portion exposed to the outside, A resin-encapsulated semiconductor device, wherein a semiconductor element is mounted on a die pad electrically independent of a terminal portion.
【請求項2】 請求項1において、ダイパッドの一部が
外部に露出されていることを特徴とする樹脂封止型半導
体装置。
2. The resin-sealed semiconductor device according to claim 1, wherein a part of the die pad is exposed to the outside.
【請求項3】 エッチングにより外形加工された、半導
体素子の端子と電気的に結線するための内部端子部と、
外部回路への接続のための外部端子部とがその表裏に相
対するように一体的に設けられた端子部を略一平面内に
二次元的に複数個、それぞれ互いに電気的に独立して配
置し、且つ端子部の内部端子と半導体素子の端子とをワ
イヤにて電気的に接続し、端子部の外部端子の一部を外
部に露出させて樹脂封止した樹脂封止型半導体装置、ま
たは前記樹脂封止型半導体装置の端子部の、外部に露出
した外部端子部の面に、回路基板等への実装のための半
田からなる外部電極を設けた樹脂封止型半導体装置であ
って、端子部を二次元的に配置する平面に沿い、各端子
部が電気的に独立した状態にして、端子部と一体的に連
結したリードを設け、半導体素子が該リード上に搭載さ
れたものであることを特徴とする樹脂封止型半導体装
置。
3. An internal terminal portion which is externally processed by etching and electrically connected to a terminal of a semiconductor element.
External terminals for connection to an external circuit and terminals integrally provided so as to face the front and back are two-dimensionally arranged on a substantially single plane, and are electrically independent of each other. A resin-sealed semiconductor device in which an internal terminal of the terminal portion and a terminal of the semiconductor element are electrically connected by a wire, and a part of the external terminal of the terminal portion is exposed to the outside and resin-sealed; or A resin-encapsulated semiconductor device in which terminal portions of the resin-encapsulated semiconductor device are provided with external electrodes made of solder for mounting on a circuit board or the like on a surface of the external terminal portion exposed to the outside, Along the plane in which the terminal portions are two-dimensionally arranged, each terminal portion is electrically independent, a lead integrally connected to the terminal portion is provided, and the semiconductor element is mounted on the lead. A resin-encapsulated semiconductor device.
【請求項4】 請求項1ないし3において、半導体素子
の端子は半導体素子の端子面の一対の辺の略中心部線上
にそって配置されており、端子部は前記中心線を挾むよ
うに対向する前記一対の各辺に沿い、それぞれ設けられ
ていることを特徴とする樹脂封止型半導体装置。
4. The semiconductor device according to claim 1, wherein the terminals of the semiconductor element are arranged along a substantially central line of a pair of sides of the terminal surface of the semiconductor element, and the terminal portions oppose each other so as to sandwich the center line. A resin-sealed semiconductor device is provided along each of the pair of sides.
【請求項5】 エッチングにより外形加工された、半導
体素子の端子と電気的に結線するための内部端子部と、
外部回路への接続のための外部端子部とが、その表裏に
相対するように一体的に設けたられた端子部を、略一平
面内に複数個、それぞれ互いに独立して配置し、各端子
部が接続リードを介して、全体を保持する外枠部に一体
連結していることを特徴とする回路部材。
5. An internal terminal portion which is externally processed by etching and electrically connected to a terminal of a semiconductor element,
An external terminal portion for connection to an external circuit and a plurality of terminal portions provided integrally so as to face each other are arranged independently in substantially one plane, and each terminal portion is provided independently. A circuit member, wherein the portion is integrally connected to an outer frame portion that holds the entire portion via a connection lead.
【請求項6】 請求項5において、ダイパッドを有し、
且つダイパッドが、接続リードを介して、全体を保持す
る外枠部に一体連結していることを特徴とする回路部
材。
6. The method according to claim 5, further comprising a die pad,
A circuit member, wherein the die pad is integrally connected to an outer frame portion that holds the whole via a connection lead.
【請求項7】 請求項6において、ダイパッドの一方の
面と外部端子部の面とが同じ一平面上に設けられている
ことを特徴とする回路部材。
7. The circuit member according to claim 6, wherein one surface of the die pad and a surface of the external terminal portion are provided on the same plane.
【請求項8】 請求項5において、ダイパッドを持たな
いもので、且つ接続リードとは別の半導体素子搭載用の
リードをそれぞれ各端子部に一体連結して設けたことを
特徴とする回路部材。
8. The circuit member according to claim 5, wherein a lead for mounting a semiconductor element, which does not have a die pad, is provided separately from the connection lead to each terminal portion.
【請求項9】 エッチングにより外形加工された、半導
体素子の端子と電気的に結線するための内部端子部と、
外部回路への接続のための外部端子部とその表裏に相
対するように一体的に設けられた端子部を略一平面内に
二次元的に複数個、それぞれ互いに電気的に独立して配
置し、端子部の内部端子と半導体素子の端子とをワイヤ
にて電気的に接続し、端子部の外部端子の一部を外部に
露出させて全体を樹脂封止した樹脂封止型半導体装置の
製造方法、または前記樹脂封止型半導体装置の端子部
の、外部に露出した外部端子部の面に、回路基板等への
実装のための半田からなる外部電極を設けた樹脂封止型
半導体装置の製造方法であって、少なくとも、(A)エ
ッチング加工にて、半導体素子の端子と電気的に結線す
るための内部端子部と、外部回路への接続のための外部
端子部とがその表裏に相対するように一体的に設けられ
た端子部を略一平面内に二次元的に複数個、それぞれ互
いに独立して配置し、各端子部が接続リードを介して全
体を保持する外枠部に一体連結している回路部材を作成
する回路部材作成工程と、(B)半導体素子を搭載する
半導体素子搭載工程と、(C)半導体素子の端子と、回
路部材の内部端子部とをワイヤにて電気的に接続するワ
イヤボンディング工程と、(D)端子部の外部端子の一
部を外部に露出させ、樹脂封止する樹脂封止工程と、
(E)回路部材の各接続リードを切断し、外枠部を除去
する外枠部分離除去工程とを有することを特徴とする樹
脂封止型半導体装置の製造方法。
9. An internal terminal portion which is externally processed by etching and electrically connected to a terminal of a semiconductor element,
External terminal portion and is two-dimensionally a plurality substantially in one plane a terminal part provided integrally so as to face its front and back for connection to an external circuit, electrically independently of each other, respectively Then, the internal terminal of the terminal portion and the terminal of the semiconductor element are electrically connected by a wire, and a part of the external terminal of the terminal portion is exposed to the outside, and the whole is resin-sealed. The manufacturing method, or a resin-sealed semiconductor device in which external terminals made of solder for mounting on a circuit board or the like are provided on the surface of the external terminal portion exposed to the outside of the terminal portion of the resin-sealed semiconductor device Wherein at least (A) an internal terminal portion for electrically connecting to a terminal of a semiconductor element and an external terminal portion for connection to an external circuit are formed on the front and back sides by etching. Terminals integrally provided to face each other A circuit member creation step of creating a circuit member in which a plurality of two-dimensionally arranged two-dimensionally independently from each other, and each terminal portion is integrally connected to an outer frame portion holding the whole via connection leads; B) a semiconductor element mounting step of mounting a semiconductor element; (C) a wire bonding step of electrically connecting terminals of the semiconductor element to internal terminals of the circuit member by wires; and (D) external parts of the terminal. A resin sealing step of exposing a part of the terminal to the outside and resin sealing;
(E) an outer frame portion separating and removing step of cutting each connection lead of the circuit member and removing the outer frame portion.
【請求項10】 請求項9における回路部材が、ダイパ
ッドを有し、且つダイパッドが、接続リードを介して、
全体を保持する外枠部に一体連結しているもので、半導
体素子搭載工程において、半導体素子をダイアタッチ剤
によりダイパッド部に、その端子面側でない面にて搭載
するものであることを特徴とする樹脂封止型半導体装置
の製造方法。
10. The circuit member according to claim 9, further comprising a die pad, wherein the die pad is connected via a connection lead.
In the semiconductor element mounting step, the semiconductor element is mounted on the die pad portion by a die attach agent on a surface other than the terminal surface side in the semiconductor element mounting step. Of manufacturing a resin-sealed semiconductor device.
【請求項11】 請求項10における回路部材のダイパ
ッドは、その一方の面と外部端子部の面とが同じ一平面
上に設けられているものであることを特徴とする樹脂封
止型半導体装置の製造方法。
11. The resin-sealed semiconductor device according to claim 10, wherein one surface of the die pad of the circuit member and the surface of the external terminal portion are provided on the same plane. Manufacturing method.
【請求項12】 請求項10ないし11における、樹脂
封止工程において、ダイパッドの一部を外部に露出する
ように、樹脂封止することを特徴とする樹脂封止型半導
体装置の製造方法。
12. The method of manufacturing a resin-encapsulated semiconductor device according to claim 10, wherein in the resin encapsulation step, the die pad is resin-encapsulated so that a part of the die pad is exposed to the outside.
【請求項13】 請求項9における回路部材が、ダイパ
ッドをもたないもので、接続リードとは別の半導体素子
搭載用のリードをそれぞれ各端子部に一体連結して設け
たもので、且つ、半導体素子をダイアタッチ剤により前
記リードに、その端子面側でない面にて搭載するもので
あることを特徴とする樹脂封止型半導体装置の製造方
法。
13. The circuit member according to claim 9, wherein the circuit member does not have a die pad, and a lead for mounting a semiconductor element different from the connection lead is provided integrally with each terminal portion, and A method of manufacturing a resin-encapsulated semiconductor device, comprising mounting a semiconductor element on a lead on a surface other than a terminal surface thereof by a die attach agent.
JP9201001A 1997-04-02 1997-07-11 Resin-sealed semiconductor device and circuit member used therein, and manufacture of resin-sealed semiconductor device Pending JPH10335566A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP9201001A JPH10335566A (en) 1997-04-02 1997-07-11 Resin-sealed semiconductor device and circuit member used therein, and manufacture of resin-sealed semiconductor device
US09/052,984 US6201292B1 (en) 1997-04-02 1998-04-01 Resin-sealed semiconductor device, circuit member used therefor
KR1019980011659A KR100297464B1 (en) 1997-04-02 1998-04-02 A resin sealed semiconductor device, a circuit member usedthereto and a method for fabricating a resin sealedsemiconductor device

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP9-97885 1997-04-02
JP9788597 1997-04-02
JP9201001A JPH10335566A (en) 1997-04-02 1997-07-11 Resin-sealed semiconductor device and circuit member used therein, and manufacture of resin-sealed semiconductor device

Related Child Applications (2)

Application Number Title Priority Date Filing Date
JP2005130978A Division JP4176092B2 (en) 1997-04-02 2005-04-28 Resin-sealed semiconductor device and manufacturing method thereof
JP2005130979A Division JP2005260271A (en) 1997-04-02 2005-04-28 Circuit member for resin-sealed semiconductor device

Publications (1)

Publication Number Publication Date
JPH10335566A true JPH10335566A (en) 1998-12-18

Family

ID=26439030

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Link
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