CN110690191A - Double-sided chip packaging structure and packaging method - Google Patents

Double-sided chip packaging structure and packaging method Download PDF

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Publication number
CN110690191A
CN110690191A CN201911069533.4A CN201911069533A CN110690191A CN 110690191 A CN110690191 A CN 110690191A CN 201911069533 A CN201911069533 A CN 201911069533A CN 110690191 A CN110690191 A CN 110690191A
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Prior art keywords
chip
pin
packaging
double
pins
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CN201911069533.4A
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Inventor
吴涛
岳茜峰
吴奇斌
吕磊
汪阳
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Changdian Technology (chuzhou) Co Ltd
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Changdian Technology (chuzhou) Co Ltd
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Priority to CN201911069533.4A priority Critical patent/CN110690191A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

The invention discloses a double-sided chip packaging structure and a packaging method, and belongs to the field of semiconductor packaging and manufacturing. Aiming at the problems of low integration level, high cost and reliability of the existing product in the prior art, the invention provides a double-sided chip packaging structure and a packaging method. The production efficiency of double-sided chip packaging products can be improved, and the time cost and the material cost are reduced.

Description

Double-sided chip packaging structure and packaging method
Technical Field
The invention relates to the field of semiconductor package manufacturing, in particular to a double-sided chip packaging structure and a packaging method.
Background
Most of the existing double-sided chip packaging structures are multi-chip packaging with a substrate as a chip carrier, and although the requirements of miniaturization and high density are met, the substrate is high in cost and is not suitable for products requiring low cost and high density.
The cost is reduced by using the lead frame as a carrier, and the existing product for carrying out chip packaging on two sides of the lead frame, such as Chinese patent CN200610029153.4, has the following method:
(1) covering a layer of thin film which is not combined with the first plastic packaging material on one surface of the lead frame;
(2) adhering the first chip to the chip seat of the lead frame through an adhesive on the other surface of the lead frame;
(3) conducting wire bonding by using the wire to complete the electrical connection between the first chip and the lead frame;
(4) the first chip, the lead on the surface of the first chip and part of the inner pins are coated by the first plastic package material;
(5) solidifying the first plastic packaging material;
(6) removing the film covering the lead frame;
(7) adhering a second chip on one surface of the lead frame by using the method in the step (2);
(8) completing the electrical connection between the second chip and the lead frame by using the method in the step (3);
(9) coating the first plastic packaging material, the second chip, the lead on the surface of the second chip and the inner pin in the lead frame by using a second plastic packaging material;
(10) solidifying the second plastic packaging material;
(11) and cutting and pin processing the whole packaging structure.
As in chinese patent CN200610029153.4, after plastic package is completed, the whole package structure needs to be punched and molded: firstly, plastic punching is carried out, excessive glue overflowing around the plastic package body is removed by utilizing a blade, and then the outer pin is bent towards the direction of the circuit board to form a shoulder part and a welding surface of the support. The outer pin structure is required to be arranged on the layout of the lead frame, and the outer pins occupy small area, so that the method is not beneficial to arranging more product units on the lead frame, is not high in arrangement density, is not beneficial to improving the production efficiency of products, and is not beneficial to reducing the time cost and the material cost. In addition, the welding surface of the outer pin is not covered by a tin layer due to the product cutting operation, so that the subsequent product patch mounting link is not firm in patch mounting, a false solder is produced, an open circuit is formed, and the mounting reliability is reduced.
Disclosure of Invention
1. Technical problem to be solved
Aiming at the problems of low integration level, high cost and reliability of the existing products in the prior art, the invention provides a double-sided chip packaging structure and a packaging method, which can improve the production efficiency of double-sided chip packaging products and reduce the time cost and the material cost.
2. Technical scheme
The purpose of the invention is realized by the following technical scheme.
A double-sided chip packaging structure comprises a packaging substrate, wherein a plurality of pins are arranged on two opposite sides or the periphery of the packaging substrate, the pins are divided into front pins and back pins, and the front pins and the back pins are not communicated with each other;
the side faces of the pins and the pin bulges connected with the side faces of the pins are arranged on the side, far away from the chip, of the front pin and the back pin;
the packaging substrate is provided with a front chip, and the front chip is electrically connected with the front pins through an electrical connection part;
the packaging substrate is provided with a back chip, and the back chip is electrically connected with the back pins through an electrical connection part;
the packaging material wraps the front chip, the back chip, the electric connection part, the region between the front pin and the back pin, at least part of the back of the front pin is exposed out of the plastic package body, and part of the back pin is exposed out of the plastic package body. .
Furthermore, the chip packaging structure further comprises a base island, wherein the front chip is arranged on the front side of the base island and/or the back chip is arranged on the back side of the base island.
Furthermore, the back pin is provided with a section of extension part close to the chip.
Furthermore, the back pin is arranged on the inner side of the front pin.
Furthermore, the front chip is a ball bonding chip or a flip chip, and the back chip is a ball bonding chip or a flip chip.
Furthermore, the electrical connection part is a solder ball and a bonding wire.
A packaging method of a double-sided chip packaging structure comprises the steps of packaging a front-sided chip, selecting a packaging substrate, half-etching the front side of the packaging substrate, mounting a front-side chip, and completing the mounting of the front-side chip after routing and packaging; the method also comprises the following steps of,
performing half etching on the back of a packaging substrate to form a front pin communicated with a front chip, a back pin communicated with the back chip, a pin side face arranged on one side of the front pin and the back pin far away from the chip, and a pin protrusion connected with the pin side face, wherein the front pin and the back pin are not electrically communicated with each other;
secondly, brushing ink on the back of the packaging substrate subjected to back half etching, exposing by using a film, removing all the ink in the region of the pin position to expose the front pin, the back pin and the metal surface with the protruding pin, and then curing and shrinking the ink;
mounting the back chip on the back of the packaging substrate brushed with the printing ink, and communicating the back chip with the back pins through the electrical connection parts;
step four, back encapsulation is carried out on the back chip to form back encapsulation, the encapsulated back pins expose the encapsulation body in partial areas, and the front pins expose the encapsulation body in at least partial peripheral areas;
and fifthly, electroplating at the corresponding position of the packaging structure after back surface packaging, electroplating tin on the front surface pins and the back surface pins, cutting and molding the product, and finishing the manufacturing of the double-sided chip packaging structure.
Furthermore, in the first step, the etched back leads are disposed inside the etched front leads.
Furthermore, when the ink is removed in the corresponding step two, the ink on the side of the front pin and the side of the back pin far away from the chip is also removed, namely the side surfaces of the pins and the side surface parts protruding from the pins are exposed; and step four, exposing the side surfaces of the encapsulated corresponding pins and the side surfaces of the pin bulges out of the packaging body, and step five, electroplating tin on the side surfaces of the pins and the side surfaces of the pin bulges.
Furthermore, the ink in the second step is photosensitive ink.
Furthermore, the encapsulation in the fourth step is manufactured through a corresponding encapsulation mold, and a cavity is formed in the position, corresponding to the flip chip, of the encapsulation mold to perform back encapsulation.
Furthermore, the front side of the packaging substrate can be half-etched or can be half-etched in the first step to form a base island, the ink corresponding to the position area of the base island is also removed in the second step, and the back chip in the third step can be arranged on the back side of the base island.
Furthermore, when the front side of the packaging substrate is half-etched, the upper half part of the back side pin can be etched and removed.
3. Advantageous effects
Compared with the prior art, the invention has the advantages that:
the pin of this scheme double-sided packaging structure exposes in the encapsulation product back at least partially, the cooperation is windowed PCB board paster upper plate, need not to carry out the operation of buckling to outer pin, the arrangement area of outer pin on the lead frame has been reduced, make more product units of arranging on the lead frame, thereby improve the production efficiency of double-sided dress chip package product, reduce time cost and material cost, and simultaneously, pin side design climbs the tin structure, the upper plate welding reliability has been increased, the packaging body can be through windowing PCB board, make the packaging body can dispel the heat to PCB board two sides, compare prior art, the radiating effect is more.
Drawings
FIG. 1 is a schematic cross-sectional view of a chip after a front-side encapsulation step;
FIG. 2 is a schematic top view of the front side chip after mounting;
FIG. 3 is a schematic cross-sectional view of the substrate after backside etching;
FIG. 4 is a schematic top view of the back surface of the substrate after etching;
FIG. 5 is a schematic cross-sectional view of a substrate after being back-inked;
FIG. 6 is a schematic top view of the back of the substrate with ink removed from the side portions of the terminal pins;
FIG. 7 is a schematic cross-sectional view of a flip-chip bond on the backside of a substrate;
FIG. 8 is a schematic top view of a flip chip bonded to the back side of a substrate;
FIG. 9 is a schematic cross-sectional view after flip-chip encapsulation;
FIG. 10 is a schematic top view of the back side of the flip chip encapsulated;
FIG. 11 is a schematic side cross-sectional view after cutting separation;
FIG. 12 is a schematic diagram of a top view of a DFN chip package;
FIG. 13 is a cross-sectional view of an exemplary structure of a half-etched backside lead;
fig. 14 is a cross-sectional view of another alternative structure of a half-etched back lead embodiment.
The reference numbers in the figures illustrate:
1. a front chip; 2. a front pin; 3. a back pin; 4. the pin protrudes; 5. a pin side; 6. printing ink; 7. a back chip; 8. back packaging; 9. packaging the front side; 10. connecting the ribs; 11. an extension portion; 12. a base island.
Detailed Description
The invention is described in detail below with reference to the drawings and specific examples.
The chip is manufactured by a series of steps of completing the packaging of a double-sided chip, forming pins from a metal plate → front film half etching → installing a front chip → pressure welding → front encapsulation → post curing → metal plate back half etching → ink brushing, exposure, development (back pin exposure) → installing a back chip → back encapsulation → cutting → test printing → inspection → packaging → warehousing, and completing the whole double-sided chip packaging structure; specific examples are as follows;
example 1
Installing the front chip 1 according to the conventional steps, wherein the specific steps are shown in fig. 1 and 2, and the method comprises a packaging substrate, wherein the packaging substrate mainly refers to a copper plate substrate, the copper plate substrate can be a large-size copper plate substrate, and the manufacturing of a double-sided chip packaging structure unit product can be carried out on the copper plate substrate in a modular manner, so that the corresponding front pins 2, the back pins 3 and the base islands 12 can be reasonably arranged. Half etching is performed on the front surface of the copper plate base material to form the upper half parts of the front surface pin 2, the back surface pin 3 and the base island 12, and the front surface chip 1 is mounted on the base island. The front chip 1 can be selected to be flip-chip or face-up according to the thickness of the product and the design requirement. The front chip 1 and the front pins 2 are connected through the electrical connection part, and the package substrate is encapsulated to form a front package 9, so that the front chip 1 is mounted. And the side, far away from the chip, of the front pin 2 and the back pin 3 is provided with a pin side surface 5, and the pin side surface 5 is provided with a pin protrusion 4, namely the pin protrusion 4 is arranged on the side, far away from the chip, of the front pin 2 and the back pin 3. Each double-sided chip packaging structure unit product is connected with a strip-shaped connecting rib 10 on the copper plate base material through pin protrusions 4 on the outer sides of the front pin 2 and the back pin 3. When a subsequent product is electroplated, the front pin 2 and the back pin 3 are tinned by the conduction of the pin bulges 4 and the strip-shaped connecting ribs 10.
After the front chip 1 is installed, the back chip 7 is installed; the method comprises the following specific steps: specific embodiments herein are exemplified in the form of an FBP package.
Step one, as shown in fig. 3 and 4, performing half etching on the back surface of the package substrate, and forming a front surface pin 2 electrically connected with the front surface chip 1 and a back surface pin 3 electrically connected with the back surface chip 7 through half etching separation by using the existing etching method, wherein the front surface pin 2 and the back surface pin 3 are not electrically connected with each other. The specific number and position of the pins can be set according to requirements. In the scheme of the embodiment, the front-side pins 2 and the back-side pins 3 are arranged around the base island (or chip). The bottom of the back pin 3 extends towards the base island, and the distance between the end part closest to the base island and the center of the base island 12 is closer to the distance between the front pin 2 and the center of the base island 12, so that when the back chip 7 is installed, the back chip 7 is in contact with the back pin 3, and meanwhile, the back chip 7 is prevented from being in contact with the front pin 2. Of course, the pin locations can be planned according to design requirements, for example, the pin locations can be disposed on two opposite sides of the package substrate, which is a DFN package type.
Certainly, the back pin 3 does not need to extend to the center of the base island, and no matter the chip is normally installed or inverted, the back pin can be realized by corresponding design as long as the pin has a certain area to enable the wire bonding/solder ball of the normally installed/inverted chip to be bonded. If the ball-bond chip is mounted on the back surface, the die attach adhesive is not conductive and contacts the front surface leads 2. It is also not necessary if the back side is flip chip mounted on the back side leads 3 by solder balls, and the flip chip 7 is spaced from the front side leads 2 without contacting the front side leads 2.
Step two, as shown in fig. 5 and 6, the back side of the packaging substrate after the back side is half-etched is brushed with ink 6, and the ink 6 is photosensitive ink, such as green oil. The silk screen of printing ink printing adopts the printing of whole piece region, uses the film to expose again, develops, gets rid of pin surface area's printing ink 6 totally, exposes front pin 2, back pin 3, base island 12, pin protrusion 4's metal surface, can also expose front pin 2, one side that back pin 3 kept away from the chip, exposes pin side 5 promptly and the side part of pin protrusion 4, helps realizing product pin side tinning, improves SMT upper plate reliability. Then, the ink 6 is cured and shrunk. .
And step three, as shown in fig. 7 and 8, mounting the back chip 7 on the back of the package substrate brushed with the ink, and communicating the back chip with the back pins 3 through the electrical connection parts. The back chip 7 may be either face-down bonded or flip-chip bonded depending on the manner of bonding. By adopting the flip chip, the back chip 7 can be arranged at the position of the back pin 3 close to the inside of the package, so that the package body is ensured to be exposed at least in part of the area of the bottom surfaces of the front pin 2 and the back pin 3 after the subsequent back encapsulation is finished. Of course, the back chip 7 may be connected by front surface mounting or ball bonding, but other methods may be used.
Step four, as shown in fig. 9 and 10, back encapsulation is performed on the chip 7 on the back side to form a back encapsulation 8, a part of the encapsulated back pins 3 is exposed out of the encapsulation body, and at least a part of the back of the front pins 2 is exposed out of the encapsulation body. The front pins 2, the pin protrusions 4 corresponding to the back pins 3 and the pin side surfaces 5 are also exposed out of the package body. The encapsulation is manufactured through a corresponding encapsulation mold, a cavity is arranged on the encapsulation mold corresponding to the position of the flip chip, and back encapsulation is carried out.
And step five, electroplating at the corresponding positions of the packaging structure after back surface packaging, wherein the front surface pins 2, the back surface pins 3 and the bottom surfaces of the pin side surfaces 5 are all electroplated with tin. And then cutting, molding and separating the modularized double-sided chip packaging structure product into single double-sided chip packaging structures, as shown in fig. 11, and finishing the manufacture of the double-sided chip packaging structure.
Preferably, in the first step of this implementation, as shown in fig. 4, a length of the extension 11 may be provided on the back pin 3 near the base island (or chip). The extension portion 11 can be used as the connection portion between the electrical connection portion of the back package 8 and the back leads 3, thereby improving the quality of electrical connection.
This product is when the installation, sets up the window that is fit for 8 sizes of back encapsulation on the PCB board to let back encapsulation 8 locate in the window, pin paster upper plate, occupation space not.
Correspondingly, the double-sided chip packaging structure comprises the following components,
the packaging structure comprises a packaging substrate, wherein a plurality of pins are arranged on the periphery of the packaging substrate, the pins are divided into a front pin 2 and a back pin 3, and the front pin 2 and the back pin 3 are not communicated with each other;
one sides of the front pin 2 and the back pin 3, which are far away from the chip, are provided with a pin side surface 5 and a pin protrusion 4 connected with the pin side surface;
the front surface of the packaging substrate is provided with a front surface chip 1, and the front surface chip 1 is electrically connected with the front surface pins 2 through an electrical connection part;
the back surface of the packaging substrate and the back surface pins 3 is attached with a back surface chip 7, and the back surface chip 7 is electrically connected with the back surface pins 3 through an electric connection part;
the encapsulation material covers the front chip 1, the back chip 7, the electrical connection part, and the area between the front pins 2 and the back pins 3; the back of the front pin 2 is at least partially exposed out of the plastic package body, the back of the back pin 3 is partially exposed out of the plastic package body, and the side surfaces 5, 4 and the back and the side surfaces of the pin are exposed out of the plastic package body.
The chip packaging and process method of the scheme, the PCB patch upper plate is windowed in a matching mode, bending operation on outer pins is not needed, the arrangement area of the outer pins on the lead frame is reduced, more product units can be arranged on the lead frame, and therefore the production efficiency of double-sided chip packaging products is improved, time cost and material cost are reduced, meanwhile, a tin climbing structure is designed on the side face of each pin, the reliability of welding of the upper plate is improved, the packaging body can be used for radiating heat to two sides of the PCB through the windowed PCB, and compared with the prior art, the heat radiating effect is better.
Example 2
This embodiment is substantially the same as embodiment 1, except that it can also be applied to various different types of package structures, for example, a DFN package structure can be designed, as shown in fig. 12, the front pins 2 and the back pins 3 are not disposed on the periphery, but disposed on two opposite sides of the package substrate.
Example 3
This embodiment is substantially the same as embodiment 1, except that the present embodiment may not be provided with a base island. In the scheme, the base island is not provided with an exposed packaging structure, and the substrate is not used as a conductive terminal for leading out an electric signal, so that the substrate is only used for bearing a chip. After the front side of the package substrate is half-etched, the front side chip 1 may be disposed in the central area of the recess, which may further control the thickness of the packaged product. After the package substrate back side is half etched, a back chip 7 may be disposed on the cured ink 6. Thus, the thickness of the whole chip can be greatly reduced. If the front side chip 1 can be a flip chip, the flip chip does not need a base island, and the flip chip is directly arranged on the pins. The back pin 3 can also etch and remove the upper half part when the front of the packaging substrate is half-etched, the back pin 3 only needs to be electrically connected with the back chip 7, and the peripheral area of the back pin 3 after the back chip is packaged exposes the packaging body, so the back pin 3 can be half-etched on the front.
Example 4
Embodiment 4 is different from embodiment 3 in that the back pins 3 are formed on the inner sides of the front pins 2, after the back surface encapsulation is completed, the back surfaces of the back pins 3 are partially exposed out of the package body, and the back surfaces of the front pins 2 are completely exposed out of the package body, so that a package body structure with two circles of exposed pins is formed, and thus, more pins can be reasonably arranged.
The invention and its embodiments have been described above schematically, without limitation, and the invention can be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The representation in the drawings is only one of the embodiments of the invention, the actual construction is not limited thereto, and any reference signs in the claims shall not limit the claims concerned. Therefore, if a person skilled in the art receives the teachings of the present invention, without inventive design, a similar structure and an embodiment to the above technical solution should be covered by the protection scope of the present patent. Furthermore, the word "comprising" does not exclude other elements or steps, and the word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. Several of the elements recited in the product claims may also be implemented by one element in software or hardware. The terms first, second, etc. are used to denote names, but not any particular order.

Claims (13)

1. A double-sided chip packaging structure is characterized by comprising a packaging substrate, wherein a plurality of pins are arranged on two opposite sides or the periphery of the packaging substrate, the pins are divided into a front pin (2) and a back pin (3), and the front pin (2) and the back pin (3) are not communicated with each other;
the side surfaces (5) of the pins and the pin bulges (4) connected with the side surfaces of the pins are arranged on the side, far away from the chip, of the front pin (2) and the back pin (3);
the front surface of the packaging substrate is provided with a front surface chip (1), and the front surface chip (1) is electrically connected with the front surface pins (2) through an electric connection part;
the back surface of the packaging substrate is provided with a back surface chip (7), and the back surface chip (7) is electrically connected with the back surface pins (3) through an electric connection part;
the packaging material coats regions among the front chip (1), the back chip (7), the electric connection part, the front pin (2) and the back pin (3), at least part of the back of the front pin (2) is exposed out of the plastic package body, and part of the back pin (3) is exposed out of the plastic package body.
2. A double-sided chip package structure according to claim 1, further comprising a base island (12), wherein the front-side chip (1) is disposed on the front side of the base island (12) and/or the back-side chip (7) is disposed on the back side of the base island (12).
3. A double-sided chip package according to claim 1, wherein the back side leads (3) are provided with an extension (11) near the chip.
4. A double-sided chip package structure according to claim 1, wherein the back leads (3) are disposed inside the front leads (2).
5. A double-sided chip package according to claim 1, wherein the front-side chip (1) is a ball-bond chip or a flip-chip, and the back-side chip (7) is a ball-bond chip or a flip-chip.
6. A double-sided chip package structure according to claim 1 or 4, wherein the lead side surface (5), the back surface and the side surface of the lead protrusion (4) are exposed out of the plastic package body.
7. A packaging method of a double-sided chip packaging structure comprises the steps of packaging a front-sided chip, selecting a packaging substrate, half-etching the front side of the rear packaging substrate, mounting a front-side chip, routing and packaging, and then finishing the mounting of the front-side chip (1);
the method also comprises the following steps of,
the method comprises the following steps that firstly, half etching is carried out on the back surface of a packaging substrate to form a front surface pin (2) communicated with a front surface chip (1), a back surface pin (3) communicated with a back surface chip (7), a pin side surface (5) arranged on one side of the front surface pin (2) and the back surface pin (3) far away from the chip, and a pin protrusion (4) connected with the pin side surface, wherein the front surface pin (2) and the back surface pin (3) are not electrically communicated with each other;
secondly, brushing ink (6) on the back of the packaging substrate subjected to back half etching, exposing by using a film, completely removing the ink (6) in the region of the pin position, exposing the metal surfaces of the front pin (2), the back pin (3) and the pin protrusion (4), and then curing and shrinking the ink (6);
thirdly, mounting the back chip (7) on the back of the packaging substrate brushed with the printing ink, and communicating the back chip with the back pins (3) through the electrical connection parts;
fourthly, back encapsulation is carried out on the back chip (7) to form a back encapsulation (8), the encapsulated back pins (3) are partially exposed out of the encapsulation body, and at least part of the back of the front pins (2) is exposed out of the encapsulation body;
and fifthly, electroplating at the corresponding position of the packaging structure after back surface packaging, electroplating tin on the front surface pins (2) and the back surface pins (3), cutting and molding the product, and finishing the manufacturing of the double-sided chip packaging structure.
8. The method for packaging a double-sided chip package structure as claimed in claim 7, wherein in the first step, the etched back leads (3) are disposed inside the etched front leads (2).
9. The packaging method of a double-sided chip package structure according to claim 7 or 8, wherein when the ink (6) is removed in the corresponding step two, the ink (6) exposing the front-side leads (2) and the side of the back-side leads (3) away from the chip is also removed, i.e. the side surfaces (5) of the leads and the side surface parts of the lead protrusions (4) are exposed; and in the fourth step, the side surfaces (5) and the side surfaces of the corresponding pin bulges (4) are exposed out of the packaging body, and in the fifth step, the side surfaces (5) and the side surfaces of the pin bulges (4) are electroplated with tin.
10. The method for packaging a double-sided chip package structure according to claim 7 or 9, wherein the ink (6) in the second step is photosensitive ink.
11. The packaging method of a double-sided chip packaging structure according to claim 7, wherein the packaging in the fourth step is performed by a corresponding packaging mold, and a cavity is formed on the packaging mold corresponding to the flip chip for back packaging.
12. The method for packaging a double-sided chip package structure according to claim 7, wherein the front side of the packaging substrate is half-etched or the base islands (12) are also half-etched in the first step, the ink (6) corresponding to the location areas of the base islands (12) is also removed in the second step, and the back chip (7) in the third step can be disposed on the back side of the base islands (12).
13. The packaging method of a double-sided chip package structure as claimed in claim 7, wherein the upper half of the back side leads (3) is etched away when the front side of the packaging substrate is half-etched.
CN201911069533.4A 2019-11-05 2019-11-05 Double-sided chip packaging structure and packaging method Pending CN110690191A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113299565A (en) * 2021-07-28 2021-08-24 江苏长晶浦联功率半导体有限公司 Chip packaging method and chip packaging structure

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113299565A (en) * 2021-07-28 2021-08-24 江苏长晶浦联功率半导体有限公司 Chip packaging method and chip packaging structure

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