JP2000049383A - Optoelectric conversion element and its manufacture - Google Patents

Optoelectric conversion element and its manufacture

Info

Publication number
JP2000049383A
JP2000049383A JP10210606A JP21060698A JP2000049383A JP 2000049383 A JP2000049383 A JP 2000049383A JP 10210606 A JP10210606 A JP 10210606A JP 21060698 A JP21060698 A JP 21060698A JP 2000049383 A JP2000049383 A JP 2000049383A
Authority
JP
Japan
Prior art keywords
package
electrode
optical element
electrodes
light emitting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10210606A
Other languages
Japanese (ja)
Other versions
JP3356068B2 (en
Inventor
Tadaaki Ikeda
忠昭 池田
Kazuya Yamaguchi
和也 山口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP21060698A priority Critical patent/JP3356068B2/en
Publication of JP2000049383A publication Critical patent/JP2000049383A/en
Application granted granted Critical
Publication of JP3356068B2 publication Critical patent/JP3356068B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/4847Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48471Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area being a ball bond, i.e. wedge-to-ball, reverse stitch
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • H01L2924/1815Shape

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Led Device Packages (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide an optoelectric conversion element that has high utilization rate of materials and moreover can emit light of multiple colors. SOLUTION: A dimple formed on the surface of a substrate 21 for manufacturing is coated with electrodes 1 and 2, an optical element is mounted to the electrode 1, and the optical element and the other electrode 2 are bonded by a wire 4 before being sealed by a resin layer 24. The resin layer 24 and the substrate 21 for manufacturing are subjected to dicing for forming a piece including at least one set of optical element and wire, and only the substrate 21 for manufacturing is eliminated from the piece, thus exposing a package 5 due to the resin layer 24 and the electrodes 1 and 2 integrated in one piece with it on the surface.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、半導体発光ダイオ
ードやフォトダイオード等の光電変換素子と及びその製
造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a photoelectric conversion element such as a semiconductor light emitting diode and a photodiode, and a method for manufacturing the same.

【0002】[0002]

【従来の技術】たとえば携帯電話やポケットベル等の小
型電子機器の画像表示部には、発光ダイオード(以下、
「LED」と記す)の中でも小型・薄型の面実装タイプ
のチップ型LEDが主として利用されている。チップL
EDは、絶縁性の基板の表裏両面に互いに導通し合う一
対の電極を設け、表面の一方の電極にLEDの下面のた
とえばn電極を導通させて搭載するとともに上面のp電
極をワイヤによって他方の電極にボンディングするとい
うのがその基本的な構成である。
2. Description of the Related Art Light-emitting diodes (hereinafter referred to as "light-emitting diodes") are provided in image display sections of small electronic devices such as cellular phones and pagers.
Among them, a small-sized and thin surface-mounted chip-type LED is mainly used. Chip L
The ED is provided with a pair of electrodes that are electrically connected to each other on both the front and back surfaces of an insulating substrate. Bonding to the electrode is the basic configuration.

【0003】図7は従来の面実装型のチップLEDの例
を示す概略図である。このチップLEDは、絶縁性の基
板50の両端に表裏両面にかけて展開させた一対の電極
51,52を備え、一方の電極51に連ねて形成したス
テージ51aの上にGaPまたはGaAlAs等の化合
物半導体を利用した発光素子53を導通搭載したもので
ある。そして、他方の電極52にはボンディングエリア
52aを形成して、発光素子53の表面電極との間にワ
イヤ54をボンディングし、これらの発光素子53及び
ワイヤ54を含んで樹脂のパッケージ55によって封止
されている。
FIG. 7 is a schematic view showing an example of a conventional surface mount type chip LED. This chip LED includes a pair of electrodes 51 and 52 developed on both sides of an insulating substrate 50 on both front and back surfaces, and a compound semiconductor such as GaP or GaAlAs is mounted on a stage 51 a formed in connection with one electrode 51. The light emitting element 53 used is conductively mounted. Then, a bonding area 52a is formed on the other electrode 52, a wire 54 is bonded between the electrode 52 and the surface electrode of the light emitting element 53, and the light emitting element 53 and the wire 54 are sealed by a resin package 55. Have been.

【0004】このようなチップLEDの製造は、ウエハ
ー状態の基板50に電極51,52の間隔にほぼ等しい
ピッチでスリットを切開しておき、メッキによって基板
50の表裏両面にこれらの電極51,52を形成する工
程から始める。そして、発光素子53の搭載及びワイヤ
54のボンディングの後にパッケージ55を金型によっ
て型製作し、最終工程のダイシングの後に図示の形状の
製品が得られる。
In manufacturing such a chip LED, slits are cut in the substrate 50 in a wafer state at a pitch substantially equal to the interval between the electrodes 51 and 52, and these electrodes 51 and 52 are formed on both front and back surfaces of the substrate 50 by plating. Starting from the step of forming. After the mounting of the light emitting element 53 and the bonding of the wire 54, the package 55 is manufactured using a mold, and after dicing in the final step, a product having the illustrated shape is obtained.

【0005】ところが、パッケージ55の成形方法は、
ウエハー状態であって電極51,52を形成した基板5
0の表面に型を載せて溶融樹脂を注入するというものな
ので、基板50には型を載せるための掛かり代が必要と
なる。すなわち、図示のようにパッケージ55が形成さ
れない部分が型の掛かり代であって、電極51,52の
ほぼ全体が型成形の固定治具のような役割を果たす。
However, the molding method of the package 55 is as follows.
Substrate 5 in wafer state on which electrodes 51 and 52 are formed
Since the mold is mounted on the surface of the mold 0 and the molten resin is injected, the substrate 50 needs a margin for mounting the mold. That is, as shown in the drawing, the portion where the package 55 is not formed is a hook for the mold, and almost the entirety of the electrodes 51 and 52 functions as a fixing jig for molding.

【0006】このように、基板50の両端部に配置する
電極51,52はパッケージ55から突き出る形状なの
で、全体の平面積が占める嵩が大きくなる。また、基板
50自体も含んでプリント基板の表面に実装されるの
で、この基板50の厚さ分だけ肉厚も大きくなる。
As described above, since the electrodes 51 and 52 disposed at both ends of the substrate 50 protrude from the package 55, the volume occupied by the entire plane area increases. Further, since the printed circuit board is mounted on the surface of the printed board including the board 50 itself, the thickness of the board 50 is increased by the thickness of the board 50.

【0007】これに対し、パッケージをチップLEDの
実質的な大きさとなるような製造方法も既に開発され、
これによって得られるチップLEDの概略縦断面を図8
に示す。
[0007] On the other hand, a manufacturing method for making the package substantially the size of the chip LED has already been developed.
FIG. 8 shows a schematic vertical cross section of the chip LED obtained by this.
Shown in

【0008】図において、パッケージ56の底部の2か
所に電極57,58をメッキ法によって形成するととも
に、パッケージ56の内部であって一方の電極57に発
光素子59を導通搭載している。そして、この発光素子
59と他方の電極58との間をワイヤ60によってボン
ディングし、電極57,58をプリント配線の上に実装
することで発光素子59を導通させることができる。
In the figure, electrodes 57 and 58 are formed at two places on the bottom of a package 56 by plating, and a light emitting element 59 is mounted on one electrode 57 inside the package 56 in a conductive manner. Then, the light emitting element 59 and the other electrode 58 are bonded by a wire 60, and the electrodes 57, 58 are mounted on the printed wiring, so that the light emitting element 59 can be made conductive.

【0009】このようにパッケージ56の底面に電極5
7,58を直に形成するようにすれば、平面の嵩が小さ
くなるほか、基板自体もなくなるので高さ寸法も小さい
製品が得られる。
As described above, the electrode 5 is provided on the bottom of the package 56.
If the layers 7, 58 are formed directly, the bulk of the plane is reduced and the substrate itself is eliminated, so that a product with a small height can be obtained.

【0010】[0010]

【発明が解決しようとする課題】図8に示したチップL
EDの製造方法は、図7の例と同様に型製作によってパ
ッケージ56を成形するというものである。すなわち、
銅合金薄板を成形用の基板としてその表面に電極57,
58をメッキによって形成し、発光素子59の搭載及び
ワイヤ60のボンディング後にパッケージ56を型製作
によって成形し、更に最終工程として基板をエッチング
によって除去する工程を踏む。
The chip L shown in FIG.
In the method of manufacturing the ED, the package 56 is formed by die manufacturing as in the example of FIG. That is,
A copper alloy thin plate is used as a forming substrate, and electrodes 57,
58 is formed by plating, and after mounting the light emitting element 59 and bonding the wires 60, the package 56 is formed by die manufacturing, and the final step of removing the substrate by etching is performed.

【0011】ところが、パッケージ56を型製作によっ
て成形するのでは、パッケージ56の外郭に沿うような
型の形状として各パッケージ56を分離する方式とする
しかない。このため、パッケージ56の分離に必要なス
ペースを型が占めるので、このスペースが基板に対して
広くなり、基板を一つの単位としたときの製品回収率が
下がり、生産性や製品歩留りに影響を及ぼす。
However, in order to form the package 56 by molding, there is no other choice but to use a method in which each package 56 is separated into a mold shape along the outer periphery of the package 56. As a result, the mold occupies a space necessary for separating the package 56, and this space is widened with respect to the substrate. As a result, the product collection rate when the substrate is made into one unit decreases, and the productivity and product yield are affected. Exert.

【0012】また、型製作によってパッケージ56を形
成するのでは、図8のような1個の発光素子59を含む
ものだけに対応する型とした場合には、1種類のチップ
LEDしか得られない。そして、複数の発光色の発光素
子を複数組み合わせた製品とする場合には、別の専用の
型が必要となり、実操業には適していない。
In the case where the package 56 is formed by die manufacturing, only one type of chip LED can be obtained if the die is a type corresponding to only one including one light emitting element 59 as shown in FIG. . When a product is obtained by combining a plurality of light-emitting elements of a plurality of emission colors, another dedicated mold is required, which is not suitable for actual operation.

【0013】更に、電極57,58はプリント基板の上
に実装されて半田付けによって導通固定されるが、これ
らの電極57,58はパッケージ56の側面まで延びて
いないので、半田付けのフィレットの確認がし難いとい
う問題もある。
Further, the electrodes 57 and 58 are mounted on a printed circuit board and are conductively fixed by soldering. However, since these electrodes 57 and 58 do not extend to the side surfaces of the package 56, the fillet for soldering is confirmed. There is also a problem that it is difficult to remove.

【0014】本発明において解決すべき課題は、材料の
使用率を高めてより経済的に製造できしかも多色発光へ
も対応可能な光電変換素子及びその製造方法を提供する
ことにある。
The problem to be solved in the present invention is to provide a photoelectric conversion element which can be manufactured more economically by increasing the usage rate of materials and which can cope with multicolor light emission, and a method for manufacturing the same.

【0015】[0015]

【課題を解決するための手段】本発明の光電変換素子の
製造方法は、製造用基板の表面に素子搭載用及びワイヤ
ボンディング用の凹状のディンプルをパターン形成する
工程と、前記ディンプルのそれぞれの内周に電極をコー
ティングする工程と、前記光学素子搭載用のディンプル
に光学素子を実装するとともにこの光学素子と前記ワイ
ヤボンディング用のディンプルとの間をワイヤでボンデ
ィングする工程と、前記製造用基板の表面を前記光学素
子とワイヤを含んで樹脂層によって封止する工程と、前
記樹脂層と製造用基板をダイシングして前記光学素子と
ワイヤとを少なくとも1組含むピースとする工程と、前
記ピースから製造用基板だけを除去して前記樹脂層によ
るパッケージとこれに一体化した前記電極を表面に露出
させる工程とを含むことを特徴とする。
According to the present invention, there is provided a method for manufacturing a photoelectric conversion element, comprising the steps of: forming a pattern of concave dimples for mounting an element and wire bonding on a surface of a manufacturing substrate; A step of coating an electrode on the periphery, a step of mounting an optical element on the dimple for mounting the optical element, and bonding a wire between the optical element and the dimple for wire bonding, and a step of bonding the surface of the manufacturing substrate. Encapsulating with a resin layer including the optical element and the wire, dicing the resin layer and a manufacturing substrate into a piece including at least one set of the optical element and the wire, and manufacturing from the piece. Exposing only the substrate for use to expose the surface of the package made of the resin layer and the electrodes integrated therewith. It is characterized in.

【0016】この製造方法では、光学素子とワイヤを封
止した樹脂層を製造用基板とともにダイシングするの
で、樹脂層によってパッケージを形成するときの型製作
による工程に比べて加工の自由度が向上し、材料使用率
も改善される。
In this manufacturing method, since the resin layer in which the optical element and the wires are sealed is diced together with the manufacturing substrate, the degree of freedom in processing is improved as compared with the step of forming a mold when the package is formed by the resin layer. Also, the material usage rate is improved.

【0017】[0017]

【発明の実施の形態】請求項1に記載の発明は、製造用
基板の表面に素子搭載用及びワイヤボンディング用の凹
状のディンプルをパターン形成する工程と、前記ディン
プルのそれぞれの内周に電極をコーティングする工程
と、前記光学素子搭載用のディンプルに光学素子を実装
するとともにこの光学素子と前記ワイヤボンディング用
のディンプルとの間をワイヤでボンディングする工程
と、前記製造用基板の表面を前記光学素子とワイヤを含
んで樹脂層によって封止する工程と、前記樹脂層と製造
用基板をダイシングして前記光学素子とワイヤとを少な
くとも1組含むピースとする工程と、前記ピースから製
造用基板だけを除去して前記樹脂層によるパッケージと
これに一体化した前記電極を表面に露出させる工程とを
含むことを特徴とする光電変換素子の製造方法であり、
光学素子とワイヤを封止した樹脂層を製造用基板ととも
にダイシングするので、複数の光学素子を一体に含むデ
バイスとする加工にも対応できるほか、パッケージの型
製作に比べて材料使用率の向上が図れるという作用を有
する。
DETAILED DESCRIPTION OF THE INVENTION The invention according to claim 1 is a step of patterning concave dimples for element mounting and wire bonding on the surface of a manufacturing substrate, and forming electrodes on the inner periphery of each of the dimples. A step of coating, a step of mounting an optical element on the dimple for mounting the optical element, and bonding a wire between the optical element and the dimple for wire bonding with a wire; And a step of sealing with a resin layer containing wires, a step of dicing the resin layer and the manufacturing substrate into a piece including at least one set of the optical element and the wire, and only the manufacturing substrate from the piece. Removing the package by the resin layer and exposing the electrode integrated with the package to the surface. A method for producing a photoelectric conversion element,
Dicing the resin layer encapsulating the optical element and the wire together with the manufacturing substrate enables the device to be integrated into a device that includes multiple optical elements, and also improves the material usage rate compared to package die manufacturing. It has the effect that it can be achieved.

【0018】請求項2に記載の発明は、前記製造用基板
の表面に素子搭載用及びワイヤボンディング用の凹状の
ディンプルをパターン形成する工程において、前記ディ
ンプルに連ねて前記ピースの端部にかけてほぼ一様の深
さのエッジ用ディンプルを形成する工程を含む請求項1
記載の光電変換素子の製造方法であり、エッジディンプ
ルにかけても電極を形成することで電極をパッケージの
側面に臨む位置まで形成できるという作用を有する。
According to a second aspect of the present invention, in the step of patterning concave dimples for element mounting and wire bonding on the surface of the manufacturing substrate, substantially one end of the piece is connected to the end of the piece following the dimple. 2. The method according to claim 1, further comprising the step of forming edge dimples of various depths.
This is a method for manufacturing a photoelectric conversion element as described above, and has an effect that an electrode can be formed up to a position facing a side surface of a package by forming an electrode even when the electrode is crossed over an edge dimple.

【0019】請求項3に記載の発明は、前記光学素子を
発光ダイオードとし、前記光学素子搭載用のディンプル
を、実装する発光ダイオードの発光層が含まれる深さま
で形成する請求項1または2記載の光電変換素子の製造
方法であり、ディンプルに形成される電極を反射面とし
て発光ダイオードの発光層からの光を効率的に取り出せ
るという作用を有する。
According to a third aspect of the present invention, the optical element is a light emitting diode, and the dimple for mounting the optical element is formed to a depth including a light emitting layer of the light emitting diode to be mounted. This is a method for manufacturing a photoelectric conversion element, and has an effect that light from a light emitting layer of a light emitting diode can be efficiently extracted using an electrode formed in a dimple as a reflection surface.

【0020】請求項4に記載の発明は、樹脂のパッケー
ジと、このパッケージの下面に形成された一対の電極
と、前記パッケージの内部に封止されて一方の電極に導
通搭載される光学素子と、この光学素子と他方の電極と
の間にボンディングされ且つ前記パッケージの内部に封
止されたワイヤとを備え、前記電極は、前記パッケージ
の周面とほぼ同じ面まで展開させたエッジを外面に臨ま
せて形成してなる光電変換素子であり、電極をパッケー
ジの周面に臨ませることでプリント基板等への実装時の
半田付けフィレットの自動認識がしやすくなるという作
用を有する。
According to a fourth aspect of the present invention, there is provided a resin package, a pair of electrodes formed on a lower surface of the package, and an optical element sealed inside the package and electrically mounted on one of the electrodes. A wire bonded between the optical element and the other electrode and sealed inside the package, wherein the electrode has an edge extended to almost the same surface as the peripheral surface of the package on the outer surface. This is a photoelectric conversion element formed so as to face, and has an effect that it is easy to automatically recognize a soldering fillet at the time of mounting on a printed circuit board or the like by making the electrodes face the peripheral surface of the package.

【0021】請求項5に記載の発明は、樹脂のパッケー
ジと、このパッケージの下面に形成された複数組の電極
と、前記パッケージの内部に封止されて各組の電極の一
方の電極に導通搭載される光学素子と、この光学素子と
他方の電極との間にボンディングされ且つ前記パッケー
ジの内部に封止されたワイヤとを備え、前記複数組の電
極は、前記パッケージの周面とほぼ同じ面まで展開させ
たエッジを外面に臨ませて形成してなる光電変換素子で
あり、一つのパッケージに複数の光学素子を備えてカラ
ー発光にも対応でき、電極をパッケージの周面に臨ませ
ることでプリント基板等への実装時の半田付けフィレッ
トの自動認識がしやすくなるという作用を有する。
According to a fifth aspect of the present invention, there is provided a resin package, a plurality of sets of electrodes formed on a lower surface of the package, and a package sealed inside the package and electrically connected to one electrode of each set of electrodes. An optical element to be mounted, and a wire bonded between the optical element and the other electrode and sealed inside the package, wherein the plurality of sets of electrodes are substantially the same as a peripheral surface of the package. A photoelectric conversion element that is formed with the edge extended to the surface facing the outer surface.One package has multiple optical elements and can respond to color light emission, and the electrode faces the peripheral surface of the package. This has an effect that the soldering fillet can be easily recognized automatically at the time of mounting on a printed circuit board or the like.

【0022】請求項6に記載の発明は、樹脂のパッケー
ジと、このパッケージの下面に形成された素子搭載用の
電極及びボンディング用の複数の電極と、前記パッケー
ジの内部に封止されて前記素子搭載用の電極に導通搭載
される複数の光学素子と、これらの光学素子のそれぞれ
とボンディング用の各電極との間にボンディングされ且
つ前記パッケージの内部に封止されたワイヤとを備え、
前記素子搭載用及びボンディング用の電極は、前記パッ
ケージの周面とほぼ同じ面まで展開させたエッジを外面
に臨ませて形成してなる光電変換素子であり、素子搭載
用の電極に複数の光学素子を搭載することによって小型
でフルカラー発光等に対応でき、電極をパッケージの周
面に臨ませることでプリント基板等への実装時の半田付
けフィレットの自動認識がしやすくなるという作用を有
する。
According to a sixth aspect of the invention, there is provided a resin package, a plurality of electrodes for mounting a device and a plurality of electrodes for bonding formed on a lower surface of the package, and the device which is sealed inside the package. A plurality of optical elements conductively mounted on the mounting electrodes, and a wire bonded between each of these optical elements and each electrode for bonding and sealed inside the package,
The element mounting and bonding electrodes are photoelectric conversion elements formed by facing the outer surface with an edge developed to almost the same surface as the peripheral surface of the package, and a plurality of optical elements are provided on the element mounting electrodes. By mounting the device, it is possible to cope with full-color light emission and the like with a small size, and it is possible to easily recognize the soldering fillet at the time of mounting on a printed board or the like by making the electrodes face the peripheral surface of the package.

【0023】請求項7に記載の発明は、前記パッケージ
には、前記光学素子に対応する位置に集光用の球面状の
レンズを前記パッケージの表面以下の高さとして形成し
てなる請求項4から6のいずれかに記載の光電変換素子
であり、レンズの集光性による光学機能の向上とプリン
ト基板等への実装の際のハンドリングの自由度の向上が
図れるという作用を有する。
According to a seventh aspect of the present invention, in the package, a spherical lens for condensing light is formed at a position corresponding to the optical element at a height below the surface of the package. 7. The photoelectric conversion element according to any one of items 1 to 6, which has an effect of improving the optical function by the light-collecting property of the lens and improving the degree of freedom of handling when mounting on a printed circuit board or the like.

【0024】請求項8に記載の発明は、前記光学素子を
発光ダイオードとし、この発光ダイオードを導通搭載す
る側の一方の電極を、凹状断面であって且つ前記発光ダ
イオードの発光層を埋没状態に含む深さに形成してなる
請求項4から7のいずれかに記載の光電変換素子であ
り、電極を反射面として発光ダイオードの発光層からの
光を効率的に取り出せるという作用を有する。
According to an eighth aspect of the present invention, the optical element is a light emitting diode, and one electrode on the side on which the light emitting diode is conductively mounted has a concave cross section and the light emitting layer of the light emitting diode is buried. The photoelectric conversion element according to any one of claims 4 to 7, wherein the photoelectric conversion element is formed at a depth including the electrode, and has a function of efficiently extracting light from the light emitting layer of the light emitting diode using the electrode as a reflecting surface.

【0025】以下に、本発明の実施の形態を面実装型の
LEDを例として図面を参照しながら説明する。
Hereinafter, embodiments of the present invention will be described with reference to the drawings, taking a surface mount type LED as an example.

【0026】図1は本発明の製造方法の工程であって基
板への電極の形成から発光素子の搭載までを順に示す概
略図であり、図の(a)〜(f)に従って説明する。
FIG. 1 is a schematic view showing the steps of the manufacturing method of the present invention, from the formation of an electrode on a substrate to the mounting of a light-emitting element, which will be described with reference to FIGS.

【0027】図(a):たとえば銅合金の薄板のロール
材を帯状に繰り出した製造用基板21の表面にスタンピ
ングまたはエッチングによって所定のパターンでディン
プル21a,21bを形成する。一方のディンプル21
aは後工程で発光素子を搭載する部分となり、他方のデ
ィンプル21bはワイヤボンディングエリアとなる部分
であり、いずれもその深さは同じである。
FIG. 1A: Dimples 21a and 21b are formed in a predetermined pattern by stamping or etching on the surface of a manufacturing substrate 21 which is formed, for example, by feeding a thin roll of copper alloy into a strip. One dimple 21
a is a portion where a light emitting element is mounted in a later step, and the other dimple 21b is a portion which becomes a wire bonding area, and each has the same depth.

【0028】図(b):製造用基板21の表面にレジス
ト膜22を塗布する。この工程では、レジスト材として
たとえば紫外線硬化樹脂(UV樹脂)を利用し、ローラ
転写法によってレジスト膜22がディンプル21a,2
1bを除く表面に一様に形成される。
FIG. 2B: A resist film 22 is applied on the surface of the manufacturing substrate 21. In this step, for example, an ultraviolet-curing resin (UV resin) is used as a resist material, and the resist film 22 is formed by dimples 21a and 21a by a roller transfer method.
It is formed uniformly on the surface except for 1b.

【0029】図(c):製造用基板21の裏面にマスク
23をマスキングによって形成する。この工程では、テ
ープまたは紫外線硬化樹脂を材料として製造用基板21
の裏面の全体をマスク23でマスキングする。
FIG. 5C: A mask 23 is formed on the back surface of the manufacturing substrate 21 by masking. In this step, the manufacturing substrate 21 is formed using a tape or an ultraviolet curable resin as a material.
Is entirely masked with a mask 23.

【0030】図(d):ディンプル21a,21bにメ
ッキ法によって電極1,2をそれぞれ形成する。この電
極1,2はAu/Ni/Auの3層メッキとして形成す
ることが好ましく、その金属光沢を光反射面として利用
する。
FIG. 4D: Electrodes 1 and 2 are formed on the dimples 21a and 21b by plating. The electrodes 1 and 2 are preferably formed as a three-layer plating of Au / Ni / Au, and the metallic luster is used as a light reflecting surface.

【0031】図(e):レジスト膜22及びマスク23
をエッチングによって除去する。これにより、ディンプ
ル21a,21bのそれぞれに電極1,2が形成された
製造用基板21として回収される。
FIG. 5E: Resist film 22 and mask 23
Is removed by etching. Thereby, it is collected as the manufacturing substrate 21 in which the electrodes 1 and 2 are formed on the dimples 21a and 21b, respectively.

【0032】図(f):ディンプル21aの電極1の上
に発光素子3を実装し、この発光素子3の表面電極3a
と他方のディンプル21bの電極2との間をワイヤ4に
よってボンディングする。
FIG. 5F: The light emitting element 3 is mounted on the electrode 1 of the dimple 21a, and the surface electrode 3a of the light emitting element 3 is mounted.
And the electrode 2 of the other dimple 21b is bonded by the wire 4.

【0033】以上までの工程により、ロール状の製造用
基板21に凹状断面の電極1,2がパターン形成され、
それぞれの電極1に発光素子3が実装される。そして、
図2に示す工程によって、樹脂封止からダイシングまで
の加工が施される。図2により各工程を順に説明する。
By the steps described above, the electrodes 1 and 2 having a concave cross section are formed on the roll-shaped manufacturing substrate 21 by patterning.
A light emitting element 3 is mounted on each electrode 1. And
Through the process shown in FIG. 2, processing from resin sealing to dicing is performed. Each step will be described in order with reference to FIG.

【0034】図(a):エポキシ樹脂等の樹脂層24を
製造用基板21の表面の全体にモールド成形する。この
樹脂層24は製造用基板21の表面に一様な肉厚として
全ての発光素子3とワイヤ4を封止してパッケージ化す
る。
FIG. 3A: A resin layer 24 such as an epoxy resin is molded over the entire surface of the manufacturing substrate 21. The resin layer 24 has a uniform thickness on the surface of the manufacturing substrate 21 and seals and packages all the light emitting elements 3 and the wires 4.

【0035】図(b):樹脂層24を積層した製造用基
板21をダイシングテーブルに移す前に製造用基板21
の裏面にシート25を貼り付け、この後ダイサーによっ
て電極1,2を含む範囲を一つの単位としてダイシング
する。このダイシングでは、シート25はそのままの状
態に残して、樹脂層24と製造用基板21だけをカット
する。
FIG. 4B: Before transferring the manufacturing substrate 21 on which the resin layer 24 is laminated to the dicing table,
The sheet 25 is adhered to the back surface of the substrate, and thereafter, dicing is performed by a dicer using the area including the electrodes 1 and 2 as one unit. In this dicing, only the resin layer 24 and the manufacturing substrate 21 are cut while leaving the sheet 25 as it is.

【0036】図(c):ダイサーによるダイシング工程
では、図中において一点鎖線で示すように、1個の発光
素子3を含むパターンとするほか、太線で囲んだ部分で
示すように2個の隣接した発光素子3を含むパターンと
してダイシングするようにしてもよい。これにより、1
個のチップLEDに2個の発光素子3を備えた製品とす
ることができ、発光素子3の発光色をそれぞれ異ならせ
ることによって、多色発光のLEDチップが得られる。
FIG. 3C: In the dicing step using a dicer, a pattern including one light-emitting element 3 as shown by a dashed line in the figure, and two adjacent ones as shown by a portion surrounded by a thick line. Dicing may be performed as a pattern including the light emitting element 3 described above. This gives 1
A product in which two light emitting elements 3 are provided in each chip LED can be obtained. By making the light emitting elements 3 emit different colors, a multicolor light emitting LED chip can be obtained.

【0037】図(d):シート25とその上に積層して
いる製造用基板21をウエットエッチング等によって溶
融除去して、最終製品としてのLEDチップを得る。
FIG. 5D: The sheet 25 and the manufacturing substrate 21 laminated thereon are melted and removed by wet etching or the like to obtain an LED chip as a final product.

【0038】図3は以上の工程によって得られた面実装
型のLEDチップの拡大縦断面図である。
FIG. 3 is an enlarged vertical sectional view of the surface mount type LED chip obtained by the above steps.

【0039】製造用基板21とともにダイシングされた
樹脂層24は、発光素子3とワイヤ4を封止したパッケ
ージ5として形成されている。そして、電極1,2をプ
リント配線基板の電極パターンに合わせて導通搭載する
ことによって、発光素子3に通電してこれを発光させる
ことができる。
The resin layer 24 diced together with the manufacturing substrate 21 is formed as a package 5 in which the light emitting element 3 and the wire 4 are sealed. Then, the electrodes 1 and 2 are conductively mounted according to the electrode pattern of the printed wiring board, so that the light emitting element 3 can be energized to emit light.

【0040】本発明では、樹脂層24を製造用基板21
の表面にモールドした後にダイシングして発光素子3を
少なくとも1個含む面実装型のLEDが得られる。した
がって、ダイシングの際のカット幅に相当する分の材料
が失われるだけであり、従来の製造方法に比べると、材
料の損失割合を低減できる。また、パッケージ5に電極
1,2が含まれた構成なので平面積を小さくできるとと
もに、基板に相当するものもないので高さ寸法も短くで
き、薄型化が図られる。
In the present invention, the resin layer 24 is
And then dicing is performed to obtain a surface-mounted LED including at least one light emitting element 3. Therefore, only the material corresponding to the cut width at the time of dicing is lost, and the loss ratio of the material can be reduced as compared with the conventional manufacturing method. In addition, since the package 5 includes the electrodes 1 and 2, the plane area can be reduced, and the height dimension can be shortened because there is no equivalent to a substrate, so that the thickness can be reduced.

【0041】図4は図2の(c)で説明した複数の発光
素子3を一つのパッケージ5に含む構成の具体例を示す
概略斜視図である。
FIG. 4 is a schematic perspective view showing a specific example of a configuration in which the plurality of light emitting elements 3 described in FIG.

【0042】これらの例においては、先に説明した製造
用基板21に設けるディンプル21a,21bのパター
ンと異なって、中央に発光素子の搭載部に対応させたデ
ィンプルを配置し、これを挟んだ領域にワイヤボンディ
ング用のディンプルを形成したものを1つのパターンと
する。
In these examples, unlike the patterns of the dimples 21a and 21b provided on the manufacturing substrate 21 described above, the dimples corresponding to the mounting portions of the light emitting elements are arranged at the center, and the region sandwiching the dimples is provided. A dimple for wire bonding is formed as one pattern.

【0043】図4の(a)の例では、パッケージ6の下
面に素子電極6aとボンディング電極6b,6cがメッ
キ法によって形成され、素子電極6aの上には2個の発
光素子7,8が導通搭載されている。そして、これらの
発光素子7,8の表面電極7a,8aとボンディング電
極6b,6cとの間にそれぞれワイヤ7b,8bがボン
ディングされている。
In the example of FIG. 4A, an element electrode 6a and bonding electrodes 6b and 6c are formed on the lower surface of the package 6 by plating, and two light emitting elements 7 and 8 are formed on the element electrode 6a. Conductive mounting. The wires 7b and 8b are bonded between the surface electrodes 7a and 8a of the light emitting elements 7 and 8 and the bonding electrodes 6b and 6c, respectively.

【0044】図4の(b)の例もほぼ同様であり、発光
素子7,8をボンディング電極6b,6cとともに一列
に並ぶ向きに配列したアセンブリとしたものであり、同
図の(a)の例と同じ部材については共通の符号で指示
する。
The example shown in FIG. 4B is substantially the same, and is an assembly in which the light emitting elements 7 and 8 are arranged in a line along with the bonding electrodes 6b and 6c. The same members as those in the example are indicated by common reference numerals.

【0045】図5は図3に示した構成に代えて、電極
1,2のそれぞれがパッケージ5の側面に一致する部分
まで延ばしたエッジ1a,2aを形成した例である。
FIG. 5 shows an example in which, instead of the structure shown in FIG. 3, the edges 1a and 2a are formed so that each of the electrodes 1 and 2 extends to a portion corresponding to the side surface of the package 5.

【0046】図中において一点鎖線で示す製造用基板2
1には、素子搭載用及びボンディング用のディンプル2
1a,21bに加えて、これらに連なるエッジ用ディン
プル21c,21dがエッチングされている。したがっ
て、メッキ法によって電極1,2を形成するとき、これ
に連なるエッジ1a,2aも一体に形成される。
The manufacturing substrate 2 shown by a dashed line in FIG.
1 is a dimple 2 for mounting the element and bonding.
In addition to 1a and 21b, edge dimples 21c and 21d connected thereto are etched. Therefore, when the electrodes 1 and 2 are formed by the plating method, the edges 1a and 2a connected to the electrodes 1 and 2 are also integrally formed.

【0047】エッジ1a,2aはパッケージ5の表面ま
で達しているので、半田付けによってプリント基板に実
装固定するとき、表面に臨んでいるエッジ1a,2aの
光学的な自動認識がより確実に行われる。したがって、
LEDの実装の安定化が可能となるほか、半田のフィレ
ットがエッジ1a,2aとプリント基板との間に形成さ
れるので、より強固なアセンブリとすることができる。
Since the edges 1a and 2a reach the surface of the package 5, when they are mounted and fixed on the printed circuit board by soldering, the optical automatic recognition of the edges 1a and 2a facing the surface is more reliably performed. . Therefore,
In addition to stabilizing the mounting of the LED, the solder fillet is formed between the edges 1a and 2a and the printed circuit board, so that a more robust assembly can be achieved.

【0048】図6は図5の例において、発光素子3に対
応する部分のパッケージ5にレンズ5aを形成したもの
である。このレンズ5aは半球面体状に形成され、その
軸線を発光素子3の光軸に一致させた関係としたもの
で、その上端はパッケージ5の上面よりも突き出さない
大きさとする。
FIG. 6 shows the example of FIG. 5 in which a lens 5a is formed on a portion of the package 5 corresponding to the light emitting element 3. The lens 5a is formed in a hemispherical shape, and its axis is aligned with the optical axis of the light emitting element 3. The upper end of the lens 5a does not protrude from the upper surface of the package 5.

【0049】このようなレンズ5aを備えると、発光素
子3からの光が集光されるので、発光輝度が向上する。
また、プリント基板上に実装するときにはバキュームの
ノズルによってパッケージ5の上面が吸着されるハンド
リングとなるが、レンズ5aは上面から突き出ていない
ので、ノズルと干渉することがなく、実装に支障をきた
すこともない。
When such a lens 5a is provided, light from the light emitting element 3 is condensed, so that light emission luminance is improved.
In addition, when mounting on a printed circuit board, handling is performed in which the upper surface of the package 5 is sucked by the vacuum nozzle, but since the lens 5a does not protrude from the upper surface, it does not interfere with the nozzle, which hinders mounting. Nor.

【0050】また、図3から図6のいずれの例において
も、発光ダイオードを利用した発光素子3はそのp−n
接合域の発光層が凹状の電極1の中に含まれるような高
さ関係とする。これにより、電極1を光反射率が高いA
u等としておけば、発光層からの光を有効に発光方向に
反射させることができるので、発光輝度の向上を図るこ
とができる。
In each of the examples shown in FIGS. 3 to 6, the light emitting element 3 using the light emitting diode has its pn
The height relationship is such that the light emitting layer in the junction region is included in the concave electrode 1. As a result, the electrode 1 has a high light reflectance A
If u or the like is set, light from the light emitting layer can be effectively reflected in the light emitting direction, so that the light emission luminance can be improved.

【0051】なお、以上の例では面実装型のLEDチッ
プとして説明したが、フォトダイオード等のICでもよ
い。
In the above example, the surface mount type LED chip has been described, but an IC such as a photodiode may be used.

【0052】[0052]

【発明の効果】本発明では、型装置によるパッケージの
製作に代えて、樹脂層と製造用基板とをダイシングによ
ってカットしてチップを得るので、型製作に比べると製
造の自由度が向上するとともに材料の有効使用率も改善
される。
According to the present invention, a chip is obtained by cutting a resin layer and a manufacturing substrate by dicing instead of manufacturing a package by a mold device. Effective utilization of the material is also improved.

【0053】また、ダイシングのパターンを変えること
で、複数の光学素子の組合せを一つのパッケージに納め
た光電変換素子を得ることができ、特に発光ダイオード
とした場合にはフルカラー発光の表示に大きく貢献でき
る。
By changing the dicing pattern, it is possible to obtain a photoelectric conversion element in which a combination of a plurality of optical elements is housed in one package. Particularly, when a light emitting diode is used, it greatly contributes to full color light emission display. it can.

【0054】更に、電極にエッジを形成するものでは、
プリント基板等への実装の際の光学系による半田付けフ
ィレットの自動認識が確実に行われるので、実装性が大
幅に向上し製品歩留りも改善される。
Further, in the case of forming an edge on an electrode,
Since the soldering fillet is automatically recognized by the optical system at the time of mounting on a printed circuit board or the like, the mountability is greatly improved and the product yield is also improved.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の製造方法における電極形成から発光素
子の実装までの工程を示す概略図
FIG. 1 is a schematic diagram showing steps from electrode formation to light emitting element mounting in a manufacturing method of the present invention.

【図2】図1の工程に続く製品の完成までの工程を示す
概略図
FIG. 2 is a schematic diagram showing a process up to the completion of a product following the process of FIG. 1;

【図3】図2の最終工程で得られたチップLEDの拡大
断面図
FIG. 3 is an enlarged sectional view of a chip LED obtained in a final step of FIG. 2;

【図4】2個の発光素子を組み込んだチップLEDの例
を示す斜視図
FIG. 4 is a perspective view showing an example of a chip LED incorporating two light emitting elements.

【図5】電極にエッジを設けたチップLEDをその製造
用基板とともに示す概略縦断面図
FIG. 5 is a schematic longitudinal sectional view showing a chip LED provided with edges on electrodes together with a substrate for manufacturing the chip LED.

【図6】パッケージにレンズを設けたチップLEDの例
を示す概略縦断面図
FIG. 6 is a schematic longitudinal sectional view showing an example of a chip LED in which a lens is provided in a package.

【図7】従来の面実装型のチップLEDの概略斜視図FIG. 7 is a schematic perspective view of a conventional surface mount type chip LED.

【図8】パッケージの下面に電極を形成する従来例を示
す縦断面図
FIG. 8 is a longitudinal sectional view showing a conventional example in which electrodes are formed on the lower surface of a package.

【符号の説明】[Explanation of symbols]

1 電極 1a エッジ 2 電極 2a エッジ 3 発光素子 3a 表面電極 4 ワイヤ 5 パッケージ 6 パッケージ 6a 素子電極 6b,6c ボンディング電極 7,8 発光素子 7a,8a 表面電極 7b,8b ワイヤ 21 製造用基板 21a,21b ディンプル 22 レジスト膜 23 マスク 24 樹脂層 25 シート Reference Signs List 1 electrode 1a edge 2 electrode 2a edge 3 light emitting element 3a surface electrode 4 wire 5 package 6 package 6a element electrode 6b, 6c bonding electrode 7,8 light emitting element 7a, 8a surface electrode 7b, 8b wire 21 manufacturing substrate 21a, 21b dimple 22 resist film 23 mask 24 resin layer 25 sheet

Claims (8)

【特許請求の範囲】[Claims] 【請求項1】 製造用基板の表面に素子搭載用及びワイ
ヤボンディング用の凹状のディンプルをパターン形成す
る工程と、 前記ディンプルのそれぞれの内周に電極をコーティング
する工程と、 前記光学素子搭載用のディンプルに光学素子を実装する
とともにこの光学素子と前記ワイヤボンディング用のデ
ィンプルとの間をワイヤでボンディングする工程と、 前記製造用基板の表面を前記光学素子とワイヤを含んで
樹脂層によって封止する工程と、 前記樹脂層と製造用基板をダイシングして前記光学素子
とワイヤとを少なくとも1組含むピースとする工程と、 前記ピースから製造用基板だけを除去して前記樹脂層に
よるパッケージとこれに一体化した前記電極を表面に露
出させる工程とを含む光電変換素子の製造方法。
1. A step of patterning concave dimples for mounting elements and wire bonding on a surface of a manufacturing substrate, a step of coating an electrode on an inner periphery of each of the dimples, A step of mounting an optical element on the dimple and bonding the optical element and the dimple for wire bonding with a wire; and sealing a surface of the manufacturing substrate with a resin layer including the optical element and the wire. Dicing the resin layer and the manufacturing substrate into a piece including at least one set of the optical element and the wire; and removing only the manufacturing substrate from the piece to form a package using the resin layer. Exposing the integrated electrode to the surface.
【請求項2】 前記製造用基板の表面に素子搭載用及び
ワイヤボンディング用の凹状のディンプルをパターン形
成する工程において、前記ディンプルに連ねて前記ピー
スの端部にかけてほぼ一様の深さのエッジ用ディンプル
を形成する工程を含む請求項1記載の光電変換素子の製
造方法。
2. In the step of patterning concave dimples for mounting elements and wire bonding on the surface of the substrate for manufacturing, an edge having a substantially uniform depth extending to an end of the piece following the dimples. The method for manufacturing a photoelectric conversion element according to claim 1, further comprising a step of forming a dimple.
【請求項3】 前記光学素子を発光ダイオードとし、前
記光学素子搭載用のディンプルを、実装する発光ダイオ
ードの発光層が含まれる深さまで形成する請求項1また
は2記載の光電変換素子の製造方法。
3. The method according to claim 1, wherein the optical element is a light emitting diode, and the dimple for mounting the optical element is formed to a depth including a light emitting layer of the light emitting diode to be mounted.
【請求項4】 樹脂のパッケージと、このパッケージの
下面に形成された一対の電極と、前記パッケージの内部
に封止されて一方の電極に導通搭載される光学素子と、
この光学素子と他方の電極との間にボンディングされ且
つ前記パッケージの内部に封止されたワイヤとを備え、
前記電極は、前記パッケージの周面とほぼ同じ面まで展
開させたエッジを外面に臨ませて形成してなる光電変換
素子。
4. A resin package, a pair of electrodes formed on a lower surface of the package, and an optical element sealed inside the package and conductively mounted on one of the electrodes.
A wire bonded between the optical element and the other electrode and sealed inside the package,
A photoelectric conversion element, wherein the electrode is formed with an edge developed to substantially the same surface as a peripheral surface of the package facing an outer surface.
【請求項5】 樹脂のパッケージと、このパッケージの
下面に形成された複数組の電極と、前記パッケージの内
部に封止されて各組の電極の一方の電極に導通搭載され
る光学素子と、この光学素子と他方の電極との間にボン
ディングされ且つ前記パッケージの内部に封止されたワ
イヤとを備え、前記複数組の電極は、前記パッケージの
周面とほぼ同じ面まで展開させたエッジを外面に臨ませ
て形成してなる光電変換素子。
5. A resin package, a plurality of sets of electrodes formed on the lower surface of the package, and an optical element sealed inside the package and electrically mounted on one of the electrodes of each set of electrodes. A wire bonded between the optical element and the other electrode and sealed inside the package, wherein the plurality of sets of electrodes have edges developed to approximately the same surface as the peripheral surface of the package. A photoelectric conversion element formed facing the outer surface.
【請求項6】 樹脂のパッケージと、このパッケージの
下面に形成された素子搭載用の電極及びボンディング用
の複数の電極と、前記パッケージの内部に封止されて前
記素子搭載用の電極に導通搭載される複数の光学素子
と、これらの光学素子のそれぞれとボンディング用の各
電極との間にボンディングされ且つ前記パッケージの内
部に封止されたワイヤとを備え、前記素子搭載用及びボ
ンディング用の電極は、前記パッケージの周面とほぼ同
じ面まで展開させたエッジを外面に臨ませて形成してな
る光電変換素子。
6. A resin package, an element mounting electrode and a plurality of bonding electrodes formed on the lower surface of the package, and electrically mounted on the element mounting electrode sealed inside the package. A plurality of optical elements, and a wire bonded between each of these optical elements and each of the bonding electrodes and sealed inside the package. Is a photoelectric conversion element formed such that an edge developed to almost the same surface as the peripheral surface of the package faces the outer surface.
【請求項7】 前記パッケージには、前記光学素子に対
応する位置に集光用の球面状のレンズを前記パッケージ
の表面以下の高さとして形成してなる請求項4から6の
いずれかに記載の光電変換素子。
7. The package according to claim 4, wherein a spherical lens for light collection is formed at a position corresponding to the optical element so as to have a height equal to or lower than the surface of the package. Photoelectric conversion element.
【請求項8】 前記光学素子を発光ダイオードとし、こ
の発光ダイオードを導通搭載する側の一方の電極を、凹
状断面であって且つ前記発光ダイオードの発光層を埋没
状態に含む深さに形成してなる請求項4から7のいずれ
かに記載の光電変換素子。
8. The optical element is a light emitting diode, and one electrode on the side on which the light emitting diode is conductively mounted is formed to have a concave cross section and a depth including a light emitting layer of the light emitting diode in a buried state. The photoelectric conversion element according to claim 4.
JP21060698A 1998-07-27 1998-07-27 Method for manufacturing photoelectric conversion element Expired - Lifetime JP3356068B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21060698A JP3356068B2 (en) 1998-07-27 1998-07-27 Method for manufacturing photoelectric conversion element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21060698A JP3356068B2 (en) 1998-07-27 1998-07-27 Method for manufacturing photoelectric conversion element

Publications (2)

Publication Number Publication Date
JP2000049383A true JP2000049383A (en) 2000-02-18
JP3356068B2 JP3356068B2 (en) 2002-12-09

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ID=16592118

Family Applications (1)

Application Number Title Priority Date Filing Date
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