KR20020058216A - Stacked semiconductor package and its manufacturing method - Google Patents

Stacked semiconductor package and its manufacturing method Download PDF

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Publication number
KR20020058216A
KR20020058216A KR1020000086253A KR20000086253A KR20020058216A KR 20020058216 A KR20020058216 A KR 20020058216A KR 1020000086253 A KR1020000086253 A KR 1020000086253A KR 20000086253 A KR20000086253 A KR 20000086253A KR 20020058216 A KR20020058216 A KR 20020058216A
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South Korea
Prior art keywords
semiconductor package
adhesive layer
wiring board
wiring pattern
semiconductor chip
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KR1020000086253A
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Korean (ko)
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KR100393102B1 (en
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임세진
김상흔
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마이클 디. 오브라이언
앰코 테크놀로지 코리아 주식회사
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Priority to KR10-2000-0086253A priority Critical patent/KR100393102B1/en
Publication of KR20020058216A publication Critical patent/KR20020058216A/en
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Publication of KR100393102B1 publication Critical patent/KR100393102B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Abstract

PURPOSE: A stacked type semiconductor package and a method for fabricating a wiring substrate used for the same are provided to reduce a fabricating cost by adhering a wiring substrate on the first semiconductor package including the first semiconductor chip and forming the second semiconductor chip on the wiring substrate. CONSTITUTION: A semiconductor chip(15) is adhered to a chip loading plate(14). A plurality of inner leads(17) are extended to an outer circumference of the semiconductor chip(15). The semiconductor chip(15) is connected with the inner leads(17) by a conductive wire(16). A sealing portion(19) is formed on the chip loading plate(14), the semiconductor chip(15), the conductive wire(16), and inner leads(17) by a sealant. A plurality of outer leads(18) are connected with the inner leads(17). A wiring substrate(30) is adhered on the sealing portion(19) of the first semiconductor package(11). A plurality of wiring patterns(33) of the wiring substrate(30) are connected with upper faces of the outer leads(18). Conductive balls(22) are fused on ball lands(32) of the wiring substrate(30).

Description

스택형 반도체패키지 및 이에 이용되는 가요성 배선기판의 제조 방법{Stacked semiconductor package and its manufacturing method}Stacked semiconductor package and a method of manufacturing a flexible wiring board for use

본 발명은 스택형 반도체패키지 및 이에 이용되는 가요성 배선기판의 제조 방법에 관한 것으로, 더욱 상세하게 설명하면 통상의 반도체패키지 상면에 또다른 반도체패키지가 스택(Stack)된 스택형 반도체패키지 및 이에 이용되는 가요성 배선기판의 제조 방법에 관한 것이다.The present invention relates to a stack-type semiconductor package and a method for manufacturing a flexible wiring board used therein. In detail, a stack-type semiconductor package in which another semiconductor package is stacked on an upper surface of a conventional semiconductor package and its use It relates to a method for producing a flexible wiring board.

통상 스택형 반도체패키지는 리드프레임이나 인쇄회로기판 등에 다수의 반도체칩을 수직방향으로 스택한 후, 상기 스택된 반도체칩끼리 또는 반도체칩과 리드프레임 또는 인쇄회로기판을 도전성와이어로 상호 본딩한 것을 말한다. 이러한 스택형 반도체패키지는 하나의 봉지부 내측에 다수의 반도체칩을 탑재함으로써 전기적으로 고기능화되고, 또한 마더보드에서의 실장밀도를 높일 수 있기 때문에 최근 대량으로 제조되고 있다.In general, a stacked semiconductor package refers to a plurality of semiconductor chips stacked in a vertical direction such as a lead frame or a printed circuit board, and then bonded to the stacked semiconductor chips or a semiconductor chip and a lead frame or a printed circuit board with conductive wires. . Such stacked semiconductor packages have been manufactured in large quantities in recent years since they are electrically functionalized by mounting a plurality of semiconductor chips inside one encapsulation portion, and the mounting density of the motherboard can be increased.

이러한 종래 스택형 반도체패키지의 한예가 도1에 도시되어 있다.One example of such a conventional stacked semiconductor package is shown in FIG.

도시된 바와 같이 통상 접착층(2')을 중심으로 그 상면에는 본드핑거(4')를 포함하는 배선패턴이 형성되어 있고, 하면에는 볼랜드(6')를 포함하는 배선패턴이 형성되어 있으며, 상기 상,하면의 배선패턴은 도전성비아홀(8')로 상호 연결된 회로기판(10')이 구비되어 있다. 상기 회로기판(10')의 상면 중앙부에는 접착제로 제1반도체칩(12')이 접착되어 있고, 상기 제1반도체칩(12')의 상면에는 접착제로 또다른 제2반도체칩(14')이 접착되어 있다.As shown, a wiring pattern including a bond finger 4 'is formed on an upper surface of the adhesive layer 2', and a wiring pattern including a ball land 6 'is formed on a lower surface of the adhesive layer 2'. The upper and lower wiring patterns are provided with circuit boards 10 'interconnected by conductive via holes 8'. The first semiconductor chip 12 'is bonded to the center of the upper surface of the circuit board 10' with an adhesive, and the second semiconductor chip 14 'is bonded to the upper surface of the first semiconductor chip 12'. Is bonded.

상기 제1반도체칩(12') 및 제2반도체칩(14')의 입출력패드는 모두 도전성와이어(16')에 의해 회로기판의 본드핑거(4')에 접속되어 있으며, 상기 회로기판(10')의 하면에 형성된 볼랜드(6')에는 다수의 도전성볼(18')이 융착되어 있다.The input / output pads of the first semiconductor chip 12 'and the second semiconductor chip 14' are both connected to the bond fingers 4 'of the circuit board by conductive wires 16', and the circuit board 10 A plurality of conductive balls 18 'are fused to the ball land 6' formed on the lower surface of ').

상기 회로기판(10')의 상면에 위치된 제1반도체칩(12'), 제2반도체칩(14') 및 도전성와이어(16') 등은 모두 봉지재로 봉지되어 소정의 봉지부(20')를 형성하고 있다.The first semiconductor chip 12 ', the second semiconductor chip 14', the conductive wire 16 ', and the like, which are located on the upper surface of the circuit board 10', are all encapsulated with an encapsulant so that the predetermined encapsulation portion 20 ').

도면중 미설명 부호 7'는 배선패턴을 외부환경으로부터 보호하기 위해 그 표면에 코팅된 커버코트이다.In the drawings, reference numeral 7 ′ is a cover coat coated on a surface thereof to protect the wiring pattern from the external environment.

그러나, 이러한 종래의 반도체패키지는 고가의 회로기판을 이용함으로써(전체 패키지 제조 비용의 60% 이상이 상기 회로기판에 할당됨), 전체적으로 반도체패키지의 원가가 높아지는 단점이 있다.However, such a conventional semiconductor package has a disadvantage in that the cost of the semiconductor package is increased by using an expensive circuit board (more than 60% of the total package manufacturing cost is allocated to the circuit board).

또한, 상기 제1반도체칩 상면에 또다른 제2반도체칩이 직접 접착되기 때문에, 상기 제1반도체칩의 와이어 본딩을 고려하여, 상기 제2반도체칩의 크기가 상기 제1반도체칩의 크기보다 반듯이 작아야 함으로써, 탑재할 수 있는 반도체칩의 크기 또는 종류에 한계가 있다.In addition, since another second semiconductor chip is directly bonded to an upper surface of the first semiconductor chip, the size of the second semiconductor chip may be larger than that of the first semiconductor chip in consideration of wire bonding of the first semiconductor chip. By being small, there is a limit to the size or type of semiconductor chip that can be mounted.

비록, 현재 동일한 크기 또는 상부의 반도체칩이 하부의 반도체칩보다 더 큰 반도체칩 스택 기술이 개발되고 있으나, 상기 반도체칩의 스택에 사용되는 접착제의 두께를 증가시켜야 함은 물론, 공정이 복잡해지고, 또한 와이어 본딩의 어려움으로 인하여 제조 비용이 상승하는 부담이 있다.Although a semiconductor chip stack technology is currently being developed in which the same size or upper semiconductor chip is larger than the lower semiconductor chip, the thickness of the adhesive used in the stack of the semiconductor chip must be increased, and the process is complicated. In addition, due to the difficulty of wire bonding, there is a burden that the manufacturing cost increases.

더불어, 제1반도체칩 상면에 접착제를 이용하여 제2반도체칩을 정확한 위치에 접착하여야 함으로써, 정밀도가 높은 장비가 요구되며, 또한 와이어 본딩을 2회에 걸쳐 수행함으로써, 그만큼 불량률이 높은 단점이 있다.In addition, by attaching the second semiconductor chip at the correct position by using an adhesive on the upper surface of the first semiconductor chip, high precision equipment is required, and by performing the wire bonding twice, there is a disadvantage that the defect rate is high. .

따라서 본 발명은 상기와 같은 종래의 문제점을 해결하기 위해 안출한 것으로, 하나의 반도체칩을 탑재한 통상의 제1반도체패키지 상면에 특정 형태의 가요성 배선기판을 접착하고, 그 상면에 통상의 제2반도체패키지를 접속함으로써, 저가인 동시에 신뢰성이 높은 스택형 반도체패키지 및 이에 이용되는 가요성 배선기판의 제조 방법을 제공하는데 있다.Accordingly, the present invention has been made to solve the above-mentioned conventional problems, and a specific type of flexible wiring board is adhered to an upper surface of a conventional first semiconductor package equipped with one semiconductor chip, and a conventional By connecting two semiconductor packages, a low-cost and reliable stack-type semiconductor package and a method of manufacturing a flexible wiring board used therein are provided.

도1은 종래의 통상적인 스택형 반도체패키지를 도시한 단면도이다.1 is a cross-sectional view showing a conventional stacked semiconductor package.

도2는 본 발명에 이용된 가요성 배선기판을 도시한 평면도이다.2 is a plan view showing a flexible wiring board used in the present invention.

도3a 내지 도3c는 본 발명에 의한 스택형 반도체패키지를 도시한 부분 단면도이다.3A to 3C are partial cross-sectional views showing a stacked semiconductor package according to the present invention.

도4a 내지 도4f는 본 발명에 가요성 배선기판의 의 제조 방법을 도시한 순차 설명도이다.4A to 4F are sequential explanatory diagrams showing a method for manufacturing a flexible wiring board according to the present invention.

- 도면중 주요 부호에 대한 설명 --Description of the main symbols in the drawings-

101,102,103; 본 발명에 의한 스택형 반도체패키지101,102,103; Stacked semiconductor package according to the present invention

11,12,13; 제1반도체패키지20; 제2반도체패키지11,12,13; First semiconductor package 20; Second Semiconductor Package

22; 도전성볼14; 칩탑재판22; Conductive ball 14; Chip board

15; 반도체칩16; 도전성와이어15; Semiconductor chip 16; Conductive Wire

17; 내부리드18; 외부리드17; Internal lead 18; External lead

19; 봉지부30; 가요성 배선기판19; Encapsulation unit 30; Flexible wiring board

31; 접착층32; 볼랜드31; Adhesive layer 32; Borland

33; 배선패턴34; 커버코트33; Wiring pattern 34; Cover coat

상기한 목적을 달성하기 위해 본 발명에 의한 스택형 반도체패키지는 봉지부의 측부 외주연으로 마더보드에 접속될 리드가 돌출된 제1반도체패키지와; 상기 봉지부의 상면에 절연성의 가요성 접착층이 접착되고, 상기 접착층의 상면에는 다수의 도전성 볼랜드가 어레이된 동시에, 상기 볼랜드로부터는 상기 제1반도체패키지의 리드 상면에까지 연장되어 접속되는 도전성 배선패턴이 형성된 가요성 배선기판과; 상기 가요성 배선기판의 볼랜드에 도전성볼을 통해 접속된 제2반도체패키지를 포함하여 이루어진 것을 특징으로 한다.In order to achieve the above object, the stack-type semiconductor package according to the present invention includes a first semiconductor package having a lead protruding from the side portion of the encapsulation portion to be connected to the motherboard; An insulating flexible adhesive layer is adhered to the upper surface of the encapsulation portion, and a plurality of conductive borlands are arrayed on the upper surface of the adhesive layer, and a conductive wiring pattern extending from and connected to the upper surface of the lead of the first semiconductor package is formed. A flexible wiring board; And a second semiconductor package connected to the ball land of the flexible wiring board through a conductive ball.

여기서, 상기 가요성 배선기판의 배선패턴은 상기 제1반도체패키지의 리드 상면에 도전성 에폭시에 의해 접착될 수 있다.Here, the wiring pattern of the flexible wiring board may be bonded to the upper surface of the lead of the first semiconductor package by a conductive epoxy.

상기 제1반도체패키지는 칩탑재판에 반도체칩이 접착되어 있고, 상기 반도체칩의 외주연으로는 다수의 내부리드가 연장되어 있으며, 상기 반도체칩과 내부리드는 도전성와이어로 접속되어 있고, 상기 칩탑재판, 반도체칩, 도전성와이어 및 내부리드는 봉지재로 봉지되어 일정 형태의 봉지부가 형성되어 있으며, 상기 봉지부 외측으로는 상기 내부리드에 연결된 외부리드가 돌출되어 있고, 상기 외부리드 상면에 상기 가요성 배선기판의 도전성 배선패턴이 접속될 수 있다.In the first semiconductor package, a semiconductor chip is bonded to a chip mounting plate, and a plurality of internal leads are extended on the outer circumference of the semiconductor chip, and the semiconductor chip and the internal lead are connected with conductive wires. The mounting plate, the semiconductor chip, the conductive wire, and the inner lead are encapsulated with an encapsulant to form a certain encapsulation portion. An outer lead connected to the inner lead protrudes outside the encapsulation portion, The conductive wiring pattern of the flexible wiring board can be connected.

또한, 상기 제1반도체패키지는 둘레 하면에 부분에칭부가 형성된 칩탑재판에 반도체칩이 접착되어 있고, 상기 반도체칩의 외주연으로는 부분에칭부가 형성된 다수의 내부리드가 위치되어 있으며, 상기 반도체칩과 리드는 도전성와이어로 연결된 동시에, 상기 칩탑재판, 반도체칩 및 리드가 봉지재로 봉지되어 일정 형태의 봉지부를 형성하고 있되, 상기 리드의 상면 일정영역은 봉지부 외측으로 노출되어 상기 가요성 배선기판의 도전성 배선패턴이 접속될 수도 있다.In addition, the first semiconductor package has a semiconductor chip bonded to a chip mounting plate having a partial etching portion on a lower surface thereof, and a plurality of internal leads having a partial etching portion are positioned on the outer circumference of the semiconductor chip. The lead and the lead are connected with conductive wires, and the chip mounting plate, the semiconductor chip, and the lead are encapsulated with an encapsulant to form a certain encapsulation portion. The conductive wiring pattern of the substrate may be connected.

상기한 목적을 달성하기 위해 본 발명에 의한 스택형 반도체패키지에 이용되는 배선기판의 제조 방법은 접착층 표면에 구리층이 형성된 원판(原板)을 제공하는 단계와; 상기 구리박막 표면에 소정 패턴을 갖는 감광막을 형성하는 단계와; 상기 감광막이 형성된 원판을 화학용액으로 에칭하여, 상기 접착층 표면에 볼랜드 및 배선패턴이 형성되도록 하는 단계와; 상기 볼랜드 및 배선패턴 상면의 감광막을 제거하는 단계와; 상기 접착층의 둘레를 일정폭만큼 제거하여 상기 배선패턴이 접착층 외주연으로 돌출되도록 하는 단계를 포함하여 이루어진 것을 특징으로 한다.In order to achieve the above object, a method of manufacturing a wiring board for use in a stacked semiconductor package according to the present invention comprises the steps of providing an original plate with a copper layer formed on the surface of the adhesive layer; Forming a photosensitive film having a predetermined pattern on the surface of the copper thin film; Etching the original plate on which the photoresist film is formed with a chemical solution to form a ball land and a wiring pattern on the surface of the adhesive layer; Removing the photoresist on the upper surface of the ball land and the wiring pattern; And removing the circumference of the adhesive layer by a predetermined width so that the wiring pattern protrudes to the outer periphery of the adhesive layer.

여기서, 상기 원판은 접착층 표면에 구리박막을 접착시켜 형성된 것이 제공될 수 있다.Here, the disc may be provided by bonding a copper thin film on the surface of the adhesive layer.

또한, 상기 원판은 접착층 표면에 구리 입자를 증착하여 형성된 것이 제공될 수도 있다.In addition, the disc may be provided by depositing copper particles on the surface of the adhesive layer.

더불어, 상기 볼랜드 및 배선패턴의 단부를 제외한 나머지 영역에는 커버코트가 코팅되는 단계가 더 포함될 수도 있다.In addition, the cover coat may be further included in the remaining areas except for the ends of the ball land and the wiring pattern.

상기와 같이 하여 본 발명에 의한 스택형 반도체패키지 및 이것에 이용되는 배선기판의 제조 방법에 의하면, 통상의 제1반도체패키지를 구비하고, 상기 제1반도체패키지의 봉지부 상면에는 배선패턴이 형성된 가요성 배선기판을 접착시키며, 그 상면에는 다시 통상의 제2반도체패키지를 접속시킴으로써, 제1반도체패키지와 제2반도체패키지가 상기 가요성 배선기판에 의해 상호 접속된다.According to the stack semiconductor package according to the present invention as described above and a method for manufacturing a wiring board used therein, a flexible first semiconductor package is provided, and a wiring pattern is formed on an upper surface of the encapsulation portion of the first semiconductor package. The first wiring package and the second semiconductor package are interconnected by the flexible wiring board by adhering a sex wiring board, and connecting the second semiconductor package to the upper surface thereof.

따라서, 본 발명은 통상의 제1반도체패키지 및 제2반도체패키지를 각각 제조하고, 별도로 가요성 배선기판을 상기 제1반도체패키지의 상면에 접착시킴으로써, 복잡한 공정을 통하지 않고서도 간단한 방법 및 구조로 스택형 반도체패키지를 구현하게 되는 장점이 있다.Accordingly, the present invention manufactures a conventional first semiconductor package and a second semiconductor package, respectively, and separately attaches a flexible wiring board to an upper surface of the first semiconductor package, thereby stacking in a simple method and structure without going through a complicated process. There is an advantage to implement the type semiconductor package.

이하 본 발명이 속한 기술분야에서 통상의 지식을 가진 자가 본 발명을 용이하게 실시할 수 있을 정도로 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 상세하게 설명하면 다음과 같다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings such that those skilled in the art can easily implement the present invention.

도2는 본 발명에 이용된 가요성 배선기판(30)을 도시한 평면도이다.2 is a plan view showing a flexible wiring board 30 used in the present invention.

도시된 바와 같이 본 발명에 이용된 가요성 배선기판(30)은 절연성의 가요성 접착층(31)(도3a 참조) 예를 들면, 가요성 필름 또는 테이프가 대략 사각판상으로구비되어 있고, 상기 접착층(31)의 중앙에는 다수의 도전성 볼랜드(32)가 어레이(Array)되어 있다. 상기 각 볼랜드(32)로부터는 도전성 배선패턴(33)이 연결된 동시에, 이 배선패턴(33)은 상기 접착층(31)의 외주연까지 일정길이 연장되어 있다. 여기서, 상기 볼랜드(32) 및 배선패턴(33)은 통상적인 구리 박막으로 형성된 것이다. 또한, 상기 볼랜드(32)를 제외한 상기 배선패턴(33) 및 접착층(31)의 표면에는 상기 배선패턴(33)을 외부 환경으로부터 보호하기 위해 커버코트(34)가 코팅되어 있다.As shown, the flexible wiring board 30 used in the present invention includes an insulating flexible adhesive layer 31 (see FIG. 3A), for example, a flexible film or tape is provided in a substantially rectangular plate shape. In the center of 31, a plurality of conductive borland 32 is arrayed. Conductive wiring patterns 33 are connected to each of the ball lands 32, and the wiring patterns 33 extend a predetermined length to the outer periphery of the adhesive layer 31. Here, the ball land 32 and the wiring pattern 33 is formed of a conventional copper thin film. In addition, the cover coat 34 is coated on the surfaces of the wiring pattern 33 and the adhesive layer 31 except for the ball land 32 to protect the wiring pattern 33 from an external environment.

한편, 이러한 가요성 배선기판(30)이 이용된 본 발명에 의한 스택형 반도체패키지(101,102,103)가 도3a 내지 도3c에 도시되어 있다.Meanwhile, the stacked semiconductor packages 101, 102, and 103 according to the present invention using such a flexible wiring board 30 are shown in Figs. 3A to 3C.

도3a의 스택형 반도체패키지(101)를 참조하면, 먼저 통상의 제1반도체패키지(11)가 구비되어 있다. 즉, 칩탑재판(14)에 반도체칩(15)이 접착되어 있고, 상기 반도체칩(15)의 외주연으로는 다수의 내부리드(17)가 연장되어 있으며, 상기 반도체칩(15)과 내부리드(17)는 도전성와이어(16)로 접속되어 있고, 상기 칩탑재판(14), 반도체칩(15), 도전성와이어(16) 및 내부리드(17)는 봉지재로 봉지되어 일정 형태의 봉지부(19)가 형성되어 있다. 상기 봉지부(19) 외측으로는 상기 내부리드(17)에 연결된 외부리드(18)가 돌출된 일반적인 리드프레임을 이용한 반도체패키지이다.Referring to the stacked semiconductor package 101 of Fig. 3A, first, a conventional first semiconductor package 11 is provided. That is, the semiconductor chip 15 is bonded to the chip mounting plate 14, and a plurality of internal leads 17 are extended on the outer periphery of the semiconductor chip 15, and the semiconductor chip 15 and the inside The lead 17 is connected by a conductive wire 16. The chip mounting plate 14, the semiconductor chip 15, the conductive wire 16 and the inner lead 17 are encapsulated with an encapsulant to encapsulate a certain shape. The part 19 is formed. Outside the encapsulation portion 19 is a semiconductor package using a general lead frame in which the outer lead 18 connected to the inner lead 17 protrudes.

여기서, 상술한 구조의 가요성 배선기판(30)이 상기 제1반도체패키지(11)의 봉지부(19) 상면에 접착되어 있으며, 상기 배선기판(30)중 배선패턴(33)은 상기 외부리드(18)의 상면에 접속되어 있다. 상기 배선패턴(33)과 외부리드(18)의 접속은통상적인 도전성 에폭시(Conductive Epoxy)를 이용하거나 또는 솔더 플레이팅(Solder Plating) 또는 탭본딩(TAB Bonding) 장비를 이용하여 수행할 수 있다.Here, the flexible wiring board 30 having the above-described structure is bonded to the upper surface of the encapsulation portion 19 of the first semiconductor package 11, and the wiring pattern 33 of the wiring board 30 is the external lead. It is connected to the upper surface of (18). Connection of the wiring pattern 33 and the external lead 18 may be performed using a conventional conductive epoxy or using solder plating or tab bonding equipment.

한편, 상기 가요성 배선기판(30)의 볼랜드(32)에는 솔더볼과 같은 도전성볼(22)에 의해 통상적인 제2반도체패키지(20)가 접속되어 있다. 이와 같은 제2반도체패키지(20)는 통상적인 볼그리드어레이(Ball Grid Array) 반도체패키지가 적당할 것이다.On the other hand, a conventional second semiconductor package 20 is connected to the ball land 32 of the flexible wiring board 30 by conductive balls 22 such as solder balls. The second semiconductor package 20 may be a conventional ball grid array semiconductor package.

다음으로 도3b의 스택형 반도체패키지(102)를 참조한다.Next, reference is made to the stacked semiconductor package 102 of FIG. 3B.

도시된 바와 같이 먼저, 제1반도체패키지(12)가 구비되어 있다. 상기 제1반도체패키지(12)는 둘레 하면에 부분에칭부(14a)가 형성된 칩탑재판(14)이 구비되어 있고, 상기 칩탑재판(14) 상면에는 반도체칩(15)이 접착되어 있다. 또한, 상기 반도체칩(15)의 외주연으로는 부분에칭부(17a)가 형성된 다수의 리드(17)가 위치되어 있으며, 상기 반도체칩(15)과 리드(17)는 도전성와이어(16)로 연결되어 있다. 또한, 상기 칩탑재판(14), 반도체칩(15) 및 리드(17)는 봉지재로 봉지되어 일정 형태의 봉지부(19)를 형성하고 있되, 상기 리드(17)의 상면 일정영역 및 하면은 봉지부(19) 외측으로 노출된 통상의 MLF(Micro Lead Frame) 패키지이다.First, as shown, the first semiconductor package 12 is provided. The first semiconductor package 12 is provided with a chip mounting plate 14 having a partial etching portion 14a formed on a lower surface thereof, and a semiconductor chip 15 is bonded to the upper surface of the chip mounting plate 14. In addition, a plurality of leads 17 having a partial etching portion 17a are positioned at the outer circumference of the semiconductor chip 15, and the semiconductor chips 15 and the leads 17 are formed of conductive wires 16. It is connected. In addition, the chip mounting plate 14, the semiconductor chip 15, and the lead 17 are encapsulated with an encapsulant to form an encapsulation portion 19 having a predetermined shape. Is a conventional MLF (Micro Lead Frame) package exposed outside the encapsulation unit 19.

여기서, 상술한 구조의 가요성 배선기판(30)은 상기 제1반도체패키지(12)의 봉지부(19) 상면에 접착되어 있으며, 상기 배선기판(30)중 배선패턴(33)은 상기 리드(17)의 상면에 접속되어 있다. 상기 배선패턴(33)과 리드(17)의 접속은 통상적인 도전성 에폭시(Conductive Epoxy)를 이용하거나 솔더 플레이팅(Solder Plating) 또는 탭본딩(TAB Bonding) 장비를 이용하여 접속할 수 있다.Here, the flexible wiring board 30 having the above-described structure is bonded to the upper surface of the encapsulation portion 19 of the first semiconductor package 12, and the wiring pattern 33 of the wiring board 30 is the lead ( 17) is connected to the upper surface. The wiring pattern 33 and the lead 17 may be connected by using a conventional conductive epoxy or by using solder plating or tab bonding equipment.

한편, 상기 가요성 배선기판(30)의 볼랜드(32)에는 솔더볼과 같은 도전성볼(22)에 의해 통상적인 제2반도체패키지(20)가 접속되어 있다. 이와 같은 제2반도체패키지(20)는 상술한 바와 같이 통상적인 볼그리드어레이(Ball Grid Array) 반도체패키지가 적당하다.On the other hand, a conventional second semiconductor package 20 is connected to the ball land 32 of the flexible wiring board 30 by conductive balls 22 such as solder balls. As described above, the second semiconductor package 20 may be a conventional ball grid array semiconductor package.

도3c의 스택형 반도체패키지(103) 역시, 제1반도체패키지(13)로서 도전성볼(20)이 어레이된 MLF 패키지가 이용될 수 있으며, 나머지 구조는 상기 도3b의 구조와 동일하므로 그 설명을 생략하기로 한다.The stacked semiconductor package 103 of FIG. 3C may also be an MLF package in which conductive balls 20 are arranged as the first semiconductor package 13, and the rest of the structure is the same as that of FIG. 3B. It will be omitted.

도4a 내지 도4f는 본 발명에 의한 가요성 배선기판의 제조 방법을 도시한 순차 설명도이며, 이를 참조하여 그 제조 방법을 상세히 설명하면 다음과 같다.4A to 4F are sequential explanatory diagrams illustrating a method of manufacturing a flexible wiring board according to the present invention. Referring to this, the method of manufacturing the flexible wiring board will be described in detail as follows.

1. 원판(原板)제공 단계로서(도4a 참조), 쉽게 휘어질 수 있는 접착층(31)(예를 들면, 필름 또는 테이프 등등)의 표면에 일정 두께로 구리층(333)이 형성된 원판(300)을 제공한다.1. A raw plate 300 in which a copper layer 333 is formed to a certain thickness on a surface of an adhesive layer 31 (for example, a film or a tape, etc.) that can be easily bent as a raw material providing step (see FIG. 4A). ).

여기서, 상기 원판(300)은 접착층(31) 표면에 얇은 구리박막(Copper Foil)이 접착된 것을 제공하거나 또는 상기 접착층(31) 표면에 구리 입자(Copper Particle)가 증착된 것을 제공할 수 있다.Here, the disc 300 may provide that a thin copper foil is adhered to the surface of the adhesive layer 31 or that copper particles are deposited on the surface of the adhesive layer 31.

2. 감광막 형성 단계로서(도4b 참조), 상기 구리층(333) 표면에 소정 패턴을 갖는 감광막(41)을 형성한다. 상기 감광막 형성 방법은 주지된 바와 같이, 소정 패턴이 그려진 마스크와 감광막을 이용하여 상기 구리층 표면에 차후 형성될 볼랜드 및 배선패턴과 같은 모양의 감광막이 형성되도록 한다. 상기 감광막 대신에 드라이필름(Dry Film)을 이용할 수도 있다.2. As a photosensitive film forming step (see FIG. 4B), a photosensitive film 41 having a predetermined pattern is formed on the surface of the copper layer 333. In the method of forming the photoresist film, a photoresist film having a shape such as a ball land and a wiring pattern to be formed later is formed on the surface of the copper layer by using a mask and a photoresist film having a predetermined pattern drawn thereon. Instead of the photosensitive film, a dry film may be used.

3. 패턴 형성 단계로서(도4c 참조), 상기 감광막(41)이 형성된 원판(300)에 황산, 염산 또는 질산과 같은 산성용액을 제공하여 상기 접착층(31) 표면에 볼랜드(32) 및 배선패턴(33) 등이 형성되도록 한다.3. As a pattern forming step (see FIG. 4C), an acid solution such as sulfuric acid, hydrochloric acid, or nitric acid is provided on the original plate 300 on which the photoresist film 41 is formed, so that the ball land 32 and the wiring pattern are formed on the surface of the adhesive layer 31. (33) and so on.

4. 감광막 제거 단계로서(도4d 참조), 상기 볼랜드(32) 및 배선패턴(33) 상면의 감광막(41)을 제거한다.4. As a photosensitive film removing step (see FIG. 4D), the photosensitive film 41 on the upper surface of the ball land 32 and the wiring pattern 33 is removed.

5. 접착층의 일정 영역 제거 단계로서(도4e 참조), 상기 접착층(31)의 둘레를 일정폭만큼 제거하여 상기 배선패턴(33)중 단부가 상기 접착층(31) 외주연으로 돌출되도록 한다.5. As a step of removing a predetermined region of the adhesive layer (see FIG. 4E), the circumference of the adhesive layer 31 is removed by a predetermined width so that an end portion of the wiring pattern 33 protrudes to the outer periphery of the adhesive layer 31.

6. 커버코트 코팅 단계로서(도4f 참조), 상기 볼랜드(32) 및 상기 접착층(31)의 외주연으로 돌출된 배선패턴(33)을 제외한 나머지 영역 즉, 접착층(31)의 상면에 커버코트(34)를 코팅함으로써, 상기 배선패턴 등이 외부 환경으로부터 보호되도록 한다.6. Cover coat coating step (see Fig. 4f), the cover coat on the remaining area, that is, the upper surface of the adhesive layer 31 except for the wiring pattern 33 protruding to the outer periphery of the ball land 32 and the adhesive layer 31 By coating 34, the wiring pattern and the like are protected from the external environment.

이상에서와 같이 본 발명은 비록 상기의 실시예에 한하여 설명하였지만 여기에만 한정되지 않으며, 본 발명의 범주 및 사상을 벗어나지 않는 범위내에서 여러가지로 변형된 실시예도 가능할 것이다. 즉, 상기 실시예에서는 제1반도체패키지로서 통상적인 리드프레임을 이용한 반도체패키지 및 MLF에 한정하여 본 발명을 설명하였으나, 이밖에도 다양한 많은 종류의 반도체패키지가 상기 제1반도체패키지로서 이용될 수 있을 것이다.As described above, although the present invention has been described with reference to the above embodiments, the present invention is not limited thereto, and various modified embodiments may be possible without departing from the scope and spirit of the present invention. That is, in the above embodiment, the present invention has been described with reference to a semiconductor package and an MLF using a conventional lead frame as the first semiconductor package. However, many other kinds of semiconductor packages may be used as the first semiconductor package.

따라서 본 발명에 의한 스택형 반도체패키지 및 이에 이용되는 가요성 배선기판의 제조 방법에 의하면, 통상의 제1반도체패키지를 구비하고, 상기 제1반도체패키지의 봉지부 상면에는 배선패턴이 형성된 가요성 배선기판을 제조하여 접착시키며, 그 상면에는 다시 통상의 제2반도체패키지를 접속시킴으로써, 제1반도체패키지와 제2반도체패키지가 상기 가요성 배선기판에 의해 간단히 접속되는 효과가 있다.Therefore, according to the stack-type semiconductor package according to the present invention and a method for manufacturing a flexible wiring board used therein, a flexible wiring having a normal first semiconductor package and having a wiring pattern formed on an upper surface of the encapsulation portion of the first semiconductor package is provided. The substrate is manufactured and bonded, and the second semiconductor package is connected to the upper surface of the second semiconductor package, and the first semiconductor package and the second semiconductor package are easily connected by the flexible wiring board.

또한, 통상의 제1반도체패키지 및 제2반도체패키지를 각각 제조하고, 또한 별도로 제조된 가요성 배선기판을 상기 제1반도체패키지의 상면에 접착시킴으로써, 복잡한 공정을 통하지 않고서도 간단한 방법 및 구조로 스택형 반도체패키지를 구현하는 효과가 있다.In addition, by manufacturing a conventional first semiconductor package and a second semiconductor package, respectively, and attaching a separately manufactured flexible wiring board to the upper surface of the first semiconductor package, the stack in a simple method and structure without going through a complicated process It is effective to implement a type semiconductor package.

Claims (5)

봉지부의 측부 외주연으로 마더보드에 접속될 리드가 돌출된 제1반도체패키지와;A first semiconductor package having a lead protruding from the side portion of the encapsulation portion to be connected to the motherboard; 상기 봉지부의 상면에 절연성의 접착층이 접착되고, 상기 접착층의 상면에는 다수의 도전성 볼랜드가 어레이된 동시에, 상기 볼랜드로부터는 상기 제1반도체패키지의 리드 상면에까지 연장되어 접속되는 도전성 배선패턴이 형성된 가요성 배선기판과;An insulating adhesive layer is adhered to the upper surface of the encapsulation portion, and a plurality of conductive borlands are arrayed on the upper surface of the adhesive layer, and a flexible wiring pattern is formed from the borland extending to and connected to the upper surface of the lead of the first semiconductor package. A wiring board; 상기 가요성 배선기판의 볼랜드에 도전성볼을 통해 접속된 제2반도체패키지를 포함하여 이루어진 스택형 반도체패키지.Stacked semiconductor package comprising a second semiconductor package connected to the ball land of the flexible wiring board through a conductive ball. 제1항에 있어서, 상기 가요성 배선기판의 배선패턴은 상기 제1반도체패키지의 리드 상면에 도전성 에폭시에 의해 접착된 것을 특징으로 하는 스택형 반도체패키지.The stack type semiconductor package of claim 1, wherein the wiring pattern of the flexible wiring board is bonded to the upper surface of the lead of the first semiconductor package by conductive epoxy. 접착층 표면에 구리층이 형성된 원판(原板)을 제공하는 단계와;Providing an original plate having a copper layer formed on the surface of the adhesive layer; 상기 구리박막 표면에 소정 패턴을 갖는 감광막을 형성하는 단계와;Forming a photosensitive film having a predetermined pattern on the surface of the copper thin film; 상기 감광막이 형성된 원판을 화학용액으로 에칭하여, 상기 접착층 표면에 볼랜드 및 배선패턴이 형성되도록 하는 단계와;Etching the original plate on which the photoresist film is formed with a chemical solution to form a ball land and a wiring pattern on the surface of the adhesive layer; 상기 볼랜드 및 배선패턴 상면의 감광막을 제거하는 단계와;Removing the photoresist on the upper surface of the ball land and the wiring pattern; 상기 접착층의 둘레를 일정폭만큼 제거하여 상기 배선패턴이 접착층 외주연으로 돌출되도록 하는 단계를 포함하여 이루어진 가요성 배선기판의 제조 방법.And removing the circumference of the adhesive layer by a predetermined width so that the wiring pattern protrudes to the outer circumferential edge of the adhesive layer. 제3항에 있어서, 상기 원판은 접착층 표면에 구리박막을 접착시켜 형성된 것 또는 접착층 표면에 구리 입자를 증착하여 형성된 것중 선택된 어느 하나가 제공됨을 특징으로 하는 가요성 배선기판의 제조 방법.The method of manufacturing a flexible wiring board according to claim 3, wherein the original plate is provided by any one selected from a copper thin film adhered to an adhesive layer surface or a copper particle deposited on an adhesive layer surface. 제3항 또는 제4항중 어느 한 항에 있어서, 상기 볼랜드 및 배선패턴의 단부를 제외한 나머지 영역에는 커버코트가 코팅되는 단계가 더 포함된 것을 특징으로 하는 가요성 배선기판의 제조 방법.The method of manufacturing a flexible wiring board according to any one of claims 3 to 4, wherein the cover coat is coated on the remaining areas except for the ends of the ball lands and the wiring patterns.
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Cited By (48)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030033611A (en) * 2001-10-24 2003-05-01 정운영 Stacked semiconductor package and fabricating method thereof
KR100772096B1 (en) * 2004-12-27 2007-11-01 주식회사 하이닉스반도체 Stack package
US8482111B2 (en) 2010-07-19 2013-07-09 Tessera, Inc. Stackable molded microelectronic packages
US8525314B2 (en) 2004-11-03 2013-09-03 Tessera, Inc. Stacked packaging improvements
US8618659B2 (en) 2011-05-03 2013-12-31 Tessera, Inc. Package-on-package assembly with wire bonds to encapsulation surface
US8623706B2 (en) 2010-11-15 2014-01-07 Tessera, Inc. Microelectronic package with terminals on dielectric mass
US8728865B2 (en) 2005-12-23 2014-05-20 Tessera, Inc. Microelectronic packages and methods therefor
US8836136B2 (en) 2011-10-17 2014-09-16 Invensas Corporation Package-on-package assembly with wire bond vias
US8835228B2 (en) 2012-05-22 2014-09-16 Invensas Corporation Substrate-less stackable package with wire-bond interconnect
US8878353B2 (en) 2012-12-20 2014-11-04 Invensas Corporation Structure for microelectronic packaging with bond elements to encapsulation surface
US8883563B1 (en) 2013-07-15 2014-11-11 Invensas Corporation Fabrication of microelectronic assemblies having stack terminals coupled by connectors extending through encapsulation
US8975738B2 (en) 2012-11-12 2015-03-10 Invensas Corporation Structure for microelectronic packaging with terminals on dielectric mass
US9023691B2 (en) 2013-07-15 2015-05-05 Invensas Corporation Microelectronic assemblies with stack terminals coupled by connectors extending through encapsulation
US9034696B2 (en) 2013-07-15 2015-05-19 Invensas Corporation Microelectronic assemblies having reinforcing collars on connectors extending through encapsulation
US9082753B2 (en) 2013-11-12 2015-07-14 Invensas Corporation Severing bond wire by kinking and twisting
US9087815B2 (en) 2013-11-12 2015-07-21 Invensas Corporation Off substrate kinking of bond wire
US9214454B2 (en) 2014-03-31 2015-12-15 Invensas Corporation Batch process fabrication of package-on-package microelectronic assemblies
US9224717B2 (en) 2011-05-03 2015-12-29 Tessera, Inc. Package-on-package assembly with wire bonds to encapsulation surface
US9324681B2 (en) 2010-12-13 2016-04-26 Tessera, Inc. Pin attachment
US9349706B2 (en) 2012-02-24 2016-05-24 Invensas Corporation Method for package-on-package assembly with wire bonds to encapsulation surface
US9391008B2 (en) 2012-07-31 2016-07-12 Invensas Corporation Reconstituted wafer-level package DRAM
US9412714B2 (en) 2014-05-30 2016-08-09 Invensas Corporation Wire bond support structure and microelectronic package including wire bonds therefrom
US9502390B2 (en) 2012-08-03 2016-11-22 Invensas Corporation BVA interposer
US9553076B2 (en) 2010-07-19 2017-01-24 Tessera, Inc. Stackable molded microelectronic packages with area array unit connectors
US9583411B2 (en) 2014-01-17 2017-02-28 Invensas Corporation Fine pitch BVA using reconstituted wafer with area array accessible for testing
US9601454B2 (en) 2013-02-01 2017-03-21 Invensas Corporation Method of forming a component having wire bonds and a stiffening layer
US9646917B2 (en) 2014-05-29 2017-05-09 Invensas Corporation Low CTE component with wire bond interconnects
US9685365B2 (en) 2013-08-08 2017-06-20 Invensas Corporation Method of forming a wire bond having a free end
US9691679B2 (en) 2012-02-24 2017-06-27 Invensas Corporation Method for package-on-package assembly with wire bonds to encapsulation surface
US9728527B2 (en) 2013-11-22 2017-08-08 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US9735084B2 (en) 2014-12-11 2017-08-15 Invensas Corporation Bond via array for thermal conductivity
US9761554B2 (en) 2015-05-07 2017-09-12 Invensas Corporation Ball bonding metal wire bond wires to metal pads
US9812402B2 (en) 2015-10-12 2017-11-07 Invensas Corporation Wire bond wires for interference shielding
US9842745B2 (en) 2012-02-17 2017-12-12 Invensas Corporation Heat spreading substrate with embedded interconnects
US9852969B2 (en) 2013-11-22 2017-12-26 Invensas Corporation Die stacks with one or more bond via arrays of wire bond wires and with one or more arrays of bump interconnects
US9888579B2 (en) 2015-03-05 2018-02-06 Invensas Corporation Pressing of wire bond wire tips to provide bent-over tips
US9911718B2 (en) 2015-11-17 2018-03-06 Invensas Corporation ‘RDL-First’ packaged microelectronic device for a package-on-package device
US9935075B2 (en) 2016-07-29 2018-04-03 Invensas Corporation Wire bonding method and apparatus for electromagnetic interference shielding
US9984992B2 (en) 2015-12-30 2018-05-29 Invensas Corporation Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces
US10008469B2 (en) 2015-04-30 2018-06-26 Invensas Corporation Wafer-level packaging using wire bond wires in place of a redistribution layer
US10008477B2 (en) 2013-09-16 2018-06-26 Invensas Corporation Microelectronic element with bond elements to encapsulation surface
US10026717B2 (en) 2013-11-22 2018-07-17 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US10181457B2 (en) 2015-10-26 2019-01-15 Invensas Corporation Microelectronic package for wafer-level chip scale packaging with fan-out
US10299368B2 (en) 2016-12-21 2019-05-21 Invensas Corporation Surface integrated waveguides and circuit structures therefor
US10332854B2 (en) 2015-10-23 2019-06-25 Invensas Corporation Anchoring structure of fine pitch bva
US10381326B2 (en) 2014-05-28 2019-08-13 Invensas Corporation Structure and method for integrated circuits packaging with increased density
US10460958B2 (en) 2013-08-07 2019-10-29 Invensas Corporation Method of manufacturing embedded packaging with preformed vias
US10490528B2 (en) 2015-10-12 2019-11-26 Invensas Corporation Embedded wire bond wires

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9659848B1 (en) 2015-11-18 2017-05-23 Invensas Corporation Stiffened wires for offset BVA

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62291125A (en) * 1986-06-11 1987-12-17 Seiko Epson Corp Manufacture of circuit board
JPH0427188A (en) * 1990-05-22 1992-01-30 Nitto Denko Corp Flexible circuit board and manufacture thereof
JPH07235636A (en) * 1994-02-21 1995-09-05 Fujitsu Ltd Semiconductor device and laminated structure thereof
JP2869969B2 (en) * 1995-04-28 1999-03-10 ソニーケミカル株式会社 Method for manufacturing flexible circuit board
KR100713898B1 (en) * 2000-10-06 2007-05-07 주식회사 하이닉스반도체 Stack package
KR20020028473A (en) * 2000-10-10 2002-04-17 박종섭 Stack package

Cited By (99)

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Publication number Priority date Publication date Assignee Title
KR20030033611A (en) * 2001-10-24 2003-05-01 정운영 Stacked semiconductor package and fabricating method thereof
US8927337B2 (en) 2004-11-03 2015-01-06 Tessera, Inc. Stacked packaging improvements
US9570416B2 (en) 2004-11-03 2017-02-14 Tessera, Inc. Stacked packaging improvements
US8525314B2 (en) 2004-11-03 2013-09-03 Tessera, Inc. Stacked packaging improvements
US8531020B2 (en) 2004-11-03 2013-09-10 Tessera, Inc. Stacked packaging improvements
US9153562B2 (en) 2004-11-03 2015-10-06 Tessera, Inc. Stacked packaging improvements
KR100772096B1 (en) * 2004-12-27 2007-11-01 주식회사 하이닉스반도체 Stack package
US8728865B2 (en) 2005-12-23 2014-05-20 Tessera, Inc. Microelectronic packages and methods therefor
US9218988B2 (en) 2005-12-23 2015-12-22 Tessera, Inc. Microelectronic packages and methods therefor
US9984901B2 (en) 2005-12-23 2018-05-29 Tessera, Inc. Method for making a microelectronic assembly having conductive elements
US10128216B2 (en) 2010-07-19 2018-11-13 Tessera, Inc. Stackable molded microelectronic packages
US9570382B2 (en) 2010-07-19 2017-02-14 Tessera, Inc. Stackable molded microelectronic packages
US8482111B2 (en) 2010-07-19 2013-07-09 Tessera, Inc. Stackable molded microelectronic packages
US9123664B2 (en) 2010-07-19 2015-09-01 Tessera, Inc. Stackable molded microelectronic packages
US8907466B2 (en) 2010-07-19 2014-12-09 Tessera, Inc. Stackable molded microelectronic packages
US9553076B2 (en) 2010-07-19 2017-01-24 Tessera, Inc. Stackable molded microelectronic packages with area array unit connectors
US8957527B2 (en) 2010-11-15 2015-02-17 Tessera, Inc. Microelectronic package with terminals on dielectric mass
US8623706B2 (en) 2010-11-15 2014-01-07 Tessera, Inc. Microelectronic package with terminals on dielectric mass
US8659164B2 (en) 2010-11-15 2014-02-25 Tessera, Inc. Microelectronic package with terminals on dielectric mass
US8637991B2 (en) 2010-11-15 2014-01-28 Tessera, Inc. Microelectronic package with terminals on dielectric mass
US9324681B2 (en) 2010-12-13 2016-04-26 Tessera, Inc. Pin attachment
US9093435B2 (en) 2011-05-03 2015-07-28 Tessera, Inc. Package-on-package assembly with wire bonds to encapsulation surface
US9224717B2 (en) 2011-05-03 2015-12-29 Tessera, Inc. Package-on-package assembly with wire bonds to encapsulation surface
US11424211B2 (en) 2011-05-03 2022-08-23 Tessera Llc Package-on-package assembly with wire bonds to encapsulation surface
US9691731B2 (en) 2011-05-03 2017-06-27 Tessera, Inc. Package-on-package assembly with wire bonds to encapsulation surface
US10593643B2 (en) 2011-05-03 2020-03-17 Tessera, Inc. Package-on-package assembly with wire bonds to encapsulation surface
US8618659B2 (en) 2011-05-03 2013-12-31 Tessera, Inc. Package-on-package assembly with wire bonds to encapsulation surface
US10062661B2 (en) 2011-05-03 2018-08-28 Tessera, Inc. Package-on-package assembly with wire bonds to encapsulation surface
US10756049B2 (en) 2011-10-17 2020-08-25 Invensas Corporation Package-on-package assembly with wire bond vias
US9105483B2 (en) 2011-10-17 2015-08-11 Invensas Corporation Package-on-package assembly with wire bond vias
US9761558B2 (en) 2011-10-17 2017-09-12 Invensas Corporation Package-on-package assembly with wire bond vias
US9252122B2 (en) 2011-10-17 2016-02-02 Invensas Corporation Package-on-package assembly with wire bond vias
US8836136B2 (en) 2011-10-17 2014-09-16 Invensas Corporation Package-on-package assembly with wire bond vias
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