KR100375168B1 - Semiconductor package and method for manufacturing the same - Google Patents
Semiconductor package and method for manufacturing the same Download PDFInfo
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- KR100375168B1 KR100375168B1 KR10-2000-0065021A KR20000065021A KR100375168B1 KR 100375168 B1 KR100375168 B1 KR 100375168B1 KR 20000065021 A KR20000065021 A KR 20000065021A KR 100375168 B1 KR100375168 B1 KR 100375168B1
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- bonding
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- circuit board
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Abstract
본 발명은 인쇄회로기판상에 반도체 칩을 부착하고, 이 반도체 칩의 상면에 회로필름 부재를 부착하여 제조된 반도체 패키지를 서로 적층하여 이루어진 새로운 구조의 반도체 패키지 및 그 제조방법에 관한 것으로서, 더욱 상세하게는 인쇄회로기판의 칩탑재영역에 접착수단을 사용하여 반도체 칩을 부착하는 공정과; 상기 각각의 반도체 칩의 상면에 본딩패드가 노출되도록 회로필름을 부착하는 공정과; 상기 반도체 칩의 본딩패드와 인쇄회로기판의 본딩영역간을 와이어로 본딩하는 공정과; 상기 회로필름의 양끝으로 돌출되며 노출되어 있는 탭 본딩용 전도성패턴을 상기 반도체 칩의 본딩패드에 절곡시켜 부착시키는 공정과; 상기 반도체 칩과 탭 본딩용 전도성패턴과 와이어등을 수지로 몰딩하는 공정과; 상기 인쇄회로기판의 저면으로 노출된 전도성패턴과 상기 회로필름의 상면으로 노출된 전도성패턴에 인출단자를 부착하는 공정으로 달성된 반도체 패키지를 적층하여 이루어진 새로운 구조의 반도체 패키지 및 그 제조방법을 제공하고자 한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package having a new structure and a method of manufacturing the same, comprising a semiconductor package attached to a printed circuit board and a semiconductor package manufactured by attaching a circuit film member to an upper surface of the semiconductor chip. Attaching the semiconductor chip to the chip mounting region of the printed circuit board by using an adhesive means; Attaching a circuit film so that a bonding pad is exposed on an upper surface of each semiconductor chip; Bonding a bonding pad of the semiconductor chip to a bonding area of the printed circuit board with a wire; Bending and attaching the exposed tab bonding conductive pattern to the bonding pad of the semiconductor chip, protruding from both ends of the circuit film; Molding the semiconductor chip, the conductive pattern for tap bonding, the wire, and the like with a resin; To provide a semiconductor package having a new structure and a method of manufacturing the same, which is obtained by laminating a semiconductor package achieved by attaching a lead terminal to a conductive pattern exposed on a bottom surface of the printed circuit board and a conductive pattern exposed on an upper surface of the circuit film. It is.
Description
본 발명은 반도체 패키지 및 그 제조방법에 관한 것으로서, 더욱 상세하게는인쇄회로기판상에 반도체 칩을 부착하고, 이 반도체 칩의 상면에 회로필름 부재를 부착하여 제조된 반도체 패키지를 서로 적층하여 이루어진 새로운 구조의 반도체 패키지 및 그 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package and a method for manufacturing the same, and more particularly, to a semiconductor package formed by attaching a semiconductor chip on a printed circuit board and attaching a circuit film member to an upper surface of the semiconductor chip. A semiconductor package having a structure and a method of manufacturing the same.
통상적으로 반도체 패키지는 전자기기의 집약적인 발달과 소형화 경향으로 고집적화, 소형화, 고기능화를 실현할 수 있는 제조 추세에 있는 바, 리드프레임, 인쇄회로기판, 필름등의 부재를 이용하여 여러가지 구조로 이루어진 다양한 종류의 패키지가 경박단소화로 개발되어 왔고, 개발중에 있다.In general, semiconductor packages are in the manufacturing trend to realize high integration, miniaturization, and high functionalization due to the intensive development and miniaturization of electronic devices, and various types having various structures using members such as lead frames, printed circuit boards, and films. Packages have been developed and are under development.
특히, 최근에는 반도체 패키지를 적층한 새로운 구조의 반도체 패키지의 개발이 이루어지고 있다.In particular, in recent years, development of a semiconductor package having a new structure in which semiconductor packages are laminated is being made.
따라서, 본 발명은 반도체 패키지를 적층한 새로운 구조의 반도체 패키지를 안출한 것으로서, 인쇄회로기판에 칩을 부착하고, 이 칩의 상면에 회로필름을 부착하여, 상기 인쇄회로기판의 본딩영역과 상기 반도체 칩의 본딩패드를 와이어 본딩하고 상기 회로필름의 탭 본딩용 전도성패턴을 반도체 칩의 본딩패드에 본딩한 후, 수지로 몰딩하여 제조된 반도체 패키지와 그 제조방법을 제공하는데 그 목적이 있다.Accordingly, the present invention is a semiconductor package having a new structure in which a semiconductor package is laminated, and a chip is attached to a printed circuit board, and a circuit film is attached to an upper surface of the chip, thereby bonding the semiconductor substrate to the bonding area of the printed circuit board. An object of the present invention is to provide a semiconductor package manufactured by molding a bonding pad of a chip and bonding a conductive pattern for tap bonding of the circuit film to a bonding pad of a semiconductor chip, and then molding the resin with a resin.
특히, 상기 반도체 패키지를 적층하여 이루어진 구조의 반도체 패키지와 그 제조방법을 제공하는데 그 목적이 있다.In particular, it is an object of the present invention to provide a semiconductor package having a structure formed by laminating the semiconductor package and a method of manufacturing the same.
도 1a,1b는 본 발명에 따른 반도체 패키지와 그 제조방법을 순서대로 나타내는 단면도.1A and 1B are cross-sectional views sequentially illustrating a semiconductor package and a method of manufacturing the same according to the present invention.
<도면의 주요 부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>
10 : 반도체 패키지 12 : 인쇄회로기판10 semiconductor package 12 printed circuit board
14 : 회로필름 16 : 탭 본딩용 전도성패턴14: circuit film 16: conductive pattern for tab bonding
18 : 와이어 20 : 반도체 칩18: wire 20: semiconductor chip
22 : 인출단자 24 : 전도성패턴22: withdrawal terminal 24: conductive pattern
26 : 솔더마스크 28 : 수지층26: solder mask 28: resin layer
30 : 수지 32 : 필름30: resin 32: film
이하, 본 발명을 첨부도면을 참조로 상세하게 설명하면 다음과 같다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
상기한 목적을 달성하기 위한 본 발명의 반도체 패키지는: 다수의 칩탑재영역이 형성된 인쇄회로기판(12)과; 상기 인쇄회로기판(12)의 칩탑재영역에 접착수단에 의하여 부착된 반도체 칩(20)과; 상기 반도체 칩(20) 상면의 본딩패드가 노출되게 접착수단에 의하여 부착된 회로필름(14)과; 상기 반도체 칩(20)의 본딩패드와 상기 인쇄회로기판(12)의 본딩영역인 전도성패턴(24)간에 연결된 와이어(18)와; 상기 회로필름(14)의 양끝으로 돌출되며 노출되어 상기 반도체 칩(20)의 본딩패드에 절곡되며 부착되는 탭 본딩용 전도성패턴(16)과; 상기 반도체 칩(20)과 와이어(18) 및 탭 본딩용 전도성패턴(16)등을 몰딩하고 있는 수지(30)와; 상기 인쇄회로기판(12)의 저면으로 노출된 전도성패턴(24)과 상기 회로필름(14)의 상면으로 노출된 전도성패턴(24)에 부착되는 인출단자(22)로 구성된 것을 특징으로 한다.The semiconductor package of the present invention for achieving the above object comprises: a printed circuit board 12 having a plurality of chip mounting region; A semiconductor chip 20 attached to the chip mounting region of the printed circuit board 12 by adhesive means; A circuit film 14 attached by an adhesive means to expose the bonding pads on the upper surface of the semiconductor chip 20; A wire 18 connected between the bonding pad of the semiconductor chip 20 and the conductive pattern 24, which is a bonding region of the printed circuit board 12; A tab bonding conductive pattern 16 protruding from both ends of the circuit film 14 to be exposed and bent and attached to a bonding pad of the semiconductor chip 20; A resin 30 molding the semiconductor chip 20, the wire 18, and the conductive pattern 16 for tab bonding; The conductive pattern 24 is exposed to the bottom surface of the printed circuit board 12 and the drawing terminal 22 is attached to the conductive pattern 24 exposed to the upper surface of the circuit film 14.
특히, 상기 인쇄회로기판(12) 저면의 전도성패턴(24)과 상기 회로필름(14) 상면의 전도성패턴(24)간을 전기적 신호 교환 가능하게 인출단자(22)로 연결 부착하여, 반도체 패키지가 적층되도록 한 것을 특징으로 한다.In particular, the semiconductor package is connected to the conductive pattern 24 on the bottom surface of the printed circuit board 12 and the conductive pattern 24 on the upper surface of the circuit film 14 by the lead terminal 22 so as to exchange electrical signals. It is characterized by being laminated.
상기 반도체 칩(20)의 상면 테두리면에는 탭 본딩용 본딩패드와 와이어 본딩용 본딩패드가 서로 교차되게 형성된 것을 특징으로 한다.The upper surface of the semiconductor chip 20 is characterized in that the tab bonding bonding pad and the wire bonding bonding pad are formed to cross each other.
상기한 목적을 달성하기 위한 본 발명의 반도체 패키지 제조방법은:The semiconductor package manufacturing method of the present invention for achieving the above object is:
인쇄회로기판(12)의 칩탑재영역에 접착수단을 사용하여 반도체 칩(20)을 부착하는 공정과; 상기 각각의 반도체 칩(20)의 상면에 본딩패드가 노출되도록 회로필름(14)을 접착수단으로 부착하는 공정과; 상기 반도체 칩(20)의 본딩패드와 인쇄회로기판(12)의 본딩영역간을 와이어(18)로 본딩하는 공정과; 상기 회로필름(14)의 양끝으로 돌출되며 노출되어 있는 탭 본딩용 전도성패턴(16)을 상기 반도체 칩(20)의 본딩패드에 절곡시켜 부착시키는 공정과; 상기 반도체 칩(20)과 탭 본딩용 전도성패턴(16)과 와이어(18)등을 수지(30)로 몰딩하는 공정과; 상기 인쇄회로기판(12)의 저면으로 노출된 전도성패턴(24)과 상기 회로필름(14)의 상면으로 노출된 전도성패턴(14)에 인출단자(22)를 부착하는 공정으로 달성된 것을 특징으로 한다.Attaching the semiconductor chip 20 to the chip mounting region of the printed circuit board 12 using an adhesive means; Attaching a circuit film (14) by adhesive means so that a bonding pad is exposed on an upper surface of each semiconductor chip (20); Bonding a bonding pad of the semiconductor chip 20 and a bonding area of the printed circuit board 12 with a wire 18; Bending and attaching the exposed tab bonding conductive pattern 16 to the bonding pad of the semiconductor chip 20, protruding from both ends of the circuit film 14; Molding the semiconductor chip 20, the tab bonding conductive pattern 16, the wire 18, and the like with a resin 30; And a drawing terminal 22 attached to the conductive pattern 24 exposed to the bottom surface of the printed circuit board 12 and the conductive pattern 14 exposed to the top surface of the circuit film 14. do.
특히, 상기 인쇄회로기판(12)의 저면에 노출된 전도성패턴(24)과 상기 회로필름(14)의 상면으로 노출된 전도성패턴(24)간을 인출단자(22)로 연결시켜 반도체 패키지(10)를 적층시키는 공정이 더 진행됨을 특징으로 한다.In particular, the semiconductor package 10 may be connected between the conductive pattern 24 exposed on the bottom surface of the printed circuit board 12 and the conductive pattern 24 exposed on the top surface of the circuit film 14 with the lead terminals 22. ) Is further characterized in that the process of laminating.
여기서 본 발명을 실시예로서, 첨부한 도면을 참조로 더욱 상세하게 설명하면 다음과 같다.Herein, the present invention will be described in more detail with reference to the accompanying drawings.
첨부한 도 1a,1b는 본 발명에 따른 반도체 패키지 및 그 제조방법을 순서대로 나타내는 단면도로서, 도면부호 12은 인쇄회로기판이다.1A and 1B are cross-sectional views sequentially illustrating a semiconductor package and a method of manufacturing the same according to the present invention, and reference numeral 12 denotes a printed circuit board.
상기 인쇄회로기판(12)은 다수개의 반도체 패키지 영역이 매트릭스 또는 스트립 형태로 형성된 부재로서, 중앙의 베이스를 이루는 수지층(28)과, 수지층(28)의 상하면에 에칭 처리되어 부착된 동재질의 전도성패턴(24)과, 이 전도성패턴(24)을 포함하며 수지층(28)의 상하면에 도포된 솔더마스크(26)층으로 구성되어 있다.The printed circuit board 12 is a member in which a plurality of semiconductor package regions are formed in a matrix or strip form, and is formed of a resin material 28 forming a central base and an etching material attached to upper and lower surfaces of the resin layer 28. It consists of a conductive pattern 24 and a solder mask 26 layer including the conductive pattern 24 and applied to the upper and lower surfaces of the resin layer 28.
좀 더 상세하게는, 상기 솔더마스크(26)층은 와이어 본딩용, 인출단자 부착용 전도성패턴(24)이 외부로 노출되게 도포되어 있다.In more detail, the solder mask 26 layer is applied such that the conductive pattern 24 for wire bonding and the lead terminal attachment is exposed to the outside.
본 발명의 반도체 패키지를 제조함에 있어서, 먼저 상기와 같은 구조의 인쇄회로기판(12)의 칩탑재영역에 반도체 칩(20)을 양면테이프나 에폭시 수지와 같은 접착수단을 사용하여 부착하게 된다.In manufacturing the semiconductor package of the present invention, first, the semiconductor chip 20 is attached to the chip mounting region of the printed circuit board 12 having the above structure by using an adhesive means such as a double-sided tape or an epoxy resin.
상기 반도체 칩(20)의 상면 테두리에는 와이어 본딩용 본딩패드와 탭 본딩용 본딩패드가 지그재그 형태로 교차되며 형성되는 바, 바깥쪽에 탭 본딩용 본딩패드를 안쪽에 와이어 본딩용 본딩패드를 형성함이 바람직하다.On the upper edge of the semiconductor chip 20, a wire bonding bonding pad and a tab bonding bonding pad are formed to cross each other in a zigzag form. desirable.
다음으로, 상기 각각의 반도체 칩(20)의 상면에 접착수단을 사용하여 회로필름(14)을 부착하는 공정을 진행시키게 된다.Next, a process of attaching the circuit film 14 to the upper surface of each semiconductor chip 20 by using an adhesive means is performed.
이때, 상기 회로필름(14)은 베이스층인 필름(32)과, 이 필름(32)상에 식각 처리된 전도성패턴(24)과, 이 전도성패턴(24)을 포함하며 도포된 솔더마스크(26)층으로 구성되어 있는 바, 상기 회로필름(14)의 사방끝으로는 탭 본딩용 전도성패턴(16)이 외부로 노출되며 돌출되어 있다.In this case, the circuit film 14 includes a film 32 as a base layer, a conductive pattern etched on the film 32, and a solder mask 26 including the conductive pattern 24. ), The tab film conductive patterns 16 are exposed to the outside and protrude outward from the four ends of the circuit film 14.
다음 공정으로, 상기 반도체 칩(20)의 와이어 본딩용 본딩패드와 인쇄회로기판(12)의 본딩영역인 전도성패턴(24)간을 와이어(18)로 본딩하는 공정을 진행하게 된다.In the next step, a process of bonding the wire bonding pad between the semiconductor chip 20 and the conductive pattern 24, which is a bonding region of the printed circuit board 12, with the wire 18 is performed.
다음 공정으로, 상기 회로필름(14)의 탭 본딩용 전도성패턴(16)을 절곡되게 눌러줌으로써, 탭 본딩용 전도성패턴(16)이 상기 반도체 칩(20)의 탭 본딩용 본딩패드에 부착되도록 한다.In the next step, the tab bonding conductive pattern 16 of the circuit film 14 is bent to be pressed so that the tab bonding conductive pattern 16 is attached to the tab bonding bond pad of the semiconductor chip 20. .
좀 더 상세하게는, 상기 탭 본딩용 전도성패턴(16)의 끝단부에 솔더와 같은전도성물질을 입혀서 열융착시킴으로써, 상기 탭 본딩용 전도성패턴(16)이 반도체 칩(20)의 탭 본딩용 본딩패드에 부착된다.More specifically, the tab bonding conductive pattern 16 bonds the tab bonding of the semiconductor chip 20 by thermally bonding a conductive material such as solder to the end of the tab bonding conductive pattern 16. It is attached to the pad.
다음 공정으로, 상기 반도체 칩(20)과, 탭 본딩용 전도성패턴(16)과, 와이어(18)등을 외부로부터 보호하기 위하여 수지(30)로 몰딩하는 공정을 진행하게 된다.In the next step, molding of the semiconductor chip 20, the tab bonding conductive pattern 16, the wire 18, and the like with the resin 30 is performed.
다음으로, 상기 인쇄회로기판(12)의 저면으로 노출된 전도성패턴(24)과, 상기 회로필름(14)의 상면으로 노출된 전도성패턴(24)에 솔더볼과 같은 인출단자(22)를 부착하는 공정을 진행시키게 된다.Next, the conductive pattern 24 exposed to the bottom surface of the printed circuit board 12 and the lead terminal 22 such as solder balls are attached to the conductive pattern 24 exposed to the upper surface of the circuit film 14. To proceed with the process.
특히, 상기 인쇄회로기판(12)의 저면에 노출된 전도성패턴(24)과, 상기 회로필름(14)의 상면으로 노출된 전도성패턴(24)간을 인출단자(22)로 연결되게 부착시킴으로써, 본 발명의 상하 적층된 구조의 반도체 패키지(10)가 완성된다.In particular, by attaching the conductive pattern 24 exposed on the bottom surface of the printed circuit board 12 and the conductive pattern 24 exposed on the upper surface of the circuit film 14 to be connected to the lead terminal 22. The semiconductor package 10 having the vertically stacked structure of the present invention is completed.
한편, 상기 인쇄회로기판(12)상에 매트릭스 또는 스트립 형태로 제조된 반도체 패키지(10)를 싱귤레이션함으로써, 낱개의 반도체 패키지로 분리할 수 있게 된다.On the other hand, by singulating the semiconductor package 10 manufactured in a matrix or strip form on the printed circuit board 12, it can be separated into a single semiconductor package.
이상에서 본 바와 같이, 본 발명에 따른 반도체 패키지 및 그 제조방법에 의하면, 반도체 칩의 본딩패드를 인쇄회로기판에 와이어 본딩을 하고, 회로필름에 탭본딩을 하여 반도체 패키지를 제조함으로써, 반도체 패키지를 용이하게 적층시킬 수 있는 장점이 있다.As described above, according to the semiconductor package and the manufacturing method thereof, the semiconductor package is manufactured by wire bonding a bonding pad of a semiconductor chip to a printed circuit board and manufacturing a semiconductor package by tap bonding the circuit film. There is an advantage that can be easily laminated.
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